# Static Timing Analysis

Project : | UART_RxTx01
Build Time : | 04/11/18 19:08:39
Device : | CY8C5888LTI-LP097
Temperature : | -40C - 85/125C
VDDA : | 5.50
VDDABUF : | 5.50
VDDD : | 5.50
VDDIO0 : | 5.50
VDDIO1 : | 5.50
VDDIO2 : | 5.50
VDDIO3 : | 5.50
VUSB : | 5.50
Voltage : | 5.5

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CyBUS_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | 59.687 MHz |
Clock_1 | CyMASTER_CLK | 76.677 kHz | 76.677 kHz | 56.430 MHz |
CyPLL_OUT | CyPLL_OUT | 24.000 MHz | 24.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : Clock_1 : Positive edge(Required Frequency 76.6773 kHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 76.6773 kHz)
Path Delay Requirement : 13041.7ns(76.6773 kHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\UART_1:BUART:tx_state_0\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 56.430 MHz | 17.721 | 13023.946 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell13 | U(0,0) | 1 | \UART_1:BUART:tx_state_0\ | \UART_1:BUART:tx_state_0\/clock_0 | \UART_1:BUART:tx_state_0\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_0\ | \UART_1:BUART:tx_state_0\/q | \UART_1:BUART:tx_bitclk_enable_pre\/main_1 | 4.236
macrocell3 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/main_1 | \UART_1:BUART:tx_bitclk_enable_pre\/q | 3.350
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.875
datapathcell1 | U(1,0) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_state_1\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 57.491 MHz | 17.394 | 13024.273 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell12 | U(1,0) | 1 | \UART_1:BUART:tx_state_1\ | \UART_1:BUART:tx_state_1\/clock_0 | \UART_1:BUART:tx_state_1\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_1\ | \UART_1:BUART:tx_state_1\/q | \UART_1:BUART:tx_bitclk_enable_pre\/main_0 | 3.909
macrocell3 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/main_0 | \UART_1:BUART:tx_bitclk_enable_pre\/q | 3.350
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.875
datapathcell1 | U(1,0) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_state_2\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 57.637 MHz | 17.350 | 13024.317 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell14 | U(1,0) | 1 | \UART_1:BUART:tx_state_2\ | \UART_1:BUART:tx_state_2\/clock_0 | \UART_1:BUART:tx_state_2\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_2\ | \UART_1:BUART:tx_state_2\/q | \UART_1:BUART:tx_bitclk_enable_pre\/main_2 | 3.865
macrocell3 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/main_2 | \UART_1:BUART:tx_bitclk_enable_pre\/q | 3.350
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.875
datapathcell1 | U(1,0) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 58.685 MHz | 17.040 | 13024.627 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell16 | U(1,1) | 1 | \UART_1:BUART:tx_ctrl_mark_last\ | \UART_1:BUART:tx_ctrl_mark_last\/clock_0 | \UART_1:BUART:tx_ctrl_mark_last\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_ctrl_mark_last\ | \UART_1:BUART:tx_ctrl_mark_last\/q | \UART_1:BUART:rx_counter_load\/main_0 | 4.768
macrocell6 | U(0,2) | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/main_0 | \UART_1:BUART:rx_counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 2.312
count7cell | U(0,2) | 1 | \UART_1:BUART:sRX:RxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1 | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 58.796 MHz | 17.008 | 13024.659 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1 | 1.940
Route |  | 1 | \UART_1:BUART:txbitcount_1\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1 | \UART_1:BUART:tx_bitclk_enable_pre\/main_4 | 2.833
macrocell3 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/main_4 | \UART_1:BUART:tx_bitclk_enable_pre\/q | 3.350
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.875
datapathcell1 | U(1,0) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2 | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 58.799 MHz | 17.007 | 13024.660 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2 | 1.940
Route |  | 1 | \UART_1:BUART:txbitcount_2\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2 | \UART_1:BUART:tx_bitclk_enable_pre\/main_3 | 2.832
macrocell3 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/main_3 | \UART_1:BUART:tx_bitclk_enable_pre\/q | 3.350
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.875
datapathcell1 | U(1,0) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0 | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 58.837 MHz | 16.996 | 13024.671 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0 | 1.940
Route |  | 1 | \UART_1:BUART:txbitcount_0\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0 | \UART_1:BUART:tx_bitclk_enable_pre\/main_5 | 2.821
macrocell3 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/main_5 | \UART_1:BUART:tx_bitclk_enable_pre\/q | 3.350
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:tx_bitclk_enable_pre\/q | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.875
datapathcell1 | U(1,0) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_state_0\/q | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load | 60.779 MHz | 16.453 | 13025.214 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell13 | U(0,0) | 1 | \UART_1:BUART:tx_state_0\ | \UART_1:BUART:tx_state_0\/clock_0 | \UART_1:BUART:tx_state_0\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_0\ | \UART_1:BUART:tx_state_0\/q | \UART_1:BUART:counter_load\/main_1 | 4.241
macrocell2 | U(0,0) | 1 | \UART_1:BUART:counter_load\ | \UART_1:BUART:counter_load\/main_1 | \UART_1:BUART:counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load\ | \UART_1:BUART:counter_load\/q | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load | 2.252
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_bitclk\/q | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load | 61.839 MHz | 16.171 | 13025.496 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell15 | U(1,1) | 1 | \UART_1:BUART:tx_bitclk\ | \UART_1:BUART:tx_bitclk\/clock_0 | \UART_1:BUART:tx_bitclk\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_bitclk\ | \UART_1:BUART:tx_bitclk\/q | \UART_1:BUART:counter_load\/main_3 | 3.959
macrocell2 | U(0,0) | 1 | \UART_1:BUART:counter_load\ | \UART_1:BUART:counter_load\/main_3 | \UART_1:BUART:counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load\ | \UART_1:BUART:counter_load\/q | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load | 2.252
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_state_1\/q | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load | 64.508 MHz | 15.502 | 13026.165 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell12 | U(1,0) | 1 | \UART_1:BUART:tx_state_1\ | \UART_1:BUART:tx_state_1\/clock_0 | \UART_1:BUART:tx_state_1\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_1\ | \UART_1:BUART:tx_state_1\/q | \UART_1:BUART:counter_load\/main_0 | 3.290
macrocell2 | U(0,0) | 1 | \UART_1:BUART:counter_load\ | \UART_1:BUART:counter_load\/main_0 | \UART_1:BUART:counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load\ | \UART_1:BUART:counter_load\/q | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load | 2.252
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : CyBUS_CLK : Positive edge(Required Frequency 24 MHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 76.6773 kHz)
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
RX(0)/fb | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 59.687 MHz | 16.754 | 24.913 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_postpoll\/main_1 | 5.634
macrocell7 | U(0,1) | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/main_1 | \UART_1:BUART:rx_postpoll\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 2.291
datapathcell2 | U(0,1) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ |  | SETUP | 3.470
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 81.646 MHz | 12.248 | 29.419 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 6.729
macrocell20 | U(0,2) | 1 | \UART_1:BUART:rx_state_2\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 81.646 MHz | 12.248 | 29.419 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 6.729
macrocell25 | U(0,2) | 1 | \UART_1:BUART:rx_status_3\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 81.780 MHz | 12.228 | 29.439 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 6.709
macrocell17 | U(0,2) | 1 | \UART_1:BUART:rx_state_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 95.529 MHz | 10.468 | 31.199 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 4.949
macrocell23 | U(0,0) | 1 | \UART_1:BUART:pollcount_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 95.529 MHz | 10.468 | 31.199 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 4.949
macrocell24 | U(0,0) | 1 | \UART_1:BUART:pollcount_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_last\/main_0 | 95.529 MHz | 10.468 | 31.199 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_last\/main_0 | 4.949
macrocell26 | U(0,0) | 1 | \UART_1:BUART:rx_last\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : Clock_1 : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\UART_1:BUART:rx_status_3\/q | \UART_1:BUART:sRX:RxSts\/status_3 | 2.159 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell25 | U(0,2) | 1 | \UART_1:BUART:rx_status_3\ | \UART_1:BUART:rx_status_3\/clock_0 | \UART_1:BUART:rx_status_3\/q | 1.250
Route |  | 1 | \UART_1:BUART:rx_status_3\ | \UART_1:BUART:rx_status_3\/q | \UART_1:BUART:sRX:RxSts\/status_3 | 2.909
statusicell2 | U(0,1) | 1 | \UART_1:BUART:sRX:RxSts\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:status_1\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_1 | 2.169 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell31 | U(1,1) | 1 | \PWM_1:PWMUDB:status_1\ | \PWM_1:PWMUDB:status_1\/clock_0 | \PWM_1:PWMUDB:status_1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_1\ | \PWM_1:PWMUDB:status_1\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_1 | 2.919
statusicell3 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 2.174 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell30 | U(0,1) | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/clock_0 | \PWM_1:PWMUDB:status_0\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 2.924
statusicell3 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | \UART_1:BUART:txn\/main_6 | 3.358 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | 0.650
Route |  | 1 | \UART_1:BUART:tx_counter_tc\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | \UART_1:BUART:txn\/main_6 | 2.708
macrocell11 | U(1,0) | 1 | \UART_1:BUART:txn\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | \UART_1:BUART:tx_state_1\/main_4 | 3.358 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | 0.650
Route |  | 1 | \UART_1:BUART:tx_counter_tc\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | \UART_1:BUART:tx_state_1\/main_4 | 2.708
macrocell12 | U(1,0) | 1 | \UART_1:BUART:tx_state_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | \UART_1:BUART:tx_state_2\/main_4 | 3.363 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(1,0) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | 0.650
Route |  | 1 | \UART_1:BUART:tx_counter_tc\ | \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc | \UART_1:BUART:tx_state_2\/main_4 | 2.713
macrocell14 | U(1,0) | 1 | \UART_1:BUART:tx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 | \UART_1:BUART:rx_load_fifo\/main_5 | 3.403 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,2) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_6 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_6\ | \UART_1:BUART:sRX:RxBitCounter\/count_6 | \UART_1:BUART:rx_load_fifo\/main_5 | 2.783
macrocell18 | U(0,2) | 1 | \UART_1:BUART:rx_load_fifo\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 | \UART_1:BUART:rx_state_2\/main_5 | 3.403 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,2) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_6 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_6\ | \UART_1:BUART:sRX:RxBitCounter\/count_6 | \UART_1:BUART:rx_state_2\/main_5 | 2.783
macrocell20 | U(0,2) | 1 | \UART_1:BUART:rx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 | \UART_1:BUART:rx_load_fifo\/main_6 | 3.407 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,2) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_5 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_5\ | \UART_1:BUART:sRX:RxBitCounter\/count_5 | \UART_1:BUART:rx_load_fifo\/main_6 | 2.787
macrocell18 | U(0,2) | 1 | \UART_1:BUART:rx_load_fifo\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 | \UART_1:BUART:rx_state_2\/main_6 | 3.407 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,2) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_5 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_5\ | \UART_1:BUART:sRX:RxBitCounter\/count_5 | \UART_1:BUART:rx_state_2\/main_6 | 2.787
macrocell20 | U(0,2) | 1 | \UART_1:BUART:rx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : CyBUS_CLK : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
RX(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 6.958 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 4.949
macrocell23 | U(0,0) | 1 | \UART_1:BUART:pollcount_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 6.958 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 4.949
macrocell24 | U(0,0) | 1 | \UART_1:BUART:pollcount_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_last\/main_0 | 6.958 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_last\/main_0 | 4.949
macrocell26 | U(0,0) | 1 | \UART_1:BUART:rx_last\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 8.718 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 6.709
macrocell17 | U(0,2) | 1 | \UART_1:BUART:rx_state_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 8.738 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 6.729
macrocell20 | U(0,2) | 1 | \UART_1:BUART:rx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 8.738 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 6.729
macrocell25 | U(0,2) | 1 | \UART_1:BUART:rx_status_3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
RX(0)/fb | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 13.284 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell1 | P12[6] | 1 | RX(0) | RX(0)/in_clock | RX(0)/fb | 2.009
Route |  | 1 | Net_45 | RX(0)/fb | \UART_1:BUART:rx_postpoll\/main_1 | 5.634
macrocell7 | U(0,1) | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/main_1 | \UART_1:BUART:rx_postpoll\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 2.291
datapathcell2 | U(0,1) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Input To Clock Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
cts(0)_PAD | \UART_1:BUART:tx_state_0\/main_5 | 18.265
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
Route |  | 1 | cts(0)_PAD | cts(0)_PAD | cts(0)/pad_in | 0.000
iocell3 | P2[6] | 1 | cts(0) | cts(0)/pad_in | cts(0)/fb | 7.338
Route |  | 1 | Net_3631 | cts(0)/fb | \UART_1:BUART:tx_state_0\/main_5 | 7.417
macrocell13 | U(0,0) | 1 | \UART_1:BUART:tx_state_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Clock path delay | 0.000

+ Clock To Output Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
\UART_1:BUART:txn\/q | TX(0)_PAD | 30.313
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell11 | U(1,0) | 1 | \UART_1:BUART:txn\ | \UART_1:BUART:txn\/clock_0 | \UART_1:BUART:txn\/q | 1.250
Route |  | 1 | \UART_1:BUART:txn\ | \UART_1:BUART:txn\/q | Net_66/main_0 | 2.538
macrocell1 | U(1,0) | 1 | Net_66 | Net_66/main_0 | Net_66/q | 3.350
Route |  | 1 | Net_66 | Net_66/q | TX(0)/pin_input | 6.208
iocell2 | P12[7] | 1 | TX(0) | TX(0)/pin_input | TX(0)/pad_out | 16.967
Route |  | 1 | TX(0)_PAD | TX(0)/pad_out | TX(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb | rts(0)_PAD | 25.935
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,1) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ | \UART_1:BUART:sRX:RxShifter:u0\/clock | \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb | 3.580
Route |  | 1 | Net_4888 | \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb | rts(0)/pin_input | 7.481
iocell4 | P2[7] | 1 | rts(0) | rts(0)/pin_input | rts(0)/pad_out | 14.874
Route |  | 1 | rts(0)_PAD | rts(0)/pad_out | rts(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000