# Static Timing Analysis

Project : | PWMExample01
Build Time : | 04/21/18 16:59:56
Device : | CY8C4245AXI-483
Temperature : | -40C - 85C
VDDA : | 3.30
VDDD : | 3.30
Voltage : | 3.3

Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
Clock_1(FFB) | Clock_1(FFB) | 12.000 MHz | 12.000 MHz | N/A |
CyHFCLK | CyHFCLK | 24.000 MHz | 24.000 MHz | N/A |
Clock_1 | CyHFCLK | 12.000 MHz | 12.000 MHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 24.000 MHz | 24.000 MHz | N/A |
CyLFCLK | CyLFCLK | 32.000 kHz | 32.000 kHz | N/A |
CyRouted1 | CyRouted1 | 24.000 MHz | 24.000 MHz | N/A |
CySYSCLK | CySYSCLK | 24.000 MHz | 24.000 MHz | N/A |

+ Clock To Output Section
+ Clock_1(FFB)

Source | Destination | Delay (ns)
--- | --- | ---
\PWM:cy_m0s8_tcpwm_1\/line_out | LED_GREEN(0)_PAD | 21.814
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
m0s8tcpwmcell | F(TCPWM,0) | 1 | \PWM:cy_m0s8_tcpwm_1\ | \PWM:cy_m0s8_tcpwm_1\/clock | \PWM:cy_m0s8_tcpwm_1\/line_out | 0.000
Route |  | 1 | Net_207 | \PWM:cy_m0s8_tcpwm_1\/line_out | LED_GREEN(0)/pin_input | 5.984
iocell1 | P0[2] | 1 | LED_GREEN(0) | LED_GREEN(0)/pin_input | LED_GREEN(0)/pad_out | 15.830
Route |  | 1 | LED_GREEN(0)_PAD | LED_GREEN(0)/pad_out | LED_GREEN(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000