# Static Timing Analysis

Project : | UART_RxTx01
Build Time : | 06/02/18 23:17:16
Device : | CY8C4247AZI-M485
Temperature : | -40C - 85C
VDDA_0 : | 5.50
VDDA_CTB : | 5.50
VDDD : | 5.50
VDDD_0 : | 5.50
VDDD_1 : | 5.50
VDDIO : | 3.30
VDDIO_1 : | 3.30
VDDIO_2 : | 3.30
VDDIO_A : | 5.50
VDDIO_A_1 : | 5.50
Voltage : | 5.5

Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyHFCLK | CyHFCLK | 24.000 MHz | 24.000 MHz | N/A |
Clock_1 | CyHFCLK | 77.922 kHz | 77.922 kHz | 55.442 MHz |
UART_1_SCBCLK | CyHFCLK | 461.538 kHz | 461.538 kHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 24.000 MHz | 24.000 MHz | N/A |
CyLFCLK | CyLFCLK | 32.000 kHz | 32.000 kHz | N/A |
CyRouted1 | CyRouted1 | 24.000 MHz | 24.000 MHz | N/A |
CySYSCLK | CySYSCLK | 24.000 MHz | 24.000 MHz | N/A |
CyWCO | CyWCO | 32.768 kHz | 32.768 kHz | N/A |
UART_1_SCBCLK(FFB) | UART_1_SCBCLK(FFB) | 461.538 kHz | 461.538 kHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : Clock_1 : Positive edge(Required Frequency 77.9221 kHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 77.9221 kHz)
Path Delay Requirement : 12833.3ns(77.9221 kHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 55.442 MHz | 18.037 | 12815.296 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 3.850
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 2.667
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 64.144 MHz | 15.590 | 12817.743 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 2.820
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 72.913 MHz | 13.715 | 12819.618 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 3.850
Route |  | 1 | \PWM_1:PWMUDB:tc_i\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:status_2\/main_1 | 2.690
macrocell2 | U(0,0) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_1 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.255
statusicell1 | U(0,0) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 85.281 MHz | 11.726 | 12821.607 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 5.680
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 2.536
macrocell8 | U(0,0) | 1 | Net_5269 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 85.339 MHz | 11.718 | 12821.615 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 5.680
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 2.528
macrocell4 | U(0,0) | 1 | \PWM_1:PWMUDB:prevCompare1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 85.339 MHz | 11.718 | 12821.615 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 5.680
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 2.528
macrocell6 | U(0,0) | 1 | \PWM_1:PWMUDB:status_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 88.944 MHz | 11.243 | 12822.090 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:status_2\/main_0 | 2.818
macrocell2 | U(0,0) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_0 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.255
statusicell1 | U(0,0) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 119.632 MHz | 8.359 | 12824.974 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell2 | U(0,0) | 1 | \PWM_1:PWMUDB:genblk1:ctrlreg\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/clock | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | 2.580
Route |  | 1 | \PWM_1:PWMUDB:control_7\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 2.269
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 132.083 MHz | 7.571 | 12825.762 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 2.811
macrocell8 | U(0,0) | 1 | Net_5269 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 142.857 MHz | 7.000 | 12826.333 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(0,0) | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/clock_0 | \PWM_1:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 2.240
macrocell6 | U(0,0) | 1 | \PWM_1:PWMUDB:status_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : Clock_1 : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\PWM_1:PWMUDB:status_1\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_1 | 1.500 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell7 | U(0,0) | 1 | \PWM_1:PWMUDB:status_1\ | \PWM_1:PWMUDB:status_1\/clock_0 | \PWM_1:PWMUDB:status_1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_1\ | \PWM_1:PWMUDB:status_1\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_1 | 2.250
statusicell1 | U(0,0) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 1.509 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell6 | U(0,0) | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/clock_0 | \PWM_1:PWMUDB:status_0\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 2.259
statusicell1 | U(0,0) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare2\/q | \PWM_1:PWMUDB:status_1\/main_0 | 3.474 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell5 | U(0,0) | 1 | \PWM_1:PWMUDB:prevCompare2\ | \PWM_1:PWMUDB:prevCompare2\/clock_0 | \PWM_1:PWMUDB:prevCompare2\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare2\ | \PWM_1:PWMUDB:prevCompare2\/q | \PWM_1:PWMUDB:status_1\/main_0 | 2.224
macrocell7 | U(0,0) | 1 | \PWM_1:PWMUDB:status_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 3.490 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(0,0) | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/clock_0 | \PWM_1:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 2.240
macrocell6 | U(0,0) | 1 | \PWM_1:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 4.061 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 2.811
macrocell8 | U(0,0) | 1 | Net_5269 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 4.070 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 2.820
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 4.309 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell2 | U(0,0) | 1 | \PWM_1:PWMUDB:genblk1:ctrlreg\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/clock | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | 2.040
Route |  | 1 | \PWM_1:PWMUDB:control_7\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 2.269
macrocell3 | U(0,0) | 1 | \PWM_1:PWMUDB:runmode_enable\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 5.658 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 3.130
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 2.528
macrocell4 | U(0,0) | 1 | \PWM_1:PWMUDB:prevCompare1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 5.658 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 3.130
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 2.528
macrocell6 | U(0,0) | 1 | \PWM_1:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 5.666 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,0) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 3.130
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 2.536
macrocell8 | U(0,0) | 1 | Net_5269 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Clock To Output Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
Net_5269/q | P1_6(0)_PAD | 27.248
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell8 | U(0,0) | 1 | Net_5269 | Net_5269/clock_0 | Net_5269/q | 1.250
Route |  | 1 | Net_5269 | Net_5269/q | Net_3983/main_1 | 2.236
macrocell1 | U(1,0) | 1 | Net_3983 | Net_3983/main_1 | Net_3983/q | 3.350
Route |  | 1 | Net_3983 | Net_3983/q | P1_6(0)/pin_input | 5.322
iocell2 | P1[6] | 1 | P1_6(0) | P1_6(0)/pin_input | P1_6(0)/pad_out | 15.090
Route |  | 1 | P1_6(0)_PAD | P1_6(0)/pad_out | P1_6(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

+ CyHFCLK

Source | Destination | Delay (ns)
--- | --- | ---
\Control_Reg_1:Sync:ctrl_reg\/control_0 | P1_6(0)_PAD | 28.601
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(1,0) | 1 | \Control_Reg_1:Sync:ctrl_reg\ | \Control_Reg_1:Sync:ctrl_reg\/busclk | \Control_Reg_1:Sync:ctrl_reg\/control_0 | 2.580
Route |  | 1 | Net_5057 | \Control_Reg_1:Sync:ctrl_reg\/control_0 | Net_3983/main_0 | 2.259
macrocell1 | U(1,0) | 1 | Net_3983 | Net_3983/main_0 | Net_3983/q | 3.350
Route |  | 1 | Net_3983 | Net_3983/q | P1_6(0)/pin_input | 5.322
iocell2 | P1[6] | 1 | P1_6(0) | P1_6(0)/pin_input | P1_6(0)/pad_out | 15.090
Route |  | 1 | P1_6(0)_PAD | P1_6(0)/pad_out | P1_6(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000