# Static Timing Analysis

Project : | UART_RxTx01
Build Time : | 06/21/18 21:43:15
Device : | CY8C5888LTI-LP097
Temperature : | -40C - 85/125C
VDDA : | 5.50
VDDABUF : | 5.50
VDDD : | 5.50
VDDIO0 : | 5.50
VDDIO1 : | 5.50
VDDIO2 : | 5.50
VDDIO3 : | 5.50
VUSB : | 5.50
Voltage : | 5.5

Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CyBUS_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | 61.278 MHz |
UART_1_IntClock | CyMASTER_CLK | 307.692 kHz | 307.692 kHz | 51.940 MHz |
Clock_1 | CyMASTER_CLK | 77.922 kHz | 77.922 kHz | 88.921 MHz |
CyPLL_OUT | CyPLL_OUT | 24.000 MHz | 24.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : Clock_1 : Positive edge(Required Frequency 77.9221 kHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 77.9221 kHz)
Path Delay Requirement : 12833.3ns(77.9221 kHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 88.921 MHz | 11.246 | 12822.087 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 2.290
Route |  | 1 | \PWM_1:PWMUDB:tc_i\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:status_2\/main_1 | 2.791
macrocell10 | U(1,2) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_1 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.315
statusicell3 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | SETUP | 0.500
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 89.750 MHz | 11.142 | 12822.191 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 2.290
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 2.792
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | SETUP | 6.060
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 97.210 MHz | 10.287 | 12823.046 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell27 | U(1,2) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:status_2\/main_0 | 2.872
macrocell10 | U(1,2) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_0 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.315
statusicell3 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | SETUP | 0.500
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 98.135 MHz | 10.190 | 12823.143 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell27 | U(1,2) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 2.880
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | SETUP | 6.060
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 120.294 MHz | 8.313 | 12825.020 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 2.510
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 2.293
macrocell28 | U(1,2) | 1 | \PWM_1:PWMUDB:prevCompare1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 120.294 MHz | 8.313 | 12825.020 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 2.510
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 2.293
macrocell30 | U(1,2) | 1 | \PWM_1:PWMUDB:status_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 120.294 MHz | 8.313 | 12825.020 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 2.510
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 2.293
macrocell32 | U(1,2) | 1 | Net_5269 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 130.976 MHz | 7.635 | 12825.698 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell27 | U(1,2) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 2.875
macrocell32 | U(1,2) | 1 | Net_5269 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare2\/q | \PWM_1:PWMUDB:status_1\/main_0 | 141.804 MHz | 7.052 | 12826.281 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell29 | U(1,2) | 1 | \PWM_1:PWMUDB:prevCompare2\ | \PWM_1:PWMUDB:prevCompare2\/clock_0 | \PWM_1:PWMUDB:prevCompare2\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare2\ | \PWM_1:PWMUDB:prevCompare2\/q | \PWM_1:PWMUDB:status_1\/main_0 | 2.292
macrocell31 | U(1,2) | 1 | \PWM_1:PWMUDB:status_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 141.844 MHz | 7.050 | 12826.283 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell28 | U(1,2) | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/clock_0 | \PWM_1:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 2.290
macrocell30 | U(1,2) | 1 | \PWM_1:PWMUDB:status_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : CyBUS_CLK : Positive edge(Required Frequency 24 MHz)
+ Destination Clock : UART_1_IntClock : Positive edge(Required Frequency 307.692 kHz)
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
Rx_1(0)/fb | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 61.278 MHz | 16.319 | 25.348 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_postpoll\/main_1 | 5.262
macrocell7 | U(0,0) | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/main_1 | \UART_1:BUART:rx_postpoll\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 2.228
datapathcell3 | U(0,0) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ |  | SETUP | 3.470
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 86.580 MHz | 11.550 | 30.117 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 6.031
macrocell24 | U(0,1) | 1 | \UART_1:BUART:pollcount_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 86.730 MHz | 11.530 | 30.137 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 6.011
macrocell23 | U(0,1) | 1 | \UART_1:BUART:pollcount_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_last\/main_0 | 86.730 MHz | 11.530 | 30.137 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_last\/main_0 | 6.011
macrocell26 | U(0,1) | 1 | \UART_1:BUART:rx_last\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 92.756 MHz | 10.781 | 30.886 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 5.262
macrocell17 | U(0,0) | 1 | \UART_1:BUART:rx_state_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 92.825 MHz | 10.773 | 30.894 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 5.254
macrocell20 | U(0,0) | 1 | \UART_1:BUART:rx_state_2\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 92.825 MHz | 10.773 | 30.894 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 5.254
macrocell25 | U(0,0) | 1 | \UART_1:BUART:rx_status_3\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : UART_1_IntClock : Positive edge(Required Frequency 307.692 kHz)
+ Destination Clock : UART_1_IntClock : Positive edge(Required Frequency 307.692 kHz)
Path Delay Requirement : 3250ns(307.692 kHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\UART_1:BUART:tx_state_1\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 51.940 MHz | 19.253 | 3230.747 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell12 | U(1,1) | 1 | \UART_1:BUART:tx_state_1\ | \UART_1:BUART:tx_state_1\/clock_0 | \UART_1:BUART:tx_state_1\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_1\ | \UART_1:BUART:tx_state_1\/q | \UART_1:BUART:counter_load_not\/main_0 | 3.986
macrocell3 | U(1,2) | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/main_0 | \UART_1:BUART:counter_load_not\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 4.477
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |  | SETUP | 6.190
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_state_2\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 52.860 MHz | 18.918 | 3231.082 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell14 | U(1,1) | 1 | \UART_1:BUART:tx_state_2\ | \UART_1:BUART:tx_state_2\/clock_0 | \UART_1:BUART:tx_state_2\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_2\ | \UART_1:BUART:tx_state_2\/q | \UART_1:BUART:counter_load_not\/main_3 | 3.651
macrocell3 | U(1,2) | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/main_3 | \UART_1:BUART:counter_load_not\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 4.477
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |  | SETUP | 6.190
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_state_0\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 53.345 MHz | 18.746 | 3231.254 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell13 | U(0,2) | 1 | \UART_1:BUART:tx_state_0\ | \UART_1:BUART:tx_state_0\/clock_0 | \UART_1:BUART:tx_state_0\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_state_0\ | \UART_1:BUART:tx_state_0\/q | \UART_1:BUART:counter_load_not\/main_1 | 3.479
macrocell3 | U(1,2) | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/main_1 | \UART_1:BUART:counter_load_not\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 4.477
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |  | SETUP | 6.190
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 54.591 MHz | 18.318 | 3231.682 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | 0.190
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | \UART_1:BUART:counter_load_not\/main_2 | 4.111
macrocell3 | U(1,2) | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/main_2 | \UART_1:BUART:counter_load_not\/q | 3.350
Route |  | 1 | \UART_1:BUART:counter_load_not\ | \UART_1:BUART:counter_load_not\/q | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 | 4.477
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |  | SETUP | 6.190
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:rx_state_0\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 60.310 MHz | 16.581 | 3233.419 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell17 | U(0,0) | 1 | \UART_1:BUART:rx_state_0\ | \UART_1:BUART:rx_state_0\/clock_0 | \UART_1:BUART:rx_state_0\/q | 1.250
Route |  | 1 | \UART_1:BUART:rx_state_0\ | \UART_1:BUART:rx_state_0\/q | \UART_1:BUART:rx_counter_load\/main_1 | 3.752
macrocell6 | U(0,1) | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/main_1 | \UART_1:BUART:rx_counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 2.869
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:rx_state_2\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 60.861 MHz | 16.431 | 3233.569 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell20 | U(0,0) | 1 | \UART_1:BUART:rx_state_2\ | \UART_1:BUART:rx_state_2\/clock_0 | \UART_1:BUART:rx_state_2\/q | 1.250
Route |  | 1 | \UART_1:BUART:rx_state_2\ | \UART_1:BUART:rx_state_2\/q | \UART_1:BUART:rx_counter_load\/main_3 | 3.602
macrocell6 | U(0,1) | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/main_3 | \UART_1:BUART:rx_counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 2.869
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:rx_state_3\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 61.451 MHz | 16.273 | 3233.727 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell19 | U(0,0) | 1 | \UART_1:BUART:rx_state_3\ | \UART_1:BUART:rx_state_3\/clock_0 | \UART_1:BUART:rx_state_3\/q | 1.250
Route |  | 1 | \UART_1:BUART:rx_state_3\ | \UART_1:BUART:rx_state_3\/q | \UART_1:BUART:rx_counter_load\/main_2 | 3.444
macrocell6 | U(0,1) | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/main_2 | \UART_1:BUART:rx_counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 2.869
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 64.679 MHz | 15.461 | 3234.539 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell16 | U(1,1) | 1 | \UART_1:BUART:tx_ctrl_mark_last\ | \UART_1:BUART:tx_ctrl_mark_last\/clock_0 | \UART_1:BUART:tx_ctrl_mark_last\/q | 1.250
Route |  | 1 | \UART_1:BUART:tx_ctrl_mark_last\ | \UART_1:BUART:tx_ctrl_mark_last\/q | \UART_1:BUART:rx_counter_load\/main_0 | 2.632
macrocell6 | U(0,1) | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/main_0 | \UART_1:BUART:rx_counter_load\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_counter_load\ | \UART_1:BUART:rx_counter_load\/q | \UART_1:BUART:sRX:RxBitCounter\/load | 2.869
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ |  | SETUP | 5.360
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:pollcount_0\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 67.760 MHz | 14.758 | 3235.242 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell24 | U(0,1) | 1 | \UART_1:BUART:pollcount_0\ | \UART_1:BUART:pollcount_0\/clock_0 | \UART_1:BUART:pollcount_0\/q | 1.250
Route |  | 1 | \UART_1:BUART:pollcount_0\ | \UART_1:BUART:pollcount_0\/q | \UART_1:BUART:rx_postpoll\/main_2 | 4.460
macrocell7 | U(0,0) | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/main_2 | \UART_1:BUART:rx_postpoll\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 2.228
datapathcell3 | U(0,0) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ |  | SETUP | 3.470
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:pollcount_1\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 69.522 MHz | 14.384 | 3235.616 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell23 | U(0,1) | 1 | \UART_1:BUART:pollcount_1\ | \UART_1:BUART:pollcount_1\/clock_0 | \UART_1:BUART:pollcount_1\/q | 1.250
Route |  | 1 | \UART_1:BUART:pollcount_1\ | \UART_1:BUART:pollcount_1\/q | \UART_1:BUART:rx_postpoll\/main_0 | 4.086
macrocell7 | U(0,0) | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/main_0 | \UART_1:BUART:rx_postpoll\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 2.228
datapathcell3 | U(0,0) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ |  | SETUP | 3.470
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : Clock_1 : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 1.545 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell30 | U(1,2) | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/clock_0 | \PWM_1:PWMUDB:status_0\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 2.295
statusicell3 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:status_1\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_1 | 1.563 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell31 | U(1,2) | 1 | \PWM_1:PWMUDB:status_1\ | \PWM_1:PWMUDB:status_1\/clock_0 | \PWM_1:PWMUDB:status_1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_1\ | \PWM_1:PWMUDB:status_1\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_1 | 2.313
statusicell3 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 2.689 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell2 | U(1,2) | 1 | \PWM_1:PWMUDB:genblk1:ctrlreg\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/clock | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | 0.360
Route |  | 1 | \PWM_1:PWMUDB:control_7\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 2.329
macrocell27 | U(1,2) | 1 | \PWM_1:PWMUDB:runmode_enable\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 3.073 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 0.780
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 2.293
macrocell28 | U(1,2) | 1 | \PWM_1:PWMUDB:prevCompare1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 3.073 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 0.780
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 2.293
macrocell30 | U(1,2) | 1 | \PWM_1:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 3.073 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 0.780
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_5269/main_1 | 2.293
macrocell32 | U(1,2) | 1 | Net_5269 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 3.540 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell28 | U(1,2) | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/clock_0 | \PWM_1:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 2.290
macrocell30 | U(1,2) | 1 | \PWM_1:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare2\/q | \PWM_1:PWMUDB:status_1\/main_0 | 3.542 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell29 | U(1,2) | 1 | \PWM_1:PWMUDB:prevCompare2\ | \PWM_1:PWMUDB:prevCompare2\/clock_0 | \PWM_1:PWMUDB:prevCompare2\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare2\ | \PWM_1:PWMUDB:prevCompare2\/q | \PWM_1:PWMUDB:status_1\/main_0 | 2.292
macrocell31 | U(1,2) | 1 | \PWM_1:PWMUDB:status_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 4.125 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell27 | U(1,2) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | Net_5269/main_0 | 2.875
macrocell32 | U(1,2) | 1 | Net_5269 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 4.130 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell27 | U(1,2) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 2.880
datapathcell4 | U(1,2) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : CyBUS_CLK : Positive edge
+ Destination Clock : UART_1_IntClock : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
Rx_1(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 7.263 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_state_2\/main_8 | 5.254
macrocell20 | U(0,0) | 1 | \UART_1:BUART:rx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 7.263 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_status_3\/main_6 | 5.254
macrocell25 | U(0,0) | 1 | \UART_1:BUART:rx_status_3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 7.271 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_state_0\/main_9 | 5.262
macrocell17 | U(0,0) | 1 | \UART_1:BUART:rx_state_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 8.020 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:pollcount_1\/main_3 | 6.011
macrocell23 | U(0,1) | 1 | \UART_1:BUART:pollcount_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:rx_last\/main_0 | 8.020 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_last\/main_0 | 6.011
macrocell26 | U(0,1) | 1 | \UART_1:BUART:rx_last\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 8.040 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:pollcount_0\/main_2 | 6.031
macrocell24 | U(0,1) | 1 | \UART_1:BUART:pollcount_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Rx_1(0)/fb | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 12.849 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell3 | P12[6] | 1 | Rx_1(0) | Rx_1(0)/in_clock | Rx_1(0)/fb | 2.009
Route |  | 1 | Net_5416 | Rx_1(0)/fb | \UART_1:BUART:rx_postpoll\/main_1 | 5.262
macrocell7 | U(0,0) | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/main_1 | \UART_1:BUART:rx_postpoll\/q | 3.350
Route |  | 1 | \UART_1:BUART:rx_postpoll\ | \UART_1:BUART:rx_postpoll\/q | \UART_1:BUART:sRX:RxShifter:u0\/route_si | 2.228
datapathcell3 | U(0,0) | 1 | \UART_1:BUART:sRX:RxShifter:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : UART_1_IntClock : Positive edge
+ Destination Clock : UART_1_IntClock : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\UART_1:BUART:rx_status_3\/q | \UART_1:BUART:sRX:RxSts\/status_3 | 1.511 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell25 | U(0,0) | 1 | \UART_1:BUART:rx_status_3\ | \UART_1:BUART:rx_status_3\/clock_0 | \UART_1:BUART:rx_status_3\/q | 1.250
Route |  | 1 | \UART_1:BUART:rx_status_3\ | \UART_1:BUART:rx_status_3\/q | \UART_1:BUART:sRX:RxSts\/status_3 | 2.261
statusicell2 | U(1,0) | 1 | \UART_1:BUART:sRX:RxSts\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | \UART_1:BUART:tx_state_2\/main_4 | 2.779 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | 0.190
Route |  | 1 | \UART_1:BUART:tx_counter_dp\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | \UART_1:BUART:tx_state_2\/main_4 | 2.589
macrocell14 | U(1,1) | 1 | \UART_1:BUART:tx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | \UART_1:BUART:txn\/main_5 | 2.793 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | 0.190
Route |  | 1 | \UART_1:BUART:tx_counter_dp\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | \UART_1:BUART:txn\/main_5 | 2.603
macrocell11 | U(1,1) | 1 | \UART_1:BUART:txn\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | \UART_1:BUART:tx_state_1\/main_4 | 2.793 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | 0.190
Route |  | 1 | \UART_1:BUART:tx_counter_dp\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg | \UART_1:BUART:tx_state_1\/main_4 | 2.603
macrocell12 | U(1,1) | 1 | \UART_1:BUART:tx_state_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 3.125 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | 0.190
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 | 2.935
datapathcell1 | U(0,1) | 1 | \UART_1:BUART:sTX:TxShifter:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_load_fifo\/main_7 | 3.171 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_4 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_4\ | \UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_load_fifo\/main_7 | 2.551
macrocell18 | U(0,0) | 1 | \UART_1:BUART:rx_load_fifo\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_state_2\/main_7 | 3.171 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_4 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_4\ | \UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_state_2\/main_7 | 2.551
macrocell20 | U(0,0) | 1 | \UART_1:BUART:rx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_state_0\/main_7 | 3.178 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_4 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_4\ | \UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_state_0\/main_7 | 2.558
macrocell17 | U(0,0) | 1 | \UART_1:BUART:rx_state_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_state_3\/main_7 | 3.178 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
count7cell | U(0,0) | 1 | \UART_1:BUART:sRX:RxBitCounter\ | \UART_1:BUART:sRX:RxBitCounter\/clock | \UART_1:BUART:sRX:RxBitCounter\/count_4 | 0.620
Route |  | 1 | \UART_1:BUART:rx_count_4\ | \UART_1:BUART:sRX:RxBitCounter\/count_4 | \UART_1:BUART:rx_state_3\/main_7 | 2.558
macrocell19 | U(0,0) | 1 | \UART_1:BUART:rx_state_3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | \UART_1:BUART:tx_state_2\/main_2 | 3.257 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | 0.190
Route |  | 1 | \UART_1:BUART:tx_bitclk_enable_pre\ | \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg | \UART_1:BUART:tx_state_2\/main_2 | 3.067
macrocell14 | U(1,1) | 1 | \UART_1:BUART:tx_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Clock To Output Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
Net_5269/q | P2_1(0)_PAD | 29.533
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell32 | U(1,2) | 1 | Net_5269 | Net_5269/clock_0 | Net_5269/q | 1.250
Route |  | 1 | Net_5269 | Net_5269/q | Net_3983/main_1 | 2.302
macrocell1 | U(0,2) | 1 | Net_3983 | Net_3983/main_1 | Net_3983/q | 3.350
Route |  | 1 | Net_3983 | Net_3983/q | P2_1(0)/pin_input | 6.740
iocell2 | P2[1] | 1 | P2_1(0) | P2_1(0)/pin_input | P2_1(0)/pad_out | 15.891
Route |  | 1 | P2_1(0)_PAD | P2_1(0)/pad_out | P2_1(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

+ CyBUS_CLK

Source | Destination | Delay (ns)
--- | --- | ---
\Control_Reg_1:Sync:ctrl_reg\/control_0 | P2_1(0)_PAD | 30.339
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,2) | 1 | \Control_Reg_1:Sync:ctrl_reg\ | \Control_Reg_1:Sync:ctrl_reg\/busclk | \Control_Reg_1:Sync:ctrl_reg\/control_0 | 2.050
Route |  | 1 | Net_5057 | \Control_Reg_1:Sync:ctrl_reg\/control_0 | Net_3983/main_0 | 2.308
macrocell1 | U(0,2) | 1 | Net_3983 | Net_3983/main_0 | Net_3983/q | 3.350
Route |  | 1 | Net_3983 | Net_3983/q | P2_1(0)/pin_input | 6.740
iocell2 | P2[1] | 1 | P2_1(0) | P2_1(0)/pin_input | P2_1(0)/pad_out | 15.891
Route |  | 1 | P2_1(0)_PAD | P2_1(0)/pad_out | P2_1(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

+ UART_1_IntClock

Source | Destination | Delay (ns)
--- | --- | ---
\UART_1:BUART:txn\/q | Tx_1(0)_PAD | 31.559
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell11 | U(1,1) | 1 | \UART_1:BUART:txn\ | \UART_1:BUART:txn\/clock_0 | \UART_1:BUART:txn\/q | 1.250
Route |  | 1 | \UART_1:BUART:txn\ | \UART_1:BUART:txn\/q | Net_5411/main_0 | 3.379
macrocell2 | U(0,2) | 1 | Net_5411 | Net_5411/main_0 | Net_5411/q | 3.350
Route |  | 1 | Net_5411 | Net_5411/q | Tx_1(0)/pin_input | 6.613
iocell4 | P12[7] | 1 | Tx_1(0) | Tx_1(0)/pin_input | Tx_1(0)/pad_out | 16.967
Route |  | 1 | Tx_1(0)_PAD | Tx_1(0)/pad_out | Tx_1(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000