                save
                listing off   ; kein Listing über diesen File

;****************************************************************************
;*                                                                          *
;*   AS 1.41 - Datei REGMSP.INC von Alfred Arnold                           *
;*   					 			            *
;*   Sinn : enthält Makro- und Registerdefinitionen für den MSP430          *
;* 									    *
;*   letzte Änderungen : 2002-01-11                                         *
;*                       2010/2011 erweitert von Matthias Koch              *
;*                                                                          *
;****************************************************************************

                ifndef  regmspinc      ; verhindert Mehrfacheinbindung

regmspinc       equ     1

                if      (MOMCPUNAME<>"MSP430")
                 fatal  "Falscher Prozessortyp eingestellt: nur MSP430 erlaubt!"
		endif

                if      MOMPASS=1
                 message "MSP430-Register+Befehlsdefinitionen (C) 1996 Alfred Arnold"
		endif

;----------------------------------------------------------------------------
; Arithmetik

adc             macro   op
                addc.attribute #0,op
                endm

dadc            macro   op
                dadd.attribute #0,op
                endm

dec             macro   op
                sub.attribute #1,op
                endm

decd            macro   op
                sub.attribute #2,op
                endm

inc             macro   op
                add.attribute #1,op
                endm

incd            macro   op
                add.attribute #2,op
                endm

sbc             macro   op
                subc.attribute #0,op
                endm

;----------------------------------------------------------------------------
; Logik

inv             macro   op
                xor.attribute #-1,op
                endm

rla             macro   op
                add.attribute op,op
                endm

rlc             macro   op
                addc.attribute op,op
                endm

;----------------------------------------------------------------------------
; Daten bewegen ;-)

clr             macro   op
                mov.attribute #0,op
                endm

clrc            macro
                bic     #1,sr
                endm

clrn            macro
                bic     #4,sr
                endm

clrz            macro
                bic     #2,sr
                endm

pop             macro   op         ; Muss hier noch ein Atribut anbringen ! Kann auch Bytes zurückladen...
                mov.attribute     @sp+,op
                endm

setc            macro
                bis     #1,sr
                endm

setn            macro
                bis     #4,sr
                endm

setz            macro
                bis     #2,sr
                endm

tst             macro   op
                cmp.attribute #0,op
                endm

;----------------------------------------------------------------------------
; Sprungbefehle

br              macro   op
                mov     op,pc
                endm

dint            macro
                bic     #8,sr
                endm

eint            macro
                bis     #8,sr
                endm

nop             macro                  ; mov #0, r3
                .word   04303h         ; den symbolischen Befehl würde AS zurückweisen
                endm

nop2            macro                  ; 1 Word, 2 Takte
                jmp $+2
                endm

ret             macro
                mov     @sp+,pc
                endm

jlo		macro	label
		jnc	label
		endm

jhs		macro	label
		jc	label
		endm

jeq		macro	label
		jz	label
		endm


;----------------------------------------------------------------------------
; General Memory Layout
; ----------------------
;
; 0000 - 000f : Special Function Registers
; 0010 - 00ff : 8bit Peripheral Modules
; 0100 - 01ff : 16bit Peripheral Modules
; 0200 - .... : RAM Memory
; .... - ffdf : Flash Memory
; ffe0 - ffff : Interrupt Vector Table
;
;----------------------------------------------------------------------------

;----------------------------------------------------------------------------
; Special Function Register of MSP430x1xx Family, Byte Access

IE1             equ     000h            ; Interrupt Enable
IE2             equ     001h
IFG1            equ     002h            ; Interrupt Flag
IFG2            equ     003h
ME1             equ     004h            ; Modul Enable
ME2             equ     005h

;----------------------------------------------------------------------------
; Flags im Statusregister

C             equ 0001h
Z             equ 0002h
N             equ 0004h
V             equ 0100h
GIE           equ 0008h
CPUOFF        equ 0010h
OSCOFF        equ 0020h
SCG0          equ 0040h
SCG1          equ 0080h

;----------------------------------------------------------------------------
; Low-Power-Mode Bitmuster

LPM0          equ CPUOFF
LPM1          equ SCG0 + CPUOFF
LPM2          equ SCG1 + CPUOFF
LPM3          equ SCG1 + SCG0 + CPUOFF
LPM4          equ SCG1 + SCG0 + OSCOFF + CPUOFF

;----------------------------------------------------------------------------
; Digital I/O, Byte Access

P1IN		equ	020h		; Input Register
P1OUT		equ	021h		; Output Register
P1DIR		equ	022h		; Direction Register
P1IFG		equ	023h		; Interrupt Flags
P1IES		equ	024h		; Interrupt Edge select
P1IE		equ	025h		; Interrupt enable
P1SEL		equ	026h		; Function select
P1SEL2          equ 041h
P1REN           equ     027h            ; Ziehwiderstand aktivieren

P2IN		equ	028h		; Input Register
P2OUT		equ	029h		; Output Register
P2DIR		equ	02Ah		; Direction Register
P2IFG		equ	02Bh		; Interrupt Flags
P2IES		equ	02Ch		; Interrupt Edge select
P2IE		equ	02Dh		; Interrupt enable
P2SEL		equ	02Eh		; Function select
P2SEL2          equ 042h
P2REN           equ     02Fh            ; Resistor enable

P3IN            equ     018h            ; Input Register
P3OUT           equ     019h            ; Output Register
P3DIR           equ     01Ah            ; Direction Register
P3SEL           equ     01Bh            ; Function select
P3REN           equ     010h            ; Ziehwiderstand aktivieren

P4IN            equ     01Ch            ; Input Register
P4OUT           equ     01Dh            ; Output Register
P4DIR           equ     01Eh            ; Direction Register
P4SEL           equ     01Fh            ; Function select
P4REN           equ     011h            ; Ziehwiderstand aktivieren

;----------------------------------------------------------------------------
; Watchdog Timer
;----------------------------------------------------------------------------
; Watchdog/Timer, Word Access
WDTCTL          equ     0120h

; INTERRUPT CONTROL
; These two bits are defined in the Special Function Registers
WDTIE         equ  01h
WDTIFG        equ  01h

; Konstanten für WDTCTL
WDTIS0        equ  0001h
WDTIS1        equ  0002h
WDTSSEL       equ  0004h
WDTCNTCL      equ  0008h
WDTTMSEL      equ  0010h
WDTNMI        equ  0020h
WDTNMIES      equ  0040h
WDTHOLD       equ  0080h
WDTPW         equ  5A00h

; WDT is clocked by fACLK (assumed 32KHz)

WDT_ADLY_1000 equ  WDTPW + WDTTMSEL + WDTCNTCL + WDTSSEL                    ; 1000ms
WDT_ADLY_250  equ  WDTPW + WDTTMSEL + WDTCNTCL + WDTSSEL + WDTIS0           ; 250ms
WDT_ADLY_16   equ  WDTPW + WDTTMSEL + WDTCNTCL + WDTSSEL + WDTIS1           ; 16ms
WDT_ADLY_1_9  equ  WDTPW + WDTTMSEL + WDTCNTCL + WDTSSEL + WDTIS1 + WDTIS0  ; 1.9ms

;----------------------------------------------------------------------------
; Basic Clock Module
;----------------------------------------------------------------------------
; Basic Clock Registers, Byte Access

DCOCTL          equ     056h
BCSCTL1         equ     057h
BCSCTL2         equ     058h
BCSCTL3         equ     053h

  ;------------------------------------------------------------------------------
  ; Konstanten für DCOCTL
  ;------------------------------------------------------------------------------

MOD0          equ      001h   ; Modulation Bit 0
MOD1          equ      002h   ; Modulation Bit 1
MOD2          equ      004h   ; Modulation Bit 2
MOD3          equ      008h   ; Modulation Bit 3
MOD4          equ      010h   ; Modulation Bit 4

DCO0          equ      020h   ; DCO Select Bit 0
DCO1          equ      040h   ; DCO Select Bit 1
DCO2          equ      080h   ; DCO Select Bit 2


  ;------------------------------------------------------------------------------
  ; Konstanten für BSCSTL1
  ;------------------------------------------------------------------------------
XT2OFF  equ 128
XTS     equ  64

; ACLK Teiler
DIVA1 equ 20h
DIVA0 equ 10h

DIVA_0        equ 000h ; 00000000b  ; ACLK Divider 0: /1
DIVA_1        equ 010h ; 00010000b  ; ACLK Divider 1: /2
DIVA_2        equ 020h ; 00100000b  ; ACLK Divider 2: /4
DIVA_3        equ 030h ; 00110000b  ; ACLK Divider 3: /8

RSEL0         equ      001h   ; Resistor Select Bit 0
RSEL1         equ      002h   ; Resistor Select Bit 1
RSEL2         equ      004h   ; Resistor Select Bit 2

  ;------------------------------------------------------------------------------
  ; Konstanten für BSCSTL2
  ;------------------------------------------------------------------------------

SELM1 equ 128
SELM0 equ 64

SELM_0 equ 0        ; DCOCLK
SELM_1 equ 64       ; DCOCLK
SELM_2 equ 128      ; XT2CLK oder LFXT1CLK or VLOCLK, falls kein XT2 vorhanden 
SELM_3 equ 128+64   ; LFXT1CLK or VLOCLK

DIVM1 equ 32
DIVM0 equ 16

DIVM_0 equ 0        ; /1
DIVM_1 equ 16       ; /2
DIVM_2 equ 32       ; /4
DIVM_3 equ 32+16    ; /8

SELS equ 8

; SMCLK - Teiler
DIVS1 equ 4
DIVS0 equ 2

DIVS_0        equ 000b  ; /1
DIVS_1        equ 010b  ; /2
DIVS_2        equ 100b  ; /4
DIVS_3        equ 110b  ; /8

DCOR equ 1

  ;------------------------------------------------------------------------------
  ; Konstanten für BSCSTL3
  ;------------------------------------------------------------------------------
XT2S1  equ 128
XT2S0  equ 64

XT2S_0 equ 0         ; 0.4 - 1 MHZ crystal or resonator
XT2S_1 equ 64        ; 1 - 3 MHz
XT2S_2 equ 128       ; 3 - 16 MHz
XT2S_3 equ 128+64    ; Digital external 0.4 - 16 MHz clock source

LFXT1S1 equ 32
LFXT1S0 equ 16

                   ; XTS=0:                        / XTS=1:
LFXT1S_0 equ 0     ; 32768 Hz Crystal of LFXT1     / 0.4 - 1 MHZ crystal or resonator
LFXT1S_1 equ 16    ; Reserved                      / 1 - 3 MHz
LFXT1S_2 equ 32    ; VLOCLK                        / 3 - 16 MHz
LFXT1S_3 equ 32+16 ; Digital external clock source / 0.4 - 16MHz Digital external clock source

XCAP1 equ 8
XCAP0 equ 4

XCAP_0 equ 0       ; 1 pF
XCAP_1 equ 4       ; 6 pF
XCAP_2 equ 8       ; 10 pF
XCAP_3 equ 8+4     ; 12.5 pF

XT2OF equ 2        ; XT2 oscillator fault
LFXT1OF equ 1      ; XT1 oscillator fault

 ; Für Oszillator-Interrupt:
OFIE  equ 2 ; In IE1
OFIFG equ 2 ; In IFG1


; Kalibrationsbytes für verschiedene Frequenzen des DCO:
CALBC1_1MHZ  equ 010FFh;
CALDCO_1MHz  equ 010FEh;

CALBC1_8MHZ  equ 010FDh;
CALDCO_8MHz  equ 010FCh;

CALBC1_12MHZ equ 010FBh;
CALDCO_12MHz equ 010FAh;

CALBC1_16MHZ equ 010F9h;
CALDCO_16MHz equ 010F8h;

;----------------------------------------------------------------------------
; Timer A

;----------------------------------------------------------------------------
; Timer_A Registers, Word Access

TACTL           equ     0160h

CCTL0           equ     0162h
TACCTL0         equ     0162h

CCTL1           equ     0164h
TACCTL1         equ     0164h

CCTL2           equ     0166h
TACCTL2         equ     0166h

CCTL3           equ     0168h
TACCTL3         equ     0168h

CCTL4           equ     016Ah
TACCTL4         equ     016Ah

TAR             equ     0170h

CCR0            equ     0172h
TACCR0          equ     0172h

CCR1            equ     0174h
TACCR1          equ     0174h

CCR2            equ     0176h
TACCR2          equ     0176h

CCR3            equ     0178h
TACCR3          equ     0178h

CCR4            equ     017Ah
TACCR4          equ     017Ah

; Timer_A Interrupt Vector, Word Access
TAIV            equ     012Eh


TASSEL2         equ    0400h  ; unused        ; to distinguish from UART SSELx
TASSEL1         equ    0200h  ; Timer A clock source select 0
TASSEL0         equ    0100h  ; Timer A clock source select 1
ID1             equ    0080h  ; Timer A clock input devider 1
ID0             equ    0040h  ; Timer A clock input devider 0
MC1             equ    0020h  ; Timer A mode control 1
MC0             equ    0010h  ; Timer A mode control 0
TACLR           equ    0004h  ; Timer A counter clear
TAIE            equ    0002h  ; Timer A counter interrupt enable
TAIFG           equ    0001h  ; Timer A counter interrupt flag

MC_0            equ    (0<<4)  ; Timer A mode control: 0 - Stop
MC_1            equ    (1<<4)  ; Timer A mode control: 1 - Up to CCR0
MC_2            equ    (2<<4)  ; Timer A mode control: 2 - Continous up
MC_3            equ    (3<<4)  ; Timer A mode control: 3 - Up/Down
ID_0            equ    (0<<6)  ; Timer A input divider: 0 - /1
ID_1            equ    (1<<6)  ; Timer A input divider: 1 - /2
ID_2            equ    (2<<6)  ; Timer A input divider: 2 - /4
ID_3            equ    (3<<6)  ; Timer A input divider: 3 - /8
TASSEL_0        equ    (0<<8)  ; Timer A clock source select: 0 - TACLK
TASSEL_1        equ    (1<<8)  ; Timer A clock source select: 1 - ACLK 
TASSEL_2        equ    (2<<8)  ; Timer A clock source select: 2 - SMCLK
TASSEL_3        equ    (3<<8)  ; Timer A clock source select: 3 - INCLK

CM1             equ    8000h  ; Capture mode 1
CM0             equ    4000h  ; Capture mode 0
CCIS1           equ    2000h  ; Capture input select 1
CCIS0           equ    1000h  ; Capture input select 0
SCS             equ    0800h  ; Capture sychronize
SCCI            equ    0400h  ; Latched capture signal (read)
CAP             equ    0100h  ; Capture mode: 1 /Compare mode : 0
OUTMOD2         equ    0080h  ; Output mode 2
OUTMOD1         equ    0040h  ; Output mode 1
OUTMOD0         equ    0020h  ; Output mode 0
CCIE            equ    0010h  ; Capture/compare interrupt enable
CCI             equ    0008h  ; Capture input signal (read)
OUT             equ    0004h  ; PWM Output signal if output mode 0
COV             equ    0002h  ; Capture/compare overflow flag
CCIFG           equ    0001h  ; Capture/compare interrupt flag

OUTMOD_0        equ    (0<<5)  ; PWM output mode: 0 - output only
OUTMOD_1        equ    (1<<5)  ; PWM output mode: 1 - set
OUTMOD_2        equ    (2<<5)  ; PWM output mode: 2 - PWM toggle/reset
OUTMOD_3        equ    (3<<5)  ; PWM output mode: 3 - PWM set/reset
OUTMOD_4        equ    (4<<5)  ; PWM output mode: 4 - toggle
OUTMOD_5        equ    (5<<5)  ; PWM output mode: 5 - Reset
OUTMOD_6        equ    (6<<5)  ; PWM output mode: 6 - PWM toggle/set
OUTMOD_7        equ    (7<<5)  ; PWM output mode: 7 - PWM reset/set
CCIS_0          equ    (0<<12) ; Capture input select: 0 - CCIxA
CCIS_1          equ    (1<<12) ; Capture input select: 1 - CCIxB
CCIS_2          equ    (2<<12) ; Capture input select: 2 - GND
CCIS_3          equ    (3<<12) ; Capture input select: 3 - Vcc
CM_0            equ    (0<<14) ; Capture mode: 0 - disabled
CM_1            equ    (1<<14) ; Capture mode: 1 - pos. edge
CM_2            equ    (2<<14) ; Capture mode: 1 - neg. edge
CM_3            equ    (3<<14) ; Capture mode: 1 - both edges

;----------------------------------------------------------------------------
; Hardware Multiplier, Word Access

;MPY		equ	0130h		; Multiply unsigned
;MPYS		equ	0132h		; Multiply signed
;MAC		equ	0134h		; MPY+ACC
;MACS		equ	0136h		; MPYS+ACC
;OP2		equ	0138h		; Second Operand
;ResLo		equ	013Ah		; Result low word
;ResHi		equ	013Ch		; Result high word
;SumExt		equ	013Eh		; Sum extend

;----------------------------------------------------------------------------

                endif                   ; von IFDEF...
		restore                 ; wieder erlauben
  listing on