
Original work:
J1a processor and Swapforth by James Bowman

19. September 2015: Mecrisp-Ice 0.1

Equipped by Matthias Koch with:

* MSP430 style IO
* Ticks counter
* Inline optimisations
* Constant folding
* Load & Save from and to SPI flash with init mechanism
* More readable disassembler
* Dictionary structure insight

* Ledcomm
* IrDA example

22. September 2015: Mecrisp-Ice 0.2

* .s will not crash anymore on deep stacks
* Disassembler improved

27. September 2015: Mecrisp-Ice 0.3

* Clock speed increased to 48 MHz
* Added randombit and random which use clock jitter
  from a free running ring oscillator

29. February 2016: Mecrisp-Ice 0.4

* Minus opcode added to CPU
* Small speed improvements
* Ice Cream Machine emulates J1a and helps building the package in one step
* Removed tethered mode

07. March 2016: Mecrisp-Ice 0.5

* Single cycle io@
* Ticks counter overflow interrupt, $1FFE is vector. Place exit or a JMP opcode there.
* Added eint and dint
* Removed SB_Warmboot

20. April 2016: Mecrisp-Ice 0.6

* Fixed faulty logic for interrupts which happen in a memory fetch cycle.

23. April 2016: Mecrisp-Ice 0.7

* New binary image for HX8K !

  + Double amount of memory: 16 kb instead of 8 kb
  + Double stack depth: 32 elements each instead of 16
  + Barrel shifter for single cycle lshift rshift arshift
  + Single cycle multiplication
  + Fast opcodes for 1+ and 1-
  + rdepth
  + 8 LEDs instead of 5
  + Lots of gates free for experiments
  - 36 MHz only
  - No IrDA
  - Variable @ needs 2 instructions and 5 cycles instead of 1 instruction and 2 cycles

* Reentrant um* and do..loop for interrupt usage

* Larger address range made a different dictionary header structure necessary
  to still accomodate flags for foldability and immediate.

* Tidied up nucleus Forth source code

* Improved compatibility with Mecrisp for MSP430:

  * Initialised variables
  * LF only instead of CR+LF

05. June 2016, Mecrisp-Ice 0.8

* New target: Nandland Go board by Russell Merrick
* Timer can be set to any value now
* Improved interrupt handling, with dint and eint as opcodes
* Added eint?

10. July 2017, Mecrisp-Ice 0.9

* Squeezed a handful of gates out of all ports:
  This allows synthesis with recent Yosys 0.7 as in Debian Stretch.
* Added VGA example for Nandlang Go
* New target: Mystorm / Blackice board by Ken Boak

22. November 2017, Mecrisp-Ice 1.0

Just tidied up a few small things:

* A few flaws less in documentation
* Corrected timer set behaviour in "icecreammachine" emulators
* Saved two bytes in each of the Forth cores
* Updated the ARM core for Mystorm target to Mecrisp-Stellaris 2.3.9

07. January 2018, Mecrisp-Ice 1.1

* Exchanged UART to Clifford Wolfs implementation from
    https://github.com/cliffordwolf/picorv32/tree/master/picosoc
* Increased baudrate for Icestick and Nandland Go to 230400 baud
* Added HX8K -8kb and -12kb targets for experiments and simplified porting
* Fixed UNUSED
* A few flaws less in documentation

28. January 2018, Mecrisp-Ice 1.2

* Bugfix for string literals when interrupts are enabled

14. April 2018, Mecrisp-Ice 1.3

* Bugfix for ['] and [char]
* Contribution by Igor Mokos: Floating point library
* Contribution by Lawrie Griffiths: Port for Blackice II board

04. November 2018, Mecrisp-Ice 1.4

* Interrupt lock & reenable logic
* Improved processor core source for synthesis
* Restructured Verilog sources

