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Mecrisp-Ice - A conveniently enhanced fork of Swapforth by James Bowman

The original Swapforth and J1a processor implementation can be found here:
http://www.excamera.com/sphinx/article-j1a-swapforth.html

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This package contains a port for Altera/Intel MAX10 FPGAs,
initially for the "terasIC DE10-Lite" board featuring an 10M50DA FPGA.

It will not be available in the mainstream releases because it is not possible
to build this with open source tools.

A closed source proprietary installation of the vendor tools is necessary.
Go for the free (as in beer) "Quartus Prime Lite Edition", version 19.1.0.
Other versions might work, too.

For a glossary and other information, refer to the README in the mainstream
Mecrisp-Ice packages.

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Notes on porting:

The smallest possible member of this family to run Mecrisp-Ice is 10M04.

Watch out for differences between these variants:

SC: Single supply - compact features
SA: Single supply - analog and flash features with RSU option
DC: Dual supply - compact features
DF: Dual supply - flash features with RSU option
DA: Dual supply - analog and flash features with RSU option

The "C" compact ones do not have block RAM initialisation.
If you have no choice but to use a "compact features" member of the family,
you need to manually take care of block RAM initialisation using flash
blocks.

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To get a first grasp on how to conquer these chips, a few notes:

The closed source proprietary Quartus software tries to hide almost everything
from your and actively obfuscates some low-level source files.

The "Avalon Bus" is phantasy. It does not exist as hardware in MAX10 FPGAs.

The names of all hard IP block macros start with "fiftyfivenm_". Look for this
identifier in autogenerated source files to find the pieces where the rubber
meets the road.

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