
`default_nettype none // Simplifies finding typos

module top(
  input oscillator,

  output D1,
  output D2,
  output PORTC0,  // 0   1  Led West
  output PORTC1,  // 1   2  Led East
  output PORTC2,  // 2   4  Led South
  input  PORTC3,  // 3   8    Button 2
  output PORTC4,  // 4  16  Led Middle
  output PORTC5,  // 5  32  Led North
  input  PORTC6,  // 6  64    Button 1
  input  PORTC7   // 7 128    Button 3
);

  wire clk = oscillator; // Directly use the oscillator, no fancy PLL config

  reg [31:0] counter;

  always @(posedge clk) counter <= counter + 1;

  assign {PORTC5, PORTC4, PORTC2, PORTC1, PORTC0, D2, D1} = counter[27:21];

endmodule
