\ GD32VF103 Register Bitfield Definitions for Mecrisp-Stellaris Forth by Matthias Koch. 
\ bitfield.xsl takes STM32Fxx.svd, config.xml and produces bitfield.fs
\ Written by Terry Porter "terry@tjporter.com.au" 2016 - 2018 and released under the GPL V2.
\ Replace 'bis!' (set bit) with 'bic!' to CLEAR bit, 'bit@' to test bit etc.


\ ADC0_STAT (read-write)
: ADC0_STAT_STRC   %1 4 lshift ADC0_STAT bis! ;  \ ADC0_STAT_STRC    Start flag of regular channel group
: ADC0_STAT_STIC   %1 3 lshift ADC0_STAT bis! ;  \ ADC0_STAT_STIC    Start flag of inserted channel group
: ADC0_STAT_EOIC   %1 2 lshift ADC0_STAT bis! ;  \ ADC0_STAT_EOIC    End of inserted group conversion flag
: ADC0_STAT_EOC   %1 1 lshift ADC0_STAT bis! ;  \ ADC0_STAT_EOC    End of group conversion flag
: ADC0_STAT_WDE   %1 0 lshift ADC0_STAT bis! ;  \ ADC0_STAT_WDE    Analog watchdog event flag

\ ADC0_CTL0 (read-write)
: ADC0_CTL0_RWDEN   %1 23 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_RWDEN    Regular channel analog watchdog enable
: ADC0_CTL0_IWDEN   %1 22 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_IWDEN    Inserted channel analog watchdog  	 enable
: ADC0_CTL0_SYNCM   ( %XXXX -- ) 16 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_SYNCM    sync mode selection
: ADC0_CTL0_DISNUM   ( %XXX -- ) 13 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_DISNUM    Number of conversions in  	 discontinuous mode
: ADC0_CTL0_DISIC   %1 12 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_DISIC    Discontinuous mode on  	 inserted channels
: ADC0_CTL0_DISRC   %1 11 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_DISRC    Discontinuous mode on regular  channels
: ADC0_CTL0_ICA   %1 10 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_ICA    Inserted channel group convert  	 automatically
: ADC0_CTL0_WDSC   %1 9 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_WDSC    When in scan mode, analog watchdog 	 is effective on a single channel
: ADC0_CTL0_SM   %1 8 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_SM    Scan mode
: ADC0_CTL0_EOICIE   %1 7 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_EOICIE    Interrupt enable for EOIC
: ADC0_CTL0_WDEIE   %1 6 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_WDEIE    Interrupt enable for WDE
: ADC0_CTL0_EOCIE   %1 5 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_EOCIE    Interrupt enable for EOC
: ADC0_CTL0_WDCHSEL   ( %XXXXX -- ) 0 lshift ADC0_CTL0 bis! ;  \ ADC0_CTL0_WDCHSEL    Analog watchdog channel select

\ ADC0_CTL1 (read-write)
: ADC0_CTL1_TSVREN   %1 23 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_TSVREN    Channel 16 and 17 enable of ADC0
: ADC0_CTL1_SWRCST   %1 22 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_SWRCST    Start on regular channel
: ADC0_CTL1_SWICST   %1 21 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_SWICST    Start on inserted channel
: ADC0_CTL1_ETERC   %1 20 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_ETERC    External trigger enable for regular channel
: ADC0_CTL1_ETSRC   ( %XXX -- ) 17 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_ETSRC    External trigger select for regular channel
: ADC0_CTL1_ETEIC   %1 15 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_ETEIC    External trigger select for inserted channel
: ADC0_CTL1_ETSIC   ( %XXX -- ) 12 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_ETSIC    External trigger select for inserted channel
: ADC0_CTL1_DAL   %1 11 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_DAL    Data alignment
: ADC0_CTL1_DMA   %1 8 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_DMA    DMA request enable
: ADC0_CTL1_RSTCLB   %1 3 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_RSTCLB    Reset calibration
: ADC0_CTL1_CLB   %1 2 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_CLB    ADC calibration
: ADC0_CTL1_CTN   %1 1 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_CTN    Continuous mode
: ADC0_CTL1_ADCON   %1 0 lshift ADC0_CTL1 bis! ;  \ ADC0_CTL1_ADCON    ADC on

\ ADC0_SAMPT0 (read-write)
: ADC0_SAMPT0_SPT10   ( %XXX -- ) 0 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT10    Channel 10 sample time  selection
: ADC0_SAMPT0_SPT11   ( %XXX -- ) 3 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT11    Channel 11 sample time  selection
: ADC0_SAMPT0_SPT12   ( %XXX -- ) 6 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT12    Channel 12 sample time  selection
: ADC0_SAMPT0_SPT13   ( %XXX -- ) 9 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT13    Channel 13 sample time  selection
: ADC0_SAMPT0_SPT14   ( %XXX -- ) 12 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT14    Channel 14 sample time  selection
: ADC0_SAMPT0_SPT15   ( %XXX -- ) 15 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT15    Channel 15 sample time  selection
: ADC0_SAMPT0_SPT16   ( %XXX -- ) 18 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT16    Channel 16 sample time  selection
: ADC0_SAMPT0_SPT17   ( %XXX -- ) 21 lshift ADC0_SAMPT0 bis! ;  \ ADC0_SAMPT0_SPT17    Channel 17 sample time  selection

\ ADC0_SAMPT1 (read-write)
: ADC0_SAMPT1_SPT0   ( %XXX -- ) 0 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT0    Channel 0 sample time  selection
: ADC0_SAMPT1_SPT1   ( %XXX -- ) 3 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT1    Channel 1 sample time  selection
: ADC0_SAMPT1_SPT2   ( %XXX -- ) 6 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT2    Channel 2 sample time  selection
: ADC0_SAMPT1_SPT3   ( %XXX -- ) 9 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT3    Channel 3 sample time  selection
: ADC0_SAMPT1_SPT4   ( %XXX -- ) 12 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT4    Channel 4 sample time  selection
: ADC0_SAMPT1_SPT5   ( %XXX -- ) 15 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT5    Channel 5 sample time  selection
: ADC0_SAMPT1_SPT6   ( %XXX -- ) 18 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT6    Channel 6 sample time  selection
: ADC0_SAMPT1_SPT7   ( %XXX -- ) 21 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT7    Channel 7 sample time  selection
: ADC0_SAMPT1_SPT8   ( %XXX -- ) 24 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT8    Channel 8 sample time  selection
: ADC0_SAMPT1_SPT9   ( %XXX -- ) 27 lshift ADC0_SAMPT1 bis! ;  \ ADC0_SAMPT1_SPT9    Channel 9 sample time  selection

\ ADC0_IOFF0 (read-write)
: ADC0_IOFF0_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC0_IOFF0 bis! ;  \ ADC0_IOFF0_IOFF    Data offset for inserted channel  0

\ ADC0_IOFF1 (read-write)
: ADC0_IOFF1_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC0_IOFF1 bis! ;  \ ADC0_IOFF1_IOFF    Data offset for inserted channel  1

\ ADC0_IOFF2 (read-write)
: ADC0_IOFF2_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC0_IOFF2 bis! ;  \ ADC0_IOFF2_IOFF    Data offset for inserted channel  2

\ ADC0_IOFF3 (read-write)
: ADC0_IOFF3_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC0_IOFF3 bis! ;  \ ADC0_IOFF3_IOFF    Data offset for inserted channel  3

\ ADC0_WDHT (read-write)
: ADC0_WDHT_WDHT   ( %XXXXXXXXXXX -- ) 0 lshift ADC0_WDHT bis! ;  \ ADC0_WDHT_WDHT    Analog watchdog higher  threshold

\ ADC0_WDLT (read-write)
: ADC0_WDLT_WDLT   ( %XXXXXXXXXXX -- ) 0 lshift ADC0_WDLT bis! ;  \ ADC0_WDLT_WDLT    Analog watchdog lower  threshold

\ ADC0_RSQ0 (read-write)
: ADC0_RSQ0_RL   ( %XXXX -- ) 20 lshift ADC0_RSQ0 bis! ;  \ ADC0_RSQ0_RL    Regular channel group  length
: ADC0_RSQ0_RSQ15   ( %XXXXX -- ) 15 lshift ADC0_RSQ0 bis! ;  \ ADC0_RSQ0_RSQ15    16th conversion in regular  sequence
: ADC0_RSQ0_RSQ14   ( %XXXXX -- ) 10 lshift ADC0_RSQ0 bis! ;  \ ADC0_RSQ0_RSQ14    15th conversion in regular  sequence
: ADC0_RSQ0_RSQ13   ( %XXXXX -- ) 5 lshift ADC0_RSQ0 bis! ;  \ ADC0_RSQ0_RSQ13    14th conversion in regular  sequence
: ADC0_RSQ0_RSQ12   ( %XXXXX -- ) 0 lshift ADC0_RSQ0 bis! ;  \ ADC0_RSQ0_RSQ12    13th conversion in regular  sequence

\ ADC0_RSQ1 (read-write)
: ADC0_RSQ1_RSQ11   ( %XXXXX -- ) 25 lshift ADC0_RSQ1 bis! ;  \ ADC0_RSQ1_RSQ11    12th conversion in regular  sequence
: ADC0_RSQ1_RSQ10   ( %XXXXX -- ) 20 lshift ADC0_RSQ1 bis! ;  \ ADC0_RSQ1_RSQ10    11th conversion in regular  sequence
: ADC0_RSQ1_RSQ9   ( %XXXXX -- ) 15 lshift ADC0_RSQ1 bis! ;  \ ADC0_RSQ1_RSQ9    10th conversion in regular  sequence
: ADC0_RSQ1_RSQ8   ( %XXXXX -- ) 10 lshift ADC0_RSQ1 bis! ;  \ ADC0_RSQ1_RSQ8    9th conversion in regular  sequence
: ADC0_RSQ1_RSQ7   ( %XXXXX -- ) 5 lshift ADC0_RSQ1 bis! ;  \ ADC0_RSQ1_RSQ7    8th conversion in regular  sequence
: ADC0_RSQ1_RSQ6   ( %XXXXX -- ) 0 lshift ADC0_RSQ1 bis! ;  \ ADC0_RSQ1_RSQ6    7th conversion in regular  sequence

\ ADC0_RSQ2 (read-write)
: ADC0_RSQ2_RSQ5   ( %XXXXX -- ) 25 lshift ADC0_RSQ2 bis! ;  \ ADC0_RSQ2_RSQ5    6th conversion in regular  sequence
: ADC0_RSQ2_RSQ4   ( %XXXXX -- ) 20 lshift ADC0_RSQ2 bis! ;  \ ADC0_RSQ2_RSQ4    5th conversion in regular  sequence
: ADC0_RSQ2_RSQ3   ( %XXXXX -- ) 15 lshift ADC0_RSQ2 bis! ;  \ ADC0_RSQ2_RSQ3    4th conversion in regular  sequence
: ADC0_RSQ2_RSQ2   ( %XXXXX -- ) 10 lshift ADC0_RSQ2 bis! ;  \ ADC0_RSQ2_RSQ2    3rd conversion in regular  sequence
: ADC0_RSQ2_RSQ1   ( %XXXXX -- ) 5 lshift ADC0_RSQ2 bis! ;  \ ADC0_RSQ2_RSQ1    2nd conversion in regular  sequence
: ADC0_RSQ2_RSQ0   ( %XXXXX -- ) 0 lshift ADC0_RSQ2 bis! ;  \ ADC0_RSQ2_RSQ0    1st conversion in regular  sequence

\ ADC0_ISQ (read-write)
: ADC0_ISQ_IL   ( %XX -- ) 20 lshift ADC0_ISQ bis! ;  \ ADC0_ISQ_IL    Inserted channel group length
: ADC0_ISQ_ISQ3   ( %XXXXX -- ) 15 lshift ADC0_ISQ bis! ;  \ ADC0_ISQ_ISQ3    4th conversion in inserted  sequence
: ADC0_ISQ_ISQ2   ( %XXXXX -- ) 10 lshift ADC0_ISQ bis! ;  \ ADC0_ISQ_ISQ2    3rd conversion in inserted  sequence
: ADC0_ISQ_ISQ1   ( %XXXXX -- ) 5 lshift ADC0_ISQ bis! ;  \ ADC0_ISQ_ISQ1    2nd conversion in inserted  sequence
: ADC0_ISQ_ISQ0   ( %XXXXX -- ) 0 lshift ADC0_ISQ bis! ;  \ ADC0_ISQ_ISQ0    1st conversion in inserted  sequence

\ ADC0_IDATA0 (read-only)
: ADC0_IDATA0_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC0_IDATA0 bis! ;  \ ADC0_IDATA0_IDATAn    Inserted number n conversion data

\ ADC0_IDATA1 (read-only)
: ADC0_IDATA1_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC0_IDATA1 bis! ;  \ ADC0_IDATA1_IDATAn    Inserted number n conversion data

\ ADC0_IDATA2 (read-only)
: ADC0_IDATA2_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC0_IDATA2 bis! ;  \ ADC0_IDATA2_IDATAn    Inserted number n conversion data

\ ADC0_IDATA3 (read-only)
: ADC0_IDATA3_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC0_IDATA3 bis! ;  \ ADC0_IDATA3_IDATAn    Inserted number n conversion data

\ ADC0_RDATA (read-only)
: ADC0_RDATA_ADC1RDTR   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift ADC0_RDATA bis! ;  \ ADC0_RDATA_ADC1RDTR    ADC regular channel data
: ADC0_RDATA_RDATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC0_RDATA bis! ;  \ ADC0_RDATA_RDATA    Regular channel data

\ ADC0_OVSAMPCTL (read-write)
: ADC0_OVSAMPCTL_DRES   ( %XX -- ) 12 lshift ADC0_OVSAMPCTL bis! ;  \ ADC0_OVSAMPCTL_DRES    ADC resolution
: ADC0_OVSAMPCTL_TOVS   %1 9 lshift ADC0_OVSAMPCTL bis! ;  \ ADC0_OVSAMPCTL_TOVS    Triggered Oversampling
: ADC0_OVSAMPCTL_OVSS   ( %XXXX -- ) 5 lshift ADC0_OVSAMPCTL bis! ;  \ ADC0_OVSAMPCTL_OVSS    Oversampling shift
: ADC0_OVSAMPCTL_OVSR   ( %XXX -- ) 2 lshift ADC0_OVSAMPCTL bis! ;  \ ADC0_OVSAMPCTL_OVSR    Oversampling ratio
: ADC0_OVSAMPCTL_OVSEN   %1 0 lshift ADC0_OVSAMPCTL bis! ;  \ ADC0_OVSAMPCTL_OVSEN    Oversampler Enable

\ ADC1_STAT (read-write)
: ADC1_STAT_STRC   %1 4 lshift ADC1_STAT bis! ;  \ ADC1_STAT_STRC    Start flag of regular channel group
: ADC1_STAT_STIC   %1 3 lshift ADC1_STAT bis! ;  \ ADC1_STAT_STIC    Start flag of inserted channel group
: ADC1_STAT_EOIC   %1 2 lshift ADC1_STAT bis! ;  \ ADC1_STAT_EOIC    End of inserted group conversion flag
: ADC1_STAT_EOC   %1 1 lshift ADC1_STAT bis! ;  \ ADC1_STAT_EOC    End of group conversion flag
: ADC1_STAT_WDE   %1 0 lshift ADC1_STAT bis! ;  \ ADC1_STAT_WDE    Analog watchdog event flag

\ ADC1_CTL0 (read-write)
: ADC1_CTL0_RWDEN   %1 23 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_RWDEN    Regular channel analog watchdog  	 enable
: ADC1_CTL0_IWDEN   %1 22 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_IWDEN    Inserted channel analog watchdog  	 enable
: ADC1_CTL0_DISNUM   ( %XXX -- ) 13 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_DISNUM    Number of conversions in  	 discontinuous mode
: ADC1_CTL0_DISIC   %1 12 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_DISIC    Discontinuous mode on  	 inserted channels
: ADC1_CTL0_DISRC   %1 11 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_DISRC    Discontinuous mode on regular  channels
: ADC1_CTL0_ICA   %1 10 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_ICA    Inserted channel group convert  	 automatically
: ADC1_CTL0_WDSC   %1 9 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_WDSC    When in scan mode, analog watchdog 	 is effective on a single channel
: ADC1_CTL0_SM   %1 8 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_SM    Scan mode
: ADC1_CTL0_EOICIE   %1 7 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_EOICIE    Interrupt enable for EOIC
: ADC1_CTL0_WDEIE   %1 6 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_WDEIE    Interrupt enable for WDE
: ADC1_CTL0_EOCIE   %1 5 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_EOCIE    Interrupt enable for EOC
: ADC1_CTL0_WDCHSEL   ( %XXXXX -- ) 0 lshift ADC1_CTL0 bis! ;  \ ADC1_CTL0_WDCHSEL    Analog watchdog channel select

\ ADC1_CTL1 (read-write)
: ADC1_CTL1_SWRCST   %1 22 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_SWRCST    Start on regular channel
: ADC1_CTL1_SWICST   %1 21 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_SWICST    Start on inserted channel
: ADC1_CTL1_ETERC   %1 20 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_ETERC    External trigger enable for regular channel
: ADC1_CTL1_ETSRC   ( %XXX -- ) 17 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_ETSRC    External trigger select for regular channel
: ADC1_CTL1_ETEIC   %1 15 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_ETEIC    External trigger enable for inserted channel
: ADC1_CTL1_ETSIC   ( %XXX -- ) 12 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_ETSIC    External trigger select for inserted channel
: ADC1_CTL1_DAL   %1 11 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_DAL    Data alignment
: ADC1_CTL1_DMA   %1 8 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_DMA    DMA request enable
: ADC1_CTL1_RSTCLB   %1 3 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_RSTCLB    Reset calibration
: ADC1_CTL1_CLB   %1 2 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_CLB    ADC calibration
: ADC1_CTL1_CTN   %1 1 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_CTN    Continuous mode
: ADC1_CTL1_ADCON   %1 0 lshift ADC1_CTL1 bis! ;  \ ADC1_CTL1_ADCON    ADC on

\ ADC1_SAMPT0 (read-write)
: ADC1_SAMPT0_SPT10   ( %XXX -- ) 0 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT10    Channel 10 sample time  selection
: ADC1_SAMPT0_SPT11   ( %XXX -- ) 3 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT11    Channel 11 sample time  selection
: ADC1_SAMPT0_SPT12   ( %XXX -- ) 6 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT12    Channel 12 sample time  selection
: ADC1_SAMPT0_SPT13   ( %XXX -- ) 9 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT13    Channel 13 sample time  selection
: ADC1_SAMPT0_SPT14   ( %XXX -- ) 12 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT14    Channel 14 sample time  selection
: ADC1_SAMPT0_SPT15   ( %XXX -- ) 15 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT15    Channel 15 sample time  selection
: ADC1_SAMPT0_SPT16   ( %XXX -- ) 18 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT16    Channel 16 sample time  selection
: ADC1_SAMPT0_SPT17   ( %XXX -- ) 21 lshift ADC1_SAMPT0 bis! ;  \ ADC1_SAMPT0_SPT17    Channel 17 sample time  selection

\ ADC1_SAMPT1 (read-write)
: ADC1_SAMPT1_SPT0   ( %XXX -- ) 0 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT0    Channel 0 sample time  selection
: ADC1_SAMPT1_SPT1   ( %XXX -- ) 3 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT1    Channel 1 sample time  selection
: ADC1_SAMPT1_SPT2   ( %XXX -- ) 6 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT2    Channel 2 sample time  selection
: ADC1_SAMPT1_SPT3   ( %XXX -- ) 9 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT3    Channel 3 sample time  selection
: ADC1_SAMPT1_SPT4   ( %XXX -- ) 12 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT4    Channel 4 sample time  selection
: ADC1_SAMPT1_SPT5   ( %XXX -- ) 15 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT5    Channel 5 sample time  selection
: ADC1_SAMPT1_SPT6   ( %XXX -- ) 18 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT6    Channel 6 sample time  selection
: ADC1_SAMPT1_SPT7   ( %XXX -- ) 21 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT7    Channel 7 sample time  selection
: ADC1_SAMPT1_SPT8   ( %XXX -- ) 24 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT8    Channel 8 sample time  selection
: ADC1_SAMPT1_SPT9   ( %XXX -- ) 27 lshift ADC1_SAMPT1 bis! ;  \ ADC1_SAMPT1_SPT9    Channel 9 sample time  selection

\ ADC1_IOFF0 (read-write)
: ADC1_IOFF0_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC1_IOFF0 bis! ;  \ ADC1_IOFF0_IOFF    Data offset for inserted channel  0

\ ADC1_IOFF1 (read-write)
: ADC1_IOFF1_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC1_IOFF1 bis! ;  \ ADC1_IOFF1_IOFF    Data offset for inserted channel  1

\ ADC1_IOFF2 (read-write)
: ADC1_IOFF2_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC1_IOFF2 bis! ;  \ ADC1_IOFF2_IOFF    Data offset for inserted channel  2

\ ADC1_IOFF3 (read-write)
: ADC1_IOFF3_IOFF   ( %XXXXXXXXXXX -- ) 0 lshift ADC1_IOFF3 bis! ;  \ ADC1_IOFF3_IOFF    Data offset for inserted channel  3

\ ADC1_WDHT (read-write)
: ADC1_WDHT_WDHT   ( %XXXXXXXXXXX -- ) 0 lshift ADC1_WDHT bis! ;  \ ADC1_WDHT_WDHT    Analog watchdog higher  threshold

\ ADC1_WDLT (read-write)
: ADC1_WDLT_WDLT   ( %XXXXXXXXXXX -- ) 0 lshift ADC1_WDLT bis! ;  \ ADC1_WDLT_WDLT    Analog watchdog lower  threshold

\ ADC1_RSQ0 (read-write)
: ADC1_RSQ0_RL   ( %XXXX -- ) 20 lshift ADC1_RSQ0 bis! ;  \ ADC1_RSQ0_RL    Regular channel group  length
: ADC1_RSQ0_RSQ15   ( %XXXXX -- ) 15 lshift ADC1_RSQ0 bis! ;  \ ADC1_RSQ0_RSQ15    16th conversion in regular  sequence
: ADC1_RSQ0_RSQ14   ( %XXXXX -- ) 10 lshift ADC1_RSQ0 bis! ;  \ ADC1_RSQ0_RSQ14    15th conversion in regular  sequence
: ADC1_RSQ0_RSQ13   ( %XXXXX -- ) 5 lshift ADC1_RSQ0 bis! ;  \ ADC1_RSQ0_RSQ13    14th conversion in regular  sequence
: ADC1_RSQ0_RSQ12   ( %XXXXX -- ) 0 lshift ADC1_RSQ0 bis! ;  \ ADC1_RSQ0_RSQ12    13th conversion in regular  sequence

\ ADC1_RSQ1 (read-write)
: ADC1_RSQ1_RSQ11   ( %XXXXX -- ) 25 lshift ADC1_RSQ1 bis! ;  \ ADC1_RSQ1_RSQ11    12th conversion in regular  sequence
: ADC1_RSQ1_RSQ10   ( %XXXXX -- ) 20 lshift ADC1_RSQ1 bis! ;  \ ADC1_RSQ1_RSQ10    11th conversion in regular  sequence
: ADC1_RSQ1_RSQ9   ( %XXXXX -- ) 15 lshift ADC1_RSQ1 bis! ;  \ ADC1_RSQ1_RSQ9    10th conversion in regular  sequence
: ADC1_RSQ1_RSQ8   ( %XXXXX -- ) 10 lshift ADC1_RSQ1 bis! ;  \ ADC1_RSQ1_RSQ8    9th conversion in regular  sequence
: ADC1_RSQ1_RSQ7   ( %XXXXX -- ) 5 lshift ADC1_RSQ1 bis! ;  \ ADC1_RSQ1_RSQ7    8th conversion in regular  sequence
: ADC1_RSQ1_RSQ6   ( %XXXXX -- ) 0 lshift ADC1_RSQ1 bis! ;  \ ADC1_RSQ1_RSQ6    7th conversion in regular  sequence

\ ADC1_RSQ2 (read-write)
: ADC1_RSQ2_RSQ5   ( %XXXXX -- ) 25 lshift ADC1_RSQ2 bis! ;  \ ADC1_RSQ2_RSQ5    6th conversion in regular  sequence
: ADC1_RSQ2_RSQ4   ( %XXXXX -- ) 20 lshift ADC1_RSQ2 bis! ;  \ ADC1_RSQ2_RSQ4    5th conversion in regular  sequence
: ADC1_RSQ2_RSQ3   ( %XXXXX -- ) 15 lshift ADC1_RSQ2 bis! ;  \ ADC1_RSQ2_RSQ3    4th conversion in regular  sequence
: ADC1_RSQ2_RSQ2   ( %XXXXX -- ) 10 lshift ADC1_RSQ2 bis! ;  \ ADC1_RSQ2_RSQ2    3rd conversion in regular  sequence
: ADC1_RSQ2_RSQ1   ( %XXXXX -- ) 5 lshift ADC1_RSQ2 bis! ;  \ ADC1_RSQ2_RSQ1    2nd conversion in regular  sequence
: ADC1_RSQ2_RSQ0   ( %XXXXX -- ) 0 lshift ADC1_RSQ2 bis! ;  \ ADC1_RSQ2_RSQ0    1st conversion in regular  sequence

\ ADC1_ISQ (read-write)
: ADC1_ISQ_IL   ( %XX -- ) 20 lshift ADC1_ISQ bis! ;  \ ADC1_ISQ_IL    Inserted channel group length
: ADC1_ISQ_ISQ3   ( %XXXXX -- ) 15 lshift ADC1_ISQ bis! ;  \ ADC1_ISQ_ISQ3    4th conversion in inserted  sequence
: ADC1_ISQ_ISQ2   ( %XXXXX -- ) 10 lshift ADC1_ISQ bis! ;  \ ADC1_ISQ_ISQ2    3rd conversion in inserted  sequence
: ADC1_ISQ_ISQ1   ( %XXXXX -- ) 5 lshift ADC1_ISQ bis! ;  \ ADC1_ISQ_ISQ1    2nd conversion in inserted  sequence
: ADC1_ISQ_ISQ0   ( %XXXXX -- ) 0 lshift ADC1_ISQ bis! ;  \ ADC1_ISQ_ISQ0    1st conversion in inserted  sequence

\ ADC1_IDATA0 (read-only)
: ADC1_IDATA0_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC1_IDATA0 bis! ;  \ ADC1_IDATA0_IDATAn    Inserted number n conversion data

\ ADC1_IDATA1 (read-only)
: ADC1_IDATA1_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC1_IDATA1 bis! ;  \ ADC1_IDATA1_IDATAn    Inserted number n conversion data

\ ADC1_IDATA2 (read-only)
: ADC1_IDATA2_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC1_IDATA2 bis! ;  \ ADC1_IDATA2_IDATAn    Inserted number n conversion data

\ ADC1_IDATA3 (read-only)
: ADC1_IDATA3_IDATAn   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC1_IDATA3 bis! ;  \ ADC1_IDATA3_IDATAn    Inserted number n conversion data

\ ADC1_RDATA (read-only)
: ADC1_RDATA_RDATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift ADC1_RDATA bis! ;  \ ADC1_RDATA_RDATA    Regular channel data

\ AFIO_EC (read-write)
: AFIO_EC_EOE   %1 7 lshift AFIO_EC bis! ;  \ AFIO_EC_EOE    Event output enable
: AFIO_EC_PORT   ( %XXX -- ) 4 lshift AFIO_EC bis! ;  \ AFIO_EC_PORT    Event output port selection
: AFIO_EC_PIN   ( %XXXX -- ) 0 lshift AFIO_EC bis! ;  \ AFIO_EC_PIN    Event output pin selection

\ AFIO_PCF0 (read-write)
: AFIO_PCF0_TIMER1ITI1_REMAP   %1 29 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_TIMER1ITI1_REMAP    TIMER1 internal trigger 1 remapping
: AFIO_PCF0_SPI2_REMAP   %1 28 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_SPI2_REMAP     SPI2/I2S2 remapping
: AFIO_PCF0_SWJ_CFG   ( %XXX -- ) 24 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_SWJ_CFG    Serial wire JTAG configuration
: AFIO_PCF0_CAN1_REMAP   %1 22 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_CAN1_REMAP    CAN1 I/O remapping
: AFIO_PCF0_TIMER4CH3_IREMAP   %1 16 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_TIMER4CH3_IREMAP    TIMER4 channel3 internal remapping
: AFIO_PCF0_PD01_REMAP   %1 15 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_PD01_REMAP    Port D0/Port D1 mapping on OSC_IN/OSC_OUT
: AFIO_PCF0_CAN0_REMAP   ( %XX -- ) 13 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_CAN0_REMAP    CAN0 alternate interface remapping
: AFIO_PCF0_TIMER3_REMAP   %1 12 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_TIMER3_REMAP    TIMER3 remapping
: AFIO_PCF0_TIMER2_REMAP   ( %XX -- ) 10 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_TIMER2_REMAP    TIMER2 remapping
: AFIO_PCF0_TIMER1_REMAP   ( %XX -- ) 8 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_TIMER1_REMAP    TIMER1 remapping
: AFIO_PCF0_TIMER0_REMAP   ( %XX -- ) 6 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_TIMER0_REMAP    TIMER0 remapping
: AFIO_PCF0_USART2_REMAP   ( %XX -- ) 4 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_USART2_REMAP    USART2 remapping
: AFIO_PCF0_USART1_REMAP   %1 3 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_USART1_REMAP    USART1 remapping
: AFIO_PCF0_USART0_REMAP   %1 2 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_USART0_REMAP    USART0 remapping
: AFIO_PCF0_I2C0_REMAP   %1 1 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_I2C0_REMAP    I2C0 remapping
: AFIO_PCF0_SPI0_REMAP   %1 0 lshift AFIO_PCF0 bis! ;  \ AFIO_PCF0_SPI0_REMAP    SPI0 remapping

\ AFIO_EXTISS0 (read-write)
: AFIO_EXTISS0_EXTI3_SS   ( %XXXX -- ) 12 lshift AFIO_EXTISS0 bis! ;  \ AFIO_EXTISS0_EXTI3_SS    EXTI 3 sources selection
: AFIO_EXTISS0_EXTI2_SS   ( %XXXX -- ) 8 lshift AFIO_EXTISS0 bis! ;  \ AFIO_EXTISS0_EXTI2_SS    EXTI 2 sources selection
: AFIO_EXTISS0_EXTI1_SS   ( %XXXX -- ) 4 lshift AFIO_EXTISS0 bis! ;  \ AFIO_EXTISS0_EXTI1_SS    EXTI 1 sources selection
: AFIO_EXTISS0_EXTI0_SS   ( %XXXX -- ) 0 lshift AFIO_EXTISS0 bis! ;  \ AFIO_EXTISS0_EXTI0_SS    EXTI 0 sources selection

\ AFIO_EXTISS1 (read-write)
: AFIO_EXTISS1_EXTI7_SS   ( %XXXX -- ) 12 lshift AFIO_EXTISS1 bis! ;  \ AFIO_EXTISS1_EXTI7_SS    EXTI 7 sources selection
: AFIO_EXTISS1_EXTI6_SS   ( %XXXX -- ) 8 lshift AFIO_EXTISS1 bis! ;  \ AFIO_EXTISS1_EXTI6_SS    EXTI 6 sources selection
: AFIO_EXTISS1_EXTI5_SS   ( %XXXX -- ) 4 lshift AFIO_EXTISS1 bis! ;  \ AFIO_EXTISS1_EXTI5_SS    EXTI 5 sources selection
: AFIO_EXTISS1_EXTI4_SS   ( %XXXX -- ) 0 lshift AFIO_EXTISS1 bis! ;  \ AFIO_EXTISS1_EXTI4_SS    EXTI 4 sources selection

\ AFIO_EXTISS2 (read-write)
: AFIO_EXTISS2_EXTI11_SS   ( %XXXX -- ) 12 lshift AFIO_EXTISS2 bis! ;  \ AFIO_EXTISS2_EXTI11_SS    EXTI 11 sources selection
: AFIO_EXTISS2_EXTI10_SS   ( %XXXX -- ) 8 lshift AFIO_EXTISS2 bis! ;  \ AFIO_EXTISS2_EXTI10_SS    EXTI 10 sources selection
: AFIO_EXTISS2_EXTI9_SS   ( %XXXX -- ) 4 lshift AFIO_EXTISS2 bis! ;  \ AFIO_EXTISS2_EXTI9_SS    EXTI 9 sources selection
: AFIO_EXTISS2_EXTI8_SS   ( %XXXX -- ) 0 lshift AFIO_EXTISS2 bis! ;  \ AFIO_EXTISS2_EXTI8_SS    EXTI 8 sources selection

\ AFIO_EXTISS3 (read-write)
: AFIO_EXTISS3_EXTI15_SS   ( %XXXX -- ) 12 lshift AFIO_EXTISS3 bis! ;  \ AFIO_EXTISS3_EXTI15_SS    EXTI 15 sources selection
: AFIO_EXTISS3_EXTI14_SS   ( %XXXX -- ) 8 lshift AFIO_EXTISS3 bis! ;  \ AFIO_EXTISS3_EXTI14_SS    EXTI 14 sources selection
: AFIO_EXTISS3_EXTI13_SS   ( %XXXX -- ) 4 lshift AFIO_EXTISS3 bis! ;  \ AFIO_EXTISS3_EXTI13_SS    EXTI 13 sources selection
: AFIO_EXTISS3_EXTI12_SS   ( %XXXX -- ) 0 lshift AFIO_EXTISS3 bis! ;  \ AFIO_EXTISS3_EXTI12_SS    EXTI 12 sources selection

\ AFIO_PCF1 (read-write)
: AFIO_PCF1_EXMC_NADV   %1 10 lshift AFIO_PCF1 bis! ;  \ AFIO_PCF1_EXMC_NADV    EXMC_NADV connect/disconnect

\ BKP_DATA0 (read-write)
: BKP_DATA0_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA0 bis! ;  \ BKP_DATA0_DATA    Backup data

\ BKP_DATA1 (read-write)
: BKP_DATA1_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA1 bis! ;  \ BKP_DATA1_DATA    Backup data

\ BKP_DATA2 (read-write)
: BKP_DATA2_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA2 bis! ;  \ BKP_DATA2_DATA    Backup data

\ BKP_DATA3 (read-write)
: BKP_DATA3_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA3 bis! ;  \ BKP_DATA3_DATA    Backup data

\ BKP_DATA4 (read-write)
: BKP_DATA4_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA4 bis! ;  \ BKP_DATA4_DATA    Backup data

\ BKP_DATA5 (read-write)
: BKP_DATA5_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA5 bis! ;  \ BKP_DATA5_DATA    Backup data

\ BKP_DATA6 (read-write)
: BKP_DATA6_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA6 bis! ;  \ BKP_DATA6_DATA    Backup data

\ BKP_DATA7 (read-write)
: BKP_DATA7_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA7 bis! ;  \ BKP_DATA7_DATA    Backup data

\ BKP_DATA8 (read-write)
: BKP_DATA8_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA8 bis! ;  \ BKP_DATA8_DATA    Backup data

\ BKP_DATA9 (read-write)
: BKP_DATA9_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA9 bis! ;  \ BKP_DATA9_DATA    Backup data

\ BKP_DATA10 (read-write)
: BKP_DATA10_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA10 bis! ;  \ BKP_DATA10_DATA    Backup data

\ BKP_DATA11 (read-write)
: BKP_DATA11_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA11 bis! ;  \ BKP_DATA11_DATA    Backup data

\ BKP_DATA12 (read-write)
: BKP_DATA12_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA12 bis! ;  \ BKP_DATA12_DATA    Backup data

\ BKP_DATA13 (read-write)
: BKP_DATA13_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA13 bis! ;  \ BKP_DATA13_DATA    Backup data

\ BKP_DATA14 (read-write)
: BKP_DATA14_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA14 bis! ;  \ BKP_DATA14_DATA    Backup data

\ BKP_DATA15 (read-write)
: BKP_DATA15_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA15 bis! ;  \ BKP_DATA15_DATA    Backup data

\ BKP_DATA16 (read-write)
: BKP_DATA16_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA16 bis! ;  \ BKP_DATA16_DATA    Backup data

\ BKP_DATA17 (read-write)
: BKP_DATA17_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA17 bis! ;  \ BKP_DATA17_DATA    Backup data

\ BKP_DATA18 (read-write)
: BKP_DATA18_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA18 bis! ;  \ BKP_DATA18_DATA    Backup data

\ BKP_DATA19 (read-write)
: BKP_DATA19_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA19 bis! ;  \ BKP_DATA19_DATA    Backup data

\ BKP_DATA20 (read-write)
: BKP_DATA20_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA20 bis! ;  \ BKP_DATA20_DATA    Backup data

\ BKP_DATA21 (read-write)
: BKP_DATA21_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA21 bis! ;  \ BKP_DATA21_DATA    Backup data

\ BKP_DATA22 (read-write)
: BKP_DATA22_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA22 bis! ;  \ BKP_DATA22_DATA    Backup data

\ BKP_DATA23 (read-write)
: BKP_DATA23_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA23 bis! ;  \ BKP_DATA23_DATA    Backup data

\ BKP_DATA24 (read-write)
: BKP_DATA24_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA24 bis! ;  \ BKP_DATA24_DATA    Backup data

\ BKP_DATA25 (read-write)
: BKP_DATA25_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA25 bis! ;  \ BKP_DATA25_DATA    Backup data

\ BKP_DATA26 (read-write)
: BKP_DATA26_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA26 bis! ;  \ BKP_DATA26_DATA    Backup data

\ BKP_DATA27 (read-write)
: BKP_DATA27_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA27 bis! ;  \ BKP_DATA27_DATA    Backup data

\ BKP_DATA28 (read-write)
: BKP_DATA28_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA28 bis! ;  \ BKP_DATA28_DATA    Backup data

\ BKP_DATA29 (read-write)
: BKP_DATA29_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA29 bis! ;  \ BKP_DATA29_DATA    Backup data

\ BKP_DATA30 (read-write)
: BKP_DATA30_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA30 bis! ;  \ BKP_DATA30_DATA    Backup data

\ BKP_DATA31 (read-write)
: BKP_DATA31_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA31 bis! ;  \ BKP_DATA31_DATA    Backup data

\ BKP_DATA32 (read-write)
: BKP_DATA32_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA32 bis! ;  \ BKP_DATA32_DATA    Backup data

\ BKP_DATA33 (read-write)
: BKP_DATA33_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA33 bis! ;  \ BKP_DATA33_DATA    Backup data

\ BKP_DATA34 (read-write)
: BKP_DATA34_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA34 bis! ;  \ BKP_DATA34_DATA    Backup data

\ BKP_DATA35 (read-write)
: BKP_DATA35_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA35 bis! ;  \ BKP_DATA35_DATA    Backup data

\ BKP_DATA36 (read-write)
: BKP_DATA36_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA36 bis! ;  \ BKP_DATA36_DATA    Backup data

\ BKP_DATA37 (read-write)
: BKP_DATA37_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA37 bis! ;  \ BKP_DATA37_DATA    Backup data

\ BKP_DATA38 (read-write)
: BKP_DATA38_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA38 bis! ;  \ BKP_DATA38_DATA    Backup data

\ BKP_DATA39 (read-write)
: BKP_DATA39_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA39 bis! ;  \ BKP_DATA39_DATA    Backup data

\ BKP_DATA40 (read-write)
: BKP_DATA40_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA40 bis! ;  \ BKP_DATA40_DATA    Backup data

\ BKP_DATA41 (read-write)
: BKP_DATA41_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift BKP_DATA41 bis! ;  \ BKP_DATA41_DATA    Backup data

\ BKP_OCTL (read-write)
: BKP_OCTL_ROSEL   %1 9 lshift BKP_OCTL bis! ;  \ BKP_OCTL_ROSEL    RTC output selection
: BKP_OCTL_ASOEN   %1 8 lshift BKP_OCTL bis! ;  \ BKP_OCTL_ASOEN    RTC alarm or second signal output enable
: BKP_OCTL_COEN   %1 7 lshift BKP_OCTL bis! ;  \ BKP_OCTL_COEN    RTC clock calibration output enable
: BKP_OCTL_RCCV   ( %XXXXXXX -- ) 0 lshift BKP_OCTL bis! ;  \ BKP_OCTL_RCCV    RTC clock calibration value

\ BKP_TPCTL (read-write)
: BKP_TPCTL_TPAL   %1 1 lshift BKP_TPCTL bis! ;  \ BKP_TPCTL_TPAL    TAMPER pin active level
: BKP_TPCTL_TPEN   %1 0 lshift BKP_TPCTL bis! ;  \ BKP_TPCTL_TPEN    TAMPER detection enable

\ BKP_TPCS (read-write)
: BKP_TPCS_TIF   %1 9 lshift BKP_TPCS bis! ;  \ BKP_TPCS_TIF    Tamper interrupt flag
: BKP_TPCS_TEF   %1 8 lshift BKP_TPCS bis! ;  \ BKP_TPCS_TEF    Tamper event flag
: BKP_TPCS_TPIE   %1 2 lshift BKP_TPCS bis! ;  \ BKP_TPCS_TPIE    Tamper interrupt enable
: BKP_TPCS_TIR   %1 1 lshift BKP_TPCS bis! ;  \ BKP_TPCS_TIR    Tamper interrupt reset
: BKP_TPCS_TER   %1 0 lshift BKP_TPCS bis! ;  \ BKP_TPCS_TER    Tamper event reset

\ CAN0_CTL (read-write)
: CAN0_CTL_DFZ   %1 16 lshift CAN0_CTL bis! ;  \ CAN0_CTL_DFZ    Debug freeze
: CAN0_CTL_SWRST   %1 15 lshift CAN0_CTL bis! ;  \ CAN0_CTL_SWRST    Software reset
: CAN0_CTL_TTC   %1 7 lshift CAN0_CTL bis! ;  \ CAN0_CTL_TTC    Time-triggered communication
: CAN0_CTL_ABOR   %1 6 lshift CAN0_CTL bis! ;  \ CAN0_CTL_ABOR    Automatic bus-off recovery
: CAN0_CTL_AWU   %1 5 lshift CAN0_CTL bis! ;  \ CAN0_CTL_AWU    Automatic wakeup
: CAN0_CTL_ARD   %1 4 lshift CAN0_CTL bis! ;  \ CAN0_CTL_ARD    Automatic retransmission disable
: CAN0_CTL_RFOD   %1 3 lshift CAN0_CTL bis! ;  \ CAN0_CTL_RFOD    Receive FIFO overwrite disable
: CAN0_CTL_TFO   %1 2 lshift CAN0_CTL bis! ;  \ CAN0_CTL_TFO    Transmit FIFO order
: CAN0_CTL_SLPWMOD   %1 1 lshift CAN0_CTL bis! ;  \ CAN0_CTL_SLPWMOD    Sleep working mode
: CAN0_CTL_IWMOD   %1 0 lshift CAN0_CTL bis! ;  \ CAN0_CTL_IWMOD    Initial working mode

\ CAN0_STAT ()
: CAN0_STAT_RXL   %1 11 lshift CAN0_STAT bis! ;  \ CAN0_STAT_RXL    RX level
: CAN0_STAT_LASTRX   %1 10 lshift CAN0_STAT bis! ;  \ CAN0_STAT_LASTRX    Last sample value of RX pin
: CAN0_STAT_RS   %1 9 lshift CAN0_STAT bis! ;  \ CAN0_STAT_RS    Receiving state
: CAN0_STAT_TS   %1 8 lshift CAN0_STAT bis! ;  \ CAN0_STAT_TS    Transmitting state
: CAN0_STAT_SLPIF   %1 4 lshift CAN0_STAT bis! ;  \ CAN0_STAT_SLPIF    Status change interrupt flag of sleep  	 working mode entering
: CAN0_STAT_WUIF   %1 3 lshift CAN0_STAT bis! ;  \ CAN0_STAT_WUIF    Status change interrupt flag of wakeup  	 from sleep working mode
: CAN0_STAT_ERRIF   %1 2 lshift CAN0_STAT bis! ;  \ CAN0_STAT_ERRIF    Error interrupt flag
: CAN0_STAT_SLPWS   %1 1 lshift CAN0_STAT bis! ;  \ CAN0_STAT_SLPWS    Sleep working state
: CAN0_STAT_IWS   %1 0 lshift CAN0_STAT bis! ;  \ CAN0_STAT_IWS    Initial working state

\ CAN0_TSTAT ()
: CAN0_TSTAT_TMLS2   %1 31 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_TMLS2    Transmit mailbox 2 last sending  	 in transmit FIFO
: CAN0_TSTAT_TMLS1   %1 30 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_TMLS1    Transmit mailbox 1 last sending  	 in transmit FIFO
: CAN0_TSTAT_TMLS0   %1 29 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_TMLS0    Transmit mailbox 0 last sending  	 in transmit FIFO
: CAN0_TSTAT_TME2   %1 28 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_TME2    Transmit mailbox 2 empty
: CAN0_TSTAT_TME1   %1 27 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_TME1    Transmit mailbox 1 empty
: CAN0_TSTAT_TME0   %1 26 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_TME0    Transmit mailbox 0 empty
: CAN0_TSTAT_NUM   ( %XX -- ) 24 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_NUM    number of the transmit FIFO mailbox in  	 which the frame will be transmitted if at least one mailbox is empty
: CAN0_TSTAT_MST2   %1 23 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MST2    Mailbox 2 stop transmitting
: CAN0_TSTAT_MTE2   %1 19 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTE2    Mailbox 2 transmit error
: CAN0_TSTAT_MAL2   %1 18 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MAL2    Mailbox 2 arbitration lost
: CAN0_TSTAT_MTFNERR2   %1 17 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTFNERR2    Mailbox 2 transmit finished and no error
: CAN0_TSTAT_MTF2   %1 16 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTF2    Mailbox 2 transmit finished
: CAN0_TSTAT_MST1   %1 15 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MST1    Mailbox 1 stop transmitting
: CAN0_TSTAT_MTE1   %1 11 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTE1    Mailbox 1 transmit error
: CAN0_TSTAT_MAL1   %1 10 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MAL1    Mailbox 1 arbitration lost
: CAN0_TSTAT_MTFNERR1   %1 9 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTFNERR1    Mailbox 1 transmit finished and no error
: CAN0_TSTAT_MTF1   %1 8 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTF1    Mailbox 1 transmit finished
: CAN0_TSTAT_MST0   %1 7 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MST0    Mailbox 0 stop transmitting
: CAN0_TSTAT_MTE0   %1 3 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTE0    Mailbox 0 transmit error
: CAN0_TSTAT_MAL0   %1 2 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MAL0    Mailbox 0 arbitration lost
: CAN0_TSTAT_MTFNERR0   %1 1 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTFNERR0    Mailbox 0 transmit finished and no error
: CAN0_TSTAT_MTF0   %1 0 lshift CAN0_TSTAT bis! ;  \ CAN0_TSTAT_MTF0    Mailbox 0 transmit finished

\ CAN0_RFIFO0 ()
: CAN0_RFIFO0_RFD0   %1 5 lshift CAN0_RFIFO0 bis! ;  \ CAN0_RFIFO0_RFD0    Receive FIFO0 dequeue
: CAN0_RFIFO0_RFO0   %1 4 lshift CAN0_RFIFO0 bis! ;  \ CAN0_RFIFO0_RFO0    Receive FIFO0 overfull
: CAN0_RFIFO0_RFF0   %1 3 lshift CAN0_RFIFO0 bis! ;  \ CAN0_RFIFO0_RFF0    Receive FIFO0 full
: CAN0_RFIFO0_RFL0   ( %XX -- ) 0 lshift CAN0_RFIFO0 bis! ;  \ CAN0_RFIFO0_RFL0    Receive FIFO0 length

\ CAN0_RFIFO1 ()
: CAN0_RFIFO1_RFD1   %1 5 lshift CAN0_RFIFO1 bis! ;  \ CAN0_RFIFO1_RFD1    Receive FIFO1 dequeue
: CAN0_RFIFO1_RFO1   %1 4 lshift CAN0_RFIFO1 bis! ;  \ CAN0_RFIFO1_RFO1    Receive FIFO1 overfull
: CAN0_RFIFO1_RFF1   %1 3 lshift CAN0_RFIFO1 bis! ;  \ CAN0_RFIFO1_RFF1    Receive FIFO1 full
: CAN0_RFIFO1_RFL1   ( %XX -- ) 0 lshift CAN0_RFIFO1 bis! ;  \ CAN0_RFIFO1_RFL1    Receive FIFO1 length

\ CAN0_INTEN (read-write)
: CAN0_INTEN_SLPWIE   %1 17 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_SLPWIE    Sleep working interrupt enable
: CAN0_INTEN_WIE   %1 16 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_WIE    Wakeup interrupt enable
: CAN0_INTEN_ERRIE   %1 15 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_ERRIE    Error interrupt enable
: CAN0_INTEN_ERRNIE   %1 11 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_ERRNIE    Error number interrupt enable
: CAN0_INTEN_BOIE   %1 10 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_BOIE    Bus-off interrupt enable
: CAN0_INTEN_PERRIE   %1 9 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_PERRIE    Passive error interrupt enable
: CAN0_INTEN_WERRIE   %1 8 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_WERRIE    Warning error interrupt enable
: CAN0_INTEN_RFOIE1   %1 6 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_RFOIE1    Receive FIFO1 overfull interrupt enable
: CAN0_INTEN_RFFIE1   %1 5 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_RFFIE1    Receive FIFO1 full interrupt enable
: CAN0_INTEN_RFNEIE1   %1 4 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_RFNEIE1    Receive FIFO1 not empty interrupt enable
: CAN0_INTEN_RFOIE0   %1 3 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_RFOIE0    Receive FIFO0 overfull interrupt enable
: CAN0_INTEN_RFFIE0   %1 2 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_RFFIE0    Receive FIFO0 full interrupt enable
: CAN0_INTEN_RFNEIE0   %1 1 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_RFNEIE0    Receive FIFO0 not empty interrupt enable
: CAN0_INTEN_TMEIE   %1 0 lshift CAN0_INTEN bis! ;  \ CAN0_INTEN_TMEIE    Transmit mailbox empty interrupt enable

\ CAN0_ERR ()
: CAN0_ERR_RECNT   ( %XXXXXXXX -- ) 24 lshift CAN0_ERR bis! ;  \ CAN0_ERR_RECNT    Receive Error Count defined  	 by the CAN standard
: CAN0_ERR_TECNT   ( %XXXXXXXX -- ) 16 lshift CAN0_ERR bis! ;  \ CAN0_ERR_TECNT    Transmit Error Count defined  	 by the CAN standard
: CAN0_ERR_ERRN   ( %XXX -- ) 4 lshift CAN0_ERR bis! ;  \ CAN0_ERR_ERRN    Error number
: CAN0_ERR_BOERR   %1 2 lshift CAN0_ERR bis! ;  \ CAN0_ERR_BOERR    Bus-off error
: CAN0_ERR_PERR   %1 1 lshift CAN0_ERR bis! ;  \ CAN0_ERR_PERR    Passive error
: CAN0_ERR_WERR   %1 0 lshift CAN0_ERR bis! ;  \ CAN0_ERR_WERR    Warning error

\ CAN0_BT (read-write)
: CAN0_BT_SCMOD   %1 31 lshift CAN0_BT bis! ;  \ CAN0_BT_SCMOD    Silent communication mode
: CAN0_BT_LCMOD   %1 30 lshift CAN0_BT bis! ;  \ CAN0_BT_LCMOD    Loopback communication mode
: CAN0_BT_SJW   ( %XX -- ) 24 lshift CAN0_BT bis! ;  \ CAN0_BT_SJW    Resynchronization jump width
: CAN0_BT_BS2   ( %XXX -- ) 20 lshift CAN0_BT bis! ;  \ CAN0_BT_BS2    Bit segment 2
: CAN0_BT_BS1   ( %XXXX -- ) 16 lshift CAN0_BT bis! ;  \ CAN0_BT_BS1    Bit segment 1
: CAN0_BT_BAUDPSC  0 lshift CAN0_BT bis! ;  \ CAN0_BT_BAUDPSC    Baud rate prescaler

\ CAN0_TMI0 (read-write)
: CAN0_TMI0_SFID_EFID  21 lshift CAN0_TMI0 bis! ;  \ CAN0_TMI0_SFID_EFID    The frame identifier
: CAN0_TMI0_EFID  3 lshift CAN0_TMI0 bis! ;  \ CAN0_TMI0_EFID    The frame identifier
: CAN0_TMI0_FF   %1 2 lshift CAN0_TMI0 bis! ;  \ CAN0_TMI0_FF    Frame format
: CAN0_TMI0_FT   %1 1 lshift CAN0_TMI0 bis! ;  \ CAN0_TMI0_FT    Frame type
: CAN0_TMI0_TEN   %1 0 lshift CAN0_TMI0 bis! ;  \ CAN0_TMI0_TEN    Transmit enable

\ CAN0_TMP0 (read-write)
: CAN0_TMP0_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN0_TMP0 bis! ;  \ CAN0_TMP0_TS    Time stamp
: CAN0_TMP0_TSEN   %1 8 lshift CAN0_TMP0 bis! ;  \ CAN0_TMP0_TSEN    Time stamp enable
: CAN0_TMP0_DLENC   ( %XXXX -- ) 0 lshift CAN0_TMP0 bis! ;  \ CAN0_TMP0_DLENC    Data length code

\ CAN0_TMDATA00 (read-write)
: CAN0_TMDATA00_DB3   ( %XXXXXXXX -- ) 24 lshift CAN0_TMDATA00 bis! ;  \ CAN0_TMDATA00_DB3    Data byte 3
: CAN0_TMDATA00_DB2   ( %XXXXXXXX -- ) 16 lshift CAN0_TMDATA00 bis! ;  \ CAN0_TMDATA00_DB2    Data byte 2
: CAN0_TMDATA00_DB1   ( %XXXXXXXX -- ) 8 lshift CAN0_TMDATA00 bis! ;  \ CAN0_TMDATA00_DB1    Data byte 1
: CAN0_TMDATA00_DB0   ( %XXXXXXXX -- ) 0 lshift CAN0_TMDATA00 bis! ;  \ CAN0_TMDATA00_DB0    Data byte 0

\ CAN0_TMDATA10 (read-write)
: CAN0_TMDATA10_DB7   ( %XXXXXXXX -- ) 24 lshift CAN0_TMDATA10 bis! ;  \ CAN0_TMDATA10_DB7    Data byte 7
: CAN0_TMDATA10_DB6   ( %XXXXXXXX -- ) 16 lshift CAN0_TMDATA10 bis! ;  \ CAN0_TMDATA10_DB6    Data byte 6
: CAN0_TMDATA10_DB5   ( %XXXXXXXX -- ) 8 lshift CAN0_TMDATA10 bis! ;  \ CAN0_TMDATA10_DB5    Data byte 5
: CAN0_TMDATA10_DB4   ( %XXXXXXXX -- ) 0 lshift CAN0_TMDATA10 bis! ;  \ CAN0_TMDATA10_DB4    Data byte 4

\ CAN0_TMI1 (read-write)
: CAN0_TMI1_SFID_EFID  21 lshift CAN0_TMI1 bis! ;  \ CAN0_TMI1_SFID_EFID    The frame identifier
: CAN0_TMI1_EFID  3 lshift CAN0_TMI1 bis! ;  \ CAN0_TMI1_EFID    The frame identifier
: CAN0_TMI1_FF   %1 2 lshift CAN0_TMI1 bis! ;  \ CAN0_TMI1_FF    Frame format
: CAN0_TMI1_FT   %1 1 lshift CAN0_TMI1 bis! ;  \ CAN0_TMI1_FT    Frame type
: CAN0_TMI1_TEN   %1 0 lshift CAN0_TMI1 bis! ;  \ CAN0_TMI1_TEN    Transmit enable

\ CAN0_TMP1 (read-write)
: CAN0_TMP1_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN0_TMP1 bis! ;  \ CAN0_TMP1_TS    Time stamp
: CAN0_TMP1_TSEN   %1 8 lshift CAN0_TMP1 bis! ;  \ CAN0_TMP1_TSEN    Time stamp enable
: CAN0_TMP1_DLENC   ( %XXXX -- ) 0 lshift CAN0_TMP1 bis! ;  \ CAN0_TMP1_DLENC    Data length code

\ CAN0_TMDATA01 (read-write)
: CAN0_TMDATA01_DB3   ( %XXXXXXXX -- ) 24 lshift CAN0_TMDATA01 bis! ;  \ CAN0_TMDATA01_DB3    Data byte 3
: CAN0_TMDATA01_DB2   ( %XXXXXXXX -- ) 16 lshift CAN0_TMDATA01 bis! ;  \ CAN0_TMDATA01_DB2    Data byte 2
: CAN0_TMDATA01_DB1   ( %XXXXXXXX -- ) 8 lshift CAN0_TMDATA01 bis! ;  \ CAN0_TMDATA01_DB1    Data byte 1
: CAN0_TMDATA01_DB0   ( %XXXXXXXX -- ) 0 lshift CAN0_TMDATA01 bis! ;  \ CAN0_TMDATA01_DB0    Data byte 0

\ CAN0_TMDATA11 (read-write)
: CAN0_TMDATA11_DB7   ( %XXXXXXXX -- ) 24 lshift CAN0_TMDATA11 bis! ;  \ CAN0_TMDATA11_DB7    Data byte 7
: CAN0_TMDATA11_DB6   ( %XXXXXXXX -- ) 16 lshift CAN0_TMDATA11 bis! ;  \ CAN0_TMDATA11_DB6    Data byte 6
: CAN0_TMDATA11_DB5   ( %XXXXXXXX -- ) 8 lshift CAN0_TMDATA11 bis! ;  \ CAN0_TMDATA11_DB5    Data byte 5
: CAN0_TMDATA11_DB4   ( %XXXXXXXX -- ) 0 lshift CAN0_TMDATA11 bis! ;  \ CAN0_TMDATA11_DB4    Data byte 4

\ CAN0_TMI2 (read-write)
: CAN0_TMI2_SFID_EFID  21 lshift CAN0_TMI2 bis! ;  \ CAN0_TMI2_SFID_EFID    The frame identifier
: CAN0_TMI2_EFID  3 lshift CAN0_TMI2 bis! ;  \ CAN0_TMI2_EFID    The frame identifier
: CAN0_TMI2_FF   %1 2 lshift CAN0_TMI2 bis! ;  \ CAN0_TMI2_FF    Frame format
: CAN0_TMI2_FT   %1 1 lshift CAN0_TMI2 bis! ;  \ CAN0_TMI2_FT    Frame type
: CAN0_TMI2_TEN   %1 0 lshift CAN0_TMI2 bis! ;  \ CAN0_TMI2_TEN    Transmit enable

\ CAN0_TMP2 (read-write)
: CAN0_TMP2_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN0_TMP2 bis! ;  \ CAN0_TMP2_TS    Time stamp
: CAN0_TMP2_TSEN   %1 8 lshift CAN0_TMP2 bis! ;  \ CAN0_TMP2_TSEN    Time stamp enable
: CAN0_TMP2_DLENC   ( %XXXX -- ) 0 lshift CAN0_TMP2 bis! ;  \ CAN0_TMP2_DLENC    Data length code

\ CAN0_TMDATA02 (read-write)
: CAN0_TMDATA02_DB3   ( %XXXXXXXX -- ) 24 lshift CAN0_TMDATA02 bis! ;  \ CAN0_TMDATA02_DB3    Data byte 3
: CAN0_TMDATA02_DB2   ( %XXXXXXXX -- ) 16 lshift CAN0_TMDATA02 bis! ;  \ CAN0_TMDATA02_DB2    Data byte 2
: CAN0_TMDATA02_DB1   ( %XXXXXXXX -- ) 8 lshift CAN0_TMDATA02 bis! ;  \ CAN0_TMDATA02_DB1    Data byte 1
: CAN0_TMDATA02_DB0   ( %XXXXXXXX -- ) 0 lshift CAN0_TMDATA02 bis! ;  \ CAN0_TMDATA02_DB0    Data byte 0

\ CAN0_TMDATA12 (read-write)
: CAN0_TMDATA12_DB7   ( %XXXXXXXX -- ) 24 lshift CAN0_TMDATA12 bis! ;  \ CAN0_TMDATA12_DB7    Data byte 7
: CAN0_TMDATA12_DB6   ( %XXXXXXXX -- ) 16 lshift CAN0_TMDATA12 bis! ;  \ CAN0_TMDATA12_DB6    Data byte 6
: CAN0_TMDATA12_DB5   ( %XXXXXXXX -- ) 8 lshift CAN0_TMDATA12 bis! ;  \ CAN0_TMDATA12_DB5    Data byte 5
: CAN0_TMDATA12_DB4   ( %XXXXXXXX -- ) 0 lshift CAN0_TMDATA12 bis! ;  \ CAN0_TMDATA12_DB4    Data byte 4

\ CAN0_RFIFOMI0 (read-only)
: CAN0_RFIFOMI0_SFID_EFID  21 lshift CAN0_RFIFOMI0 bis! ;  \ CAN0_RFIFOMI0_SFID_EFID    The frame identifier
: CAN0_RFIFOMI0_EFID  3 lshift CAN0_RFIFOMI0 bis! ;  \ CAN0_RFIFOMI0_EFID    The frame identifier
: CAN0_RFIFOMI0_FF   %1 2 lshift CAN0_RFIFOMI0 bis! ;  \ CAN0_RFIFOMI0_FF    Frame format
: CAN0_RFIFOMI0_FT   %1 1 lshift CAN0_RFIFOMI0 bis! ;  \ CAN0_RFIFOMI0_FT    Frame type

\ CAN0_RFIFOMP0 (read-only)
: CAN0_RFIFOMP0_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN0_RFIFOMP0 bis! ;  \ CAN0_RFIFOMP0_TS    Time stamp
: CAN0_RFIFOMP0_FI   ( %XXXXXXXX -- ) 8 lshift CAN0_RFIFOMP0 bis! ;  \ CAN0_RFIFOMP0_FI    Filtering index
: CAN0_RFIFOMP0_DLENC   ( %XXXX -- ) 0 lshift CAN0_RFIFOMP0 bis! ;  \ CAN0_RFIFOMP0_DLENC    Data length code

\ CAN0_RFIFOMDATA00 (read-only)
: CAN0_RFIFOMDATA00_DB3   ( %XXXXXXXX -- ) 24 lshift CAN0_RFIFOMDATA00 bis! ;  \ CAN0_RFIFOMDATA00_DB3    Data byte 3
: CAN0_RFIFOMDATA00_DB2   ( %XXXXXXXX -- ) 16 lshift CAN0_RFIFOMDATA00 bis! ;  \ CAN0_RFIFOMDATA00_DB2    Data byte 2
: CAN0_RFIFOMDATA00_DB1   ( %XXXXXXXX -- ) 8 lshift CAN0_RFIFOMDATA00 bis! ;  \ CAN0_RFIFOMDATA00_DB1    Data byte 1
: CAN0_RFIFOMDATA00_DB0   ( %XXXXXXXX -- ) 0 lshift CAN0_RFIFOMDATA00 bis! ;  \ CAN0_RFIFOMDATA00_DB0    Data byte 0

\ CAN0_RFIFOMDATA10 (read-only)
: CAN0_RFIFOMDATA10_DB7   ( %XXXXXXXX -- ) 24 lshift CAN0_RFIFOMDATA10 bis! ;  \ CAN0_RFIFOMDATA10_DB7    Data byte 7
: CAN0_RFIFOMDATA10_DB6   ( %XXXXXXXX -- ) 16 lshift CAN0_RFIFOMDATA10 bis! ;  \ CAN0_RFIFOMDATA10_DB6    Data byte 6
: CAN0_RFIFOMDATA10_DB5   ( %XXXXXXXX -- ) 8 lshift CAN0_RFIFOMDATA10 bis! ;  \ CAN0_RFIFOMDATA10_DB5    Data byte 5
: CAN0_RFIFOMDATA10_DB4   ( %XXXXXXXX -- ) 0 lshift CAN0_RFIFOMDATA10 bis! ;  \ CAN0_RFIFOMDATA10_DB4    Data byte 4

\ CAN0_RFIFOMI1 (read-only)
: CAN0_RFIFOMI1_SFID_EFID  21 lshift CAN0_RFIFOMI1 bis! ;  \ CAN0_RFIFOMI1_SFID_EFID    The frame identifier
: CAN0_RFIFOMI1_EFID  3 lshift CAN0_RFIFOMI1 bis! ;  \ CAN0_RFIFOMI1_EFID    The frame identifier
: CAN0_RFIFOMI1_FF   %1 2 lshift CAN0_RFIFOMI1 bis! ;  \ CAN0_RFIFOMI1_FF    Frame format
: CAN0_RFIFOMI1_FT   %1 1 lshift CAN0_RFIFOMI1 bis! ;  \ CAN0_RFIFOMI1_FT    Frame type

\ CAN0_RFIFOMP1 (read-only)
: CAN0_RFIFOMP1_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN0_RFIFOMP1 bis! ;  \ CAN0_RFIFOMP1_TS    Time stamp
: CAN0_RFIFOMP1_FI   ( %XXXXXXXX -- ) 8 lshift CAN0_RFIFOMP1 bis! ;  \ CAN0_RFIFOMP1_FI    Filtering index
: CAN0_RFIFOMP1_DLENC   ( %XXXX -- ) 0 lshift CAN0_RFIFOMP1 bis! ;  \ CAN0_RFIFOMP1_DLENC    Data length code

\ CAN0_RFIFOMDATA01 (read-only)
: CAN0_RFIFOMDATA01_DB3   ( %XXXXXXXX -- ) 24 lshift CAN0_RFIFOMDATA01 bis! ;  \ CAN0_RFIFOMDATA01_DB3    Data byte 3
: CAN0_RFIFOMDATA01_DB2   ( %XXXXXXXX -- ) 16 lshift CAN0_RFIFOMDATA01 bis! ;  \ CAN0_RFIFOMDATA01_DB2    Data byte 2
: CAN0_RFIFOMDATA01_DB1   ( %XXXXXXXX -- ) 8 lshift CAN0_RFIFOMDATA01 bis! ;  \ CAN0_RFIFOMDATA01_DB1    Data byte 1
: CAN0_RFIFOMDATA01_DB0   ( %XXXXXXXX -- ) 0 lshift CAN0_RFIFOMDATA01 bis! ;  \ CAN0_RFIFOMDATA01_DB0    Data byte 0

\ CAN0_RFIFOMDATA11 (read-only)
: CAN0_RFIFOMDATA11_DB7   ( %XXXXXXXX -- ) 24 lshift CAN0_RFIFOMDATA11 bis! ;  \ CAN0_RFIFOMDATA11_DB7    Data byte 7
: CAN0_RFIFOMDATA11_DB6   ( %XXXXXXXX -- ) 16 lshift CAN0_RFIFOMDATA11 bis! ;  \ CAN0_RFIFOMDATA11_DB6    Data byte 6
: CAN0_RFIFOMDATA11_DB5   ( %XXXXXXXX -- ) 8 lshift CAN0_RFIFOMDATA11 bis! ;  \ CAN0_RFIFOMDATA11_DB5    Data byte 5
: CAN0_RFIFOMDATA11_DB4   ( %XXXXXXXX -- ) 0 lshift CAN0_RFIFOMDATA11 bis! ;  \ CAN0_RFIFOMDATA11_DB4    Data byte 4

\ CAN0_FCTL (read-write)
: CAN0_FCTL_HBC1F   ( %XXXXXX -- ) 8 lshift CAN0_FCTL bis! ;  \ CAN0_FCTL_HBC1F    Header bank of CAN1 filter
: CAN0_FCTL_FLD   %1 0 lshift CAN0_FCTL bis! ;  \ CAN0_FCTL_FLD    Filter lock disable

\ CAN0_FMCFG (read-write)
: CAN0_FMCFG_FMOD27   %1 27 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD27    Filter mode
: CAN0_FMCFG_FMOD26   %1 26 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD26    Filter mode
: CAN0_FMCFG_FMOD25   %1 25 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD25    Filter mode
: CAN0_FMCFG_FMOD24   %1 24 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD24    Filter mode
: CAN0_FMCFG_FMOD23   %1 23 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD23    Filter mode
: CAN0_FMCFG_FMOD22   %1 22 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD22    Filter mode
: CAN0_FMCFG_FMOD21   %1 21 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD21    Filter mode
: CAN0_FMCFG_FMOD20   %1 20 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD20    Filter mode
: CAN0_FMCFG_FMOD19   %1 19 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD19    Filter mode
: CAN0_FMCFG_FMOD18   %1 18 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD18    Filter mode
: CAN0_FMCFG_FMOD17   %1 17 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD17    Filter mode
: CAN0_FMCFG_FMOD16   %1 16 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD16    Filter mode
: CAN0_FMCFG_FMOD15   %1 15 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD15    Filter mode
: CAN0_FMCFG_FMOD14   %1 14 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD14    Filter mode
: CAN0_FMCFG_FMOD13   %1 13 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD13    Filter mode
: CAN0_FMCFG_FMOD12   %1 12 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD12    Filter mode
: CAN0_FMCFG_FMOD11   %1 11 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD11    Filter mode
: CAN0_FMCFG_FMOD10   %1 10 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD10    Filter mode
: CAN0_FMCFG_FMOD9   %1 9 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD9    Filter mode
: CAN0_FMCFG_FMOD8   %1 8 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD8    Filter mode
: CAN0_FMCFG_FMOD7   %1 7 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD7    Filter mode
: CAN0_FMCFG_FMOD6   %1 6 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD6    Filter mode
: CAN0_FMCFG_FMOD5   %1 5 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD5    Filter mode
: CAN0_FMCFG_FMOD4   %1 4 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD4    Filter mode
: CAN0_FMCFG_FMOD3   %1 3 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD3    Filter mode
: CAN0_FMCFG_FMOD2   %1 2 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD2    Filter mode
: CAN0_FMCFG_FMOD1   %1 1 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD1    Filter mode
: CAN0_FMCFG_FMOD0   %1 0 lshift CAN0_FMCFG bis! ;  \ CAN0_FMCFG_FMOD0    Filter mode

\ CAN0_FSCFG (read-write)
: CAN0_FSCFG_FS0   %1 0 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS0    Filter scale configuration
: CAN0_FSCFG_FS1   %1 1 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS1    Filter scale configuration
: CAN0_FSCFG_FS2   %1 2 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS2    Filter scale configuration
: CAN0_FSCFG_FS3   %1 3 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS3    Filter scale configuration
: CAN0_FSCFG_FS4   %1 4 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS4    Filter scale configuration
: CAN0_FSCFG_FS5   %1 5 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS5    Filter scale configuration
: CAN0_FSCFG_FS6   %1 6 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS6    Filter scale configuration
: CAN0_FSCFG_FS7   %1 7 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS7    Filter scale configuration
: CAN0_FSCFG_FS8   %1 8 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS8    Filter scale configuration
: CAN0_FSCFG_FS9   %1 9 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS9    Filter scale configuration
: CAN0_FSCFG_FS10   %1 10 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS10    Filter scale configuration
: CAN0_FSCFG_FS11   %1 11 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS11    Filter scale configuration
: CAN0_FSCFG_FS12   %1 12 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS12    Filter scale configuration
: CAN0_FSCFG_FS13   %1 13 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS13    Filter scale configuration
: CAN0_FSCFG_FS14   %1 14 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS14    Filter scale configuration
: CAN0_FSCFG_FS15   %1 15 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS15    Filter scale configuration
: CAN0_FSCFG_FS16   %1 16 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS16    Filter scale configuration
: CAN0_FSCFG_FS17   %1 17 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS17    Filter scale configuration
: CAN0_FSCFG_FS18   %1 18 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS18    Filter scale configuration
: CAN0_FSCFG_FS19   %1 19 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS19    Filter scale configuration
: CAN0_FSCFG_FS20   %1 20 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS20    Filter scale configuration
: CAN0_FSCFG_FS21   %1 21 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS21    Filter scale configuration
: CAN0_FSCFG_FS22   %1 22 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS22    Filter scale configuration
: CAN0_FSCFG_FS23   %1 23 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS23    Filter scale configuration
: CAN0_FSCFG_FS24   %1 24 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS24    Filter scale configuration
: CAN0_FSCFG_FS25   %1 25 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS25    Filter scale configuration
: CAN0_FSCFG_FS26   %1 26 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS26    Filter scale configuration
: CAN0_FSCFG_FS27   %1 27 lshift CAN0_FSCFG bis! ;  \ CAN0_FSCFG_FS27    Filter scale configuration

\ CAN0_FAFIFO (read-write)
: CAN0_FAFIFO_FAF0   %1 0 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF0    Filter 0 associated with FIFO
: CAN0_FAFIFO_FAF1   %1 1 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF1    Filter 1 associated with FIFO
: CAN0_FAFIFO_FAF2   %1 2 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF2    Filter 2 associated with FIFO
: CAN0_FAFIFO_FAF3   %1 3 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF3    Filter 3 associated with FIFO
: CAN0_FAFIFO_FAF4   %1 4 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF4    Filter 4 associated with FIFO
: CAN0_FAFIFO_FAF5   %1 5 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF5    Filter 5 associated with FIFO
: CAN0_FAFIFO_FAF6   %1 6 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF6    Filter 6 associated with FIFO
: CAN0_FAFIFO_FAF7   %1 7 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF7    Filter 7 associated with FIFO
: CAN0_FAFIFO_FAF8   %1 8 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF8    Filter 8 associated with FIFO
: CAN0_FAFIFO_FAF9   %1 9 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF9    Filter 9 associated with FIFO
: CAN0_FAFIFO_FAF10   %1 10 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF10    Filter 10 associated with FIFO
: CAN0_FAFIFO_FAF11   %1 11 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF11    Filter 11 associated with FIFO
: CAN0_FAFIFO_FAF12   %1 12 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF12    Filter 12 associated with FIFO
: CAN0_FAFIFO_FAF13   %1 13 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF13    Filter 13 associated with FIFO
: CAN0_FAFIFO_FAF14   %1 14 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF14    Filter 14 associated with FIFO
: CAN0_FAFIFO_FAF15   %1 15 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF15    Filter 15 associated with FIFO
: CAN0_FAFIFO_FAF16   %1 16 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF16    Filter 16 associated with FIFO
: CAN0_FAFIFO_FAF17   %1 17 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF17    Filter 17 associated with FIFO
: CAN0_FAFIFO_FAF18   %1 18 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF18    Filter 18 associated with FIFO
: CAN0_FAFIFO_FAF19   %1 19 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF19    Filter 19 associated with FIFO
: CAN0_FAFIFO_FAF20   %1 20 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF20    Filter 20 associated with FIFO
: CAN0_FAFIFO_FAF21   %1 21 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF21    Filter 21 associated with FIFO
: CAN0_FAFIFO_FAF22   %1 22 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF22    Filter 22 associated with FIFO
: CAN0_FAFIFO_FAF23   %1 23 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF23    Filter 23 associated with FIFO
: CAN0_FAFIFO_FAF24   %1 24 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF24    Filter 24 associated with FIFO
: CAN0_FAFIFO_FAF25   %1 25 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF25    Filter 25 associated with FIFO
: CAN0_FAFIFO_FAF26   %1 26 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF26    Filter 26 associated with FIFO
: CAN0_FAFIFO_FAF27   %1 27 lshift CAN0_FAFIFO bis! ;  \ CAN0_FAFIFO_FAF27    Filter 27 associated with FIFO

\ CAN0_FW (read-write)
: CAN0_FW_FW0   %1 0 lshift CAN0_FW bis! ;  \ CAN0_FW_FW0    Filter working
: CAN0_FW_FW1   %1 1 lshift CAN0_FW bis! ;  \ CAN0_FW_FW1    Filter working
: CAN0_FW_FW2   %1 2 lshift CAN0_FW bis! ;  \ CAN0_FW_FW2    Filter working
: CAN0_FW_FW3   %1 3 lshift CAN0_FW bis! ;  \ CAN0_FW_FW3    Filter working
: CAN0_FW_FW4   %1 4 lshift CAN0_FW bis! ;  \ CAN0_FW_FW4    Filter working
: CAN0_FW_FW5   %1 5 lshift CAN0_FW bis! ;  \ CAN0_FW_FW5    Filter working
: CAN0_FW_FW6   %1 6 lshift CAN0_FW bis! ;  \ CAN0_FW_FW6    Filter working
: CAN0_FW_FW7   %1 7 lshift CAN0_FW bis! ;  \ CAN0_FW_FW7    Filter working
: CAN0_FW_FW8   %1 8 lshift CAN0_FW bis! ;  \ CAN0_FW_FW8    Filter working
: CAN0_FW_FW9   %1 9 lshift CAN0_FW bis! ;  \ CAN0_FW_FW9    Filter working
: CAN0_FW_FW10   %1 10 lshift CAN0_FW bis! ;  \ CAN0_FW_FW10    Filter working
: CAN0_FW_FW11   %1 11 lshift CAN0_FW bis! ;  \ CAN0_FW_FW11    Filter working
: CAN0_FW_FW12   %1 12 lshift CAN0_FW bis! ;  \ CAN0_FW_FW12    Filter working
: CAN0_FW_FW13   %1 13 lshift CAN0_FW bis! ;  \ CAN0_FW_FW13    Filter working
: CAN0_FW_FW14   %1 14 lshift CAN0_FW bis! ;  \ CAN0_FW_FW14    Filter working
: CAN0_FW_FW15   %1 15 lshift CAN0_FW bis! ;  \ CAN0_FW_FW15    Filter working
: CAN0_FW_FW16   %1 16 lshift CAN0_FW bis! ;  \ CAN0_FW_FW16    Filter working
: CAN0_FW_FW17   %1 17 lshift CAN0_FW bis! ;  \ CAN0_FW_FW17    Filter working
: CAN0_FW_FW18   %1 18 lshift CAN0_FW bis! ;  \ CAN0_FW_FW18    Filter working
: CAN0_FW_FW19   %1 19 lshift CAN0_FW bis! ;  \ CAN0_FW_FW19    Filter working
: CAN0_FW_FW20   %1 20 lshift CAN0_FW bis! ;  \ CAN0_FW_FW20    Filter working
: CAN0_FW_FW21   %1 21 lshift CAN0_FW bis! ;  \ CAN0_FW_FW21    Filter working
: CAN0_FW_FW22   %1 22 lshift CAN0_FW bis! ;  \ CAN0_FW_FW22    Filter working
: CAN0_FW_FW23   %1 23 lshift CAN0_FW bis! ;  \ CAN0_FW_FW23    Filter working
: CAN0_FW_FW24   %1 24 lshift CAN0_FW bis! ;  \ CAN0_FW_FW24    Filter working
: CAN0_FW_FW25   %1 25 lshift CAN0_FW bis! ;  \ CAN0_FW_FW25    Filter working
: CAN0_FW_FW26   %1 26 lshift CAN0_FW bis! ;  \ CAN0_FW_FW26    Filter working
: CAN0_FW_FW27   %1 27 lshift CAN0_FW bis! ;  \ CAN0_FW_FW27    Filter working

\ CAN0_F0DATA0 (read-write)
: CAN0_F0DATA0_FD0   %1 0 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD0    Filter bits
: CAN0_F0DATA0_FD1   %1 1 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD1    Filter bits
: CAN0_F0DATA0_FD2   %1 2 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD2    Filter bits
: CAN0_F0DATA0_FD3   %1 3 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD3    Filter bits
: CAN0_F0DATA0_FD4   %1 4 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD4    Filter bits
: CAN0_F0DATA0_FD5   %1 5 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD5    Filter bits
: CAN0_F0DATA0_FD6   %1 6 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD6    Filter bits
: CAN0_F0DATA0_FD7   %1 7 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD7    Filter bits
: CAN0_F0DATA0_FD8   %1 8 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD8    Filter bits
: CAN0_F0DATA0_FD9   %1 9 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD9    Filter bits
: CAN0_F0DATA0_FD10   %1 10 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD10    Filter bits
: CAN0_F0DATA0_FD11   %1 11 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD11    Filter bits
: CAN0_F0DATA0_FD12   %1 12 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD12    Filter bits
: CAN0_F0DATA0_FD13   %1 13 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD13    Filter bits
: CAN0_F0DATA0_FD14   %1 14 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD14    Filter bits
: CAN0_F0DATA0_FD15   %1 15 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD15    Filter bits
: CAN0_F0DATA0_FD16   %1 16 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD16    Filter bits
: CAN0_F0DATA0_FD17   %1 17 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD17    Filter bits
: CAN0_F0DATA0_FD18   %1 18 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD18    Filter bits
: CAN0_F0DATA0_FD19   %1 19 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD19    Filter bits
: CAN0_F0DATA0_FD20   %1 20 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD20    Filter bits
: CAN0_F0DATA0_FD21   %1 21 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD21    Filter bits
: CAN0_F0DATA0_FD22   %1 22 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD22    Filter bits
: CAN0_F0DATA0_FD23   %1 23 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD23    Filter bits
: CAN0_F0DATA0_FD24   %1 24 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD24    Filter bits
: CAN0_F0DATA0_FD25   %1 25 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD25    Filter bits
: CAN0_F0DATA0_FD26   %1 26 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD26    Filter bits
: CAN0_F0DATA0_FD27   %1 27 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD27    Filter bits
: CAN0_F0DATA0_FD28   %1 28 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD28    Filter bits
: CAN0_F0DATA0_FD29   %1 29 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD29    Filter bits
: CAN0_F0DATA0_FD30   %1 30 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD30    Filter bits
: CAN0_F0DATA0_FD31   %1 31 lshift CAN0_F0DATA0 bis! ;  \ CAN0_F0DATA0_FD31    Filter bits

\ CAN0_F0DATA1 (read-write)
: CAN0_F0DATA1_FD0   %1 0 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD0    Filter bits
: CAN0_F0DATA1_FD1   %1 1 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD1    Filter bits
: CAN0_F0DATA1_FD2   %1 2 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD2    Filter bits
: CAN0_F0DATA1_FD3   %1 3 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD3    Filter bits
: CAN0_F0DATA1_FD4   %1 4 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD4    Filter bits
: CAN0_F0DATA1_FD5   %1 5 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD5    Filter bits
: CAN0_F0DATA1_FD6   %1 6 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD6    Filter bits
: CAN0_F0DATA1_FD7   %1 7 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD7    Filter bits
: CAN0_F0DATA1_FD8   %1 8 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD8    Filter bits
: CAN0_F0DATA1_FD9   %1 9 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD9    Filter bits
: CAN0_F0DATA1_FD10   %1 10 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD10    Filter bits
: CAN0_F0DATA1_FD11   %1 11 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD11    Filter bits
: CAN0_F0DATA1_FD12   %1 12 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD12    Filter bits
: CAN0_F0DATA1_FD13   %1 13 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD13    Filter bits
: CAN0_F0DATA1_FD14   %1 14 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD14    Filter bits
: CAN0_F0DATA1_FD15   %1 15 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD15    Filter bits
: CAN0_F0DATA1_FD16   %1 16 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD16    Filter bits
: CAN0_F0DATA1_FD17   %1 17 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD17    Filter bits
: CAN0_F0DATA1_FD18   %1 18 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD18    Filter bits
: CAN0_F0DATA1_FD19   %1 19 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD19    Filter bits
: CAN0_F0DATA1_FD20   %1 20 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD20    Filter bits
: CAN0_F0DATA1_FD21   %1 21 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD21    Filter bits
: CAN0_F0DATA1_FD22   %1 22 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD22    Filter bits
: CAN0_F0DATA1_FD23   %1 23 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD23    Filter bits
: CAN0_F0DATA1_FD24   %1 24 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD24    Filter bits
: CAN0_F0DATA1_FD25   %1 25 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD25    Filter bits
: CAN0_F0DATA1_FD26   %1 26 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD26    Filter bits
: CAN0_F0DATA1_FD27   %1 27 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD27    Filter bits
: CAN0_F0DATA1_FD28   %1 28 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD28    Filter bits
: CAN0_F0DATA1_FD29   %1 29 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD29    Filter bits
: CAN0_F0DATA1_FD30   %1 30 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD30    Filter bits
: CAN0_F0DATA1_FD31   %1 31 lshift CAN0_F0DATA1 bis! ;  \ CAN0_F0DATA1_FD31    Filter bits

\ CAN0_F1DATA0 (read-write)
: CAN0_F1DATA0_FD0   %1 0 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD0    Filter bits
: CAN0_F1DATA0_FD1   %1 1 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD1    Filter bits
: CAN0_F1DATA0_FD2   %1 2 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD2    Filter bits
: CAN0_F1DATA0_FD3   %1 3 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD3    Filter bits
: CAN0_F1DATA0_FD4   %1 4 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD4    Filter bits
: CAN0_F1DATA0_FD5   %1 5 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD5    Filter bits
: CAN0_F1DATA0_FD6   %1 6 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD6    Filter bits
: CAN0_F1DATA0_FD7   %1 7 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD7    Filter bits
: CAN0_F1DATA0_FD8   %1 8 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD8    Filter bits
: CAN0_F1DATA0_FD9   %1 9 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD9    Filter bits
: CAN0_F1DATA0_FD10   %1 10 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD10    Filter bits
: CAN0_F1DATA0_FD11   %1 11 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD11    Filter bits
: CAN0_F1DATA0_FD12   %1 12 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD12    Filter bits
: CAN0_F1DATA0_FD13   %1 13 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD13    Filter bits
: CAN0_F1DATA0_FD14   %1 14 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD14    Filter bits
: CAN0_F1DATA0_FD15   %1 15 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD15    Filter bits
: CAN0_F1DATA0_FD16   %1 16 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD16    Filter bits
: CAN0_F1DATA0_FD17   %1 17 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD17    Filter bits
: CAN0_F1DATA0_FD18   %1 18 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD18    Filter bits
: CAN0_F1DATA0_FD19   %1 19 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD19    Filter bits
: CAN0_F1DATA0_FD20   %1 20 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD20    Filter bits
: CAN0_F1DATA0_FD21   %1 21 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD21    Filter bits
: CAN0_F1DATA0_FD22   %1 22 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD22    Filter bits
: CAN0_F1DATA0_FD23   %1 23 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD23    Filter bits
: CAN0_F1DATA0_FD24   %1 24 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD24    Filter bits
: CAN0_F1DATA0_FD25   %1 25 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD25    Filter bits
: CAN0_F1DATA0_FD26   %1 26 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD26    Filter bits
: CAN0_F1DATA0_FD27   %1 27 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD27    Filter bits
: CAN0_F1DATA0_FD28   %1 28 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD28    Filter bits
: CAN0_F1DATA0_FD29   %1 29 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD29    Filter bits
: CAN0_F1DATA0_FD30   %1 30 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD30    Filter bits
: CAN0_F1DATA0_FD31   %1 31 lshift CAN0_F1DATA0 bis! ;  \ CAN0_F1DATA0_FD31    Filter bits

\ CAN0_F1DATA1 (read-write)
: CAN0_F1DATA1_FD0   %1 0 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD0    Filter bits
: CAN0_F1DATA1_FD1   %1 1 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD1    Filter bits
: CAN0_F1DATA1_FD2   %1 2 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD2    Filter bits
: CAN0_F1DATA1_FD3   %1 3 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD3    Filter bits
: CAN0_F1DATA1_FD4   %1 4 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD4    Filter bits
: CAN0_F1DATA1_FD5   %1 5 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD5    Filter bits
: CAN0_F1DATA1_FD6   %1 6 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD6    Filter bits
: CAN0_F1DATA1_FD7   %1 7 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD7    Filter bits
: CAN0_F1DATA1_FD8   %1 8 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD8    Filter bits
: CAN0_F1DATA1_FD9   %1 9 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD9    Filter bits
: CAN0_F1DATA1_FD10   %1 10 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD10    Filter bits
: CAN0_F1DATA1_FD11   %1 11 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD11    Filter bits
: CAN0_F1DATA1_FD12   %1 12 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD12    Filter bits
: CAN0_F1DATA1_FD13   %1 13 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD13    Filter bits
: CAN0_F1DATA1_FD14   %1 14 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD14    Filter bits
: CAN0_F1DATA1_FD15   %1 15 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD15    Filter bits
: CAN0_F1DATA1_FD16   %1 16 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD16    Filter bits
: CAN0_F1DATA1_FD17   %1 17 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD17    Filter bits
: CAN0_F1DATA1_FD18   %1 18 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD18    Filter bits
: CAN0_F1DATA1_FD19   %1 19 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD19    Filter bits
: CAN0_F1DATA1_FD20   %1 20 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD20    Filter bits
: CAN0_F1DATA1_FD21   %1 21 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD21    Filter bits
: CAN0_F1DATA1_FD22   %1 22 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD22    Filter bits
: CAN0_F1DATA1_FD23   %1 23 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD23    Filter bits
: CAN0_F1DATA1_FD24   %1 24 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD24    Filter bits
: CAN0_F1DATA1_FD25   %1 25 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD25    Filter bits
: CAN0_F1DATA1_FD26   %1 26 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD26    Filter bits
: CAN0_F1DATA1_FD27   %1 27 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD27    Filter bits
: CAN0_F1DATA1_FD28   %1 28 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD28    Filter bits
: CAN0_F1DATA1_FD29   %1 29 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD29    Filter bits
: CAN0_F1DATA1_FD30   %1 30 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD30    Filter bits
: CAN0_F1DATA1_FD31   %1 31 lshift CAN0_F1DATA1 bis! ;  \ CAN0_F1DATA1_FD31    Filter bits

\ CAN0_F2DATA0 (read-write)
: CAN0_F2DATA0_FD0   %1 0 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD0    Filter bits
: CAN0_F2DATA0_FD1   %1 1 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD1    Filter bits
: CAN0_F2DATA0_FD2   %1 2 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD2    Filter bits
: CAN0_F2DATA0_FD3   %1 3 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD3    Filter bits
: CAN0_F2DATA0_FD4   %1 4 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD4    Filter bits
: CAN0_F2DATA0_FD5   %1 5 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD5    Filter bits
: CAN0_F2DATA0_FD6   %1 6 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD6    Filter bits
: CAN0_F2DATA0_FD7   %1 7 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD7    Filter bits
: CAN0_F2DATA0_FD8   %1 8 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD8    Filter bits
: CAN0_F2DATA0_FD9   %1 9 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD9    Filter bits
: CAN0_F2DATA0_FD10   %1 10 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD10    Filter bits
: CAN0_F2DATA0_FD11   %1 11 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD11    Filter bits
: CAN0_F2DATA0_FD12   %1 12 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD12    Filter bits
: CAN0_F2DATA0_FD13   %1 13 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD13    Filter bits
: CAN0_F2DATA0_FD14   %1 14 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD14    Filter bits
: CAN0_F2DATA0_FD15   %1 15 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD15    Filter bits
: CAN0_F2DATA0_FD16   %1 16 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD16    Filter bits
: CAN0_F2DATA0_FD17   %1 17 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD17    Filter bits
: CAN0_F2DATA0_FD18   %1 18 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD18    Filter bits
: CAN0_F2DATA0_FD19   %1 19 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD19    Filter bits
: CAN0_F2DATA0_FD20   %1 20 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD20    Filter bits
: CAN0_F2DATA0_FD21   %1 21 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD21    Filter bits
: CAN0_F2DATA0_FD22   %1 22 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD22    Filter bits
: CAN0_F2DATA0_FD23   %1 23 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD23    Filter bits
: CAN0_F2DATA0_FD24   %1 24 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD24    Filter bits
: CAN0_F2DATA0_FD25   %1 25 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD25    Filter bits
: CAN0_F2DATA0_FD26   %1 26 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD26    Filter bits
: CAN0_F2DATA0_FD27   %1 27 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD27    Filter bits
: CAN0_F2DATA0_FD28   %1 28 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD28    Filter bits
: CAN0_F2DATA0_FD29   %1 29 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD29    Filter bits
: CAN0_F2DATA0_FD30   %1 30 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD30    Filter bits
: CAN0_F2DATA0_FD31   %1 31 lshift CAN0_F2DATA0 bis! ;  \ CAN0_F2DATA0_FD31    Filter bits

\ CAN0_F2DATA1 (read-write)
: CAN0_F2DATA1_FD0   %1 0 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD0    Filter bits
: CAN0_F2DATA1_FD1   %1 1 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD1    Filter bits
: CAN0_F2DATA1_FD2   %1 2 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD2    Filter bits
: CAN0_F2DATA1_FD3   %1 3 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD3    Filter bits
: CAN0_F2DATA1_FD4   %1 4 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD4    Filter bits
: CAN0_F2DATA1_FD5   %1 5 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD5    Filter bits
: CAN0_F2DATA1_FD6   %1 6 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD6    Filter bits
: CAN0_F2DATA1_FD7   %1 7 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD7    Filter bits
: CAN0_F2DATA1_FD8   %1 8 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD8    Filter bits
: CAN0_F2DATA1_FD9   %1 9 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD9    Filter bits
: CAN0_F2DATA1_FD10   %1 10 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD10    Filter bits
: CAN0_F2DATA1_FD11   %1 11 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD11    Filter bits
: CAN0_F2DATA1_FD12   %1 12 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD12    Filter bits
: CAN0_F2DATA1_FD13   %1 13 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD13    Filter bits
: CAN0_F2DATA1_FD14   %1 14 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD14    Filter bits
: CAN0_F2DATA1_FD15   %1 15 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD15    Filter bits
: CAN0_F2DATA1_FD16   %1 16 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD16    Filter bits
: CAN0_F2DATA1_FD17   %1 17 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD17    Filter bits
: CAN0_F2DATA1_FD18   %1 18 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD18    Filter bits
: CAN0_F2DATA1_FD19   %1 19 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD19    Filter bits
: CAN0_F2DATA1_FD20   %1 20 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD20    Filter bits
: CAN0_F2DATA1_FD21   %1 21 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD21    Filter bits
: CAN0_F2DATA1_FD22   %1 22 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD22    Filter bits
: CAN0_F2DATA1_FD23   %1 23 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD23    Filter bits
: CAN0_F2DATA1_FD24   %1 24 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD24    Filter bits
: CAN0_F2DATA1_FD25   %1 25 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD25    Filter bits
: CAN0_F2DATA1_FD26   %1 26 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD26    Filter bits
: CAN0_F2DATA1_FD27   %1 27 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD27    Filter bits
: CAN0_F2DATA1_FD28   %1 28 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD28    Filter bits
: CAN0_F2DATA1_FD29   %1 29 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD29    Filter bits
: CAN0_F2DATA1_FD30   %1 30 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD30    Filter bits
: CAN0_F2DATA1_FD31   %1 31 lshift CAN0_F2DATA1 bis! ;  \ CAN0_F2DATA1_FD31    Filter bits

\ CAN0_F3DATA0 (read-write)
: CAN0_F3DATA0_FD0   %1 0 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD0    Filter bits
: CAN0_F3DATA0_FD1   %1 1 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD1    Filter bits
: CAN0_F3DATA0_FD2   %1 2 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD2    Filter bits
: CAN0_F3DATA0_FD3   %1 3 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD3    Filter bits
: CAN0_F3DATA0_FD4   %1 4 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD4    Filter bits
: CAN0_F3DATA0_FD5   %1 5 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD5    Filter bits
: CAN0_F3DATA0_FD6   %1 6 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD6    Filter bits
: CAN0_F3DATA0_FD7   %1 7 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD7    Filter bits
: CAN0_F3DATA0_FD8   %1 8 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD8    Filter bits
: CAN0_F3DATA0_FD9   %1 9 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD9    Filter bits
: CAN0_F3DATA0_FD10   %1 10 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD10    Filter bits
: CAN0_F3DATA0_FD11   %1 11 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD11    Filter bits
: CAN0_F3DATA0_FD12   %1 12 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD12    Filter bits
: CAN0_F3DATA0_FD13   %1 13 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD13    Filter bits
: CAN0_F3DATA0_FD14   %1 14 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD14    Filter bits
: CAN0_F3DATA0_FD15   %1 15 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD15    Filter bits
: CAN0_F3DATA0_FD16   %1 16 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD16    Filter bits
: CAN0_F3DATA0_FD17   %1 17 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD17    Filter bits
: CAN0_F3DATA0_FD18   %1 18 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD18    Filter bits
: CAN0_F3DATA0_FD19   %1 19 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD19    Filter bits
: CAN0_F3DATA0_FD20   %1 20 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD20    Filter bits
: CAN0_F3DATA0_FD21   %1 21 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD21    Filter bits
: CAN0_F3DATA0_FD22   %1 22 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD22    Filter bits
: CAN0_F3DATA0_FD23   %1 23 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD23    Filter bits
: CAN0_F3DATA0_FD24   %1 24 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD24    Filter bits
: CAN0_F3DATA0_FD25   %1 25 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD25    Filter bits
: CAN0_F3DATA0_FD26   %1 26 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD26    Filter bits
: CAN0_F3DATA0_FD27   %1 27 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD27    Filter bits
: CAN0_F3DATA0_FD28   %1 28 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD28    Filter bits
: CAN0_F3DATA0_FD29   %1 29 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD29    Filter bits
: CAN0_F3DATA0_FD30   %1 30 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD30    Filter bits
: CAN0_F3DATA0_FD31   %1 31 lshift CAN0_F3DATA0 bis! ;  \ CAN0_F3DATA0_FD31    Filter bits

\ CAN0_F3DATA1 (read-write)
: CAN0_F3DATA1_FD0   %1 0 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD0    Filter bits
: CAN0_F3DATA1_FD1   %1 1 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD1    Filter bits
: CAN0_F3DATA1_FD2   %1 2 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD2    Filter bits
: CAN0_F3DATA1_FD3   %1 3 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD3    Filter bits
: CAN0_F3DATA1_FD4   %1 4 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD4    Filter bits
: CAN0_F3DATA1_FD5   %1 5 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD5    Filter bits
: CAN0_F3DATA1_FD6   %1 6 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD6    Filter bits
: CAN0_F3DATA1_FD7   %1 7 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD7    Filter bits
: CAN0_F3DATA1_FD8   %1 8 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD8    Filter bits
: CAN0_F3DATA1_FD9   %1 9 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD9    Filter bits
: CAN0_F3DATA1_FD10   %1 10 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD10    Filter bits
: CAN0_F3DATA1_FD11   %1 11 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD11    Filter bits
: CAN0_F3DATA1_FD12   %1 12 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD12    Filter bits
: CAN0_F3DATA1_FD13   %1 13 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD13    Filter bits
: CAN0_F3DATA1_FD14   %1 14 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD14    Filter bits
: CAN0_F3DATA1_FD15   %1 15 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD15    Filter bits
: CAN0_F3DATA1_FD16   %1 16 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD16    Filter bits
: CAN0_F3DATA1_FD17   %1 17 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD17    Filter bits
: CAN0_F3DATA1_FD18   %1 18 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD18    Filter bits
: CAN0_F3DATA1_FD19   %1 19 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD19    Filter bits
: CAN0_F3DATA1_FD20   %1 20 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD20    Filter bits
: CAN0_F3DATA1_FD21   %1 21 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD21    Filter bits
: CAN0_F3DATA1_FD22   %1 22 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD22    Filter bits
: CAN0_F3DATA1_FD23   %1 23 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD23    Filter bits
: CAN0_F3DATA1_FD24   %1 24 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD24    Filter bits
: CAN0_F3DATA1_FD25   %1 25 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD25    Filter bits
: CAN0_F3DATA1_FD26   %1 26 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD26    Filter bits
: CAN0_F3DATA1_FD27   %1 27 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD27    Filter bits
: CAN0_F3DATA1_FD28   %1 28 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD28    Filter bits
: CAN0_F3DATA1_FD29   %1 29 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD29    Filter bits
: CAN0_F3DATA1_FD30   %1 30 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD30    Filter bits
: CAN0_F3DATA1_FD31   %1 31 lshift CAN0_F3DATA1 bis! ;  \ CAN0_F3DATA1_FD31    Filter bits

\ CAN0_F4DATA0 (read-write)
: CAN0_F4DATA0_FD0   %1 0 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD0    Filter bits
: CAN0_F4DATA0_FD1   %1 1 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD1    Filter bits
: CAN0_F4DATA0_FD2   %1 2 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD2    Filter bits
: CAN0_F4DATA0_FD3   %1 3 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD3    Filter bits
: CAN0_F4DATA0_FD4   %1 4 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD4    Filter bits
: CAN0_F4DATA0_FD5   %1 5 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD5    Filter bits
: CAN0_F4DATA0_FD6   %1 6 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD6    Filter bits
: CAN0_F4DATA0_FD7   %1 7 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD7    Filter bits
: CAN0_F4DATA0_FD8   %1 8 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD8    Filter bits
: CAN0_F4DATA0_FD9   %1 9 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD9    Filter bits
: CAN0_F4DATA0_FD10   %1 10 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD10    Filter bits
: CAN0_F4DATA0_FD11   %1 11 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD11    Filter bits
: CAN0_F4DATA0_FD12   %1 12 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD12    Filter bits
: CAN0_F4DATA0_FD13   %1 13 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD13    Filter bits
: CAN0_F4DATA0_FD14   %1 14 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD14    Filter bits
: CAN0_F4DATA0_FD15   %1 15 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD15    Filter bits
: CAN0_F4DATA0_FD16   %1 16 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD16    Filter bits
: CAN0_F4DATA0_FD17   %1 17 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD17    Filter bits
: CAN0_F4DATA0_FD18   %1 18 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD18    Filter bits
: CAN0_F4DATA0_FD19   %1 19 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD19    Filter bits
: CAN0_F4DATA0_FD20   %1 20 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD20    Filter bits
: CAN0_F4DATA0_FD21   %1 21 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD21    Filter bits
: CAN0_F4DATA0_FD22   %1 22 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD22    Filter bits
: CAN0_F4DATA0_FD23   %1 23 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD23    Filter bits
: CAN0_F4DATA0_FD24   %1 24 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD24    Filter bits
: CAN0_F4DATA0_FD25   %1 25 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD25    Filter bits
: CAN0_F4DATA0_FD26   %1 26 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD26    Filter bits
: CAN0_F4DATA0_FD27   %1 27 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD27    Filter bits
: CAN0_F4DATA0_FD28   %1 28 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD28    Filter bits
: CAN0_F4DATA0_FD29   %1 29 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD29    Filter bits
: CAN0_F4DATA0_FD30   %1 30 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD30    Filter bits
: CAN0_F4DATA0_FD31   %1 31 lshift CAN0_F4DATA0 bis! ;  \ CAN0_F4DATA0_FD31    Filter bits

\ CAN0_F4DATA1 (read-write)
: CAN0_F4DATA1_FD0   %1 0 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD0    Filter bits
: CAN0_F4DATA1_FD1   %1 1 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD1    Filter bits
: CAN0_F4DATA1_FD2   %1 2 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD2    Filter bits
: CAN0_F4DATA1_FD3   %1 3 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD3    Filter bits
: CAN0_F4DATA1_FD4   %1 4 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD4    Filter bits
: CAN0_F4DATA1_FD5   %1 5 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD5    Filter bits
: CAN0_F4DATA1_FD6   %1 6 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD6    Filter bits
: CAN0_F4DATA1_FD7   %1 7 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD7    Filter bits
: CAN0_F4DATA1_FD8   %1 8 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD8    Filter bits
: CAN0_F4DATA1_FD9   %1 9 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD9    Filter bits
: CAN0_F4DATA1_FD10   %1 10 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD10    Filter bits
: CAN0_F4DATA1_FD11   %1 11 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD11    Filter bits
: CAN0_F4DATA1_FD12   %1 12 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD12    Filter bits
: CAN0_F4DATA1_FD13   %1 13 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD13    Filter bits
: CAN0_F4DATA1_FD14   %1 14 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD14    Filter bits
: CAN0_F4DATA1_FD15   %1 15 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD15    Filter bits
: CAN0_F4DATA1_FD16   %1 16 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD16    Filter bits
: CAN0_F4DATA1_FD17   %1 17 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD17    Filter bits
: CAN0_F4DATA1_FD18   %1 18 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD18    Filter bits
: CAN0_F4DATA1_FD19   %1 19 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD19    Filter bits
: CAN0_F4DATA1_FD20   %1 20 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD20    Filter bits
: CAN0_F4DATA1_FD21   %1 21 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD21    Filter bits
: CAN0_F4DATA1_FD22   %1 22 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD22    Filter bits
: CAN0_F4DATA1_FD23   %1 23 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD23    Filter bits
: CAN0_F4DATA1_FD24   %1 24 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD24    Filter bits
: CAN0_F4DATA1_FD25   %1 25 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD25    Filter bits
: CAN0_F4DATA1_FD26   %1 26 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD26    Filter bits
: CAN0_F4DATA1_FD27   %1 27 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD27    Filter bits
: CAN0_F4DATA1_FD28   %1 28 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD28    Filter bits
: CAN0_F4DATA1_FD29   %1 29 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD29    Filter bits
: CAN0_F4DATA1_FD30   %1 30 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD30    Filter bits
: CAN0_F4DATA1_FD31   %1 31 lshift CAN0_F4DATA1 bis! ;  \ CAN0_F4DATA1_FD31    Filter bits

\ CAN0_F5DATA0 (read-write)
: CAN0_F5DATA0_FD0   %1 0 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD0    Filter bits
: CAN0_F5DATA0_FD1   %1 1 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD1    Filter bits
: CAN0_F5DATA0_FD2   %1 2 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD2    Filter bits
: CAN0_F5DATA0_FD3   %1 3 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD3    Filter bits
: CAN0_F5DATA0_FD4   %1 4 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD4    Filter bits
: CAN0_F5DATA0_FD5   %1 5 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD5    Filter bits
: CAN0_F5DATA0_FD6   %1 6 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD6    Filter bits
: CAN0_F5DATA0_FD7   %1 7 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD7    Filter bits
: CAN0_F5DATA0_FD8   %1 8 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD8    Filter bits
: CAN0_F5DATA0_FD9   %1 9 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD9    Filter bits
: CAN0_F5DATA0_FD10   %1 10 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD10    Filter bits
: CAN0_F5DATA0_FD11   %1 11 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD11    Filter bits
: CAN0_F5DATA0_FD12   %1 12 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD12    Filter bits
: CAN0_F5DATA0_FD13   %1 13 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD13    Filter bits
: CAN0_F5DATA0_FD14   %1 14 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD14    Filter bits
: CAN0_F5DATA0_FD15   %1 15 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD15    Filter bits
: CAN0_F5DATA0_FD16   %1 16 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD16    Filter bits
: CAN0_F5DATA0_FD17   %1 17 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD17    Filter bits
: CAN0_F5DATA0_FD18   %1 18 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD18    Filter bits
: CAN0_F5DATA0_FD19   %1 19 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD19    Filter bits
: CAN0_F5DATA0_FD20   %1 20 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD20    Filter bits
: CAN0_F5DATA0_FD21   %1 21 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD21    Filter bits
: CAN0_F5DATA0_FD22   %1 22 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD22    Filter bits
: CAN0_F5DATA0_FD23   %1 23 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD23    Filter bits
: CAN0_F5DATA0_FD24   %1 24 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD24    Filter bits
: CAN0_F5DATA0_FD25   %1 25 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD25    Filter bits
: CAN0_F5DATA0_FD26   %1 26 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD26    Filter bits
: CAN0_F5DATA0_FD27   %1 27 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD27    Filter bits
: CAN0_F5DATA0_FD28   %1 28 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD28    Filter bits
: CAN0_F5DATA0_FD29   %1 29 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD29    Filter bits
: CAN0_F5DATA0_FD30   %1 30 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD30    Filter bits
: CAN0_F5DATA0_FD31   %1 31 lshift CAN0_F5DATA0 bis! ;  \ CAN0_F5DATA0_FD31    Filter bits

\ CAN0_F5DATA1 (read-write)
: CAN0_F5DATA1_FD0   %1 0 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD0    Filter bits
: CAN0_F5DATA1_FD1   %1 1 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD1    Filter bits
: CAN0_F5DATA1_FD2   %1 2 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD2    Filter bits
: CAN0_F5DATA1_FD3   %1 3 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD3    Filter bits
: CAN0_F5DATA1_FD4   %1 4 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD4    Filter bits
: CAN0_F5DATA1_FD5   %1 5 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD5    Filter bits
: CAN0_F5DATA1_FD6   %1 6 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD6    Filter bits
: CAN0_F5DATA1_FD7   %1 7 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD7    Filter bits
: CAN0_F5DATA1_FD8   %1 8 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD8    Filter bits
: CAN0_F5DATA1_FD9   %1 9 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD9    Filter bits
: CAN0_F5DATA1_FD10   %1 10 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD10    Filter bits
: CAN0_F5DATA1_FD11   %1 11 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD11    Filter bits
: CAN0_F5DATA1_FD12   %1 12 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD12    Filter bits
: CAN0_F5DATA1_FD13   %1 13 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD13    Filter bits
: CAN0_F5DATA1_FD14   %1 14 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD14    Filter bits
: CAN0_F5DATA1_FD15   %1 15 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD15    Filter bits
: CAN0_F5DATA1_FD16   %1 16 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD16    Filter bits
: CAN0_F5DATA1_FD17   %1 17 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD17    Filter bits
: CAN0_F5DATA1_FD18   %1 18 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD18    Filter bits
: CAN0_F5DATA1_FD19   %1 19 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD19    Filter bits
: CAN0_F5DATA1_FD20   %1 20 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD20    Filter bits
: CAN0_F5DATA1_FD21   %1 21 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD21    Filter bits
: CAN0_F5DATA1_FD22   %1 22 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD22    Filter bits
: CAN0_F5DATA1_FD23   %1 23 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD23    Filter bits
: CAN0_F5DATA1_FD24   %1 24 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD24    Filter bits
: CAN0_F5DATA1_FD25   %1 25 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD25    Filter bits
: CAN0_F5DATA1_FD26   %1 26 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD26    Filter bits
: CAN0_F5DATA1_FD27   %1 27 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD27    Filter bits
: CAN0_F5DATA1_FD28   %1 28 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD28    Filter bits
: CAN0_F5DATA1_FD29   %1 29 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD29    Filter bits
: CAN0_F5DATA1_FD30   %1 30 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD30    Filter bits
: CAN0_F5DATA1_FD31   %1 31 lshift CAN0_F5DATA1 bis! ;  \ CAN0_F5DATA1_FD31    Filter bits

\ CAN0_F6DATA0 (read-write)
: CAN0_F6DATA0_FD0   %1 0 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD0    Filter bits
: CAN0_F6DATA0_FD1   %1 1 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD1    Filter bits
: CAN0_F6DATA0_FD2   %1 2 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD2    Filter bits
: CAN0_F6DATA0_FD3   %1 3 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD3    Filter bits
: CAN0_F6DATA0_FD4   %1 4 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD4    Filter bits
: CAN0_F6DATA0_FD5   %1 5 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD5    Filter bits
: CAN0_F6DATA0_FD6   %1 6 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD6    Filter bits
: CAN0_F6DATA0_FD7   %1 7 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD7    Filter bits
: CAN0_F6DATA0_FD8   %1 8 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD8    Filter bits
: CAN0_F6DATA0_FD9   %1 9 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD9    Filter bits
: CAN0_F6DATA0_FD10   %1 10 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD10    Filter bits
: CAN0_F6DATA0_FD11   %1 11 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD11    Filter bits
: CAN0_F6DATA0_FD12   %1 12 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD12    Filter bits
: CAN0_F6DATA0_FD13   %1 13 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD13    Filter bits
: CAN0_F6DATA0_FD14   %1 14 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD14    Filter bits
: CAN0_F6DATA0_FD15   %1 15 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD15    Filter bits
: CAN0_F6DATA0_FD16   %1 16 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD16    Filter bits
: CAN0_F6DATA0_FD17   %1 17 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD17    Filter bits
: CAN0_F6DATA0_FD18   %1 18 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD18    Filter bits
: CAN0_F6DATA0_FD19   %1 19 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD19    Filter bits
: CAN0_F6DATA0_FD20   %1 20 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD20    Filter bits
: CAN0_F6DATA0_FD21   %1 21 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD21    Filter bits
: CAN0_F6DATA0_FD22   %1 22 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD22    Filter bits
: CAN0_F6DATA0_FD23   %1 23 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD23    Filter bits
: CAN0_F6DATA0_FD24   %1 24 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD24    Filter bits
: CAN0_F6DATA0_FD25   %1 25 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD25    Filter bits
: CAN0_F6DATA0_FD26   %1 26 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD26    Filter bits
: CAN0_F6DATA0_FD27   %1 27 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD27    Filter bits
: CAN0_F6DATA0_FD28   %1 28 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD28    Filter bits
: CAN0_F6DATA0_FD29   %1 29 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD29    Filter bits
: CAN0_F6DATA0_FD30   %1 30 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD30    Filter bits
: CAN0_F6DATA0_FD31   %1 31 lshift CAN0_F6DATA0 bis! ;  \ CAN0_F6DATA0_FD31    Filter bits

\ CAN0_F6DATA1 (read-write)
: CAN0_F6DATA1_FD0   %1 0 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD0    Filter bits
: CAN0_F6DATA1_FD1   %1 1 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD1    Filter bits
: CAN0_F6DATA1_FD2   %1 2 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD2    Filter bits
: CAN0_F6DATA1_FD3   %1 3 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD3    Filter bits
: CAN0_F6DATA1_FD4   %1 4 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD4    Filter bits
: CAN0_F6DATA1_FD5   %1 5 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD5    Filter bits
: CAN0_F6DATA1_FD6   %1 6 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD6    Filter bits
: CAN0_F6DATA1_FD7   %1 7 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD7    Filter bits
: CAN0_F6DATA1_FD8   %1 8 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD8    Filter bits
: CAN0_F6DATA1_FD9   %1 9 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD9    Filter bits
: CAN0_F6DATA1_FD10   %1 10 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD10    Filter bits
: CAN0_F6DATA1_FD11   %1 11 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD11    Filter bits
: CAN0_F6DATA1_FD12   %1 12 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD12    Filter bits
: CAN0_F6DATA1_FD13   %1 13 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD13    Filter bits
: CAN0_F6DATA1_FD14   %1 14 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD14    Filter bits
: CAN0_F6DATA1_FD15   %1 15 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD15    Filter bits
: CAN0_F6DATA1_FD16   %1 16 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD16    Filter bits
: CAN0_F6DATA1_FD17   %1 17 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD17    Filter bits
: CAN0_F6DATA1_FD18   %1 18 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD18    Filter bits
: CAN0_F6DATA1_FD19   %1 19 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD19    Filter bits
: CAN0_F6DATA1_FD20   %1 20 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD20    Filter bits
: CAN0_F6DATA1_FD21   %1 21 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD21    Filter bits
: CAN0_F6DATA1_FD22   %1 22 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD22    Filter bits
: CAN0_F6DATA1_FD23   %1 23 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD23    Filter bits
: CAN0_F6DATA1_FD24   %1 24 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD24    Filter bits
: CAN0_F6DATA1_FD25   %1 25 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD25    Filter bits
: CAN0_F6DATA1_FD26   %1 26 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD26    Filter bits
: CAN0_F6DATA1_FD27   %1 27 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD27    Filter bits
: CAN0_F6DATA1_FD28   %1 28 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD28    Filter bits
: CAN0_F6DATA1_FD29   %1 29 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD29    Filter bits
: CAN0_F6DATA1_FD30   %1 30 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD30    Filter bits
: CAN0_F6DATA1_FD31   %1 31 lshift CAN0_F6DATA1 bis! ;  \ CAN0_F6DATA1_FD31    Filter bits

\ CAN0_F7DATA0 (read-write)
: CAN0_F7DATA0_FD0   %1 0 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD0    Filter bits
: CAN0_F7DATA0_FD1   %1 1 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD1    Filter bits
: CAN0_F7DATA0_FD2   %1 2 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD2    Filter bits
: CAN0_F7DATA0_FD3   %1 3 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD3    Filter bits
: CAN0_F7DATA0_FD4   %1 4 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD4    Filter bits
: CAN0_F7DATA0_FD5   %1 5 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD5    Filter bits
: CAN0_F7DATA0_FD6   %1 6 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD6    Filter bits
: CAN0_F7DATA0_FD7   %1 7 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD7    Filter bits
: CAN0_F7DATA0_FD8   %1 8 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD8    Filter bits
: CAN0_F7DATA0_FD9   %1 9 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD9    Filter bits
: CAN0_F7DATA0_FD10   %1 10 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD10    Filter bits
: CAN0_F7DATA0_FD11   %1 11 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD11    Filter bits
: CAN0_F7DATA0_FD12   %1 12 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD12    Filter bits
: CAN0_F7DATA0_FD13   %1 13 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD13    Filter bits
: CAN0_F7DATA0_FD14   %1 14 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD14    Filter bits
: CAN0_F7DATA0_FD15   %1 15 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD15    Filter bits
: CAN0_F7DATA0_FD16   %1 16 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD16    Filter bits
: CAN0_F7DATA0_FD17   %1 17 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD17    Filter bits
: CAN0_F7DATA0_FD18   %1 18 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD18    Filter bits
: CAN0_F7DATA0_FD19   %1 19 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD19    Filter bits
: CAN0_F7DATA0_FD20   %1 20 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD20    Filter bits
: CAN0_F7DATA0_FD21   %1 21 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD21    Filter bits
: CAN0_F7DATA0_FD22   %1 22 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD22    Filter bits
: CAN0_F7DATA0_FD23   %1 23 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD23    Filter bits
: CAN0_F7DATA0_FD24   %1 24 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD24    Filter bits
: CAN0_F7DATA0_FD25   %1 25 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD25    Filter bits
: CAN0_F7DATA0_FD26   %1 26 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD26    Filter bits
: CAN0_F7DATA0_FD27   %1 27 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD27    Filter bits
: CAN0_F7DATA0_FD28   %1 28 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD28    Filter bits
: CAN0_F7DATA0_FD29   %1 29 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD29    Filter bits
: CAN0_F7DATA0_FD30   %1 30 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD30    Filter bits
: CAN0_F7DATA0_FD31   %1 31 lshift CAN0_F7DATA0 bis! ;  \ CAN0_F7DATA0_FD31    Filter bits

\ CAN0_F7DATA1 (read-write)
: CAN0_F7DATA1_FD0   %1 0 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD0    Filter bits
: CAN0_F7DATA1_FD1   %1 1 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD1    Filter bits
: CAN0_F7DATA1_FD2   %1 2 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD2    Filter bits
: CAN0_F7DATA1_FD3   %1 3 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD3    Filter bits
: CAN0_F7DATA1_FD4   %1 4 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD4    Filter bits
: CAN0_F7DATA1_FD5   %1 5 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD5    Filter bits
: CAN0_F7DATA1_FD6   %1 6 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD6    Filter bits
: CAN0_F7DATA1_FD7   %1 7 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD7    Filter bits
: CAN0_F7DATA1_FD8   %1 8 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD8    Filter bits
: CAN0_F7DATA1_FD9   %1 9 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD9    Filter bits
: CAN0_F7DATA1_FD10   %1 10 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD10    Filter bits
: CAN0_F7DATA1_FD11   %1 11 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD11    Filter bits
: CAN0_F7DATA1_FD12   %1 12 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD12    Filter bits
: CAN0_F7DATA1_FD13   %1 13 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD13    Filter bits
: CAN0_F7DATA1_FD14   %1 14 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD14    Filter bits
: CAN0_F7DATA1_FD15   %1 15 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD15    Filter bits
: CAN0_F7DATA1_FD16   %1 16 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD16    Filter bits
: CAN0_F7DATA1_FD17   %1 17 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD17    Filter bits
: CAN0_F7DATA1_FD18   %1 18 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD18    Filter bits
: CAN0_F7DATA1_FD19   %1 19 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD19    Filter bits
: CAN0_F7DATA1_FD20   %1 20 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD20    Filter bits
: CAN0_F7DATA1_FD21   %1 21 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD21    Filter bits
: CAN0_F7DATA1_FD22   %1 22 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD22    Filter bits
: CAN0_F7DATA1_FD23   %1 23 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD23    Filter bits
: CAN0_F7DATA1_FD24   %1 24 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD24    Filter bits
: CAN0_F7DATA1_FD25   %1 25 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD25    Filter bits
: CAN0_F7DATA1_FD26   %1 26 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD26    Filter bits
: CAN0_F7DATA1_FD27   %1 27 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD27    Filter bits
: CAN0_F7DATA1_FD28   %1 28 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD28    Filter bits
: CAN0_F7DATA1_FD29   %1 29 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD29    Filter bits
: CAN0_F7DATA1_FD30   %1 30 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD30    Filter bits
: CAN0_F7DATA1_FD31   %1 31 lshift CAN0_F7DATA1 bis! ;  \ CAN0_F7DATA1_FD31    Filter bits

\ CAN0_F8DATA0 (read-write)
: CAN0_F8DATA0_FD0   %1 0 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD0    Filter bits
: CAN0_F8DATA0_FD1   %1 1 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD1    Filter bits
: CAN0_F8DATA0_FD2   %1 2 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD2    Filter bits
: CAN0_F8DATA0_FD3   %1 3 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD3    Filter bits
: CAN0_F8DATA0_FD4   %1 4 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD4    Filter bits
: CAN0_F8DATA0_FD5   %1 5 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD5    Filter bits
: CAN0_F8DATA0_FD6   %1 6 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD6    Filter bits
: CAN0_F8DATA0_FD7   %1 7 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD7    Filter bits
: CAN0_F8DATA0_FD8   %1 8 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD8    Filter bits
: CAN0_F8DATA0_FD9   %1 9 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD9    Filter bits
: CAN0_F8DATA0_FD10   %1 10 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD10    Filter bits
: CAN0_F8DATA0_FD11   %1 11 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD11    Filter bits
: CAN0_F8DATA0_FD12   %1 12 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD12    Filter bits
: CAN0_F8DATA0_FD13   %1 13 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD13    Filter bits
: CAN0_F8DATA0_FD14   %1 14 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD14    Filter bits
: CAN0_F8DATA0_FD15   %1 15 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD15    Filter bits
: CAN0_F8DATA0_FD16   %1 16 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD16    Filter bits
: CAN0_F8DATA0_FD17   %1 17 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD17    Filter bits
: CAN0_F8DATA0_FD18   %1 18 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD18    Filter bits
: CAN0_F8DATA0_FD19   %1 19 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD19    Filter bits
: CAN0_F8DATA0_FD20   %1 20 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD20    Filter bits
: CAN0_F8DATA0_FD21   %1 21 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD21    Filter bits
: CAN0_F8DATA0_FD22   %1 22 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD22    Filter bits
: CAN0_F8DATA0_FD23   %1 23 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD23    Filter bits
: CAN0_F8DATA0_FD24   %1 24 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD24    Filter bits
: CAN0_F8DATA0_FD25   %1 25 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD25    Filter bits
: CAN0_F8DATA0_FD26   %1 26 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD26    Filter bits
: CAN0_F8DATA0_FD27   %1 27 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD27    Filter bits
: CAN0_F8DATA0_FD28   %1 28 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD28    Filter bits
: CAN0_F8DATA0_FD29   %1 29 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD29    Filter bits
: CAN0_F8DATA0_FD30   %1 30 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD30    Filter bits
: CAN0_F8DATA0_FD31   %1 31 lshift CAN0_F8DATA0 bis! ;  \ CAN0_F8DATA0_FD31    Filter bits

\ CAN0_F8DATA1 (read-write)
: CAN0_F8DATA1_FD0   %1 0 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD0    Filter bits
: CAN0_F8DATA1_FD1   %1 1 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD1    Filter bits
: CAN0_F8DATA1_FD2   %1 2 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD2    Filter bits
: CAN0_F8DATA1_FD3   %1 3 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD3    Filter bits
: CAN0_F8DATA1_FD4   %1 4 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD4    Filter bits
: CAN0_F8DATA1_FD5   %1 5 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD5    Filter bits
: CAN0_F8DATA1_FD6   %1 6 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD6    Filter bits
: CAN0_F8DATA1_FD7   %1 7 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD7    Filter bits
: CAN0_F8DATA1_FD8   %1 8 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD8    Filter bits
: CAN0_F8DATA1_FD9   %1 9 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD9    Filter bits
: CAN0_F8DATA1_FD10   %1 10 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD10    Filter bits
: CAN0_F8DATA1_FD11   %1 11 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD11    Filter bits
: CAN0_F8DATA1_FD12   %1 12 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD12    Filter bits
: CAN0_F8DATA1_FD13   %1 13 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD13    Filter bits
: CAN0_F8DATA1_FD14   %1 14 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD14    Filter bits
: CAN0_F8DATA1_FD15   %1 15 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD15    Filter bits
: CAN0_F8DATA1_FD16   %1 16 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD16    Filter bits
: CAN0_F8DATA1_FD17   %1 17 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD17    Filter bits
: CAN0_F8DATA1_FD18   %1 18 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD18    Filter bits
: CAN0_F8DATA1_FD19   %1 19 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD19    Filter bits
: CAN0_F8DATA1_FD20   %1 20 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD20    Filter bits
: CAN0_F8DATA1_FD21   %1 21 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD21    Filter bits
: CAN0_F8DATA1_FD22   %1 22 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD22    Filter bits
: CAN0_F8DATA1_FD23   %1 23 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD23    Filter bits
: CAN0_F8DATA1_FD24   %1 24 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD24    Filter bits
: CAN0_F8DATA1_FD25   %1 25 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD25    Filter bits
: CAN0_F8DATA1_FD26   %1 26 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD26    Filter bits
: CAN0_F8DATA1_FD27   %1 27 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD27    Filter bits
: CAN0_F8DATA1_FD28   %1 28 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD28    Filter bits
: CAN0_F8DATA1_FD29   %1 29 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD29    Filter bits
: CAN0_F8DATA1_FD30   %1 30 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD30    Filter bits
: CAN0_F8DATA1_FD31   %1 31 lshift CAN0_F8DATA1 bis! ;  \ CAN0_F8DATA1_FD31    Filter bits

\ CAN0_F9DATA0 (read-write)
: CAN0_F9DATA0_FD0   %1 0 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD0    Filter bits
: CAN0_F9DATA0_FD1   %1 1 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD1    Filter bits
: CAN0_F9DATA0_FD2   %1 2 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD2    Filter bits
: CAN0_F9DATA0_FD3   %1 3 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD3    Filter bits
: CAN0_F9DATA0_FD4   %1 4 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD4    Filter bits
: CAN0_F9DATA0_FD5   %1 5 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD5    Filter bits
: CAN0_F9DATA0_FD6   %1 6 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD6    Filter bits
: CAN0_F9DATA0_FD7   %1 7 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD7    Filter bits
: CAN0_F9DATA0_FD8   %1 8 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD8    Filter bits
: CAN0_F9DATA0_FD9   %1 9 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD9    Filter bits
: CAN0_F9DATA0_FD10   %1 10 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD10    Filter bits
: CAN0_F9DATA0_FD11   %1 11 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD11    Filter bits
: CAN0_F9DATA0_FD12   %1 12 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD12    Filter bits
: CAN0_F9DATA0_FD13   %1 13 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD13    Filter bits
: CAN0_F9DATA0_FD14   %1 14 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD14    Filter bits
: CAN0_F9DATA0_FD15   %1 15 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD15    Filter bits
: CAN0_F9DATA0_FD16   %1 16 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD16    Filter bits
: CAN0_F9DATA0_FD17   %1 17 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD17    Filter bits
: CAN0_F9DATA0_FD18   %1 18 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD18    Filter bits
: CAN0_F9DATA0_FD19   %1 19 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD19    Filter bits
: CAN0_F9DATA0_FD20   %1 20 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD20    Filter bits
: CAN0_F9DATA0_FD21   %1 21 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD21    Filter bits
: CAN0_F9DATA0_FD22   %1 22 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD22    Filter bits
: CAN0_F9DATA0_FD23   %1 23 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD23    Filter bits
: CAN0_F9DATA0_FD24   %1 24 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD24    Filter bits
: CAN0_F9DATA0_FD25   %1 25 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD25    Filter bits
: CAN0_F9DATA0_FD26   %1 26 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD26    Filter bits
: CAN0_F9DATA0_FD27   %1 27 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD27    Filter bits
: CAN0_F9DATA0_FD28   %1 28 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD28    Filter bits
: CAN0_F9DATA0_FD29   %1 29 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD29    Filter bits
: CAN0_F9DATA0_FD30   %1 30 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD30    Filter bits
: CAN0_F9DATA0_FD31   %1 31 lshift CAN0_F9DATA0 bis! ;  \ CAN0_F9DATA0_FD31    Filter bits

\ CAN0_F9DATA1 (read-write)
: CAN0_F9DATA1_FD0   %1 0 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD0    Filter bits
: CAN0_F9DATA1_FD1   %1 1 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD1    Filter bits
: CAN0_F9DATA1_FD2   %1 2 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD2    Filter bits
: CAN0_F9DATA1_FD3   %1 3 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD3    Filter bits
: CAN0_F9DATA1_FD4   %1 4 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD4    Filter bits
: CAN0_F9DATA1_FD5   %1 5 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD5    Filter bits
: CAN0_F9DATA1_FD6   %1 6 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD6    Filter bits
: CAN0_F9DATA1_FD7   %1 7 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD7    Filter bits
: CAN0_F9DATA1_FD8   %1 8 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD8    Filter bits
: CAN0_F9DATA1_FD9   %1 9 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD9    Filter bits
: CAN0_F9DATA1_FD10   %1 10 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD10    Filter bits
: CAN0_F9DATA1_FD11   %1 11 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD11    Filter bits
: CAN0_F9DATA1_FD12   %1 12 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD12    Filter bits
: CAN0_F9DATA1_FD13   %1 13 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD13    Filter bits
: CAN0_F9DATA1_FD14   %1 14 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD14    Filter bits
: CAN0_F9DATA1_FD15   %1 15 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD15    Filter bits
: CAN0_F9DATA1_FD16   %1 16 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD16    Filter bits
: CAN0_F9DATA1_FD17   %1 17 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD17    Filter bits
: CAN0_F9DATA1_FD18   %1 18 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD18    Filter bits
: CAN0_F9DATA1_FD19   %1 19 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD19    Filter bits
: CAN0_F9DATA1_FD20   %1 20 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD20    Filter bits
: CAN0_F9DATA1_FD21   %1 21 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD21    Filter bits
: CAN0_F9DATA1_FD22   %1 22 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD22    Filter bits
: CAN0_F9DATA1_FD23   %1 23 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD23    Filter bits
: CAN0_F9DATA1_FD24   %1 24 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD24    Filter bits
: CAN0_F9DATA1_FD25   %1 25 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD25    Filter bits
: CAN0_F9DATA1_FD26   %1 26 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD26    Filter bits
: CAN0_F9DATA1_FD27   %1 27 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD27    Filter bits
: CAN0_F9DATA1_FD28   %1 28 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD28    Filter bits
: CAN0_F9DATA1_FD29   %1 29 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD29    Filter bits
: CAN0_F9DATA1_FD30   %1 30 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD30    Filter bits
: CAN0_F9DATA1_FD31   %1 31 lshift CAN0_F9DATA1 bis! ;  \ CAN0_F9DATA1_FD31    Filter bits

\ CAN0_F10DATA0 (read-write)
: CAN0_F10DATA0_FD0   %1 0 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD0    Filter bits
: CAN0_F10DATA0_FD1   %1 1 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD1    Filter bits
: CAN0_F10DATA0_FD2   %1 2 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD2    Filter bits
: CAN0_F10DATA0_FD3   %1 3 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD3    Filter bits
: CAN0_F10DATA0_FD4   %1 4 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD4    Filter bits
: CAN0_F10DATA0_FD5   %1 5 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD5    Filter bits
: CAN0_F10DATA0_FD6   %1 6 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD6    Filter bits
: CAN0_F10DATA0_FD7   %1 7 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD7    Filter bits
: CAN0_F10DATA0_FD8   %1 8 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD8    Filter bits
: CAN0_F10DATA0_FD9   %1 9 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD9    Filter bits
: CAN0_F10DATA0_FD10   %1 10 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD10    Filter bits
: CAN0_F10DATA0_FD11   %1 11 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD11    Filter bits
: CAN0_F10DATA0_FD12   %1 12 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD12    Filter bits
: CAN0_F10DATA0_FD13   %1 13 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD13    Filter bits
: CAN0_F10DATA0_FD14   %1 14 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD14    Filter bits
: CAN0_F10DATA0_FD15   %1 15 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD15    Filter bits
: CAN0_F10DATA0_FD16   %1 16 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD16    Filter bits
: CAN0_F10DATA0_FD17   %1 17 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD17    Filter bits
: CAN0_F10DATA0_FD18   %1 18 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD18    Filter bits
: CAN0_F10DATA0_FD19   %1 19 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD19    Filter bits
: CAN0_F10DATA0_FD20   %1 20 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD20    Filter bits
: CAN0_F10DATA0_FD21   %1 21 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD21    Filter bits
: CAN0_F10DATA0_FD22   %1 22 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD22    Filter bits
: CAN0_F10DATA0_FD23   %1 23 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD23    Filter bits
: CAN0_F10DATA0_FD24   %1 24 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD24    Filter bits
: CAN0_F10DATA0_FD25   %1 25 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD25    Filter bits
: CAN0_F10DATA0_FD26   %1 26 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD26    Filter bits
: CAN0_F10DATA0_FD27   %1 27 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD27    Filter bits
: CAN0_F10DATA0_FD28   %1 28 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD28    Filter bits
: CAN0_F10DATA0_FD29   %1 29 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD29    Filter bits
: CAN0_F10DATA0_FD30   %1 30 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD30    Filter bits
: CAN0_F10DATA0_FD31   %1 31 lshift CAN0_F10DATA0 bis! ;  \ CAN0_F10DATA0_FD31    Filter bits

\ CAN0_F10DATA1 (read-write)
: CAN0_F10DATA1_FD0   %1 0 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD0    Filter bits
: CAN0_F10DATA1_FD1   %1 1 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD1    Filter bits
: CAN0_F10DATA1_FD2   %1 2 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD2    Filter bits
: CAN0_F10DATA1_FD3   %1 3 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD3    Filter bits
: CAN0_F10DATA1_FD4   %1 4 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD4    Filter bits
: CAN0_F10DATA1_FD5   %1 5 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD5    Filter bits
: CAN0_F10DATA1_FD6   %1 6 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD6    Filter bits
: CAN0_F10DATA1_FD7   %1 7 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD7    Filter bits
: CAN0_F10DATA1_FD8   %1 8 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD8    Filter bits
: CAN0_F10DATA1_FD9   %1 9 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD9    Filter bits
: CAN0_F10DATA1_FD10   %1 10 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD10    Filter bits
: CAN0_F10DATA1_FD11   %1 11 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD11    Filter bits
: CAN0_F10DATA1_FD12   %1 12 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD12    Filter bits
: CAN0_F10DATA1_FD13   %1 13 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD13    Filter bits
: CAN0_F10DATA1_FD14   %1 14 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD14    Filter bits
: CAN0_F10DATA1_FD15   %1 15 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD15    Filter bits
: CAN0_F10DATA1_FD16   %1 16 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD16    Filter bits
: CAN0_F10DATA1_FD17   %1 17 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD17    Filter bits
: CAN0_F10DATA1_FD18   %1 18 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD18    Filter bits
: CAN0_F10DATA1_FD19   %1 19 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD19    Filter bits
: CAN0_F10DATA1_FD20   %1 20 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD20    Filter bits
: CAN0_F10DATA1_FD21   %1 21 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD21    Filter bits
: CAN0_F10DATA1_FD22   %1 22 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD22    Filter bits
: CAN0_F10DATA1_FD23   %1 23 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD23    Filter bits
: CAN0_F10DATA1_FD24   %1 24 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD24    Filter bits
: CAN0_F10DATA1_FD25   %1 25 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD25    Filter bits
: CAN0_F10DATA1_FD26   %1 26 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD26    Filter bits
: CAN0_F10DATA1_FD27   %1 27 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD27    Filter bits
: CAN0_F10DATA1_FD28   %1 28 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD28    Filter bits
: CAN0_F10DATA1_FD29   %1 29 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD29    Filter bits
: CAN0_F10DATA1_FD30   %1 30 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD30    Filter bits
: CAN0_F10DATA1_FD31   %1 31 lshift CAN0_F10DATA1 bis! ;  \ CAN0_F10DATA1_FD31    Filter bits

\ CAN0_F11DATA0 (read-write)
: CAN0_F11DATA0_FD0   %1 0 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD0    Filter bits
: CAN0_F11DATA0_FD1   %1 1 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD1    Filter bits
: CAN0_F11DATA0_FD2   %1 2 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD2    Filter bits
: CAN0_F11DATA0_FD3   %1 3 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD3    Filter bits
: CAN0_F11DATA0_FD4   %1 4 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD4    Filter bits
: CAN0_F11DATA0_FD5   %1 5 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD5    Filter bits
: CAN0_F11DATA0_FD6   %1 6 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD6    Filter bits
: CAN0_F11DATA0_FD7   %1 7 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD7    Filter bits
: CAN0_F11DATA0_FD8   %1 8 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD8    Filter bits
: CAN0_F11DATA0_FD9   %1 9 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD9    Filter bits
: CAN0_F11DATA0_FD10   %1 10 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD10    Filter bits
: CAN0_F11DATA0_FD11   %1 11 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD11    Filter bits
: CAN0_F11DATA0_FD12   %1 12 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD12    Filter bits
: CAN0_F11DATA0_FD13   %1 13 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD13    Filter bits
: CAN0_F11DATA0_FD14   %1 14 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD14    Filter bits
: CAN0_F11DATA0_FD15   %1 15 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD15    Filter bits
: CAN0_F11DATA0_FD16   %1 16 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD16    Filter bits
: CAN0_F11DATA0_FD17   %1 17 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD17    Filter bits
: CAN0_F11DATA0_FD18   %1 18 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD18    Filter bits
: CAN0_F11DATA0_FD19   %1 19 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD19    Filter bits
: CAN0_F11DATA0_FD20   %1 20 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD20    Filter bits
: CAN0_F11DATA0_FD21   %1 21 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD21    Filter bits
: CAN0_F11DATA0_FD22   %1 22 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD22    Filter bits
: CAN0_F11DATA0_FD23   %1 23 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD23    Filter bits
: CAN0_F11DATA0_FD24   %1 24 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD24    Filter bits
: CAN0_F11DATA0_FD25   %1 25 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD25    Filter bits
: CAN0_F11DATA0_FD26   %1 26 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD26    Filter bits
: CAN0_F11DATA0_FD27   %1 27 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD27    Filter bits
: CAN0_F11DATA0_FD28   %1 28 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD28    Filter bits
: CAN0_F11DATA0_FD29   %1 29 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD29    Filter bits
: CAN0_F11DATA0_FD30   %1 30 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD30    Filter bits
: CAN0_F11DATA0_FD31   %1 31 lshift CAN0_F11DATA0 bis! ;  \ CAN0_F11DATA0_FD31    Filter bits

\ CAN0_F11DATA1 (read-write)
: CAN0_F11DATA1_FD0   %1 0 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD0    Filter bits
: CAN0_F11DATA1_FD1   %1 1 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD1    Filter bits
: CAN0_F11DATA1_FD2   %1 2 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD2    Filter bits
: CAN0_F11DATA1_FD3   %1 3 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD3    Filter bits
: CAN0_F11DATA1_FD4   %1 4 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD4    Filter bits
: CAN0_F11DATA1_FD5   %1 5 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD5    Filter bits
: CAN0_F11DATA1_FD6   %1 6 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD6    Filter bits
: CAN0_F11DATA1_FD7   %1 7 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD7    Filter bits
: CAN0_F11DATA1_FD8   %1 8 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD8    Filter bits
: CAN0_F11DATA1_FD9   %1 9 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD9    Filter bits
: CAN0_F11DATA1_FD10   %1 10 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD10    Filter bits
: CAN0_F11DATA1_FD11   %1 11 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD11    Filter bits
: CAN0_F11DATA1_FD12   %1 12 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD12    Filter bits
: CAN0_F11DATA1_FD13   %1 13 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD13    Filter bits
: CAN0_F11DATA1_FD14   %1 14 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD14    Filter bits
: CAN0_F11DATA1_FD15   %1 15 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD15    Filter bits
: CAN0_F11DATA1_FD16   %1 16 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD16    Filter bits
: CAN0_F11DATA1_FD17   %1 17 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD17    Filter bits
: CAN0_F11DATA1_FD18   %1 18 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD18    Filter bits
: CAN0_F11DATA1_FD19   %1 19 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD19    Filter bits
: CAN0_F11DATA1_FD20   %1 20 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD20    Filter bits
: CAN0_F11DATA1_FD21   %1 21 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD21    Filter bits
: CAN0_F11DATA1_FD22   %1 22 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD22    Filter bits
: CAN0_F11DATA1_FD23   %1 23 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD23    Filter bits
: CAN0_F11DATA1_FD24   %1 24 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD24    Filter bits
: CAN0_F11DATA1_FD25   %1 25 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD25    Filter bits
: CAN0_F11DATA1_FD26   %1 26 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD26    Filter bits
: CAN0_F11DATA1_FD27   %1 27 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD27    Filter bits
: CAN0_F11DATA1_FD28   %1 28 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD28    Filter bits
: CAN0_F11DATA1_FD29   %1 29 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD29    Filter bits
: CAN0_F11DATA1_FD30   %1 30 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD30    Filter bits
: CAN0_F11DATA1_FD31   %1 31 lshift CAN0_F11DATA1 bis! ;  \ CAN0_F11DATA1_FD31    Filter bits

\ CAN0_F12DATA0 (read-write)
: CAN0_F12DATA0_FD0   %1 0 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD0    Filter bits
: CAN0_F12DATA0_FD1   %1 1 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD1    Filter bits
: CAN0_F12DATA0_FD2   %1 2 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD2    Filter bits
: CAN0_F12DATA0_FD3   %1 3 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD3    Filter bits
: CAN0_F12DATA0_FD4   %1 4 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD4    Filter bits
: CAN0_F12DATA0_FD5   %1 5 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD5    Filter bits
: CAN0_F12DATA0_FD6   %1 6 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD6    Filter bits
: CAN0_F12DATA0_FD7   %1 7 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD7    Filter bits
: CAN0_F12DATA0_FD8   %1 8 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD8    Filter bits
: CAN0_F12DATA0_FD9   %1 9 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD9    Filter bits
: CAN0_F12DATA0_FD10   %1 10 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD10    Filter bits
: CAN0_F12DATA0_FD11   %1 11 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD11    Filter bits
: CAN0_F12DATA0_FD12   %1 12 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD12    Filter bits
: CAN0_F12DATA0_FD13   %1 13 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD13    Filter bits
: CAN0_F12DATA0_FD14   %1 14 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD14    Filter bits
: CAN0_F12DATA0_FD15   %1 15 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD15    Filter bits
: CAN0_F12DATA0_FD16   %1 16 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD16    Filter bits
: CAN0_F12DATA0_FD17   %1 17 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD17    Filter bits
: CAN0_F12DATA0_FD18   %1 18 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD18    Filter bits
: CAN0_F12DATA0_FD19   %1 19 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD19    Filter bits
: CAN0_F12DATA0_FD20   %1 20 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD20    Filter bits
: CAN0_F12DATA0_FD21   %1 21 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD21    Filter bits
: CAN0_F12DATA0_FD22   %1 22 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD22    Filter bits
: CAN0_F12DATA0_FD23   %1 23 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD23    Filter bits
: CAN0_F12DATA0_FD24   %1 24 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD24    Filter bits
: CAN0_F12DATA0_FD25   %1 25 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD25    Filter bits
: CAN0_F12DATA0_FD26   %1 26 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD26    Filter bits
: CAN0_F12DATA0_FD27   %1 27 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD27    Filter bits
: CAN0_F12DATA0_FD28   %1 28 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD28    Filter bits
: CAN0_F12DATA0_FD29   %1 29 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD29    Filter bits
: CAN0_F12DATA0_FD30   %1 30 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD30    Filter bits
: CAN0_F12DATA0_FD31   %1 31 lshift CAN0_F12DATA0 bis! ;  \ CAN0_F12DATA0_FD31    Filter bits

\ CAN0_F12DATA1 (read-write)
: CAN0_F12DATA1_FD0   %1 0 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD0    Filter bits
: CAN0_F12DATA1_FD1   %1 1 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD1    Filter bits
: CAN0_F12DATA1_FD2   %1 2 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD2    Filter bits
: CAN0_F12DATA1_FD3   %1 3 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD3    Filter bits
: CAN0_F12DATA1_FD4   %1 4 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD4    Filter bits
: CAN0_F12DATA1_FD5   %1 5 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD5    Filter bits
: CAN0_F12DATA1_FD6   %1 6 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD6    Filter bits
: CAN0_F12DATA1_FD7   %1 7 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD7    Filter bits
: CAN0_F12DATA1_FD8   %1 8 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD8    Filter bits
: CAN0_F12DATA1_FD9   %1 9 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD9    Filter bits
: CAN0_F12DATA1_FD10   %1 10 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD10    Filter bits
: CAN0_F12DATA1_FD11   %1 11 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD11    Filter bits
: CAN0_F12DATA1_FD12   %1 12 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD12    Filter bits
: CAN0_F12DATA1_FD13   %1 13 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD13    Filter bits
: CAN0_F12DATA1_FD14   %1 14 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD14    Filter bits
: CAN0_F12DATA1_FD15   %1 15 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD15    Filter bits
: CAN0_F12DATA1_FD16   %1 16 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD16    Filter bits
: CAN0_F12DATA1_FD17   %1 17 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD17    Filter bits
: CAN0_F12DATA1_FD18   %1 18 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD18    Filter bits
: CAN0_F12DATA1_FD19   %1 19 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD19    Filter bits
: CAN0_F12DATA1_FD20   %1 20 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD20    Filter bits
: CAN0_F12DATA1_FD21   %1 21 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD21    Filter bits
: CAN0_F12DATA1_FD22   %1 22 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD22    Filter bits
: CAN0_F12DATA1_FD23   %1 23 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD23    Filter bits
: CAN0_F12DATA1_FD24   %1 24 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD24    Filter bits
: CAN0_F12DATA1_FD25   %1 25 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD25    Filter bits
: CAN0_F12DATA1_FD26   %1 26 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD26    Filter bits
: CAN0_F12DATA1_FD27   %1 27 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD27    Filter bits
: CAN0_F12DATA1_FD28   %1 28 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD28    Filter bits
: CAN0_F12DATA1_FD29   %1 29 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD29    Filter bits
: CAN0_F12DATA1_FD30   %1 30 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD30    Filter bits
: CAN0_F12DATA1_FD31   %1 31 lshift CAN0_F12DATA1 bis! ;  \ CAN0_F12DATA1_FD31    Filter bits

\ CAN0_F13DATA0 (read-write)
: CAN0_F13DATA0_FD0   %1 0 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD0    Filter bits
: CAN0_F13DATA0_FD1   %1 1 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD1    Filter bits
: CAN0_F13DATA0_FD2   %1 2 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD2    Filter bits
: CAN0_F13DATA0_FD3   %1 3 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD3    Filter bits
: CAN0_F13DATA0_FD4   %1 4 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD4    Filter bits
: CAN0_F13DATA0_FD5   %1 5 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD5    Filter bits
: CAN0_F13DATA0_FD6   %1 6 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD6    Filter bits
: CAN0_F13DATA0_FD7   %1 7 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD7    Filter bits
: CAN0_F13DATA0_FD8   %1 8 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD8    Filter bits
: CAN0_F13DATA0_FD9   %1 9 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD9    Filter bits
: CAN0_F13DATA0_FD10   %1 10 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD10    Filter bits
: CAN0_F13DATA0_FD11   %1 11 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD11    Filter bits
: CAN0_F13DATA0_FD12   %1 12 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD12    Filter bits
: CAN0_F13DATA0_FD13   %1 13 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD13    Filter bits
: CAN0_F13DATA0_FD14   %1 14 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD14    Filter bits
: CAN0_F13DATA0_FD15   %1 15 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD15    Filter bits
: CAN0_F13DATA0_FD16   %1 16 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD16    Filter bits
: CAN0_F13DATA0_FD17   %1 17 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD17    Filter bits
: CAN0_F13DATA0_FD18   %1 18 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD18    Filter bits
: CAN0_F13DATA0_FD19   %1 19 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD19    Filter bits
: CAN0_F13DATA0_FD20   %1 20 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD20    Filter bits
: CAN0_F13DATA0_FD21   %1 21 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD21    Filter bits
: CAN0_F13DATA0_FD22   %1 22 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD22    Filter bits
: CAN0_F13DATA0_FD23   %1 23 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD23    Filter bits
: CAN0_F13DATA0_FD24   %1 24 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD24    Filter bits
: CAN0_F13DATA0_FD25   %1 25 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD25    Filter bits
: CAN0_F13DATA0_FD26   %1 26 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD26    Filter bits
: CAN0_F13DATA0_FD27   %1 27 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD27    Filter bits
: CAN0_F13DATA0_FD28   %1 28 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD28    Filter bits
: CAN0_F13DATA0_FD29   %1 29 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD29    Filter bits
: CAN0_F13DATA0_FD30   %1 30 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD30    Filter bits
: CAN0_F13DATA0_FD31   %1 31 lshift CAN0_F13DATA0 bis! ;  \ CAN0_F13DATA0_FD31    Filter bits

\ CAN0_F13DATA1 (read-write)
: CAN0_F13DATA1_FD0   %1 0 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD0    Filter bits
: CAN0_F13DATA1_FD1   %1 1 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD1    Filter bits
: CAN0_F13DATA1_FD2   %1 2 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD2    Filter bits
: CAN0_F13DATA1_FD3   %1 3 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD3    Filter bits
: CAN0_F13DATA1_FD4   %1 4 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD4    Filter bits
: CAN0_F13DATA1_FD5   %1 5 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD5    Filter bits
: CAN0_F13DATA1_FD6   %1 6 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD6    Filter bits
: CAN0_F13DATA1_FD7   %1 7 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD7    Filter bits
: CAN0_F13DATA1_FD8   %1 8 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD8    Filter bits
: CAN0_F13DATA1_FD9   %1 9 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD9    Filter bits
: CAN0_F13DATA1_FD10   %1 10 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD10    Filter bits
: CAN0_F13DATA1_FD11   %1 11 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD11    Filter bits
: CAN0_F13DATA1_FD12   %1 12 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD12    Filter bits
: CAN0_F13DATA1_FD13   %1 13 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD13    Filter bits
: CAN0_F13DATA1_FD14   %1 14 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD14    Filter bits
: CAN0_F13DATA1_FD15   %1 15 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD15    Filter bits
: CAN0_F13DATA1_FD16   %1 16 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD16    Filter bits
: CAN0_F13DATA1_FD17   %1 17 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD17    Filter bits
: CAN0_F13DATA1_FD18   %1 18 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD18    Filter bits
: CAN0_F13DATA1_FD19   %1 19 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD19    Filter bits
: CAN0_F13DATA1_FD20   %1 20 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD20    Filter bits
: CAN0_F13DATA1_FD21   %1 21 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD21    Filter bits
: CAN0_F13DATA1_FD22   %1 22 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD22    Filter bits
: CAN0_F13DATA1_FD23   %1 23 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD23    Filter bits
: CAN0_F13DATA1_FD24   %1 24 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD24    Filter bits
: CAN0_F13DATA1_FD25   %1 25 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD25    Filter bits
: CAN0_F13DATA1_FD26   %1 26 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD26    Filter bits
: CAN0_F13DATA1_FD27   %1 27 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD27    Filter bits
: CAN0_F13DATA1_FD28   %1 28 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD28    Filter bits
: CAN0_F13DATA1_FD29   %1 29 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD29    Filter bits
: CAN0_F13DATA1_FD30   %1 30 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD30    Filter bits
: CAN0_F13DATA1_FD31   %1 31 lshift CAN0_F13DATA1 bis! ;  \ CAN0_F13DATA1_FD31    Filter bits

\ CAN0_F14DATA0 (read-write)
: CAN0_F14DATA0_FD0   %1 0 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD0    Filter bits
: CAN0_F14DATA0_FD1   %1 1 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD1    Filter bits
: CAN0_F14DATA0_FD2   %1 2 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD2    Filter bits
: CAN0_F14DATA0_FD3   %1 3 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD3    Filter bits
: CAN0_F14DATA0_FD4   %1 4 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD4    Filter bits
: CAN0_F14DATA0_FD5   %1 5 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD5    Filter bits
: CAN0_F14DATA0_FD6   %1 6 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD6    Filter bits
: CAN0_F14DATA0_FD7   %1 7 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD7    Filter bits
: CAN0_F14DATA0_FD8   %1 8 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD8    Filter bits
: CAN0_F14DATA0_FD9   %1 9 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD9    Filter bits
: CAN0_F14DATA0_FD10   %1 10 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD10    Filter bits
: CAN0_F14DATA0_FD11   %1 11 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD11    Filter bits
: CAN0_F14DATA0_FD12   %1 12 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD12    Filter bits
: CAN0_F14DATA0_FD13   %1 13 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD13    Filter bits
: CAN0_F14DATA0_FD14   %1 14 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD14    Filter bits
: CAN0_F14DATA0_FD15   %1 15 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD15    Filter bits
: CAN0_F14DATA0_FD16   %1 16 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD16    Filter bits
: CAN0_F14DATA0_FD17   %1 17 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD17    Filter bits
: CAN0_F14DATA0_FD18   %1 18 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD18    Filter bits
: CAN0_F14DATA0_FD19   %1 19 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD19    Filter bits
: CAN0_F14DATA0_FD20   %1 20 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD20    Filter bits
: CAN0_F14DATA0_FD21   %1 21 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD21    Filter bits
: CAN0_F14DATA0_FD22   %1 22 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD22    Filter bits
: CAN0_F14DATA0_FD23   %1 23 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD23    Filter bits
: CAN0_F14DATA0_FD24   %1 24 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD24    Filter bits
: CAN0_F14DATA0_FD25   %1 25 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD25    Filter bits
: CAN0_F14DATA0_FD26   %1 26 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD26    Filter bits
: CAN0_F14DATA0_FD27   %1 27 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD27    Filter bits
: CAN0_F14DATA0_FD28   %1 28 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD28    Filter bits
: CAN0_F14DATA0_FD29   %1 29 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD29    Filter bits
: CAN0_F14DATA0_FD30   %1 30 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD30    Filter bits
: CAN0_F14DATA0_FD31   %1 31 lshift CAN0_F14DATA0 bis! ;  \ CAN0_F14DATA0_FD31    Filter bits

\ CAN0_F14DATA1 (read-write)
: CAN0_F14DATA1_FD0   %1 0 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD0    Filter bits
: CAN0_F14DATA1_FD1   %1 1 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD1    Filter bits
: CAN0_F14DATA1_FD2   %1 2 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD2    Filter bits
: CAN0_F14DATA1_FD3   %1 3 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD3    Filter bits
: CAN0_F14DATA1_FD4   %1 4 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD4    Filter bits
: CAN0_F14DATA1_FD5   %1 5 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD5    Filter bits
: CAN0_F14DATA1_FD6   %1 6 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD6    Filter bits
: CAN0_F14DATA1_FD7   %1 7 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD7    Filter bits
: CAN0_F14DATA1_FD8   %1 8 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD8    Filter bits
: CAN0_F14DATA1_FD9   %1 9 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD9    Filter bits
: CAN0_F14DATA1_FD10   %1 10 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD10    Filter bits
: CAN0_F14DATA1_FD11   %1 11 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD11    Filter bits
: CAN0_F14DATA1_FD12   %1 12 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD12    Filter bits
: CAN0_F14DATA1_FD13   %1 13 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD13    Filter bits
: CAN0_F14DATA1_FD14   %1 14 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD14    Filter bits
: CAN0_F14DATA1_FD15   %1 15 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD15    Filter bits
: CAN0_F14DATA1_FD16   %1 16 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD16    Filter bits
: CAN0_F14DATA1_FD17   %1 17 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD17    Filter bits
: CAN0_F14DATA1_FD18   %1 18 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD18    Filter bits
: CAN0_F14DATA1_FD19   %1 19 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD19    Filter bits
: CAN0_F14DATA1_FD20   %1 20 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD20    Filter bits
: CAN0_F14DATA1_FD21   %1 21 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD21    Filter bits
: CAN0_F14DATA1_FD22   %1 22 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD22    Filter bits
: CAN0_F14DATA1_FD23   %1 23 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD23    Filter bits
: CAN0_F14DATA1_FD24   %1 24 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD24    Filter bits
: CAN0_F14DATA1_FD25   %1 25 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD25    Filter bits
: CAN0_F14DATA1_FD26   %1 26 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD26    Filter bits
: CAN0_F14DATA1_FD27   %1 27 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD27    Filter bits
: CAN0_F14DATA1_FD28   %1 28 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD28    Filter bits
: CAN0_F14DATA1_FD29   %1 29 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD29    Filter bits
: CAN0_F14DATA1_FD30   %1 30 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD30    Filter bits
: CAN0_F14DATA1_FD31   %1 31 lshift CAN0_F14DATA1 bis! ;  \ CAN0_F14DATA1_FD31    Filter bits

\ CAN0_F15DATA0 (read-write)
: CAN0_F15DATA0_FD0   %1 0 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD0    Filter bits
: CAN0_F15DATA0_FD1   %1 1 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD1    Filter bits
: CAN0_F15DATA0_FD2   %1 2 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD2    Filter bits
: CAN0_F15DATA0_FD3   %1 3 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD3    Filter bits
: CAN0_F15DATA0_FD4   %1 4 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD4    Filter bits
: CAN0_F15DATA0_FD5   %1 5 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD5    Filter bits
: CAN0_F15DATA0_FD6   %1 6 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD6    Filter bits
: CAN0_F15DATA0_FD7   %1 7 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD7    Filter bits
: CAN0_F15DATA0_FD8   %1 8 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD8    Filter bits
: CAN0_F15DATA0_FD9   %1 9 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD9    Filter bits
: CAN0_F15DATA0_FD10   %1 10 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD10    Filter bits
: CAN0_F15DATA0_FD11   %1 11 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD11    Filter bits
: CAN0_F15DATA0_FD12   %1 12 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD12    Filter bits
: CAN0_F15DATA0_FD13   %1 13 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD13    Filter bits
: CAN0_F15DATA0_FD14   %1 14 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD14    Filter bits
: CAN0_F15DATA0_FD15   %1 15 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD15    Filter bits
: CAN0_F15DATA0_FD16   %1 16 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD16    Filter bits
: CAN0_F15DATA0_FD17   %1 17 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD17    Filter bits
: CAN0_F15DATA0_FD18   %1 18 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD18    Filter bits
: CAN0_F15DATA0_FD19   %1 19 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD19    Filter bits
: CAN0_F15DATA0_FD20   %1 20 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD20    Filter bits
: CAN0_F15DATA0_FD21   %1 21 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD21    Filter bits
: CAN0_F15DATA0_FD22   %1 22 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD22    Filter bits
: CAN0_F15DATA0_FD23   %1 23 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD23    Filter bits
: CAN0_F15DATA0_FD24   %1 24 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD24    Filter bits
: CAN0_F15DATA0_FD25   %1 25 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD25    Filter bits
: CAN0_F15DATA0_FD26   %1 26 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD26    Filter bits
: CAN0_F15DATA0_FD27   %1 27 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD27    Filter bits
: CAN0_F15DATA0_FD28   %1 28 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD28    Filter bits
: CAN0_F15DATA0_FD29   %1 29 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD29    Filter bits
: CAN0_F15DATA0_FD30   %1 30 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD30    Filter bits
: CAN0_F15DATA0_FD31   %1 31 lshift CAN0_F15DATA0 bis! ;  \ CAN0_F15DATA0_FD31    Filter bits

\ CAN0_F15DATA1 (read-write)
: CAN0_F15DATA1_FD0   %1 0 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD0    Filter bits
: CAN0_F15DATA1_FD1   %1 1 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD1    Filter bits
: CAN0_F15DATA1_FD2   %1 2 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD2    Filter bits
: CAN0_F15DATA1_FD3   %1 3 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD3    Filter bits
: CAN0_F15DATA1_FD4   %1 4 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD4    Filter bits
: CAN0_F15DATA1_FD5   %1 5 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD5    Filter bits
: CAN0_F15DATA1_FD6   %1 6 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD6    Filter bits
: CAN0_F15DATA1_FD7   %1 7 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD7    Filter bits
: CAN0_F15DATA1_FD8   %1 8 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD8    Filter bits
: CAN0_F15DATA1_FD9   %1 9 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD9    Filter bits
: CAN0_F15DATA1_FD10   %1 10 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD10    Filter bits
: CAN0_F15DATA1_FD11   %1 11 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD11    Filter bits
: CAN0_F15DATA1_FD12   %1 12 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD12    Filter bits
: CAN0_F15DATA1_FD13   %1 13 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD13    Filter bits
: CAN0_F15DATA1_FD14   %1 14 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD14    Filter bits
: CAN0_F15DATA1_FD15   %1 15 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD15    Filter bits
: CAN0_F15DATA1_FD16   %1 16 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD16    Filter bits
: CAN0_F15DATA1_FD17   %1 17 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD17    Filter bits
: CAN0_F15DATA1_FD18   %1 18 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD18    Filter bits
: CAN0_F15DATA1_FD19   %1 19 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD19    Filter bits
: CAN0_F15DATA1_FD20   %1 20 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD20    Filter bits
: CAN0_F15DATA1_FD21   %1 21 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD21    Filter bits
: CAN0_F15DATA1_FD22   %1 22 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD22    Filter bits
: CAN0_F15DATA1_FD23   %1 23 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD23    Filter bits
: CAN0_F15DATA1_FD24   %1 24 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD24    Filter bits
: CAN0_F15DATA1_FD25   %1 25 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD25    Filter bits
: CAN0_F15DATA1_FD26   %1 26 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD26    Filter bits
: CAN0_F15DATA1_FD27   %1 27 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD27    Filter bits
: CAN0_F15DATA1_FD28   %1 28 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD28    Filter bits
: CAN0_F15DATA1_FD29   %1 29 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD29    Filter bits
: CAN0_F15DATA1_FD30   %1 30 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD30    Filter bits
: CAN0_F15DATA1_FD31   %1 31 lshift CAN0_F15DATA1 bis! ;  \ CAN0_F15DATA1_FD31    Filter bits

\ CAN0_F16DATA0 (read-write)
: CAN0_F16DATA0_FD0   %1 0 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD0    Filter bits
: CAN0_F16DATA0_FD1   %1 1 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD1    Filter bits
: CAN0_F16DATA0_FD2   %1 2 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD2    Filter bits
: CAN0_F16DATA0_FD3   %1 3 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD3    Filter bits
: CAN0_F16DATA0_FD4   %1 4 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD4    Filter bits
: CAN0_F16DATA0_FD5   %1 5 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD5    Filter bits
: CAN0_F16DATA0_FD6   %1 6 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD6    Filter bits
: CAN0_F16DATA0_FD7   %1 7 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD7    Filter bits
: CAN0_F16DATA0_FD8   %1 8 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD8    Filter bits
: CAN0_F16DATA0_FD9   %1 9 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD9    Filter bits
: CAN0_F16DATA0_FD10   %1 10 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD10    Filter bits
: CAN0_F16DATA0_FD11   %1 11 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD11    Filter bits
: CAN0_F16DATA0_FD12   %1 12 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD12    Filter bits
: CAN0_F16DATA0_FD13   %1 13 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD13    Filter bits
: CAN0_F16DATA0_FD14   %1 14 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD14    Filter bits
: CAN0_F16DATA0_FD15   %1 15 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD15    Filter bits
: CAN0_F16DATA0_FD16   %1 16 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD16    Filter bits
: CAN0_F16DATA0_FD17   %1 17 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD17    Filter bits
: CAN0_F16DATA0_FD18   %1 18 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD18    Filter bits
: CAN0_F16DATA0_FD19   %1 19 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD19    Filter bits
: CAN0_F16DATA0_FD20   %1 20 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD20    Filter bits
: CAN0_F16DATA0_FD21   %1 21 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD21    Filter bits
: CAN0_F16DATA0_FD22   %1 22 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD22    Filter bits
: CAN0_F16DATA0_FD23   %1 23 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD23    Filter bits
: CAN0_F16DATA0_FD24   %1 24 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD24    Filter bits
: CAN0_F16DATA0_FD25   %1 25 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD25    Filter bits
: CAN0_F16DATA0_FD26   %1 26 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD26    Filter bits
: CAN0_F16DATA0_FD27   %1 27 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD27    Filter bits
: CAN0_F16DATA0_FD28   %1 28 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD28    Filter bits
: CAN0_F16DATA0_FD29   %1 29 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD29    Filter bits
: CAN0_F16DATA0_FD30   %1 30 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD30    Filter bits
: CAN0_F16DATA0_FD31   %1 31 lshift CAN0_F16DATA0 bis! ;  \ CAN0_F16DATA0_FD31    Filter bits

\ CAN0_F16DATA1 (read-write)
: CAN0_F16DATA1_FD0   %1 0 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD0    Filter bits
: CAN0_F16DATA1_FD1   %1 1 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD1    Filter bits
: CAN0_F16DATA1_FD2   %1 2 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD2    Filter bits
: CAN0_F16DATA1_FD3   %1 3 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD3    Filter bits
: CAN0_F16DATA1_FD4   %1 4 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD4    Filter bits
: CAN0_F16DATA1_FD5   %1 5 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD5    Filter bits
: CAN0_F16DATA1_FD6   %1 6 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD6    Filter bits
: CAN0_F16DATA1_FD7   %1 7 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD7    Filter bits
: CAN0_F16DATA1_FD8   %1 8 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD8    Filter bits
: CAN0_F16DATA1_FD9   %1 9 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD9    Filter bits
: CAN0_F16DATA1_FD10   %1 10 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD10    Filter bits
: CAN0_F16DATA1_FD11   %1 11 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD11    Filter bits
: CAN0_F16DATA1_FD12   %1 12 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD12    Filter bits
: CAN0_F16DATA1_FD13   %1 13 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD13    Filter bits
: CAN0_F16DATA1_FD14   %1 14 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD14    Filter bits
: CAN0_F16DATA1_FD15   %1 15 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD15    Filter bits
: CAN0_F16DATA1_FD16   %1 16 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD16    Filter bits
: CAN0_F16DATA1_FD17   %1 17 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD17    Filter bits
: CAN0_F16DATA1_FD18   %1 18 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD18    Filter bits
: CAN0_F16DATA1_FD19   %1 19 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD19    Filter bits
: CAN0_F16DATA1_FD20   %1 20 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD20    Filter bits
: CAN0_F16DATA1_FD21   %1 21 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD21    Filter bits
: CAN0_F16DATA1_FD22   %1 22 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD22    Filter bits
: CAN0_F16DATA1_FD23   %1 23 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD23    Filter bits
: CAN0_F16DATA1_FD24   %1 24 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD24    Filter bits
: CAN0_F16DATA1_FD25   %1 25 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD25    Filter bits
: CAN0_F16DATA1_FD26   %1 26 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD26    Filter bits
: CAN0_F16DATA1_FD27   %1 27 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD27    Filter bits
: CAN0_F16DATA1_FD28   %1 28 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD28    Filter bits
: CAN0_F16DATA1_FD29   %1 29 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD29    Filter bits
: CAN0_F16DATA1_FD30   %1 30 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD30    Filter bits
: CAN0_F16DATA1_FD31   %1 31 lshift CAN0_F16DATA1 bis! ;  \ CAN0_F16DATA1_FD31    Filter bits

\ CAN0_F17DATA0 (read-write)
: CAN0_F17DATA0_FD0   %1 0 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD0    Filter bits
: CAN0_F17DATA0_FD1   %1 1 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD1    Filter bits
: CAN0_F17DATA0_FD2   %1 2 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD2    Filter bits
: CAN0_F17DATA0_FD3   %1 3 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD3    Filter bits
: CAN0_F17DATA0_FD4   %1 4 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD4    Filter bits
: CAN0_F17DATA0_FD5   %1 5 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD5    Filter bits
: CAN0_F17DATA0_FD6   %1 6 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD6    Filter bits
: CAN0_F17DATA0_FD7   %1 7 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD7    Filter bits
: CAN0_F17DATA0_FD8   %1 8 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD8    Filter bits
: CAN0_F17DATA0_FD9   %1 9 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD9    Filter bits
: CAN0_F17DATA0_FD10   %1 10 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD10    Filter bits
: CAN0_F17DATA0_FD11   %1 11 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD11    Filter bits
: CAN0_F17DATA0_FD12   %1 12 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD12    Filter bits
: CAN0_F17DATA0_FD13   %1 13 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD13    Filter bits
: CAN0_F17DATA0_FD14   %1 14 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD14    Filter bits
: CAN0_F17DATA0_FD15   %1 15 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD15    Filter bits
: CAN0_F17DATA0_FD16   %1 16 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD16    Filter bits
: CAN0_F17DATA0_FD17   %1 17 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD17    Filter bits
: CAN0_F17DATA0_FD18   %1 18 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD18    Filter bits
: CAN0_F17DATA0_FD19   %1 19 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD19    Filter bits
: CAN0_F17DATA0_FD20   %1 20 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD20    Filter bits
: CAN0_F17DATA0_FD21   %1 21 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD21    Filter bits
: CAN0_F17DATA0_FD22   %1 22 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD22    Filter bits
: CAN0_F17DATA0_FD23   %1 23 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD23    Filter bits
: CAN0_F17DATA0_FD24   %1 24 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD24    Filter bits
: CAN0_F17DATA0_FD25   %1 25 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD25    Filter bits
: CAN0_F17DATA0_FD26   %1 26 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD26    Filter bits
: CAN0_F17DATA0_FD27   %1 27 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD27    Filter bits
: CAN0_F17DATA0_FD28   %1 28 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD28    Filter bits
: CAN0_F17DATA0_FD29   %1 29 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD29    Filter bits
: CAN0_F17DATA0_FD30   %1 30 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD30    Filter bits
: CAN0_F17DATA0_FD31   %1 31 lshift CAN0_F17DATA0 bis! ;  \ CAN0_F17DATA0_FD31    Filter bits

\ CAN0_F17DATA1 (read-write)
: CAN0_F17DATA1_FD0   %1 0 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD0    Filter bits
: CAN0_F17DATA1_FD1   %1 1 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD1    Filter bits
: CAN0_F17DATA1_FD2   %1 2 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD2    Filter bits
: CAN0_F17DATA1_FD3   %1 3 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD3    Filter bits
: CAN0_F17DATA1_FD4   %1 4 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD4    Filter bits
: CAN0_F17DATA1_FD5   %1 5 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD5    Filter bits
: CAN0_F17DATA1_FD6   %1 6 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD6    Filter bits
: CAN0_F17DATA1_FD7   %1 7 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD7    Filter bits
: CAN0_F17DATA1_FD8   %1 8 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD8    Filter bits
: CAN0_F17DATA1_FD9   %1 9 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD9    Filter bits
: CAN0_F17DATA1_FD10   %1 10 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD10    Filter bits
: CAN0_F17DATA1_FD11   %1 11 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD11    Filter bits
: CAN0_F17DATA1_FD12   %1 12 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD12    Filter bits
: CAN0_F17DATA1_FD13   %1 13 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD13    Filter bits
: CAN0_F17DATA1_FD14   %1 14 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD14    Filter bits
: CAN0_F17DATA1_FD15   %1 15 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD15    Filter bits
: CAN0_F17DATA1_FD16   %1 16 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD16    Filter bits
: CAN0_F17DATA1_FD17   %1 17 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD17    Filter bits
: CAN0_F17DATA1_FD18   %1 18 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD18    Filter bits
: CAN0_F17DATA1_FD19   %1 19 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD19    Filter bits
: CAN0_F17DATA1_FD20   %1 20 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD20    Filter bits
: CAN0_F17DATA1_FD21   %1 21 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD21    Filter bits
: CAN0_F17DATA1_FD22   %1 22 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD22    Filter bits
: CAN0_F17DATA1_FD23   %1 23 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD23    Filter bits
: CAN0_F17DATA1_FD24   %1 24 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD24    Filter bits
: CAN0_F17DATA1_FD25   %1 25 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD25    Filter bits
: CAN0_F17DATA1_FD26   %1 26 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD26    Filter bits
: CAN0_F17DATA1_FD27   %1 27 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD27    Filter bits
: CAN0_F17DATA1_FD28   %1 28 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD28    Filter bits
: CAN0_F17DATA1_FD29   %1 29 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD29    Filter bits
: CAN0_F17DATA1_FD30   %1 30 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD30    Filter bits
: CAN0_F17DATA1_FD31   %1 31 lshift CAN0_F17DATA1 bis! ;  \ CAN0_F17DATA1_FD31    Filter bits

\ CAN0_F18DATA0 (read-write)
: CAN0_F18DATA0_FD0   %1 0 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD0    Filter bits
: CAN0_F18DATA0_FD1   %1 1 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD1    Filter bits
: CAN0_F18DATA0_FD2   %1 2 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD2    Filter bits
: CAN0_F18DATA0_FD3   %1 3 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD3    Filter bits
: CAN0_F18DATA0_FD4   %1 4 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD4    Filter bits
: CAN0_F18DATA0_FD5   %1 5 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD5    Filter bits
: CAN0_F18DATA0_FD6   %1 6 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD6    Filter bits
: CAN0_F18DATA0_FD7   %1 7 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD7    Filter bits
: CAN0_F18DATA0_FD8   %1 8 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD8    Filter bits
: CAN0_F18DATA0_FD9   %1 9 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD9    Filter bits
: CAN0_F18DATA0_FD10   %1 10 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD10    Filter bits
: CAN0_F18DATA0_FD11   %1 11 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD11    Filter bits
: CAN0_F18DATA0_FD12   %1 12 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD12    Filter bits
: CAN0_F18DATA0_FD13   %1 13 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD13    Filter bits
: CAN0_F18DATA0_FD14   %1 14 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD14    Filter bits
: CAN0_F18DATA0_FD15   %1 15 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD15    Filter bits
: CAN0_F18DATA0_FD16   %1 16 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD16    Filter bits
: CAN0_F18DATA0_FD17   %1 17 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD17    Filter bits
: CAN0_F18DATA0_FD18   %1 18 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD18    Filter bits
: CAN0_F18DATA0_FD19   %1 19 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD19    Filter bits
: CAN0_F18DATA0_FD20   %1 20 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD20    Filter bits
: CAN0_F18DATA0_FD21   %1 21 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD21    Filter bits
: CAN0_F18DATA0_FD22   %1 22 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD22    Filter bits
: CAN0_F18DATA0_FD23   %1 23 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD23    Filter bits
: CAN0_F18DATA0_FD24   %1 24 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD24    Filter bits
: CAN0_F18DATA0_FD25   %1 25 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD25    Filter bits
: CAN0_F18DATA0_FD26   %1 26 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD26    Filter bits
: CAN0_F18DATA0_FD27   %1 27 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD27    Filter bits
: CAN0_F18DATA0_FD28   %1 28 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD28    Filter bits
: CAN0_F18DATA0_FD29   %1 29 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD29    Filter bits
: CAN0_F18DATA0_FD30   %1 30 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD30    Filter bits
: CAN0_F18DATA0_FD31   %1 31 lshift CAN0_F18DATA0 bis! ;  \ CAN0_F18DATA0_FD31    Filter bits

\ CAN0_F18DATA1 (read-write)
: CAN0_F18DATA1_FD0   %1 0 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD0    Filter bits
: CAN0_F18DATA1_FD1   %1 1 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD1    Filter bits
: CAN0_F18DATA1_FD2   %1 2 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD2    Filter bits
: CAN0_F18DATA1_FD3   %1 3 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD3    Filter bits
: CAN0_F18DATA1_FD4   %1 4 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD4    Filter bits
: CAN0_F18DATA1_FD5   %1 5 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD5    Filter bits
: CAN0_F18DATA1_FD6   %1 6 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD6    Filter bits
: CAN0_F18DATA1_FD7   %1 7 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD7    Filter bits
: CAN0_F18DATA1_FD8   %1 8 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD8    Filter bits
: CAN0_F18DATA1_FD9   %1 9 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD9    Filter bits
: CAN0_F18DATA1_FD10   %1 10 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD10    Filter bits
: CAN0_F18DATA1_FD11   %1 11 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD11    Filter bits
: CAN0_F18DATA1_FD12   %1 12 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD12    Filter bits
: CAN0_F18DATA1_FD13   %1 13 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD13    Filter bits
: CAN0_F18DATA1_FD14   %1 14 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD14    Filter bits
: CAN0_F18DATA1_FD15   %1 15 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD15    Filter bits
: CAN0_F18DATA1_FD16   %1 16 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD16    Filter bits
: CAN0_F18DATA1_FD17   %1 17 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD17    Filter bits
: CAN0_F18DATA1_FD18   %1 18 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD18    Filter bits
: CAN0_F18DATA1_FD19   %1 19 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD19    Filter bits
: CAN0_F18DATA1_FD20   %1 20 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD20    Filter bits
: CAN0_F18DATA1_FD21   %1 21 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD21    Filter bits
: CAN0_F18DATA1_FD22   %1 22 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD22    Filter bits
: CAN0_F18DATA1_FD23   %1 23 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD23    Filter bits
: CAN0_F18DATA1_FD24   %1 24 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD24    Filter bits
: CAN0_F18DATA1_FD25   %1 25 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD25    Filter bits
: CAN0_F18DATA1_FD26   %1 26 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD26    Filter bits
: CAN0_F18DATA1_FD27   %1 27 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD27    Filter bits
: CAN0_F18DATA1_FD28   %1 28 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD28    Filter bits
: CAN0_F18DATA1_FD29   %1 29 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD29    Filter bits
: CAN0_F18DATA1_FD30   %1 30 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD30    Filter bits
: CAN0_F18DATA1_FD31   %1 31 lshift CAN0_F18DATA1 bis! ;  \ CAN0_F18DATA1_FD31    Filter bits

\ CAN0_F19DATA0 (read-write)
: CAN0_F19DATA0_FD0   %1 0 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD0    Filter bits
: CAN0_F19DATA0_FD1   %1 1 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD1    Filter bits
: CAN0_F19DATA0_FD2   %1 2 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD2    Filter bits
: CAN0_F19DATA0_FD3   %1 3 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD3    Filter bits
: CAN0_F19DATA0_FD4   %1 4 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD4    Filter bits
: CAN0_F19DATA0_FD5   %1 5 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD5    Filter bits
: CAN0_F19DATA0_FD6   %1 6 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD6    Filter bits
: CAN0_F19DATA0_FD7   %1 7 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD7    Filter bits
: CAN0_F19DATA0_FD8   %1 8 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD8    Filter bits
: CAN0_F19DATA0_FD9   %1 9 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD9    Filter bits
: CAN0_F19DATA0_FD10   %1 10 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD10    Filter bits
: CAN0_F19DATA0_FD11   %1 11 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD11    Filter bits
: CAN0_F19DATA0_FD12   %1 12 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD12    Filter bits
: CAN0_F19DATA0_FD13   %1 13 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD13    Filter bits
: CAN0_F19DATA0_FD14   %1 14 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD14    Filter bits
: CAN0_F19DATA0_FD15   %1 15 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD15    Filter bits
: CAN0_F19DATA0_FD16   %1 16 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD16    Filter bits
: CAN0_F19DATA0_FD17   %1 17 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD17    Filter bits
: CAN0_F19DATA0_FD18   %1 18 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD18    Filter bits
: CAN0_F19DATA0_FD19   %1 19 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD19    Filter bits
: CAN0_F19DATA0_FD20   %1 20 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD20    Filter bits
: CAN0_F19DATA0_FD21   %1 21 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD21    Filter bits
: CAN0_F19DATA0_FD22   %1 22 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD22    Filter bits
: CAN0_F19DATA0_FD23   %1 23 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD23    Filter bits
: CAN0_F19DATA0_FD24   %1 24 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD24    Filter bits
: CAN0_F19DATA0_FD25   %1 25 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD25    Filter bits
: CAN0_F19DATA0_FD26   %1 26 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD26    Filter bits
: CAN0_F19DATA0_FD27   %1 27 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD27    Filter bits
: CAN0_F19DATA0_FD28   %1 28 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD28    Filter bits
: CAN0_F19DATA0_FD29   %1 29 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD29    Filter bits
: CAN0_F19DATA0_FD30   %1 30 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD30    Filter bits
: CAN0_F19DATA0_FD31   %1 31 lshift CAN0_F19DATA0 bis! ;  \ CAN0_F19DATA0_FD31    Filter bits

\ CAN0_F19DATA1 (read-write)
: CAN0_F19DATA1_FD0   %1 0 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD0    Filter bits
: CAN0_F19DATA1_FD1   %1 1 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD1    Filter bits
: CAN0_F19DATA1_FD2   %1 2 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD2    Filter bits
: CAN0_F19DATA1_FD3   %1 3 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD3    Filter bits
: CAN0_F19DATA1_FD4   %1 4 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD4    Filter bits
: CAN0_F19DATA1_FD5   %1 5 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD5    Filter bits
: CAN0_F19DATA1_FD6   %1 6 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD6    Filter bits
: CAN0_F19DATA1_FD7   %1 7 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD7    Filter bits
: CAN0_F19DATA1_FD8   %1 8 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD8    Filter bits
: CAN0_F19DATA1_FD9   %1 9 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD9    Filter bits
: CAN0_F19DATA1_FD10   %1 10 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD10    Filter bits
: CAN0_F19DATA1_FD11   %1 11 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD11    Filter bits
: CAN0_F19DATA1_FD12   %1 12 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD12    Filter bits
: CAN0_F19DATA1_FD13   %1 13 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD13    Filter bits
: CAN0_F19DATA1_FD14   %1 14 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD14    Filter bits
: CAN0_F19DATA1_FD15   %1 15 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD15    Filter bits
: CAN0_F19DATA1_FD16   %1 16 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD16    Filter bits
: CAN0_F19DATA1_FD17   %1 17 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD17    Filter bits
: CAN0_F19DATA1_FD18   %1 18 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD18    Filter bits
: CAN0_F19DATA1_FD19   %1 19 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD19    Filter bits
: CAN0_F19DATA1_FD20   %1 20 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD20    Filter bits
: CAN0_F19DATA1_FD21   %1 21 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD21    Filter bits
: CAN0_F19DATA1_FD22   %1 22 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD22    Filter bits
: CAN0_F19DATA1_FD23   %1 23 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD23    Filter bits
: CAN0_F19DATA1_FD24   %1 24 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD24    Filter bits
: CAN0_F19DATA1_FD25   %1 25 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD25    Filter bits
: CAN0_F19DATA1_FD26   %1 26 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD26    Filter bits
: CAN0_F19DATA1_FD27   %1 27 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD27    Filter bits
: CAN0_F19DATA1_FD28   %1 28 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD28    Filter bits
: CAN0_F19DATA1_FD29   %1 29 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD29    Filter bits
: CAN0_F19DATA1_FD30   %1 30 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD30    Filter bits
: CAN0_F19DATA1_FD31   %1 31 lshift CAN0_F19DATA1 bis! ;  \ CAN0_F19DATA1_FD31    Filter bits

\ CAN0_F20DATA0 (read-write)
: CAN0_F20DATA0_FD0   %1 0 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD0    Filter bits
: CAN0_F20DATA0_FD1   %1 1 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD1    Filter bits
: CAN0_F20DATA0_FD2   %1 2 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD2    Filter bits
: CAN0_F20DATA0_FD3   %1 3 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD3    Filter bits
: CAN0_F20DATA0_FD4   %1 4 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD4    Filter bits
: CAN0_F20DATA0_FD5   %1 5 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD5    Filter bits
: CAN0_F20DATA0_FD6   %1 6 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD6    Filter bits
: CAN0_F20DATA0_FD7   %1 7 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD7    Filter bits
: CAN0_F20DATA0_FD8   %1 8 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD8    Filter bits
: CAN0_F20DATA0_FD9   %1 9 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD9    Filter bits
: CAN0_F20DATA0_FD10   %1 10 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD10    Filter bits
: CAN0_F20DATA0_FD11   %1 11 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD11    Filter bits
: CAN0_F20DATA0_FD12   %1 12 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD12    Filter bits
: CAN0_F20DATA0_FD13   %1 13 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD13    Filter bits
: CAN0_F20DATA0_FD14   %1 14 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD14    Filter bits
: CAN0_F20DATA0_FD15   %1 15 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD15    Filter bits
: CAN0_F20DATA0_FD16   %1 16 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD16    Filter bits
: CAN0_F20DATA0_FD17   %1 17 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD17    Filter bits
: CAN0_F20DATA0_FD18   %1 18 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD18    Filter bits
: CAN0_F20DATA0_FD19   %1 19 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD19    Filter bits
: CAN0_F20DATA0_FD20   %1 20 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD20    Filter bits
: CAN0_F20DATA0_FD21   %1 21 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD21    Filter bits
: CAN0_F20DATA0_FD22   %1 22 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD22    Filter bits
: CAN0_F20DATA0_FD23   %1 23 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD23    Filter bits
: CAN0_F20DATA0_FD24   %1 24 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD24    Filter bits
: CAN0_F20DATA0_FD25   %1 25 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD25    Filter bits
: CAN0_F20DATA0_FD26   %1 26 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD26    Filter bits
: CAN0_F20DATA0_FD27   %1 27 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD27    Filter bits
: CAN0_F20DATA0_FD28   %1 28 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD28    Filter bits
: CAN0_F20DATA0_FD29   %1 29 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD29    Filter bits
: CAN0_F20DATA0_FD30   %1 30 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD30    Filter bits
: CAN0_F20DATA0_FD31   %1 31 lshift CAN0_F20DATA0 bis! ;  \ CAN0_F20DATA0_FD31    Filter bits

\ CAN0_F20DATA1 (read-write)
: CAN0_F20DATA1_FD0   %1 0 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD0    Filter bits
: CAN0_F20DATA1_FD1   %1 1 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD1    Filter bits
: CAN0_F20DATA1_FD2   %1 2 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD2    Filter bits
: CAN0_F20DATA1_FD3   %1 3 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD3    Filter bits
: CAN0_F20DATA1_FD4   %1 4 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD4    Filter bits
: CAN0_F20DATA1_FD5   %1 5 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD5    Filter bits
: CAN0_F20DATA1_FD6   %1 6 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD6    Filter bits
: CAN0_F20DATA1_FD7   %1 7 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD7    Filter bits
: CAN0_F20DATA1_FD8   %1 8 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD8    Filter bits
: CAN0_F20DATA1_FD9   %1 9 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD9    Filter bits
: CAN0_F20DATA1_FD10   %1 10 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD10    Filter bits
: CAN0_F20DATA1_FD11   %1 11 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD11    Filter bits
: CAN0_F20DATA1_FD12   %1 12 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD12    Filter bits
: CAN0_F20DATA1_FD13   %1 13 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD13    Filter bits
: CAN0_F20DATA1_FD14   %1 14 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD14    Filter bits
: CAN0_F20DATA1_FD15   %1 15 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD15    Filter bits
: CAN0_F20DATA1_FD16   %1 16 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD16    Filter bits
: CAN0_F20DATA1_FD17   %1 17 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD17    Filter bits
: CAN0_F20DATA1_FD18   %1 18 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD18    Filter bits
: CAN0_F20DATA1_FD19   %1 19 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD19    Filter bits
: CAN0_F20DATA1_FD20   %1 20 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD20    Filter bits
: CAN0_F20DATA1_FD21   %1 21 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD21    Filter bits
: CAN0_F20DATA1_FD22   %1 22 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD22    Filter bits
: CAN0_F20DATA1_FD23   %1 23 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD23    Filter bits
: CAN0_F20DATA1_FD24   %1 24 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD24    Filter bits
: CAN0_F20DATA1_FD25   %1 25 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD25    Filter bits
: CAN0_F20DATA1_FD26   %1 26 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD26    Filter bits
: CAN0_F20DATA1_FD27   %1 27 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD27    Filter bits
: CAN0_F20DATA1_FD28   %1 28 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD28    Filter bits
: CAN0_F20DATA1_FD29   %1 29 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD29    Filter bits
: CAN0_F20DATA1_FD30   %1 30 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD30    Filter bits
: CAN0_F20DATA1_FD31   %1 31 lshift CAN0_F20DATA1 bis! ;  \ CAN0_F20DATA1_FD31    Filter bits

\ CAN0_F21DATA0 (read-write)
: CAN0_F21DATA0_FD0   %1 0 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD0    Filter bits
: CAN0_F21DATA0_FD1   %1 1 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD1    Filter bits
: CAN0_F21DATA0_FD2   %1 2 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD2    Filter bits
: CAN0_F21DATA0_FD3   %1 3 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD3    Filter bits
: CAN0_F21DATA0_FD4   %1 4 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD4    Filter bits
: CAN0_F21DATA0_FD5   %1 5 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD5    Filter bits
: CAN0_F21DATA0_FD6   %1 6 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD6    Filter bits
: CAN0_F21DATA0_FD7   %1 7 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD7    Filter bits
: CAN0_F21DATA0_FD8   %1 8 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD8    Filter bits
: CAN0_F21DATA0_FD9   %1 9 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD9    Filter bits
: CAN0_F21DATA0_FD10   %1 10 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD10    Filter bits
: CAN0_F21DATA0_FD11   %1 11 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD11    Filter bits
: CAN0_F21DATA0_FD12   %1 12 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD12    Filter bits
: CAN0_F21DATA0_FD13   %1 13 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD13    Filter bits
: CAN0_F21DATA0_FD14   %1 14 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD14    Filter bits
: CAN0_F21DATA0_FD15   %1 15 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD15    Filter bits
: CAN0_F21DATA0_FD16   %1 16 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD16    Filter bits
: CAN0_F21DATA0_FD17   %1 17 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD17    Filter bits
: CAN0_F21DATA0_FD18   %1 18 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD18    Filter bits
: CAN0_F21DATA0_FD19   %1 19 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD19    Filter bits
: CAN0_F21DATA0_FD20   %1 20 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD20    Filter bits
: CAN0_F21DATA0_FD21   %1 21 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD21    Filter bits
: CAN0_F21DATA0_FD22   %1 22 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD22    Filter bits
: CAN0_F21DATA0_FD23   %1 23 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD23    Filter bits
: CAN0_F21DATA0_FD24   %1 24 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD24    Filter bits
: CAN0_F21DATA0_FD25   %1 25 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD25    Filter bits
: CAN0_F21DATA0_FD26   %1 26 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD26    Filter bits
: CAN0_F21DATA0_FD27   %1 27 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD27    Filter bits
: CAN0_F21DATA0_FD28   %1 28 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD28    Filter bits
: CAN0_F21DATA0_FD29   %1 29 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD29    Filter bits
: CAN0_F21DATA0_FD30   %1 30 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD30    Filter bits
: CAN0_F21DATA0_FD31   %1 31 lshift CAN0_F21DATA0 bis! ;  \ CAN0_F21DATA0_FD31    Filter bits

\ CAN0_F21DATA1 (read-write)
: CAN0_F21DATA1_FD0   %1 0 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD0    Filter bits
: CAN0_F21DATA1_FD1   %1 1 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD1    Filter bits
: CAN0_F21DATA1_FD2   %1 2 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD2    Filter bits
: CAN0_F21DATA1_FD3   %1 3 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD3    Filter bits
: CAN0_F21DATA1_FD4   %1 4 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD4    Filter bits
: CAN0_F21DATA1_FD5   %1 5 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD5    Filter bits
: CAN0_F21DATA1_FD6   %1 6 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD6    Filter bits
: CAN0_F21DATA1_FD7   %1 7 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD7    Filter bits
: CAN0_F21DATA1_FD8   %1 8 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD8    Filter bits
: CAN0_F21DATA1_FD9   %1 9 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD9    Filter bits
: CAN0_F21DATA1_FD10   %1 10 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD10    Filter bits
: CAN0_F21DATA1_FD11   %1 11 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD11    Filter bits
: CAN0_F21DATA1_FD12   %1 12 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD12    Filter bits
: CAN0_F21DATA1_FD13   %1 13 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD13    Filter bits
: CAN0_F21DATA1_FD14   %1 14 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD14    Filter bits
: CAN0_F21DATA1_FD15   %1 15 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD15    Filter bits
: CAN0_F21DATA1_FD16   %1 16 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD16    Filter bits
: CAN0_F21DATA1_FD17   %1 17 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD17    Filter bits
: CAN0_F21DATA1_FD18   %1 18 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD18    Filter bits
: CAN0_F21DATA1_FD19   %1 19 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD19    Filter bits
: CAN0_F21DATA1_FD20   %1 20 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD20    Filter bits
: CAN0_F21DATA1_FD21   %1 21 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD21    Filter bits
: CAN0_F21DATA1_FD22   %1 22 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD22    Filter bits
: CAN0_F21DATA1_FD23   %1 23 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD23    Filter bits
: CAN0_F21DATA1_FD24   %1 24 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD24    Filter bits
: CAN0_F21DATA1_FD25   %1 25 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD25    Filter bits
: CAN0_F21DATA1_FD26   %1 26 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD26    Filter bits
: CAN0_F21DATA1_FD27   %1 27 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD27    Filter bits
: CAN0_F21DATA1_FD28   %1 28 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD28    Filter bits
: CAN0_F21DATA1_FD29   %1 29 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD29    Filter bits
: CAN0_F21DATA1_FD30   %1 30 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD30    Filter bits
: CAN0_F21DATA1_FD31   %1 31 lshift CAN0_F21DATA1 bis! ;  \ CAN0_F21DATA1_FD31    Filter bits

\ CAN0_F22DATA0 (read-write)
: CAN0_F22DATA0_FD0   %1 0 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD0    Filter bits
: CAN0_F22DATA0_FD1   %1 1 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD1    Filter bits
: CAN0_F22DATA0_FD2   %1 2 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD2    Filter bits
: CAN0_F22DATA0_FD3   %1 3 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD3    Filter bits
: CAN0_F22DATA0_FD4   %1 4 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD4    Filter bits
: CAN0_F22DATA0_FD5   %1 5 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD5    Filter bits
: CAN0_F22DATA0_FD6   %1 6 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD6    Filter bits
: CAN0_F22DATA0_FD7   %1 7 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD7    Filter bits
: CAN0_F22DATA0_FD8   %1 8 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD8    Filter bits
: CAN0_F22DATA0_FD9   %1 9 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD9    Filter bits
: CAN0_F22DATA0_FD10   %1 10 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD10    Filter bits
: CAN0_F22DATA0_FD11   %1 11 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD11    Filter bits
: CAN0_F22DATA0_FD12   %1 12 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD12    Filter bits
: CAN0_F22DATA0_FD13   %1 13 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD13    Filter bits
: CAN0_F22DATA0_FD14   %1 14 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD14    Filter bits
: CAN0_F22DATA0_FD15   %1 15 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD15    Filter bits
: CAN0_F22DATA0_FD16   %1 16 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD16    Filter bits
: CAN0_F22DATA0_FD17   %1 17 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD17    Filter bits
: CAN0_F22DATA0_FD18   %1 18 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD18    Filter bits
: CAN0_F22DATA0_FD19   %1 19 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD19    Filter bits
: CAN0_F22DATA0_FD20   %1 20 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD20    Filter bits
: CAN0_F22DATA0_FD21   %1 21 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD21    Filter bits
: CAN0_F22DATA0_FD22   %1 22 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD22    Filter bits
: CAN0_F22DATA0_FD23   %1 23 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD23    Filter bits
: CAN0_F22DATA0_FD24   %1 24 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD24    Filter bits
: CAN0_F22DATA0_FD25   %1 25 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD25    Filter bits
: CAN0_F22DATA0_FD26   %1 26 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD26    Filter bits
: CAN0_F22DATA0_FD27   %1 27 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD27    Filter bits
: CAN0_F22DATA0_FD28   %1 28 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD28    Filter bits
: CAN0_F22DATA0_FD29   %1 29 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD29    Filter bits
: CAN0_F22DATA0_FD30   %1 30 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD30    Filter bits
: CAN0_F22DATA0_FD31   %1 31 lshift CAN0_F22DATA0 bis! ;  \ CAN0_F22DATA0_FD31    Filter bits

\ CAN0_F22DATA1 (read-write)
: CAN0_F22DATA1_FD0   %1 0 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD0    Filter bits
: CAN0_F22DATA1_FD1   %1 1 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD1    Filter bits
: CAN0_F22DATA1_FD2   %1 2 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD2    Filter bits
: CAN0_F22DATA1_FD3   %1 3 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD3    Filter bits
: CAN0_F22DATA1_FD4   %1 4 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD4    Filter bits
: CAN0_F22DATA1_FD5   %1 5 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD5    Filter bits
: CAN0_F22DATA1_FD6   %1 6 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD6    Filter bits
: CAN0_F22DATA1_FD7   %1 7 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD7    Filter bits
: CAN0_F22DATA1_FD8   %1 8 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD8    Filter bits
: CAN0_F22DATA1_FD9   %1 9 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD9    Filter bits
: CAN0_F22DATA1_FD10   %1 10 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD10    Filter bits
: CAN0_F22DATA1_FD11   %1 11 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD11    Filter bits
: CAN0_F22DATA1_FD12   %1 12 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD12    Filter bits
: CAN0_F22DATA1_FD13   %1 13 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD13    Filter bits
: CAN0_F22DATA1_FD14   %1 14 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD14    Filter bits
: CAN0_F22DATA1_FD15   %1 15 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD15    Filter bits
: CAN0_F22DATA1_FD16   %1 16 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD16    Filter bits
: CAN0_F22DATA1_FD17   %1 17 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD17    Filter bits
: CAN0_F22DATA1_FD18   %1 18 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD18    Filter bits
: CAN0_F22DATA1_FD19   %1 19 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD19    Filter bits
: CAN0_F22DATA1_FD20   %1 20 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD20    Filter bits
: CAN0_F22DATA1_FD21   %1 21 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD21    Filter bits
: CAN0_F22DATA1_FD22   %1 22 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD22    Filter bits
: CAN0_F22DATA1_FD23   %1 23 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD23    Filter bits
: CAN0_F22DATA1_FD24   %1 24 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD24    Filter bits
: CAN0_F22DATA1_FD25   %1 25 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD25    Filter bits
: CAN0_F22DATA1_FD26   %1 26 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD26    Filter bits
: CAN0_F22DATA1_FD27   %1 27 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD27    Filter bits
: CAN0_F22DATA1_FD28   %1 28 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD28    Filter bits
: CAN0_F22DATA1_FD29   %1 29 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD29    Filter bits
: CAN0_F22DATA1_FD30   %1 30 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD30    Filter bits
: CAN0_F22DATA1_FD31   %1 31 lshift CAN0_F22DATA1 bis! ;  \ CAN0_F22DATA1_FD31    Filter bits

\ CAN0_F23DATA0 (read-write)
: CAN0_F23DATA0_FD0   %1 0 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD0    Filter bits
: CAN0_F23DATA0_FD1   %1 1 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD1    Filter bits
: CAN0_F23DATA0_FD2   %1 2 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD2    Filter bits
: CAN0_F23DATA0_FD3   %1 3 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD3    Filter bits
: CAN0_F23DATA0_FD4   %1 4 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD4    Filter bits
: CAN0_F23DATA0_FD5   %1 5 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD5    Filter bits
: CAN0_F23DATA0_FD6   %1 6 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD6    Filter bits
: CAN0_F23DATA0_FD7   %1 7 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD7    Filter bits
: CAN0_F23DATA0_FD8   %1 8 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD8    Filter bits
: CAN0_F23DATA0_FD9   %1 9 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD9    Filter bits
: CAN0_F23DATA0_FD10   %1 10 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD10    Filter bits
: CAN0_F23DATA0_FD11   %1 11 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD11    Filter bits
: CAN0_F23DATA0_FD12   %1 12 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD12    Filter bits
: CAN0_F23DATA0_FD13   %1 13 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD13    Filter bits
: CAN0_F23DATA0_FD14   %1 14 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD14    Filter bits
: CAN0_F23DATA0_FD15   %1 15 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD15    Filter bits
: CAN0_F23DATA0_FD16   %1 16 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD16    Filter bits
: CAN0_F23DATA0_FD17   %1 17 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD17    Filter bits
: CAN0_F23DATA0_FD18   %1 18 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD18    Filter bits
: CAN0_F23DATA0_FD19   %1 19 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD19    Filter bits
: CAN0_F23DATA0_FD20   %1 20 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD20    Filter bits
: CAN0_F23DATA0_FD21   %1 21 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD21    Filter bits
: CAN0_F23DATA0_FD22   %1 22 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD22    Filter bits
: CAN0_F23DATA0_FD23   %1 23 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD23    Filter bits
: CAN0_F23DATA0_FD24   %1 24 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD24    Filter bits
: CAN0_F23DATA0_FD25   %1 25 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD25    Filter bits
: CAN0_F23DATA0_FD26   %1 26 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD26    Filter bits
: CAN0_F23DATA0_FD27   %1 27 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD27    Filter bits
: CAN0_F23DATA0_FD28   %1 28 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD28    Filter bits
: CAN0_F23DATA0_FD29   %1 29 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD29    Filter bits
: CAN0_F23DATA0_FD30   %1 30 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD30    Filter bits
: CAN0_F23DATA0_FD31   %1 31 lshift CAN0_F23DATA0 bis! ;  \ CAN0_F23DATA0_FD31    Filter bits

\ CAN0_F23DATA1 (read-write)
: CAN0_F23DATA1_FD0   %1 0 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD0    Filter bits
: CAN0_F23DATA1_FD1   %1 1 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD1    Filter bits
: CAN0_F23DATA1_FD2   %1 2 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD2    Filter bits
: CAN0_F23DATA1_FD3   %1 3 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD3    Filter bits
: CAN0_F23DATA1_FD4   %1 4 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD4    Filter bits
: CAN0_F23DATA1_FD5   %1 5 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD5    Filter bits
: CAN0_F23DATA1_FD6   %1 6 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD6    Filter bits
: CAN0_F23DATA1_FD7   %1 7 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD7    Filter bits
: CAN0_F23DATA1_FD8   %1 8 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD8    Filter bits
: CAN0_F23DATA1_FD9   %1 9 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD9    Filter bits
: CAN0_F23DATA1_FD10   %1 10 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD10    Filter bits
: CAN0_F23DATA1_FD11   %1 11 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD11    Filter bits
: CAN0_F23DATA1_FD12   %1 12 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD12    Filter bits
: CAN0_F23DATA1_FD13   %1 13 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD13    Filter bits
: CAN0_F23DATA1_FD14   %1 14 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD14    Filter bits
: CAN0_F23DATA1_FD15   %1 15 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD15    Filter bits
: CAN0_F23DATA1_FD16   %1 16 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD16    Filter bits
: CAN0_F23DATA1_FD17   %1 17 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD17    Filter bits
: CAN0_F23DATA1_FD18   %1 18 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD18    Filter bits
: CAN0_F23DATA1_FD19   %1 19 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD19    Filter bits
: CAN0_F23DATA1_FD20   %1 20 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD20    Filter bits
: CAN0_F23DATA1_FD21   %1 21 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD21    Filter bits
: CAN0_F23DATA1_FD22   %1 22 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD22    Filter bits
: CAN0_F23DATA1_FD23   %1 23 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD23    Filter bits
: CAN0_F23DATA1_FD24   %1 24 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD24    Filter bits
: CAN0_F23DATA1_FD25   %1 25 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD25    Filter bits
: CAN0_F23DATA1_FD26   %1 26 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD26    Filter bits
: CAN0_F23DATA1_FD27   %1 27 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD27    Filter bits
: CAN0_F23DATA1_FD28   %1 28 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD28    Filter bits
: CAN0_F23DATA1_FD29   %1 29 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD29    Filter bits
: CAN0_F23DATA1_FD30   %1 30 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD30    Filter bits
: CAN0_F23DATA1_FD31   %1 31 lshift CAN0_F23DATA1 bis! ;  \ CAN0_F23DATA1_FD31    Filter bits

\ CAN0_F24DATA0 (read-write)
: CAN0_F24DATA0_FD0   %1 0 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD0    Filter bits
: CAN0_F24DATA0_FD1   %1 1 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD1    Filter bits
: CAN0_F24DATA0_FD2   %1 2 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD2    Filter bits
: CAN0_F24DATA0_FD3   %1 3 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD3    Filter bits
: CAN0_F24DATA0_FD4   %1 4 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD4    Filter bits
: CAN0_F24DATA0_FD5   %1 5 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD5    Filter bits
: CAN0_F24DATA0_FD6   %1 6 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD6    Filter bits
: CAN0_F24DATA0_FD7   %1 7 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD7    Filter bits
: CAN0_F24DATA0_FD8   %1 8 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD8    Filter bits
: CAN0_F24DATA0_FD9   %1 9 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD9    Filter bits
: CAN0_F24DATA0_FD10   %1 10 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD10    Filter bits
: CAN0_F24DATA0_FD11   %1 11 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD11    Filter bits
: CAN0_F24DATA0_FD12   %1 12 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD12    Filter bits
: CAN0_F24DATA0_FD13   %1 13 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD13    Filter bits
: CAN0_F24DATA0_FD14   %1 14 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD14    Filter bits
: CAN0_F24DATA0_FD15   %1 15 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD15    Filter bits
: CAN0_F24DATA0_FD16   %1 16 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD16    Filter bits
: CAN0_F24DATA0_FD17   %1 17 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD17    Filter bits
: CAN0_F24DATA0_FD18   %1 18 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD18    Filter bits
: CAN0_F24DATA0_FD19   %1 19 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD19    Filter bits
: CAN0_F24DATA0_FD20   %1 20 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD20    Filter bits
: CAN0_F24DATA0_FD21   %1 21 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD21    Filter bits
: CAN0_F24DATA0_FD22   %1 22 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD22    Filter bits
: CAN0_F24DATA0_FD23   %1 23 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD23    Filter bits
: CAN0_F24DATA0_FD24   %1 24 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD24    Filter bits
: CAN0_F24DATA0_FD25   %1 25 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD25    Filter bits
: CAN0_F24DATA0_FD26   %1 26 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD26    Filter bits
: CAN0_F24DATA0_FD27   %1 27 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD27    Filter bits
: CAN0_F24DATA0_FD28   %1 28 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD28    Filter bits
: CAN0_F24DATA0_FD29   %1 29 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD29    Filter bits
: CAN0_F24DATA0_FD30   %1 30 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD30    Filter bits
: CAN0_F24DATA0_FD31   %1 31 lshift CAN0_F24DATA0 bis! ;  \ CAN0_F24DATA0_FD31    Filter bits

\ CAN0_F24DATA1 (read-write)
: CAN0_F24DATA1_FD0   %1 0 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD0    Filter bits
: CAN0_F24DATA1_FD1   %1 1 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD1    Filter bits
: CAN0_F24DATA1_FD2   %1 2 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD2    Filter bits
: CAN0_F24DATA1_FD3   %1 3 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD3    Filter bits
: CAN0_F24DATA1_FD4   %1 4 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD4    Filter bits
: CAN0_F24DATA1_FD5   %1 5 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD5    Filter bits
: CAN0_F24DATA1_FD6   %1 6 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD6    Filter bits
: CAN0_F24DATA1_FD7   %1 7 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD7    Filter bits
: CAN0_F24DATA1_FD8   %1 8 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD8    Filter bits
: CAN0_F24DATA1_FD9   %1 9 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD9    Filter bits
: CAN0_F24DATA1_FD10   %1 10 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD10    Filter bits
: CAN0_F24DATA1_FD11   %1 11 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD11    Filter bits
: CAN0_F24DATA1_FD12   %1 12 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD12    Filter bits
: CAN0_F24DATA1_FD13   %1 13 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD13    Filter bits
: CAN0_F24DATA1_FD14   %1 14 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD14    Filter bits
: CAN0_F24DATA1_FD15   %1 15 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD15    Filter bits
: CAN0_F24DATA1_FD16   %1 16 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD16    Filter bits
: CAN0_F24DATA1_FD17   %1 17 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD17    Filter bits
: CAN0_F24DATA1_FD18   %1 18 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD18    Filter bits
: CAN0_F24DATA1_FD19   %1 19 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD19    Filter bits
: CAN0_F24DATA1_FD20   %1 20 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD20    Filter bits
: CAN0_F24DATA1_FD21   %1 21 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD21    Filter bits
: CAN0_F24DATA1_FD22   %1 22 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD22    Filter bits
: CAN0_F24DATA1_FD23   %1 23 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD23    Filter bits
: CAN0_F24DATA1_FD24   %1 24 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD24    Filter bits
: CAN0_F24DATA1_FD25   %1 25 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD25    Filter bits
: CAN0_F24DATA1_FD26   %1 26 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD26    Filter bits
: CAN0_F24DATA1_FD27   %1 27 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD27    Filter bits
: CAN0_F24DATA1_FD28   %1 28 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD28    Filter bits
: CAN0_F24DATA1_FD29   %1 29 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD29    Filter bits
: CAN0_F24DATA1_FD30   %1 30 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD30    Filter bits
: CAN0_F24DATA1_FD31   %1 31 lshift CAN0_F24DATA1 bis! ;  \ CAN0_F24DATA1_FD31    Filter bits

\ CAN0_F25DATA0 (read-write)
: CAN0_F25DATA0_FD0   %1 0 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD0    Filter bits
: CAN0_F25DATA0_FD1   %1 1 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD1    Filter bits
: CAN0_F25DATA0_FD2   %1 2 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD2    Filter bits
: CAN0_F25DATA0_FD3   %1 3 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD3    Filter bits
: CAN0_F25DATA0_FD4   %1 4 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD4    Filter bits
: CAN0_F25DATA0_FD5   %1 5 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD5    Filter bits
: CAN0_F25DATA0_FD6   %1 6 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD6    Filter bits
: CAN0_F25DATA0_FD7   %1 7 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD7    Filter bits
: CAN0_F25DATA0_FD8   %1 8 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD8    Filter bits
: CAN0_F25DATA0_FD9   %1 9 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD9    Filter bits
: CAN0_F25DATA0_FD10   %1 10 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD10    Filter bits
: CAN0_F25DATA0_FD11   %1 11 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD11    Filter bits
: CAN0_F25DATA0_FD12   %1 12 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD12    Filter bits
: CAN0_F25DATA0_FD13   %1 13 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD13    Filter bits
: CAN0_F25DATA0_FD14   %1 14 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD14    Filter bits
: CAN0_F25DATA0_FD15   %1 15 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD15    Filter bits
: CAN0_F25DATA0_FD16   %1 16 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD16    Filter bits
: CAN0_F25DATA0_FD17   %1 17 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD17    Filter bits
: CAN0_F25DATA0_FD18   %1 18 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD18    Filter bits
: CAN0_F25DATA0_FD19   %1 19 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD19    Filter bits
: CAN0_F25DATA0_FD20   %1 20 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD20    Filter bits
: CAN0_F25DATA0_FD21   %1 21 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD21    Filter bits
: CAN0_F25DATA0_FD22   %1 22 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD22    Filter bits
: CAN0_F25DATA0_FD23   %1 23 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD23    Filter bits
: CAN0_F25DATA0_FD24   %1 24 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD24    Filter bits
: CAN0_F25DATA0_FD25   %1 25 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD25    Filter bits
: CAN0_F25DATA0_FD26   %1 26 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD26    Filter bits
: CAN0_F25DATA0_FD27   %1 27 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD27    Filter bits
: CAN0_F25DATA0_FD28   %1 28 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD28    Filter bits
: CAN0_F25DATA0_FD29   %1 29 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD29    Filter bits
: CAN0_F25DATA0_FD30   %1 30 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD30    Filter bits
: CAN0_F25DATA0_FD31   %1 31 lshift CAN0_F25DATA0 bis! ;  \ CAN0_F25DATA0_FD31    Filter bits

\ CAN0_F25DATA1 (read-write)
: CAN0_F25DATA1_FD0   %1 0 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD0    Filter bits
: CAN0_F25DATA1_FD1   %1 1 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD1    Filter bits
: CAN0_F25DATA1_FD2   %1 2 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD2    Filter bits
: CAN0_F25DATA1_FD3   %1 3 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD3    Filter bits
: CAN0_F25DATA1_FD4   %1 4 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD4    Filter bits
: CAN0_F25DATA1_FD5   %1 5 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD5    Filter bits
: CAN0_F25DATA1_FD6   %1 6 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD6    Filter bits
: CAN0_F25DATA1_FD7   %1 7 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD7    Filter bits
: CAN0_F25DATA1_FD8   %1 8 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD8    Filter bits
: CAN0_F25DATA1_FD9   %1 9 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD9    Filter bits
: CAN0_F25DATA1_FD10   %1 10 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD10    Filter bits
: CAN0_F25DATA1_FD11   %1 11 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD11    Filter bits
: CAN0_F25DATA1_FD12   %1 12 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD12    Filter bits
: CAN0_F25DATA1_FD13   %1 13 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD13    Filter bits
: CAN0_F25DATA1_FD14   %1 14 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD14    Filter bits
: CAN0_F25DATA1_FD15   %1 15 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD15    Filter bits
: CAN0_F25DATA1_FD16   %1 16 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD16    Filter bits
: CAN0_F25DATA1_FD17   %1 17 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD17    Filter bits
: CAN0_F25DATA1_FD18   %1 18 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD18    Filter bits
: CAN0_F25DATA1_FD19   %1 19 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD19    Filter bits
: CAN0_F25DATA1_FD20   %1 20 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD20    Filter bits
: CAN0_F25DATA1_FD21   %1 21 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD21    Filter bits
: CAN0_F25DATA1_FD22   %1 22 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD22    Filter bits
: CAN0_F25DATA1_FD23   %1 23 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD23    Filter bits
: CAN0_F25DATA1_FD24   %1 24 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD24    Filter bits
: CAN0_F25DATA1_FD25   %1 25 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD25    Filter bits
: CAN0_F25DATA1_FD26   %1 26 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD26    Filter bits
: CAN0_F25DATA1_FD27   %1 27 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD27    Filter bits
: CAN0_F25DATA1_FD28   %1 28 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD28    Filter bits
: CAN0_F25DATA1_FD29   %1 29 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD29    Filter bits
: CAN0_F25DATA1_FD30   %1 30 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD30    Filter bits
: CAN0_F25DATA1_FD31   %1 31 lshift CAN0_F25DATA1 bis! ;  \ CAN0_F25DATA1_FD31    Filter bits

\ CAN0_F26DATA0 (read-write)
: CAN0_F26DATA0_FD0   %1 0 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD0    Filter bits
: CAN0_F26DATA0_FD1   %1 1 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD1    Filter bits
: CAN0_F26DATA0_FD2   %1 2 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD2    Filter bits
: CAN0_F26DATA0_FD3   %1 3 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD3    Filter bits
: CAN0_F26DATA0_FD4   %1 4 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD4    Filter bits
: CAN0_F26DATA0_FD5   %1 5 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD5    Filter bits
: CAN0_F26DATA0_FD6   %1 6 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD6    Filter bits
: CAN0_F26DATA0_FD7   %1 7 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD7    Filter bits
: CAN0_F26DATA0_FD8   %1 8 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD8    Filter bits
: CAN0_F26DATA0_FD9   %1 9 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD9    Filter bits
: CAN0_F26DATA0_FD10   %1 10 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD10    Filter bits
: CAN0_F26DATA0_FD11   %1 11 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD11    Filter bits
: CAN0_F26DATA0_FD12   %1 12 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD12    Filter bits
: CAN0_F26DATA0_FD13   %1 13 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD13    Filter bits
: CAN0_F26DATA0_FD14   %1 14 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD14    Filter bits
: CAN0_F26DATA0_FD15   %1 15 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD15    Filter bits
: CAN0_F26DATA0_FD16   %1 16 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD16    Filter bits
: CAN0_F26DATA0_FD17   %1 17 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD17    Filter bits
: CAN0_F26DATA0_FD18   %1 18 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD18    Filter bits
: CAN0_F26DATA0_FD19   %1 19 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD19    Filter bits
: CAN0_F26DATA0_FD20   %1 20 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD20    Filter bits
: CAN0_F26DATA0_FD21   %1 21 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD21    Filter bits
: CAN0_F26DATA0_FD22   %1 22 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD22    Filter bits
: CAN0_F26DATA0_FD23   %1 23 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD23    Filter bits
: CAN0_F26DATA0_FD24   %1 24 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD24    Filter bits
: CAN0_F26DATA0_FD25   %1 25 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD25    Filter bits
: CAN0_F26DATA0_FD26   %1 26 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD26    Filter bits
: CAN0_F26DATA0_FD27   %1 27 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD27    Filter bits
: CAN0_F26DATA0_FD28   %1 28 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD28    Filter bits
: CAN0_F26DATA0_FD29   %1 29 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD29    Filter bits
: CAN0_F26DATA0_FD30   %1 30 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD30    Filter bits
: CAN0_F26DATA0_FD31   %1 31 lshift CAN0_F26DATA0 bis! ;  \ CAN0_F26DATA0_FD31    Filter bits

\ CAN0_F26DATA1 (read-write)
: CAN0_F26DATA1_FD0   %1 0 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD0    Filter bits
: CAN0_F26DATA1_FD1   %1 1 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD1    Filter bits
: CAN0_F26DATA1_FD2   %1 2 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD2    Filter bits
: CAN0_F26DATA1_FD3   %1 3 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD3    Filter bits
: CAN0_F26DATA1_FD4   %1 4 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD4    Filter bits
: CAN0_F26DATA1_FD5   %1 5 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD5    Filter bits
: CAN0_F26DATA1_FD6   %1 6 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD6    Filter bits
: CAN0_F26DATA1_FD7   %1 7 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD7    Filter bits
: CAN0_F26DATA1_FD8   %1 8 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD8    Filter bits
: CAN0_F26DATA1_FD9   %1 9 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD9    Filter bits
: CAN0_F26DATA1_FD10   %1 10 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD10    Filter bits
: CAN0_F26DATA1_FD11   %1 11 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD11    Filter bits
: CAN0_F26DATA1_FD12   %1 12 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD12    Filter bits
: CAN0_F26DATA1_FD13   %1 13 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD13    Filter bits
: CAN0_F26DATA1_FD14   %1 14 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD14    Filter bits
: CAN0_F26DATA1_FD15   %1 15 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD15    Filter bits
: CAN0_F26DATA1_FD16   %1 16 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD16    Filter bits
: CAN0_F26DATA1_FD17   %1 17 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD17    Filter bits
: CAN0_F26DATA1_FD18   %1 18 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD18    Filter bits
: CAN0_F26DATA1_FD19   %1 19 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD19    Filter bits
: CAN0_F26DATA1_FD20   %1 20 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD20    Filter bits
: CAN0_F26DATA1_FD21   %1 21 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD21    Filter bits
: CAN0_F26DATA1_FD22   %1 22 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD22    Filter bits
: CAN0_F26DATA1_FD23   %1 23 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD23    Filter bits
: CAN0_F26DATA1_FD24   %1 24 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD24    Filter bits
: CAN0_F26DATA1_FD25   %1 25 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD25    Filter bits
: CAN0_F26DATA1_FD26   %1 26 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD26    Filter bits
: CAN0_F26DATA1_FD27   %1 27 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD27    Filter bits
: CAN0_F26DATA1_FD28   %1 28 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD28    Filter bits
: CAN0_F26DATA1_FD29   %1 29 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD29    Filter bits
: CAN0_F26DATA1_FD30   %1 30 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD30    Filter bits
: CAN0_F26DATA1_FD31   %1 31 lshift CAN0_F26DATA1 bis! ;  \ CAN0_F26DATA1_FD31    Filter bits

\ CAN0_F27DATA0 (read-write)
: CAN0_F27DATA0_FD0   %1 0 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD0    Filter bits
: CAN0_F27DATA0_FD1   %1 1 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD1    Filter bits
: CAN0_F27DATA0_FD2   %1 2 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD2    Filter bits
: CAN0_F27DATA0_FD3   %1 3 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD3    Filter bits
: CAN0_F27DATA0_FD4   %1 4 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD4    Filter bits
: CAN0_F27DATA0_FD5   %1 5 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD5    Filter bits
: CAN0_F27DATA0_FD6   %1 6 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD6    Filter bits
: CAN0_F27DATA0_FD7   %1 7 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD7    Filter bits
: CAN0_F27DATA0_FD8   %1 8 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD8    Filter bits
: CAN0_F27DATA0_FD9   %1 9 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD9    Filter bits
: CAN0_F27DATA0_FD10   %1 10 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD10    Filter bits
: CAN0_F27DATA0_FD11   %1 11 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD11    Filter bits
: CAN0_F27DATA0_FD12   %1 12 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD12    Filter bits
: CAN0_F27DATA0_FD13   %1 13 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD13    Filter bits
: CAN0_F27DATA0_FD14   %1 14 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD14    Filter bits
: CAN0_F27DATA0_FD15   %1 15 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD15    Filter bits
: CAN0_F27DATA0_FD16   %1 16 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD16    Filter bits
: CAN0_F27DATA0_FD17   %1 17 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD17    Filter bits
: CAN0_F27DATA0_FD18   %1 18 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD18    Filter bits
: CAN0_F27DATA0_FD19   %1 19 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD19    Filter bits
: CAN0_F27DATA0_FD20   %1 20 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD20    Filter bits
: CAN0_F27DATA0_FD21   %1 21 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD21    Filter bits
: CAN0_F27DATA0_FD22   %1 22 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD22    Filter bits
: CAN0_F27DATA0_FD23   %1 23 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD23    Filter bits
: CAN0_F27DATA0_FD24   %1 24 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD24    Filter bits
: CAN0_F27DATA0_FD25   %1 25 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD25    Filter bits
: CAN0_F27DATA0_FD26   %1 26 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD26    Filter bits
: CAN0_F27DATA0_FD27   %1 27 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD27    Filter bits
: CAN0_F27DATA0_FD28   %1 28 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD28    Filter bits
: CAN0_F27DATA0_FD29   %1 29 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD29    Filter bits
: CAN0_F27DATA0_FD30   %1 30 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD30    Filter bits
: CAN0_F27DATA0_FD31   %1 31 lshift CAN0_F27DATA0 bis! ;  \ CAN0_F27DATA0_FD31    Filter bits

\ CAN0_F27DATA1 (read-write)
: CAN0_F27DATA1_FD0   %1 0 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD0    Filter bits
: CAN0_F27DATA1_FD1   %1 1 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD1    Filter bits
: CAN0_F27DATA1_FD2   %1 2 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD2    Filter bits
: CAN0_F27DATA1_FD3   %1 3 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD3    Filter bits
: CAN0_F27DATA1_FD4   %1 4 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD4    Filter bits
: CAN0_F27DATA1_FD5   %1 5 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD5    Filter bits
: CAN0_F27DATA1_FD6   %1 6 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD6    Filter bits
: CAN0_F27DATA1_FD7   %1 7 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD7    Filter bits
: CAN0_F27DATA1_FD8   %1 8 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD8    Filter bits
: CAN0_F27DATA1_FD9   %1 9 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD9    Filter bits
: CAN0_F27DATA1_FD10   %1 10 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD10    Filter bits
: CAN0_F27DATA1_FD11   %1 11 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD11    Filter bits
: CAN0_F27DATA1_FD12   %1 12 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD12    Filter bits
: CAN0_F27DATA1_FD13   %1 13 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD13    Filter bits
: CAN0_F27DATA1_FD14   %1 14 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD14    Filter bits
: CAN0_F27DATA1_FD15   %1 15 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD15    Filter bits
: CAN0_F27DATA1_FD16   %1 16 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD16    Filter bits
: CAN0_F27DATA1_FD17   %1 17 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD17    Filter bits
: CAN0_F27DATA1_FD18   %1 18 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD18    Filter bits
: CAN0_F27DATA1_FD19   %1 19 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD19    Filter bits
: CAN0_F27DATA1_FD20   %1 20 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD20    Filter bits
: CAN0_F27DATA1_FD21   %1 21 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD21    Filter bits
: CAN0_F27DATA1_FD22   %1 22 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD22    Filter bits
: CAN0_F27DATA1_FD23   %1 23 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD23    Filter bits
: CAN0_F27DATA1_FD24   %1 24 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD24    Filter bits
: CAN0_F27DATA1_FD25   %1 25 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD25    Filter bits
: CAN0_F27DATA1_FD26   %1 26 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD26    Filter bits
: CAN0_F27DATA1_FD27   %1 27 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD27    Filter bits
: CAN0_F27DATA1_FD28   %1 28 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD28    Filter bits
: CAN0_F27DATA1_FD29   %1 29 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD29    Filter bits
: CAN0_F27DATA1_FD30   %1 30 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD30    Filter bits
: CAN0_F27DATA1_FD31   %1 31 lshift CAN0_F27DATA1 bis! ;  \ CAN0_F27DATA1_FD31    Filter bits

\ CAN1_CTL (read-write)
: CAN1_CTL_DFZ   %1 16 lshift CAN1_CTL bis! ;  \ CAN1_CTL_DFZ    Debug freeze
: CAN1_CTL_SWRST   %1 15 lshift CAN1_CTL bis! ;  \ CAN1_CTL_SWRST    Software reset
: CAN1_CTL_TTC   %1 7 lshift CAN1_CTL bis! ;  \ CAN1_CTL_TTC    Time-triggered communication
: CAN1_CTL_ABOR   %1 6 lshift CAN1_CTL bis! ;  \ CAN1_CTL_ABOR    Automatic bus-off recovery
: CAN1_CTL_AWU   %1 5 lshift CAN1_CTL bis! ;  \ CAN1_CTL_AWU    Automatic wakeup
: CAN1_CTL_ARD   %1 4 lshift CAN1_CTL bis! ;  \ CAN1_CTL_ARD    Automatic retransmission disable
: CAN1_CTL_RFOD   %1 3 lshift CAN1_CTL bis! ;  \ CAN1_CTL_RFOD    Receive FIFO overwrite disable
: CAN1_CTL_TFO   %1 2 lshift CAN1_CTL bis! ;  \ CAN1_CTL_TFO    Transmit FIFO order
: CAN1_CTL_SLPWMOD   %1 1 lshift CAN1_CTL bis! ;  \ CAN1_CTL_SLPWMOD    Sleep working mode
: CAN1_CTL_IWMOD   %1 0 lshift CAN1_CTL bis! ;  \ CAN1_CTL_IWMOD    Initial working mode

\ CAN1_STAT ()
: CAN1_STAT_RXL   %1 11 lshift CAN1_STAT bis! ;  \ CAN1_STAT_RXL    RX level
: CAN1_STAT_LASTRX   %1 10 lshift CAN1_STAT bis! ;  \ CAN1_STAT_LASTRX    Last sample value of RX pin
: CAN1_STAT_RS   %1 9 lshift CAN1_STAT bis! ;  \ CAN1_STAT_RS    Receiving state
: CAN1_STAT_TS   %1 8 lshift CAN1_STAT bis! ;  \ CAN1_STAT_TS    Transmitting state
: CAN1_STAT_SLPIF   %1 4 lshift CAN1_STAT bis! ;  \ CAN1_STAT_SLPIF    Status change interrupt flag of sleep  	 working mode entering
: CAN1_STAT_WUIF   %1 3 lshift CAN1_STAT bis! ;  \ CAN1_STAT_WUIF    Status change interrupt flag of wakeup  	 from sleep working mode
: CAN1_STAT_ERRIF   %1 2 lshift CAN1_STAT bis! ;  \ CAN1_STAT_ERRIF    Error interrupt flag
: CAN1_STAT_SLPWS   %1 1 lshift CAN1_STAT bis! ;  \ CAN1_STAT_SLPWS    Sleep working state
: CAN1_STAT_IWS   %1 0 lshift CAN1_STAT bis! ;  \ CAN1_STAT_IWS    Initial working state

\ CAN1_TSTAT ()
: CAN1_TSTAT_TMLS2   %1 31 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_TMLS2    Transmit mailbox 2 last sending  	 in transmit FIFO
: CAN1_TSTAT_TMLS1   %1 30 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_TMLS1    Transmit mailbox 1 last sending  	 in transmit FIFO
: CAN1_TSTAT_TMLS0   %1 29 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_TMLS0    Transmit mailbox 0 last sending  	 in transmit FIFO
: CAN1_TSTAT_TME2   %1 28 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_TME2    Transmit mailbox 2 empty
: CAN1_TSTAT_TME1   %1 27 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_TME1    Transmit mailbox 1 empty
: CAN1_TSTAT_TME0   %1 26 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_TME0    Transmit mailbox 0 empty
: CAN1_TSTAT_NUM   ( %XX -- ) 24 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_NUM    number of the transmit FIFO mailbox in  	 which the frame will be transmitted if at least one mailbox is empty
: CAN1_TSTAT_MST2   %1 23 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MST2    Mailbox 2 stop transmitting
: CAN1_TSTAT_MTE2   %1 19 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTE2    Mailbox 2 transmit error
: CAN1_TSTAT_MAL2   %1 18 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MAL2    Mailbox 2 arbitration lost
: CAN1_TSTAT_MTFNERR2   %1 17 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTFNERR2    Mailbox 2 transmit finished and no error
: CAN1_TSTAT_MTF2   %1 16 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTF2    Mailbox 2 transmit finished
: CAN1_TSTAT_MST1   %1 15 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MST1    Mailbox 1 stop transmitting
: CAN1_TSTAT_MTE1   %1 11 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTE1    Mailbox 1 transmit error
: CAN1_TSTAT_MAL1   %1 10 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MAL1    Mailbox 1 arbitration lost
: CAN1_TSTAT_MTFNERR1   %1 9 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTFNERR1    Mailbox 1 transmit finished and no error
: CAN1_TSTAT_MTF1   %1 8 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTF1    Mailbox 1 transmit finished
: CAN1_TSTAT_MST0   %1 7 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MST0    Mailbox 0 stop transmitting
: CAN1_TSTAT_MTE0   %1 3 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTE0    Mailbox 0 transmit error
: CAN1_TSTAT_MAL0   %1 2 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MAL0    Mailbox 0 arbitration lost
: CAN1_TSTAT_MTFNERR0   %1 1 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTFNERR0    Mailbox 0 transmit finished and no error
: CAN1_TSTAT_MTF0   %1 0 lshift CAN1_TSTAT bis! ;  \ CAN1_TSTAT_MTF0    Mailbox 0 transmit finished

\ CAN1_RFIFO0 ()
: CAN1_RFIFO0_RFD0   %1 5 lshift CAN1_RFIFO0 bis! ;  \ CAN1_RFIFO0_RFD0    Receive FIFO0 dequeue
: CAN1_RFIFO0_RFO0   %1 4 lshift CAN1_RFIFO0 bis! ;  \ CAN1_RFIFO0_RFO0    Receive FIFO0 overfull
: CAN1_RFIFO0_RFF0   %1 3 lshift CAN1_RFIFO0 bis! ;  \ CAN1_RFIFO0_RFF0    Receive FIFO0 full
: CAN1_RFIFO0_RFL0   ( %XX -- ) 0 lshift CAN1_RFIFO0 bis! ;  \ CAN1_RFIFO0_RFL0    Receive FIFO0 length

\ CAN1_RFIFO1 ()
: CAN1_RFIFO1_RFD1   %1 5 lshift CAN1_RFIFO1 bis! ;  \ CAN1_RFIFO1_RFD1    Receive FIFO1 dequeue
: CAN1_RFIFO1_RFO1   %1 4 lshift CAN1_RFIFO1 bis! ;  \ CAN1_RFIFO1_RFO1    Receive FIFO1 overfull
: CAN1_RFIFO1_RFF1   %1 3 lshift CAN1_RFIFO1 bis! ;  \ CAN1_RFIFO1_RFF1    Receive FIFO1 full
: CAN1_RFIFO1_RFL1   ( %XX -- ) 0 lshift CAN1_RFIFO1 bis! ;  \ CAN1_RFIFO1_RFL1    Receive FIFO1 length

\ CAN1_INTEN (read-write)
: CAN1_INTEN_SLPWIE   %1 17 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_SLPWIE    Sleep working interrupt enable
: CAN1_INTEN_WIE   %1 16 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_WIE    Wakeup interrupt enable
: CAN1_INTEN_ERRIE   %1 15 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_ERRIE    Error interrupt enable
: CAN1_INTEN_ERRNIE   %1 11 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_ERRNIE    Error number interrupt enable
: CAN1_INTEN_BOIE   %1 10 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_BOIE    Bus-off interrupt enable
: CAN1_INTEN_PERRIE   %1 9 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_PERRIE    Passive error interrupt enable
: CAN1_INTEN_WERRIE   %1 8 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_WERRIE    Warning error interrupt enable
: CAN1_INTEN_RFOIE1   %1 6 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_RFOIE1    Receive FIFO1 overfull interrupt enable
: CAN1_INTEN_RFFIE1   %1 5 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_RFFIE1    Receive FIFO1 full interrupt enable
: CAN1_INTEN_RFNEIE1   %1 4 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_RFNEIE1    Receive FIFO1 not empty interrupt enable
: CAN1_INTEN_RFOIE0   %1 3 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_RFOIE0    Receive FIFO0 overfull interrupt enable
: CAN1_INTEN_RFFIE0   %1 2 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_RFFIE0    Receive FIFO0 full interrupt enable
: CAN1_INTEN_RFNEIE0   %1 1 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_RFNEIE0    Receive FIFO0 not empty interrupt enable
: CAN1_INTEN_TMEIE   %1 0 lshift CAN1_INTEN bis! ;  \ CAN1_INTEN_TMEIE    Transmit mailbox empty interrupt enable

\ CAN1_ERR ()
: CAN1_ERR_RECNT   ( %XXXXXXXX -- ) 24 lshift CAN1_ERR bis! ;  \ CAN1_ERR_RECNT    Receive Error Count defined  	 by the CAN standard
: CAN1_ERR_TECNT   ( %XXXXXXXX -- ) 16 lshift CAN1_ERR bis! ;  \ CAN1_ERR_TECNT    Transmit Error Count defined  	 by the CAN standard
: CAN1_ERR_ERRN   ( %XXX -- ) 4 lshift CAN1_ERR bis! ;  \ CAN1_ERR_ERRN    Error number
: CAN1_ERR_BOERR   %1 2 lshift CAN1_ERR bis! ;  \ CAN1_ERR_BOERR    Bus-off error
: CAN1_ERR_PERR   %1 1 lshift CAN1_ERR bis! ;  \ CAN1_ERR_PERR    Passive error
: CAN1_ERR_WERR   %1 0 lshift CAN1_ERR bis! ;  \ CAN1_ERR_WERR    Warning error

\ CAN1_BT (read-write)
: CAN1_BT_SCMOD   %1 31 lshift CAN1_BT bis! ;  \ CAN1_BT_SCMOD    Silent communication mode
: CAN1_BT_LCMOD   %1 30 lshift CAN1_BT bis! ;  \ CAN1_BT_LCMOD    Loopback communication mode
: CAN1_BT_SJW   ( %XX -- ) 24 lshift CAN1_BT bis! ;  \ CAN1_BT_SJW    Resynchronization jump width
: CAN1_BT_BS2   ( %XXX -- ) 20 lshift CAN1_BT bis! ;  \ CAN1_BT_BS2    Bit segment 2
: CAN1_BT_BS1   ( %XXXX -- ) 16 lshift CAN1_BT bis! ;  \ CAN1_BT_BS1    Bit segment 1
: CAN1_BT_BAUDPSC  0 lshift CAN1_BT bis! ;  \ CAN1_BT_BAUDPSC    Baud rate prescaler

\ CAN1_TMI0 (read-write)
: CAN1_TMI0_SFID_EFID  21 lshift CAN1_TMI0 bis! ;  \ CAN1_TMI0_SFID_EFID    The frame identifier
: CAN1_TMI0_EFID  3 lshift CAN1_TMI0 bis! ;  \ CAN1_TMI0_EFID    The frame identifier
: CAN1_TMI0_FF   %1 2 lshift CAN1_TMI0 bis! ;  \ CAN1_TMI0_FF    Frame format
: CAN1_TMI0_FT   %1 1 lshift CAN1_TMI0 bis! ;  \ CAN1_TMI0_FT    Frame type
: CAN1_TMI0_TEN   %1 0 lshift CAN1_TMI0 bis! ;  \ CAN1_TMI0_TEN    Transmit enable

\ CAN1_TMP0 (read-write)
: CAN1_TMP0_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN1_TMP0 bis! ;  \ CAN1_TMP0_TS    Time stamp
: CAN1_TMP0_TSEN   %1 8 lshift CAN1_TMP0 bis! ;  \ CAN1_TMP0_TSEN    Time stamp enable
: CAN1_TMP0_DLENC   ( %XXXX -- ) 0 lshift CAN1_TMP0 bis! ;  \ CAN1_TMP0_DLENC    Data length code

\ CAN1_TMDATA00 (read-write)
: CAN1_TMDATA00_DB3   ( %XXXXXXXX -- ) 24 lshift CAN1_TMDATA00 bis! ;  \ CAN1_TMDATA00_DB3    Data byte 3
: CAN1_TMDATA00_DB2   ( %XXXXXXXX -- ) 16 lshift CAN1_TMDATA00 bis! ;  \ CAN1_TMDATA00_DB2    Data byte 2
: CAN1_TMDATA00_DB1   ( %XXXXXXXX -- ) 8 lshift CAN1_TMDATA00 bis! ;  \ CAN1_TMDATA00_DB1    Data byte 1
: CAN1_TMDATA00_DB0   ( %XXXXXXXX -- ) 0 lshift CAN1_TMDATA00 bis! ;  \ CAN1_TMDATA00_DB0    Data byte 0

\ CAN1_TMDATA10 (read-write)
: CAN1_TMDATA10_DB7   ( %XXXXXXXX -- ) 24 lshift CAN1_TMDATA10 bis! ;  \ CAN1_TMDATA10_DB7    Data byte 7
: CAN1_TMDATA10_DB6   ( %XXXXXXXX -- ) 16 lshift CAN1_TMDATA10 bis! ;  \ CAN1_TMDATA10_DB6    Data byte 6
: CAN1_TMDATA10_DB5   ( %XXXXXXXX -- ) 8 lshift CAN1_TMDATA10 bis! ;  \ CAN1_TMDATA10_DB5    Data byte 5
: CAN1_TMDATA10_DB4   ( %XXXXXXXX -- ) 0 lshift CAN1_TMDATA10 bis! ;  \ CAN1_TMDATA10_DB4    Data byte 4

\ CAN1_TMI1 (read-write)
: CAN1_TMI1_SFID_EFID  21 lshift CAN1_TMI1 bis! ;  \ CAN1_TMI1_SFID_EFID    The frame identifier
: CAN1_TMI1_EFID  3 lshift CAN1_TMI1 bis! ;  \ CAN1_TMI1_EFID    The frame identifier
: CAN1_TMI1_FF   %1 2 lshift CAN1_TMI1 bis! ;  \ CAN1_TMI1_FF    Frame format
: CAN1_TMI1_FT   %1 1 lshift CAN1_TMI1 bis! ;  \ CAN1_TMI1_FT    Frame type
: CAN1_TMI1_TEN   %1 0 lshift CAN1_TMI1 bis! ;  \ CAN1_TMI1_TEN    Transmit enable

\ CAN1_TMP1 (read-write)
: CAN1_TMP1_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN1_TMP1 bis! ;  \ CAN1_TMP1_TS    Time stamp
: CAN1_TMP1_TSEN   %1 8 lshift CAN1_TMP1 bis! ;  \ CAN1_TMP1_TSEN    Time stamp enable
: CAN1_TMP1_DLENC   ( %XXXX -- ) 0 lshift CAN1_TMP1 bis! ;  \ CAN1_TMP1_DLENC    Data length code

\ CAN1_TMDATA01 (read-write)
: CAN1_TMDATA01_DB3   ( %XXXXXXXX -- ) 24 lshift CAN1_TMDATA01 bis! ;  \ CAN1_TMDATA01_DB3    Data byte 3
: CAN1_TMDATA01_DB2   ( %XXXXXXXX -- ) 16 lshift CAN1_TMDATA01 bis! ;  \ CAN1_TMDATA01_DB2    Data byte 2
: CAN1_TMDATA01_DB1   ( %XXXXXXXX -- ) 8 lshift CAN1_TMDATA01 bis! ;  \ CAN1_TMDATA01_DB1    Data byte 1
: CAN1_TMDATA01_DB0   ( %XXXXXXXX -- ) 0 lshift CAN1_TMDATA01 bis! ;  \ CAN1_TMDATA01_DB0    Data byte 0

\ CAN1_TMDATA11 (read-write)
: CAN1_TMDATA11_DB7   ( %XXXXXXXX -- ) 24 lshift CAN1_TMDATA11 bis! ;  \ CAN1_TMDATA11_DB7    Data byte 7
: CAN1_TMDATA11_DB6   ( %XXXXXXXX -- ) 16 lshift CAN1_TMDATA11 bis! ;  \ CAN1_TMDATA11_DB6    Data byte 6
: CAN1_TMDATA11_DB5   ( %XXXXXXXX -- ) 8 lshift CAN1_TMDATA11 bis! ;  \ CAN1_TMDATA11_DB5    Data byte 5
: CAN1_TMDATA11_DB4   ( %XXXXXXXX -- ) 0 lshift CAN1_TMDATA11 bis! ;  \ CAN1_TMDATA11_DB4    Data byte 4

\ CAN1_TMI2 (read-write)
: CAN1_TMI2_SFID_EFID  21 lshift CAN1_TMI2 bis! ;  \ CAN1_TMI2_SFID_EFID    The frame identifier
: CAN1_TMI2_EFID  3 lshift CAN1_TMI2 bis! ;  \ CAN1_TMI2_EFID    The frame identifier
: CAN1_TMI2_FF   %1 2 lshift CAN1_TMI2 bis! ;  \ CAN1_TMI2_FF    Frame format
: CAN1_TMI2_FT   %1 1 lshift CAN1_TMI2 bis! ;  \ CAN1_TMI2_FT    Frame type
: CAN1_TMI2_TEN   %1 0 lshift CAN1_TMI2 bis! ;  \ CAN1_TMI2_TEN    Transmit enable

\ CAN1_TMP2 (read-write)
: CAN1_TMP2_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN1_TMP2 bis! ;  \ CAN1_TMP2_TS    Time stamp
: CAN1_TMP2_TSEN   %1 8 lshift CAN1_TMP2 bis! ;  \ CAN1_TMP2_TSEN    Time stamp enable
: CAN1_TMP2_DLENC   ( %XXXX -- ) 0 lshift CAN1_TMP2 bis! ;  \ CAN1_TMP2_DLENC    Data length code

\ CAN1_TMDATA02 (read-write)
: CAN1_TMDATA02_DB3   ( %XXXXXXXX -- ) 24 lshift CAN1_TMDATA02 bis! ;  \ CAN1_TMDATA02_DB3    Data byte 3
: CAN1_TMDATA02_DB2   ( %XXXXXXXX -- ) 16 lshift CAN1_TMDATA02 bis! ;  \ CAN1_TMDATA02_DB2    Data byte 2
: CAN1_TMDATA02_DB1   ( %XXXXXXXX -- ) 8 lshift CAN1_TMDATA02 bis! ;  \ CAN1_TMDATA02_DB1    Data byte 1
: CAN1_TMDATA02_DB0   ( %XXXXXXXX -- ) 0 lshift CAN1_TMDATA02 bis! ;  \ CAN1_TMDATA02_DB0    Data byte 0

\ CAN1_TMDATA12 (read-write)
: CAN1_TMDATA12_DB7   ( %XXXXXXXX -- ) 24 lshift CAN1_TMDATA12 bis! ;  \ CAN1_TMDATA12_DB7    Data byte 7
: CAN1_TMDATA12_DB6   ( %XXXXXXXX -- ) 16 lshift CAN1_TMDATA12 bis! ;  \ CAN1_TMDATA12_DB6    Data byte 6
: CAN1_TMDATA12_DB5   ( %XXXXXXXX -- ) 8 lshift CAN1_TMDATA12 bis! ;  \ CAN1_TMDATA12_DB5    Data byte 5
: CAN1_TMDATA12_DB4   ( %XXXXXXXX -- ) 0 lshift CAN1_TMDATA12 bis! ;  \ CAN1_TMDATA12_DB4    Data byte 4

\ CAN1_RFIFOMI0 (read-only)
: CAN1_RFIFOMI0_SFID_EFID  21 lshift CAN1_RFIFOMI0 bis! ;  \ CAN1_RFIFOMI0_SFID_EFID    The frame identifier
: CAN1_RFIFOMI0_EFID  3 lshift CAN1_RFIFOMI0 bis! ;  \ CAN1_RFIFOMI0_EFID    The frame identifier
: CAN1_RFIFOMI0_FF   %1 2 lshift CAN1_RFIFOMI0 bis! ;  \ CAN1_RFIFOMI0_FF    Frame format
: CAN1_RFIFOMI0_FT   %1 1 lshift CAN1_RFIFOMI0 bis! ;  \ CAN1_RFIFOMI0_FT    Frame type

\ CAN1_RFIFOMP0 (read-only)
: CAN1_RFIFOMP0_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN1_RFIFOMP0 bis! ;  \ CAN1_RFIFOMP0_TS    Time stamp
: CAN1_RFIFOMP0_FI   ( %XXXXXXXX -- ) 8 lshift CAN1_RFIFOMP0 bis! ;  \ CAN1_RFIFOMP0_FI    Filtering index
: CAN1_RFIFOMP0_DLENC   ( %XXXX -- ) 0 lshift CAN1_RFIFOMP0 bis! ;  \ CAN1_RFIFOMP0_DLENC    Data length code

\ CAN1_RFIFOMDATA00 (read-only)
: CAN1_RFIFOMDATA00_DB3   ( %XXXXXXXX -- ) 24 lshift CAN1_RFIFOMDATA00 bis! ;  \ CAN1_RFIFOMDATA00_DB3    Data byte 3
: CAN1_RFIFOMDATA00_DB2   ( %XXXXXXXX -- ) 16 lshift CAN1_RFIFOMDATA00 bis! ;  \ CAN1_RFIFOMDATA00_DB2    Data byte 2
: CAN1_RFIFOMDATA00_DB1   ( %XXXXXXXX -- ) 8 lshift CAN1_RFIFOMDATA00 bis! ;  \ CAN1_RFIFOMDATA00_DB1    Data byte 1
: CAN1_RFIFOMDATA00_DB0   ( %XXXXXXXX -- ) 0 lshift CAN1_RFIFOMDATA00 bis! ;  \ CAN1_RFIFOMDATA00_DB0    Data byte 0

\ CAN1_RFIFOMDATA10 (read-only)
: CAN1_RFIFOMDATA10_DB7   ( %XXXXXXXX -- ) 24 lshift CAN1_RFIFOMDATA10 bis! ;  \ CAN1_RFIFOMDATA10_DB7    Data byte 7
: CAN1_RFIFOMDATA10_DB6   ( %XXXXXXXX -- ) 16 lshift CAN1_RFIFOMDATA10 bis! ;  \ CAN1_RFIFOMDATA10_DB6    Data byte 6
: CAN1_RFIFOMDATA10_DB5   ( %XXXXXXXX -- ) 8 lshift CAN1_RFIFOMDATA10 bis! ;  \ CAN1_RFIFOMDATA10_DB5    Data byte 5
: CAN1_RFIFOMDATA10_DB4   ( %XXXXXXXX -- ) 0 lshift CAN1_RFIFOMDATA10 bis! ;  \ CAN1_RFIFOMDATA10_DB4    Data byte 4

\ CAN1_RFIFOMI1 (read-only)
: CAN1_RFIFOMI1_SFID_EFID  21 lshift CAN1_RFIFOMI1 bis! ;  \ CAN1_RFIFOMI1_SFID_EFID    The frame identifier
: CAN1_RFIFOMI1_EFID  3 lshift CAN1_RFIFOMI1 bis! ;  \ CAN1_RFIFOMI1_EFID    The frame identifier
: CAN1_RFIFOMI1_FF   %1 2 lshift CAN1_RFIFOMI1 bis! ;  \ CAN1_RFIFOMI1_FF    Frame format
: CAN1_RFIFOMI1_FT   %1 1 lshift CAN1_RFIFOMI1 bis! ;  \ CAN1_RFIFOMI1_FT    Frame type

\ CAN1_RFIFOMP1 (read-only)
: CAN1_RFIFOMP1_TS   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift CAN1_RFIFOMP1 bis! ;  \ CAN1_RFIFOMP1_TS    Time stamp
: CAN1_RFIFOMP1_FI   ( %XXXXXXXX -- ) 8 lshift CAN1_RFIFOMP1 bis! ;  \ CAN1_RFIFOMP1_FI    Filtering index
: CAN1_RFIFOMP1_DLENC   ( %XXXX -- ) 0 lshift CAN1_RFIFOMP1 bis! ;  \ CAN1_RFIFOMP1_DLENC    Data length code

\ CAN1_RFIFOMDATA01 (read-only)
: CAN1_RFIFOMDATA01_DB3   ( %XXXXXXXX -- ) 24 lshift CAN1_RFIFOMDATA01 bis! ;  \ CAN1_RFIFOMDATA01_DB3    Data byte 3
: CAN1_RFIFOMDATA01_DB2   ( %XXXXXXXX -- ) 16 lshift CAN1_RFIFOMDATA01 bis! ;  \ CAN1_RFIFOMDATA01_DB2    Data byte 2
: CAN1_RFIFOMDATA01_DB1   ( %XXXXXXXX -- ) 8 lshift CAN1_RFIFOMDATA01 bis! ;  \ CAN1_RFIFOMDATA01_DB1    Data byte 1
: CAN1_RFIFOMDATA01_DB0   ( %XXXXXXXX -- ) 0 lshift CAN1_RFIFOMDATA01 bis! ;  \ CAN1_RFIFOMDATA01_DB0    Data byte 0

\ CAN1_RFIFOMDATA11 (read-only)
: CAN1_RFIFOMDATA11_DB7   ( %XXXXXXXX -- ) 24 lshift CAN1_RFIFOMDATA11 bis! ;  \ CAN1_RFIFOMDATA11_DB7    Data byte 7
: CAN1_RFIFOMDATA11_DB6   ( %XXXXXXXX -- ) 16 lshift CAN1_RFIFOMDATA11 bis! ;  \ CAN1_RFIFOMDATA11_DB6    Data byte 6
: CAN1_RFIFOMDATA11_DB5   ( %XXXXXXXX -- ) 8 lshift CAN1_RFIFOMDATA11 bis! ;  \ CAN1_RFIFOMDATA11_DB5    Data byte 5
: CAN1_RFIFOMDATA11_DB4   ( %XXXXXXXX -- ) 0 lshift CAN1_RFIFOMDATA11 bis! ;  \ CAN1_RFIFOMDATA11_DB4    Data byte 4

\ CAN1_FCTL (read-write)
: CAN1_FCTL_HBC1F   ( %XXXXXX -- ) 8 lshift CAN1_FCTL bis! ;  \ CAN1_FCTL_HBC1F    Header bank of CAN1 filter
: CAN1_FCTL_FLD   %1 0 lshift CAN1_FCTL bis! ;  \ CAN1_FCTL_FLD    Filter lock disable

\ CAN1_FMCFG (read-write)
: CAN1_FMCFG_FMOD27   %1 27 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD27    Filter mode
: CAN1_FMCFG_FMOD26   %1 26 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD26    Filter mode
: CAN1_FMCFG_FMOD25   %1 25 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD25    Filter mode
: CAN1_FMCFG_FMOD24   %1 24 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD24    Filter mode
: CAN1_FMCFG_FMOD23   %1 23 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD23    Filter mode
: CAN1_FMCFG_FMOD22   %1 22 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD22    Filter mode
: CAN1_FMCFG_FMOD21   %1 21 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD21    Filter mode
: CAN1_FMCFG_FMOD20   %1 20 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD20    Filter mode
: CAN1_FMCFG_FMOD19   %1 19 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD19    Filter mode
: CAN1_FMCFG_FMOD18   %1 18 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD18    Filter mode
: CAN1_FMCFG_FMOD17   %1 17 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD17    Filter mode
: CAN1_FMCFG_FMOD16   %1 16 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD16    Filter mode
: CAN1_FMCFG_FMOD15   %1 15 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD15    Filter mode
: CAN1_FMCFG_FMOD14   %1 14 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD14    Filter mode
: CAN1_FMCFG_FMOD13   %1 13 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD13    Filter mode
: CAN1_FMCFG_FMOD12   %1 12 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD12    Filter mode
: CAN1_FMCFG_FMOD11   %1 11 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD11    Filter mode
: CAN1_FMCFG_FMOD10   %1 10 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD10    Filter mode
: CAN1_FMCFG_FMOD9   %1 9 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD9    Filter mode
: CAN1_FMCFG_FMOD8   %1 8 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD8    Filter mode
: CAN1_FMCFG_FMOD7   %1 7 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD7    Filter mode
: CAN1_FMCFG_FMOD6   %1 6 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD6    Filter mode
: CAN1_FMCFG_FMOD5   %1 5 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD5    Filter mode
: CAN1_FMCFG_FMOD4   %1 4 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD4    Filter mode
: CAN1_FMCFG_FMOD3   %1 3 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD3    Filter mode
: CAN1_FMCFG_FMOD2   %1 2 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD2    Filter mode
: CAN1_FMCFG_FMOD1   %1 1 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD1    Filter mode
: CAN1_FMCFG_FMOD0   %1 0 lshift CAN1_FMCFG bis! ;  \ CAN1_FMCFG_FMOD0    Filter mode

\ CAN1_FSCFG (read-write)
: CAN1_FSCFG_FS0   %1 0 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS0    Filter scale configuration
: CAN1_FSCFG_FS1   %1 1 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS1    Filter scale configuration
: CAN1_FSCFG_FS2   %1 2 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS2    Filter scale configuration
: CAN1_FSCFG_FS3   %1 3 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS3    Filter scale configuration
: CAN1_FSCFG_FS4   %1 4 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS4    Filter scale configuration
: CAN1_FSCFG_FS5   %1 5 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS5    Filter scale configuration
: CAN1_FSCFG_FS6   %1 6 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS6    Filter scale configuration
: CAN1_FSCFG_FS7   %1 7 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS7    Filter scale configuration
: CAN1_FSCFG_FS8   %1 8 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS8    Filter scale configuration
: CAN1_FSCFG_FS9   %1 9 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS9    Filter scale configuration
: CAN1_FSCFG_FS10   %1 10 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS10    Filter scale configuration
: CAN1_FSCFG_FS11   %1 11 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS11    Filter scale configuration
: CAN1_FSCFG_FS12   %1 12 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS12    Filter scale configuration
: CAN1_FSCFG_FS13   %1 13 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS13    Filter scale configuration
: CAN1_FSCFG_FS14   %1 14 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS14    Filter scale configuration
: CAN1_FSCFG_FS15   %1 15 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS15    Filter scale configuration
: CAN1_FSCFG_FS16   %1 16 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS16    Filter scale configuration
: CAN1_FSCFG_FS17   %1 17 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS17    Filter scale configuration
: CAN1_FSCFG_FS18   %1 18 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS18    Filter scale configuration
: CAN1_FSCFG_FS19   %1 19 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS19    Filter scale configuration
: CAN1_FSCFG_FS20   %1 20 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS20    Filter scale configuration
: CAN1_FSCFG_FS21   %1 21 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS21    Filter scale configuration
: CAN1_FSCFG_FS22   %1 22 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS22    Filter scale configuration
: CAN1_FSCFG_FS23   %1 23 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS23    Filter scale configuration
: CAN1_FSCFG_FS24   %1 24 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS24    Filter scale configuration
: CAN1_FSCFG_FS25   %1 25 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS25    Filter scale configuration
: CAN1_FSCFG_FS26   %1 26 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS26    Filter scale configuration
: CAN1_FSCFG_FS27   %1 27 lshift CAN1_FSCFG bis! ;  \ CAN1_FSCFG_FS27    Filter scale configuration

\ CAN1_FAFIFO (read-write)
: CAN1_FAFIFO_FAF0   %1 0 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF0    Filter 0 associated with FIFO
: CAN1_FAFIFO_FAF1   %1 1 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF1    Filter 1 associated with FIFO
: CAN1_FAFIFO_FAF2   %1 2 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF2    Filter 2 associated with FIFO
: CAN1_FAFIFO_FAF3   %1 3 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF3    Filter 3 associated with FIFO
: CAN1_FAFIFO_FAF4   %1 4 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF4    Filter 4 associated with FIFO
: CAN1_FAFIFO_FAF5   %1 5 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF5    Filter 5 associated with FIFO
: CAN1_FAFIFO_FAF6   %1 6 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF6    Filter 6 associated with FIFO
: CAN1_FAFIFO_FAF7   %1 7 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF7    Filter 7 associated with FIFO
: CAN1_FAFIFO_FAF8   %1 8 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF8    Filter 8 associated with FIFO
: CAN1_FAFIFO_FAF9   %1 9 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF9    Filter 9 associated with FIFO
: CAN1_FAFIFO_FAF10   %1 10 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF10    Filter 10 associated with FIFO
: CAN1_FAFIFO_FAF11   %1 11 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF11    Filter 11 associated with FIFO
: CAN1_FAFIFO_FAF12   %1 12 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF12    Filter 12 associated with FIFO
: CAN1_FAFIFO_FAF13   %1 13 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF13    Filter 13 associated with FIFO
: CAN1_FAFIFO_FAF14   %1 14 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF14    Filter 14 associated with FIFO
: CAN1_FAFIFO_FAF15   %1 15 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF15    Filter 15 associated with FIFO
: CAN1_FAFIFO_FAF16   %1 16 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF16    Filter 16 associated with FIFO
: CAN1_FAFIFO_FAF17   %1 17 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF17    Filter 17 associated with FIFO
: CAN1_FAFIFO_FAF18   %1 18 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF18    Filter 18 associated with FIFO
: CAN1_FAFIFO_FAF19   %1 19 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF19    Filter 19 associated with FIFO
: CAN1_FAFIFO_FAF20   %1 20 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF20    Filter 20 associated with FIFO
: CAN1_FAFIFO_FAF21   %1 21 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF21    Filter 21 associated with FIFO
: CAN1_FAFIFO_FAF22   %1 22 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF22    Filter 22 associated with FIFO
: CAN1_FAFIFO_FAF23   %1 23 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF23    Filter 23 associated with FIFO
: CAN1_FAFIFO_FAF24   %1 24 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF24    Filter 24 associated with FIFO
: CAN1_FAFIFO_FAF25   %1 25 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF25    Filter 25 associated with FIFO
: CAN1_FAFIFO_FAF26   %1 26 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF26    Filter 26 associated with FIFO
: CAN1_FAFIFO_FAF27   %1 27 lshift CAN1_FAFIFO bis! ;  \ CAN1_FAFIFO_FAF27    Filter 27 associated with FIFO

\ CAN1_FW (read-write)
: CAN1_FW_FW0   %1 0 lshift CAN1_FW bis! ;  \ CAN1_FW_FW0    Filter working
: CAN1_FW_FW1   %1 1 lshift CAN1_FW bis! ;  \ CAN1_FW_FW1    Filter working
: CAN1_FW_FW2   %1 2 lshift CAN1_FW bis! ;  \ CAN1_FW_FW2    Filter working
: CAN1_FW_FW3   %1 3 lshift CAN1_FW bis! ;  \ CAN1_FW_FW3    Filter working
: CAN1_FW_FW4   %1 4 lshift CAN1_FW bis! ;  \ CAN1_FW_FW4    Filter working
: CAN1_FW_FW5   %1 5 lshift CAN1_FW bis! ;  \ CAN1_FW_FW5    Filter working
: CAN1_FW_FW6   %1 6 lshift CAN1_FW bis! ;  \ CAN1_FW_FW6    Filter working
: CAN1_FW_FW7   %1 7 lshift CAN1_FW bis! ;  \ CAN1_FW_FW7    Filter working
: CAN1_FW_FW8   %1 8 lshift CAN1_FW bis! ;  \ CAN1_FW_FW8    Filter working
: CAN1_FW_FW9   %1 9 lshift CAN1_FW bis! ;  \ CAN1_FW_FW9    Filter working
: CAN1_FW_FW10   %1 10 lshift CAN1_FW bis! ;  \ CAN1_FW_FW10    Filter working
: CAN1_FW_FW11   %1 11 lshift CAN1_FW bis! ;  \ CAN1_FW_FW11    Filter working
: CAN1_FW_FW12   %1 12 lshift CAN1_FW bis! ;  \ CAN1_FW_FW12    Filter working
: CAN1_FW_FW13   %1 13 lshift CAN1_FW bis! ;  \ CAN1_FW_FW13    Filter working
: CAN1_FW_FW14   %1 14 lshift CAN1_FW bis! ;  \ CAN1_FW_FW14    Filter working
: CAN1_FW_FW15   %1 15 lshift CAN1_FW bis! ;  \ CAN1_FW_FW15    Filter working
: CAN1_FW_FW16   %1 16 lshift CAN1_FW bis! ;  \ CAN1_FW_FW16    Filter working
: CAN1_FW_FW17   %1 17 lshift CAN1_FW bis! ;  \ CAN1_FW_FW17    Filter working
: CAN1_FW_FW18   %1 18 lshift CAN1_FW bis! ;  \ CAN1_FW_FW18    Filter working
: CAN1_FW_FW19   %1 19 lshift CAN1_FW bis! ;  \ CAN1_FW_FW19    Filter working
: CAN1_FW_FW20   %1 20 lshift CAN1_FW bis! ;  \ CAN1_FW_FW20    Filter working
: CAN1_FW_FW21   %1 21 lshift CAN1_FW bis! ;  \ CAN1_FW_FW21    Filter working
: CAN1_FW_FW22   %1 22 lshift CAN1_FW bis! ;  \ CAN1_FW_FW22    Filter working
: CAN1_FW_FW23   %1 23 lshift CAN1_FW bis! ;  \ CAN1_FW_FW23    Filter working
: CAN1_FW_FW24   %1 24 lshift CAN1_FW bis! ;  \ CAN1_FW_FW24    Filter working
: CAN1_FW_FW25   %1 25 lshift CAN1_FW bis! ;  \ CAN1_FW_FW25    Filter working
: CAN1_FW_FW26   %1 26 lshift CAN1_FW bis! ;  \ CAN1_FW_FW26    Filter working
: CAN1_FW_FW27   %1 27 lshift CAN1_FW bis! ;  \ CAN1_FW_FW27    Filter working

\ CAN1_F0DATA0 (read-write)
: CAN1_F0DATA0_FD0   %1 0 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD0    Filter bits
: CAN1_F0DATA0_FD1   %1 1 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD1    Filter bits
: CAN1_F0DATA0_FD2   %1 2 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD2    Filter bits
: CAN1_F0DATA0_FD3   %1 3 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD3    Filter bits
: CAN1_F0DATA0_FD4   %1 4 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD4    Filter bits
: CAN1_F0DATA0_FD5   %1 5 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD5    Filter bits
: CAN1_F0DATA0_FD6   %1 6 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD6    Filter bits
: CAN1_F0DATA0_FD7   %1 7 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD7    Filter bits
: CAN1_F0DATA0_FD8   %1 8 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD8    Filter bits
: CAN1_F0DATA0_FD9   %1 9 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD9    Filter bits
: CAN1_F0DATA0_FD10   %1 10 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD10    Filter bits
: CAN1_F0DATA0_FD11   %1 11 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD11    Filter bits
: CAN1_F0DATA0_FD12   %1 12 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD12    Filter bits
: CAN1_F0DATA0_FD13   %1 13 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD13    Filter bits
: CAN1_F0DATA0_FD14   %1 14 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD14    Filter bits
: CAN1_F0DATA0_FD15   %1 15 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD15    Filter bits
: CAN1_F0DATA0_FD16   %1 16 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD16    Filter bits
: CAN1_F0DATA0_FD17   %1 17 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD17    Filter bits
: CAN1_F0DATA0_FD18   %1 18 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD18    Filter bits
: CAN1_F0DATA0_FD19   %1 19 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD19    Filter bits
: CAN1_F0DATA0_FD20   %1 20 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD20    Filter bits
: CAN1_F0DATA0_FD21   %1 21 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD21    Filter bits
: CAN1_F0DATA0_FD22   %1 22 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD22    Filter bits
: CAN1_F0DATA0_FD23   %1 23 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD23    Filter bits
: CAN1_F0DATA0_FD24   %1 24 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD24    Filter bits
: CAN1_F0DATA0_FD25   %1 25 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD25    Filter bits
: CAN1_F0DATA0_FD26   %1 26 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD26    Filter bits
: CAN1_F0DATA0_FD27   %1 27 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD27    Filter bits
: CAN1_F0DATA0_FD28   %1 28 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD28    Filter bits
: CAN1_F0DATA0_FD29   %1 29 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD29    Filter bits
: CAN1_F0DATA0_FD30   %1 30 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD30    Filter bits
: CAN1_F0DATA0_FD31   %1 31 lshift CAN1_F0DATA0 bis! ;  \ CAN1_F0DATA0_FD31    Filter bits

\ CAN1_F0DATA1 (read-write)
: CAN1_F0DATA1_FD0   %1 0 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD0    Filter bits
: CAN1_F0DATA1_FD1   %1 1 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD1    Filter bits
: CAN1_F0DATA1_FD2   %1 2 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD2    Filter bits
: CAN1_F0DATA1_FD3   %1 3 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD3    Filter bits
: CAN1_F0DATA1_FD4   %1 4 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD4    Filter bits
: CAN1_F0DATA1_FD5   %1 5 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD5    Filter bits
: CAN1_F0DATA1_FD6   %1 6 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD6    Filter bits
: CAN1_F0DATA1_FD7   %1 7 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD7    Filter bits
: CAN1_F0DATA1_FD8   %1 8 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD8    Filter bits
: CAN1_F0DATA1_FD9   %1 9 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD9    Filter bits
: CAN1_F0DATA1_FD10   %1 10 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD10    Filter bits
: CAN1_F0DATA1_FD11   %1 11 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD11    Filter bits
: CAN1_F0DATA1_FD12   %1 12 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD12    Filter bits
: CAN1_F0DATA1_FD13   %1 13 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD13    Filter bits
: CAN1_F0DATA1_FD14   %1 14 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD14    Filter bits
: CAN1_F0DATA1_FD15   %1 15 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD15    Filter bits
: CAN1_F0DATA1_FD16   %1 16 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD16    Filter bits
: CAN1_F0DATA1_FD17   %1 17 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD17    Filter bits
: CAN1_F0DATA1_FD18   %1 18 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD18    Filter bits
: CAN1_F0DATA1_FD19   %1 19 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD19    Filter bits
: CAN1_F0DATA1_FD20   %1 20 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD20    Filter bits
: CAN1_F0DATA1_FD21   %1 21 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD21    Filter bits
: CAN1_F0DATA1_FD22   %1 22 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD22    Filter bits
: CAN1_F0DATA1_FD23   %1 23 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD23    Filter bits
: CAN1_F0DATA1_FD24   %1 24 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD24    Filter bits
: CAN1_F0DATA1_FD25   %1 25 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD25    Filter bits
: CAN1_F0DATA1_FD26   %1 26 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD26    Filter bits
: CAN1_F0DATA1_FD27   %1 27 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD27    Filter bits
: CAN1_F0DATA1_FD28   %1 28 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD28    Filter bits
: CAN1_F0DATA1_FD29   %1 29 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD29    Filter bits
: CAN1_F0DATA1_FD30   %1 30 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD30    Filter bits
: CAN1_F0DATA1_FD31   %1 31 lshift CAN1_F0DATA1 bis! ;  \ CAN1_F0DATA1_FD31    Filter bits

\ CAN1_F1DATA0 (read-write)
: CAN1_F1DATA0_FD0   %1 0 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD0    Filter bits
: CAN1_F1DATA0_FD1   %1 1 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD1    Filter bits
: CAN1_F1DATA0_FD2   %1 2 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD2    Filter bits
: CAN1_F1DATA0_FD3   %1 3 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD3    Filter bits
: CAN1_F1DATA0_FD4   %1 4 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD4    Filter bits
: CAN1_F1DATA0_FD5   %1 5 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD5    Filter bits
: CAN1_F1DATA0_FD6   %1 6 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD6    Filter bits
: CAN1_F1DATA0_FD7   %1 7 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD7    Filter bits
: CAN1_F1DATA0_FD8   %1 8 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD8    Filter bits
: CAN1_F1DATA0_FD9   %1 9 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD9    Filter bits
: CAN1_F1DATA0_FD10   %1 10 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD10    Filter bits
: CAN1_F1DATA0_FD11   %1 11 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD11    Filter bits
: CAN1_F1DATA0_FD12   %1 12 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD12    Filter bits
: CAN1_F1DATA0_FD13   %1 13 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD13    Filter bits
: CAN1_F1DATA0_FD14   %1 14 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD14    Filter bits
: CAN1_F1DATA0_FD15   %1 15 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD15    Filter bits
: CAN1_F1DATA0_FD16   %1 16 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD16    Filter bits
: CAN1_F1DATA0_FD17   %1 17 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD17    Filter bits
: CAN1_F1DATA0_FD18   %1 18 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD18    Filter bits
: CAN1_F1DATA0_FD19   %1 19 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD19    Filter bits
: CAN1_F1DATA0_FD20   %1 20 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD20    Filter bits
: CAN1_F1DATA0_FD21   %1 21 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD21    Filter bits
: CAN1_F1DATA0_FD22   %1 22 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD22    Filter bits
: CAN1_F1DATA0_FD23   %1 23 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD23    Filter bits
: CAN1_F1DATA0_FD24   %1 24 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD24    Filter bits
: CAN1_F1DATA0_FD25   %1 25 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD25    Filter bits
: CAN1_F1DATA0_FD26   %1 26 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD26    Filter bits
: CAN1_F1DATA0_FD27   %1 27 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD27    Filter bits
: CAN1_F1DATA0_FD28   %1 28 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD28    Filter bits
: CAN1_F1DATA0_FD29   %1 29 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD29    Filter bits
: CAN1_F1DATA0_FD30   %1 30 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD30    Filter bits
: CAN1_F1DATA0_FD31   %1 31 lshift CAN1_F1DATA0 bis! ;  \ CAN1_F1DATA0_FD31    Filter bits

\ CAN1_F1DATA1 (read-write)
: CAN1_F1DATA1_FD0   %1 0 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD0    Filter bits
: CAN1_F1DATA1_FD1   %1 1 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD1    Filter bits
: CAN1_F1DATA1_FD2   %1 2 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD2    Filter bits
: CAN1_F1DATA1_FD3   %1 3 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD3    Filter bits
: CAN1_F1DATA1_FD4   %1 4 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD4    Filter bits
: CAN1_F1DATA1_FD5   %1 5 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD5    Filter bits
: CAN1_F1DATA1_FD6   %1 6 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD6    Filter bits
: CAN1_F1DATA1_FD7   %1 7 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD7    Filter bits
: CAN1_F1DATA1_FD8   %1 8 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD8    Filter bits
: CAN1_F1DATA1_FD9   %1 9 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD9    Filter bits
: CAN1_F1DATA1_FD10   %1 10 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD10    Filter bits
: CAN1_F1DATA1_FD11   %1 11 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD11    Filter bits
: CAN1_F1DATA1_FD12   %1 12 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD12    Filter bits
: CAN1_F1DATA1_FD13   %1 13 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD13    Filter bits
: CAN1_F1DATA1_FD14   %1 14 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD14    Filter bits
: CAN1_F1DATA1_FD15   %1 15 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD15    Filter bits
: CAN1_F1DATA1_FD16   %1 16 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD16    Filter bits
: CAN1_F1DATA1_FD17   %1 17 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD17    Filter bits
: CAN1_F1DATA1_FD18   %1 18 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD18    Filter bits
: CAN1_F1DATA1_FD19   %1 19 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD19    Filter bits
: CAN1_F1DATA1_FD20   %1 20 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD20    Filter bits
: CAN1_F1DATA1_FD21   %1 21 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD21    Filter bits
: CAN1_F1DATA1_FD22   %1 22 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD22    Filter bits
: CAN1_F1DATA1_FD23   %1 23 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD23    Filter bits
: CAN1_F1DATA1_FD24   %1 24 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD24    Filter bits
: CAN1_F1DATA1_FD25   %1 25 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD25    Filter bits
: CAN1_F1DATA1_FD26   %1 26 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD26    Filter bits
: CAN1_F1DATA1_FD27   %1 27 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD27    Filter bits
: CAN1_F1DATA1_FD28   %1 28 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD28    Filter bits
: CAN1_F1DATA1_FD29   %1 29 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD29    Filter bits
: CAN1_F1DATA1_FD30   %1 30 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD30    Filter bits
: CAN1_F1DATA1_FD31   %1 31 lshift CAN1_F1DATA1 bis! ;  \ CAN1_F1DATA1_FD31    Filter bits

\ CAN1_F2DATA0 (read-write)
: CAN1_F2DATA0_FD0   %1 0 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD0    Filter bits
: CAN1_F2DATA0_FD1   %1 1 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD1    Filter bits
: CAN1_F2DATA0_FD2   %1 2 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD2    Filter bits
: CAN1_F2DATA0_FD3   %1 3 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD3    Filter bits
: CAN1_F2DATA0_FD4   %1 4 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD4    Filter bits
: CAN1_F2DATA0_FD5   %1 5 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD5    Filter bits
: CAN1_F2DATA0_FD6   %1 6 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD6    Filter bits
: CAN1_F2DATA0_FD7   %1 7 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD7    Filter bits
: CAN1_F2DATA0_FD8   %1 8 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD8    Filter bits
: CAN1_F2DATA0_FD9   %1 9 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD9    Filter bits
: CAN1_F2DATA0_FD10   %1 10 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD10    Filter bits
: CAN1_F2DATA0_FD11   %1 11 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD11    Filter bits
: CAN1_F2DATA0_FD12   %1 12 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD12    Filter bits
: CAN1_F2DATA0_FD13   %1 13 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD13    Filter bits
: CAN1_F2DATA0_FD14   %1 14 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD14    Filter bits
: CAN1_F2DATA0_FD15   %1 15 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD15    Filter bits
: CAN1_F2DATA0_FD16   %1 16 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD16    Filter bits
: CAN1_F2DATA0_FD17   %1 17 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD17    Filter bits
: CAN1_F2DATA0_FD18   %1 18 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD18    Filter bits
: CAN1_F2DATA0_FD19   %1 19 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD19    Filter bits
: CAN1_F2DATA0_FD20   %1 20 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD20    Filter bits
: CAN1_F2DATA0_FD21   %1 21 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD21    Filter bits
: CAN1_F2DATA0_FD22   %1 22 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD22    Filter bits
: CAN1_F2DATA0_FD23   %1 23 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD23    Filter bits
: CAN1_F2DATA0_FD24   %1 24 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD24    Filter bits
: CAN1_F2DATA0_FD25   %1 25 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD25    Filter bits
: CAN1_F2DATA0_FD26   %1 26 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD26    Filter bits
: CAN1_F2DATA0_FD27   %1 27 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD27    Filter bits
: CAN1_F2DATA0_FD28   %1 28 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD28    Filter bits
: CAN1_F2DATA0_FD29   %1 29 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD29    Filter bits
: CAN1_F2DATA0_FD30   %1 30 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD30    Filter bits
: CAN1_F2DATA0_FD31   %1 31 lshift CAN1_F2DATA0 bis! ;  \ CAN1_F2DATA0_FD31    Filter bits

\ CAN1_F2DATA1 (read-write)
: CAN1_F2DATA1_FD0   %1 0 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD0    Filter bits
: CAN1_F2DATA1_FD1   %1 1 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD1    Filter bits
: CAN1_F2DATA1_FD2   %1 2 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD2    Filter bits
: CAN1_F2DATA1_FD3   %1 3 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD3    Filter bits
: CAN1_F2DATA1_FD4   %1 4 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD4    Filter bits
: CAN1_F2DATA1_FD5   %1 5 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD5    Filter bits
: CAN1_F2DATA1_FD6   %1 6 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD6    Filter bits
: CAN1_F2DATA1_FD7   %1 7 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD7    Filter bits
: CAN1_F2DATA1_FD8   %1 8 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD8    Filter bits
: CAN1_F2DATA1_FD9   %1 9 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD9    Filter bits
: CAN1_F2DATA1_FD10   %1 10 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD10    Filter bits
: CAN1_F2DATA1_FD11   %1 11 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD11    Filter bits
: CAN1_F2DATA1_FD12   %1 12 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD12    Filter bits
: CAN1_F2DATA1_FD13   %1 13 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD13    Filter bits
: CAN1_F2DATA1_FD14   %1 14 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD14    Filter bits
: CAN1_F2DATA1_FD15   %1 15 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD15    Filter bits
: CAN1_F2DATA1_FD16   %1 16 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD16    Filter bits
: CAN1_F2DATA1_FD17   %1 17 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD17    Filter bits
: CAN1_F2DATA1_FD18   %1 18 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD18    Filter bits
: CAN1_F2DATA1_FD19   %1 19 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD19    Filter bits
: CAN1_F2DATA1_FD20   %1 20 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD20    Filter bits
: CAN1_F2DATA1_FD21   %1 21 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD21    Filter bits
: CAN1_F2DATA1_FD22   %1 22 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD22    Filter bits
: CAN1_F2DATA1_FD23   %1 23 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD23    Filter bits
: CAN1_F2DATA1_FD24   %1 24 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD24    Filter bits
: CAN1_F2DATA1_FD25   %1 25 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD25    Filter bits
: CAN1_F2DATA1_FD26   %1 26 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD26    Filter bits
: CAN1_F2DATA1_FD27   %1 27 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD27    Filter bits
: CAN1_F2DATA1_FD28   %1 28 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD28    Filter bits
: CAN1_F2DATA1_FD29   %1 29 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD29    Filter bits
: CAN1_F2DATA1_FD30   %1 30 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD30    Filter bits
: CAN1_F2DATA1_FD31   %1 31 lshift CAN1_F2DATA1 bis! ;  \ CAN1_F2DATA1_FD31    Filter bits

\ CAN1_F3DATA0 (read-write)
: CAN1_F3DATA0_FD0   %1 0 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD0    Filter bits
: CAN1_F3DATA0_FD1   %1 1 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD1    Filter bits
: CAN1_F3DATA0_FD2   %1 2 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD2    Filter bits
: CAN1_F3DATA0_FD3   %1 3 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD3    Filter bits
: CAN1_F3DATA0_FD4   %1 4 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD4    Filter bits
: CAN1_F3DATA0_FD5   %1 5 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD5    Filter bits
: CAN1_F3DATA0_FD6   %1 6 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD6    Filter bits
: CAN1_F3DATA0_FD7   %1 7 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD7    Filter bits
: CAN1_F3DATA0_FD8   %1 8 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD8    Filter bits
: CAN1_F3DATA0_FD9   %1 9 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD9    Filter bits
: CAN1_F3DATA0_FD10   %1 10 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD10    Filter bits
: CAN1_F3DATA0_FD11   %1 11 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD11    Filter bits
: CAN1_F3DATA0_FD12   %1 12 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD12    Filter bits
: CAN1_F3DATA0_FD13   %1 13 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD13    Filter bits
: CAN1_F3DATA0_FD14   %1 14 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD14    Filter bits
: CAN1_F3DATA0_FD15   %1 15 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD15    Filter bits
: CAN1_F3DATA0_FD16   %1 16 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD16    Filter bits
: CAN1_F3DATA0_FD17   %1 17 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD17    Filter bits
: CAN1_F3DATA0_FD18   %1 18 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD18    Filter bits
: CAN1_F3DATA0_FD19   %1 19 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD19    Filter bits
: CAN1_F3DATA0_FD20   %1 20 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD20    Filter bits
: CAN1_F3DATA0_FD21   %1 21 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD21    Filter bits
: CAN1_F3DATA0_FD22   %1 22 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD22    Filter bits
: CAN1_F3DATA0_FD23   %1 23 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD23    Filter bits
: CAN1_F3DATA0_FD24   %1 24 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD24    Filter bits
: CAN1_F3DATA0_FD25   %1 25 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD25    Filter bits
: CAN1_F3DATA0_FD26   %1 26 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD26    Filter bits
: CAN1_F3DATA0_FD27   %1 27 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD27    Filter bits
: CAN1_F3DATA0_FD28   %1 28 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD28    Filter bits
: CAN1_F3DATA0_FD29   %1 29 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD29    Filter bits
: CAN1_F3DATA0_FD30   %1 30 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD30    Filter bits
: CAN1_F3DATA0_FD31   %1 31 lshift CAN1_F3DATA0 bis! ;  \ CAN1_F3DATA0_FD31    Filter bits

\ CAN1_F3DATA1 (read-write)
: CAN1_F3DATA1_FD0   %1 0 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD0    Filter bits
: CAN1_F3DATA1_FD1   %1 1 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD1    Filter bits
: CAN1_F3DATA1_FD2   %1 2 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD2    Filter bits
: CAN1_F3DATA1_FD3   %1 3 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD3    Filter bits
: CAN1_F3DATA1_FD4   %1 4 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD4    Filter bits
: CAN1_F3DATA1_FD5   %1 5 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD5    Filter bits
: CAN1_F3DATA1_FD6   %1 6 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD6    Filter bits
: CAN1_F3DATA1_FD7   %1 7 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD7    Filter bits
: CAN1_F3DATA1_FD8   %1 8 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD8    Filter bits
: CAN1_F3DATA1_FD9   %1 9 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD9    Filter bits
: CAN1_F3DATA1_FD10   %1 10 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD10    Filter bits
: CAN1_F3DATA1_FD11   %1 11 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD11    Filter bits
: CAN1_F3DATA1_FD12   %1 12 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD12    Filter bits
: CAN1_F3DATA1_FD13   %1 13 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD13    Filter bits
: CAN1_F3DATA1_FD14   %1 14 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD14    Filter bits
: CAN1_F3DATA1_FD15   %1 15 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD15    Filter bits
: CAN1_F3DATA1_FD16   %1 16 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD16    Filter bits
: CAN1_F3DATA1_FD17   %1 17 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD17    Filter bits
: CAN1_F3DATA1_FD18   %1 18 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD18    Filter bits
: CAN1_F3DATA1_FD19   %1 19 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD19    Filter bits
: CAN1_F3DATA1_FD20   %1 20 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD20    Filter bits
: CAN1_F3DATA1_FD21   %1 21 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD21    Filter bits
: CAN1_F3DATA1_FD22   %1 22 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD22    Filter bits
: CAN1_F3DATA1_FD23   %1 23 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD23    Filter bits
: CAN1_F3DATA1_FD24   %1 24 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD24    Filter bits
: CAN1_F3DATA1_FD25   %1 25 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD25    Filter bits
: CAN1_F3DATA1_FD26   %1 26 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD26    Filter bits
: CAN1_F3DATA1_FD27   %1 27 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD27    Filter bits
: CAN1_F3DATA1_FD28   %1 28 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD28    Filter bits
: CAN1_F3DATA1_FD29   %1 29 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD29    Filter bits
: CAN1_F3DATA1_FD30   %1 30 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD30    Filter bits
: CAN1_F3DATA1_FD31   %1 31 lshift CAN1_F3DATA1 bis! ;  \ CAN1_F3DATA1_FD31    Filter bits

\ CAN1_F4DATA0 (read-write)
: CAN1_F4DATA0_FD0   %1 0 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD0    Filter bits
: CAN1_F4DATA0_FD1   %1 1 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD1    Filter bits
: CAN1_F4DATA0_FD2   %1 2 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD2    Filter bits
: CAN1_F4DATA0_FD3   %1 3 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD3    Filter bits
: CAN1_F4DATA0_FD4   %1 4 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD4    Filter bits
: CAN1_F4DATA0_FD5   %1 5 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD5    Filter bits
: CAN1_F4DATA0_FD6   %1 6 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD6    Filter bits
: CAN1_F4DATA0_FD7   %1 7 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD7    Filter bits
: CAN1_F4DATA0_FD8   %1 8 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD8    Filter bits
: CAN1_F4DATA0_FD9   %1 9 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD9    Filter bits
: CAN1_F4DATA0_FD10   %1 10 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD10    Filter bits
: CAN1_F4DATA0_FD11   %1 11 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD11    Filter bits
: CAN1_F4DATA0_FD12   %1 12 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD12    Filter bits
: CAN1_F4DATA0_FD13   %1 13 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD13    Filter bits
: CAN1_F4DATA0_FD14   %1 14 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD14    Filter bits
: CAN1_F4DATA0_FD15   %1 15 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD15    Filter bits
: CAN1_F4DATA0_FD16   %1 16 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD16    Filter bits
: CAN1_F4DATA0_FD17   %1 17 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD17    Filter bits
: CAN1_F4DATA0_FD18   %1 18 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD18    Filter bits
: CAN1_F4DATA0_FD19   %1 19 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD19    Filter bits
: CAN1_F4DATA0_FD20   %1 20 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD20    Filter bits
: CAN1_F4DATA0_FD21   %1 21 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD21    Filter bits
: CAN1_F4DATA0_FD22   %1 22 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD22    Filter bits
: CAN1_F4DATA0_FD23   %1 23 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD23    Filter bits
: CAN1_F4DATA0_FD24   %1 24 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD24    Filter bits
: CAN1_F4DATA0_FD25   %1 25 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD25    Filter bits
: CAN1_F4DATA0_FD26   %1 26 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD26    Filter bits
: CAN1_F4DATA0_FD27   %1 27 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD27    Filter bits
: CAN1_F4DATA0_FD28   %1 28 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD28    Filter bits
: CAN1_F4DATA0_FD29   %1 29 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD29    Filter bits
: CAN1_F4DATA0_FD30   %1 30 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD30    Filter bits
: CAN1_F4DATA0_FD31   %1 31 lshift CAN1_F4DATA0 bis! ;  \ CAN1_F4DATA0_FD31    Filter bits

\ CAN1_F4DATA1 (read-write)
: CAN1_F4DATA1_FD0   %1 0 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD0    Filter bits
: CAN1_F4DATA1_FD1   %1 1 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD1    Filter bits
: CAN1_F4DATA1_FD2   %1 2 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD2    Filter bits
: CAN1_F4DATA1_FD3   %1 3 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD3    Filter bits
: CAN1_F4DATA1_FD4   %1 4 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD4    Filter bits
: CAN1_F4DATA1_FD5   %1 5 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD5    Filter bits
: CAN1_F4DATA1_FD6   %1 6 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD6    Filter bits
: CAN1_F4DATA1_FD7   %1 7 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD7    Filter bits
: CAN1_F4DATA1_FD8   %1 8 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD8    Filter bits
: CAN1_F4DATA1_FD9   %1 9 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD9    Filter bits
: CAN1_F4DATA1_FD10   %1 10 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD10    Filter bits
: CAN1_F4DATA1_FD11   %1 11 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD11    Filter bits
: CAN1_F4DATA1_FD12   %1 12 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD12    Filter bits
: CAN1_F4DATA1_FD13   %1 13 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD13    Filter bits
: CAN1_F4DATA1_FD14   %1 14 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD14    Filter bits
: CAN1_F4DATA1_FD15   %1 15 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD15    Filter bits
: CAN1_F4DATA1_FD16   %1 16 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD16    Filter bits
: CAN1_F4DATA1_FD17   %1 17 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD17    Filter bits
: CAN1_F4DATA1_FD18   %1 18 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD18    Filter bits
: CAN1_F4DATA1_FD19   %1 19 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD19    Filter bits
: CAN1_F4DATA1_FD20   %1 20 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD20    Filter bits
: CAN1_F4DATA1_FD21   %1 21 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD21    Filter bits
: CAN1_F4DATA1_FD22   %1 22 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD22    Filter bits
: CAN1_F4DATA1_FD23   %1 23 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD23    Filter bits
: CAN1_F4DATA1_FD24   %1 24 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD24    Filter bits
: CAN1_F4DATA1_FD25   %1 25 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD25    Filter bits
: CAN1_F4DATA1_FD26   %1 26 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD26    Filter bits
: CAN1_F4DATA1_FD27   %1 27 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD27    Filter bits
: CAN1_F4DATA1_FD28   %1 28 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD28    Filter bits
: CAN1_F4DATA1_FD29   %1 29 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD29    Filter bits
: CAN1_F4DATA1_FD30   %1 30 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD30    Filter bits
: CAN1_F4DATA1_FD31   %1 31 lshift CAN1_F4DATA1 bis! ;  \ CAN1_F4DATA1_FD31    Filter bits

\ CAN1_F5DATA0 (read-write)
: CAN1_F5DATA0_FD0   %1 0 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD0    Filter bits
: CAN1_F5DATA0_FD1   %1 1 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD1    Filter bits
: CAN1_F5DATA0_FD2   %1 2 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD2    Filter bits
: CAN1_F5DATA0_FD3   %1 3 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD3    Filter bits
: CAN1_F5DATA0_FD4   %1 4 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD4    Filter bits
: CAN1_F5DATA0_FD5   %1 5 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD5    Filter bits
: CAN1_F5DATA0_FD6   %1 6 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD6    Filter bits
: CAN1_F5DATA0_FD7   %1 7 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD7    Filter bits
: CAN1_F5DATA0_FD8   %1 8 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD8    Filter bits
: CAN1_F5DATA0_FD9   %1 9 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD9    Filter bits
: CAN1_F5DATA0_FD10   %1 10 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD10    Filter bits
: CAN1_F5DATA0_FD11   %1 11 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD11    Filter bits
: CAN1_F5DATA0_FD12   %1 12 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD12    Filter bits
: CAN1_F5DATA0_FD13   %1 13 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD13    Filter bits
: CAN1_F5DATA0_FD14   %1 14 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD14    Filter bits
: CAN1_F5DATA0_FD15   %1 15 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD15    Filter bits
: CAN1_F5DATA0_FD16   %1 16 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD16    Filter bits
: CAN1_F5DATA0_FD17   %1 17 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD17    Filter bits
: CAN1_F5DATA0_FD18   %1 18 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD18    Filter bits
: CAN1_F5DATA0_FD19   %1 19 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD19    Filter bits
: CAN1_F5DATA0_FD20   %1 20 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD20    Filter bits
: CAN1_F5DATA0_FD21   %1 21 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD21    Filter bits
: CAN1_F5DATA0_FD22   %1 22 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD22    Filter bits
: CAN1_F5DATA0_FD23   %1 23 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD23    Filter bits
: CAN1_F5DATA0_FD24   %1 24 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD24    Filter bits
: CAN1_F5DATA0_FD25   %1 25 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD25    Filter bits
: CAN1_F5DATA0_FD26   %1 26 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD26    Filter bits
: CAN1_F5DATA0_FD27   %1 27 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD27    Filter bits
: CAN1_F5DATA0_FD28   %1 28 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD28    Filter bits
: CAN1_F5DATA0_FD29   %1 29 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD29    Filter bits
: CAN1_F5DATA0_FD30   %1 30 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD30    Filter bits
: CAN1_F5DATA0_FD31   %1 31 lshift CAN1_F5DATA0 bis! ;  \ CAN1_F5DATA0_FD31    Filter bits

\ CAN1_F5DATA1 (read-write)
: CAN1_F5DATA1_FD0   %1 0 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD0    Filter bits
: CAN1_F5DATA1_FD1   %1 1 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD1    Filter bits
: CAN1_F5DATA1_FD2   %1 2 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD2    Filter bits
: CAN1_F5DATA1_FD3   %1 3 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD3    Filter bits
: CAN1_F5DATA1_FD4   %1 4 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD4    Filter bits
: CAN1_F5DATA1_FD5   %1 5 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD5    Filter bits
: CAN1_F5DATA1_FD6   %1 6 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD6    Filter bits
: CAN1_F5DATA1_FD7   %1 7 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD7    Filter bits
: CAN1_F5DATA1_FD8   %1 8 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD8    Filter bits
: CAN1_F5DATA1_FD9   %1 9 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD9    Filter bits
: CAN1_F5DATA1_FD10   %1 10 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD10    Filter bits
: CAN1_F5DATA1_FD11   %1 11 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD11    Filter bits
: CAN1_F5DATA1_FD12   %1 12 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD12    Filter bits
: CAN1_F5DATA1_FD13   %1 13 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD13    Filter bits
: CAN1_F5DATA1_FD14   %1 14 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD14    Filter bits
: CAN1_F5DATA1_FD15   %1 15 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD15    Filter bits
: CAN1_F5DATA1_FD16   %1 16 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD16    Filter bits
: CAN1_F5DATA1_FD17   %1 17 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD17    Filter bits
: CAN1_F5DATA1_FD18   %1 18 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD18    Filter bits
: CAN1_F5DATA1_FD19   %1 19 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD19    Filter bits
: CAN1_F5DATA1_FD20   %1 20 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD20    Filter bits
: CAN1_F5DATA1_FD21   %1 21 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD21    Filter bits
: CAN1_F5DATA1_FD22   %1 22 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD22    Filter bits
: CAN1_F5DATA1_FD23   %1 23 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD23    Filter bits
: CAN1_F5DATA1_FD24   %1 24 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD24    Filter bits
: CAN1_F5DATA1_FD25   %1 25 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD25    Filter bits
: CAN1_F5DATA1_FD26   %1 26 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD26    Filter bits
: CAN1_F5DATA1_FD27   %1 27 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD27    Filter bits
: CAN1_F5DATA1_FD28   %1 28 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD28    Filter bits
: CAN1_F5DATA1_FD29   %1 29 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD29    Filter bits
: CAN1_F5DATA1_FD30   %1 30 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD30    Filter bits
: CAN1_F5DATA1_FD31   %1 31 lshift CAN1_F5DATA1 bis! ;  \ CAN1_F5DATA1_FD31    Filter bits

\ CAN1_F6DATA0 (read-write)
: CAN1_F6DATA0_FD0   %1 0 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD0    Filter bits
: CAN1_F6DATA0_FD1   %1 1 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD1    Filter bits
: CAN1_F6DATA0_FD2   %1 2 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD2    Filter bits
: CAN1_F6DATA0_FD3   %1 3 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD3    Filter bits
: CAN1_F6DATA0_FD4   %1 4 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD4    Filter bits
: CAN1_F6DATA0_FD5   %1 5 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD5    Filter bits
: CAN1_F6DATA0_FD6   %1 6 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD6    Filter bits
: CAN1_F6DATA0_FD7   %1 7 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD7    Filter bits
: CAN1_F6DATA0_FD8   %1 8 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD8    Filter bits
: CAN1_F6DATA0_FD9   %1 9 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD9    Filter bits
: CAN1_F6DATA0_FD10   %1 10 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD10    Filter bits
: CAN1_F6DATA0_FD11   %1 11 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD11    Filter bits
: CAN1_F6DATA0_FD12   %1 12 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD12    Filter bits
: CAN1_F6DATA0_FD13   %1 13 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD13    Filter bits
: CAN1_F6DATA0_FD14   %1 14 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD14    Filter bits
: CAN1_F6DATA0_FD15   %1 15 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD15    Filter bits
: CAN1_F6DATA0_FD16   %1 16 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD16    Filter bits
: CAN1_F6DATA0_FD17   %1 17 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD17    Filter bits
: CAN1_F6DATA0_FD18   %1 18 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD18    Filter bits
: CAN1_F6DATA0_FD19   %1 19 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD19    Filter bits
: CAN1_F6DATA0_FD20   %1 20 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD20    Filter bits
: CAN1_F6DATA0_FD21   %1 21 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD21    Filter bits
: CAN1_F6DATA0_FD22   %1 22 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD22    Filter bits
: CAN1_F6DATA0_FD23   %1 23 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD23    Filter bits
: CAN1_F6DATA0_FD24   %1 24 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD24    Filter bits
: CAN1_F6DATA0_FD25   %1 25 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD25    Filter bits
: CAN1_F6DATA0_FD26   %1 26 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD26    Filter bits
: CAN1_F6DATA0_FD27   %1 27 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD27    Filter bits
: CAN1_F6DATA0_FD28   %1 28 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD28    Filter bits
: CAN1_F6DATA0_FD29   %1 29 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD29    Filter bits
: CAN1_F6DATA0_FD30   %1 30 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD30    Filter bits
: CAN1_F6DATA0_FD31   %1 31 lshift CAN1_F6DATA0 bis! ;  \ CAN1_F6DATA0_FD31    Filter bits

\ CAN1_F6DATA1 (read-write)
: CAN1_F6DATA1_FD0   %1 0 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD0    Filter bits
: CAN1_F6DATA1_FD1   %1 1 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD1    Filter bits
: CAN1_F6DATA1_FD2   %1 2 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD2    Filter bits
: CAN1_F6DATA1_FD3   %1 3 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD3    Filter bits
: CAN1_F6DATA1_FD4   %1 4 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD4    Filter bits
: CAN1_F6DATA1_FD5   %1 5 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD5    Filter bits
: CAN1_F6DATA1_FD6   %1 6 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD6    Filter bits
: CAN1_F6DATA1_FD7   %1 7 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD7    Filter bits
: CAN1_F6DATA1_FD8   %1 8 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD8    Filter bits
: CAN1_F6DATA1_FD9   %1 9 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD9    Filter bits
: CAN1_F6DATA1_FD10   %1 10 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD10    Filter bits
: CAN1_F6DATA1_FD11   %1 11 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD11    Filter bits
: CAN1_F6DATA1_FD12   %1 12 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD12    Filter bits
: CAN1_F6DATA1_FD13   %1 13 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD13    Filter bits
: CAN1_F6DATA1_FD14   %1 14 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD14    Filter bits
: CAN1_F6DATA1_FD15   %1 15 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD15    Filter bits
: CAN1_F6DATA1_FD16   %1 16 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD16    Filter bits
: CAN1_F6DATA1_FD17   %1 17 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD17    Filter bits
: CAN1_F6DATA1_FD18   %1 18 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD18    Filter bits
: CAN1_F6DATA1_FD19   %1 19 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD19    Filter bits
: CAN1_F6DATA1_FD20   %1 20 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD20    Filter bits
: CAN1_F6DATA1_FD21   %1 21 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD21    Filter bits
: CAN1_F6DATA1_FD22   %1 22 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD22    Filter bits
: CAN1_F6DATA1_FD23   %1 23 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD23    Filter bits
: CAN1_F6DATA1_FD24   %1 24 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD24    Filter bits
: CAN1_F6DATA1_FD25   %1 25 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD25    Filter bits
: CAN1_F6DATA1_FD26   %1 26 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD26    Filter bits
: CAN1_F6DATA1_FD27   %1 27 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD27    Filter bits
: CAN1_F6DATA1_FD28   %1 28 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD28    Filter bits
: CAN1_F6DATA1_FD29   %1 29 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD29    Filter bits
: CAN1_F6DATA1_FD30   %1 30 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD30    Filter bits
: CAN1_F6DATA1_FD31   %1 31 lshift CAN1_F6DATA1 bis! ;  \ CAN1_F6DATA1_FD31    Filter bits

\ CAN1_F7DATA0 (read-write)
: CAN1_F7DATA0_FD0   %1 0 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD0    Filter bits
: CAN1_F7DATA0_FD1   %1 1 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD1    Filter bits
: CAN1_F7DATA0_FD2   %1 2 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD2    Filter bits
: CAN1_F7DATA0_FD3   %1 3 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD3    Filter bits
: CAN1_F7DATA0_FD4   %1 4 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD4    Filter bits
: CAN1_F7DATA0_FD5   %1 5 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD5    Filter bits
: CAN1_F7DATA0_FD6   %1 6 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD6    Filter bits
: CAN1_F7DATA0_FD7   %1 7 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD7    Filter bits
: CAN1_F7DATA0_FD8   %1 8 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD8    Filter bits
: CAN1_F7DATA0_FD9   %1 9 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD9    Filter bits
: CAN1_F7DATA0_FD10   %1 10 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD10    Filter bits
: CAN1_F7DATA0_FD11   %1 11 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD11    Filter bits
: CAN1_F7DATA0_FD12   %1 12 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD12    Filter bits
: CAN1_F7DATA0_FD13   %1 13 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD13    Filter bits
: CAN1_F7DATA0_FD14   %1 14 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD14    Filter bits
: CAN1_F7DATA0_FD15   %1 15 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD15    Filter bits
: CAN1_F7DATA0_FD16   %1 16 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD16    Filter bits
: CAN1_F7DATA0_FD17   %1 17 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD17    Filter bits
: CAN1_F7DATA0_FD18   %1 18 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD18    Filter bits
: CAN1_F7DATA0_FD19   %1 19 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD19    Filter bits
: CAN1_F7DATA0_FD20   %1 20 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD20    Filter bits
: CAN1_F7DATA0_FD21   %1 21 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD21    Filter bits
: CAN1_F7DATA0_FD22   %1 22 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD22    Filter bits
: CAN1_F7DATA0_FD23   %1 23 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD23    Filter bits
: CAN1_F7DATA0_FD24   %1 24 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD24    Filter bits
: CAN1_F7DATA0_FD25   %1 25 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD25    Filter bits
: CAN1_F7DATA0_FD26   %1 26 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD26    Filter bits
: CAN1_F7DATA0_FD27   %1 27 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD27    Filter bits
: CAN1_F7DATA0_FD28   %1 28 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD28    Filter bits
: CAN1_F7DATA0_FD29   %1 29 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD29    Filter bits
: CAN1_F7DATA0_FD30   %1 30 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD30    Filter bits
: CAN1_F7DATA0_FD31   %1 31 lshift CAN1_F7DATA0 bis! ;  \ CAN1_F7DATA0_FD31    Filter bits

\ CAN1_F7DATA1 (read-write)
: CAN1_F7DATA1_FD0   %1 0 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD0    Filter bits
: CAN1_F7DATA1_FD1   %1 1 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD1    Filter bits
: CAN1_F7DATA1_FD2   %1 2 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD2    Filter bits
: CAN1_F7DATA1_FD3   %1 3 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD3    Filter bits
: CAN1_F7DATA1_FD4   %1 4 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD4    Filter bits
: CAN1_F7DATA1_FD5   %1 5 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD5    Filter bits
: CAN1_F7DATA1_FD6   %1 6 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD6    Filter bits
: CAN1_F7DATA1_FD7   %1 7 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD7    Filter bits
: CAN1_F7DATA1_FD8   %1 8 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD8    Filter bits
: CAN1_F7DATA1_FD9   %1 9 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD9    Filter bits
: CAN1_F7DATA1_FD10   %1 10 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD10    Filter bits
: CAN1_F7DATA1_FD11   %1 11 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD11    Filter bits
: CAN1_F7DATA1_FD12   %1 12 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD12    Filter bits
: CAN1_F7DATA1_FD13   %1 13 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD13    Filter bits
: CAN1_F7DATA1_FD14   %1 14 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD14    Filter bits
: CAN1_F7DATA1_FD15   %1 15 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD15    Filter bits
: CAN1_F7DATA1_FD16   %1 16 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD16    Filter bits
: CAN1_F7DATA1_FD17   %1 17 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD17    Filter bits
: CAN1_F7DATA1_FD18   %1 18 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD18    Filter bits
: CAN1_F7DATA1_FD19   %1 19 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD19    Filter bits
: CAN1_F7DATA1_FD20   %1 20 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD20    Filter bits
: CAN1_F7DATA1_FD21   %1 21 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD21    Filter bits
: CAN1_F7DATA1_FD22   %1 22 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD22    Filter bits
: CAN1_F7DATA1_FD23   %1 23 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD23    Filter bits
: CAN1_F7DATA1_FD24   %1 24 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD24    Filter bits
: CAN1_F7DATA1_FD25   %1 25 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD25    Filter bits
: CAN1_F7DATA1_FD26   %1 26 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD26    Filter bits
: CAN1_F7DATA1_FD27   %1 27 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD27    Filter bits
: CAN1_F7DATA1_FD28   %1 28 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD28    Filter bits
: CAN1_F7DATA1_FD29   %1 29 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD29    Filter bits
: CAN1_F7DATA1_FD30   %1 30 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD30    Filter bits
: CAN1_F7DATA1_FD31   %1 31 lshift CAN1_F7DATA1 bis! ;  \ CAN1_F7DATA1_FD31    Filter bits

\ CAN1_F8DATA0 (read-write)
: CAN1_F8DATA0_FD0   %1 0 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD0    Filter bits
: CAN1_F8DATA0_FD1   %1 1 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD1    Filter bits
: CAN1_F8DATA0_FD2   %1 2 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD2    Filter bits
: CAN1_F8DATA0_FD3   %1 3 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD3    Filter bits
: CAN1_F8DATA0_FD4   %1 4 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD4    Filter bits
: CAN1_F8DATA0_FD5   %1 5 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD5    Filter bits
: CAN1_F8DATA0_FD6   %1 6 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD6    Filter bits
: CAN1_F8DATA0_FD7   %1 7 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD7    Filter bits
: CAN1_F8DATA0_FD8   %1 8 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD8    Filter bits
: CAN1_F8DATA0_FD9   %1 9 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD9    Filter bits
: CAN1_F8DATA0_FD10   %1 10 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD10    Filter bits
: CAN1_F8DATA0_FD11   %1 11 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD11    Filter bits
: CAN1_F8DATA0_FD12   %1 12 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD12    Filter bits
: CAN1_F8DATA0_FD13   %1 13 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD13    Filter bits
: CAN1_F8DATA0_FD14   %1 14 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD14    Filter bits
: CAN1_F8DATA0_FD15   %1 15 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD15    Filter bits
: CAN1_F8DATA0_FD16   %1 16 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD16    Filter bits
: CAN1_F8DATA0_FD17   %1 17 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD17    Filter bits
: CAN1_F8DATA0_FD18   %1 18 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD18    Filter bits
: CAN1_F8DATA0_FD19   %1 19 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD19    Filter bits
: CAN1_F8DATA0_FD20   %1 20 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD20    Filter bits
: CAN1_F8DATA0_FD21   %1 21 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD21    Filter bits
: CAN1_F8DATA0_FD22   %1 22 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD22    Filter bits
: CAN1_F8DATA0_FD23   %1 23 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD23    Filter bits
: CAN1_F8DATA0_FD24   %1 24 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD24    Filter bits
: CAN1_F8DATA0_FD25   %1 25 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD25    Filter bits
: CAN1_F8DATA0_FD26   %1 26 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD26    Filter bits
: CAN1_F8DATA0_FD27   %1 27 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD27    Filter bits
: CAN1_F8DATA0_FD28   %1 28 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD28    Filter bits
: CAN1_F8DATA0_FD29   %1 29 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD29    Filter bits
: CAN1_F8DATA0_FD30   %1 30 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD30    Filter bits
: CAN1_F8DATA0_FD31   %1 31 lshift CAN1_F8DATA0 bis! ;  \ CAN1_F8DATA0_FD31    Filter bits

\ CAN1_F8DATA1 (read-write)
: CAN1_F8DATA1_FD0   %1 0 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD0    Filter bits
: CAN1_F8DATA1_FD1   %1 1 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD1    Filter bits
: CAN1_F8DATA1_FD2   %1 2 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD2    Filter bits
: CAN1_F8DATA1_FD3   %1 3 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD3    Filter bits
: CAN1_F8DATA1_FD4   %1 4 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD4    Filter bits
: CAN1_F8DATA1_FD5   %1 5 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD5    Filter bits
: CAN1_F8DATA1_FD6   %1 6 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD6    Filter bits
: CAN1_F8DATA1_FD7   %1 7 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD7    Filter bits
: CAN1_F8DATA1_FD8   %1 8 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD8    Filter bits
: CAN1_F8DATA1_FD9   %1 9 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD9    Filter bits
: CAN1_F8DATA1_FD10   %1 10 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD10    Filter bits
: CAN1_F8DATA1_FD11   %1 11 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD11    Filter bits
: CAN1_F8DATA1_FD12   %1 12 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD12    Filter bits
: CAN1_F8DATA1_FD13   %1 13 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD13    Filter bits
: CAN1_F8DATA1_FD14   %1 14 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD14    Filter bits
: CAN1_F8DATA1_FD15   %1 15 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD15    Filter bits
: CAN1_F8DATA1_FD16   %1 16 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD16    Filter bits
: CAN1_F8DATA1_FD17   %1 17 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD17    Filter bits
: CAN1_F8DATA1_FD18   %1 18 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD18    Filter bits
: CAN1_F8DATA1_FD19   %1 19 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD19    Filter bits
: CAN1_F8DATA1_FD20   %1 20 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD20    Filter bits
: CAN1_F8DATA1_FD21   %1 21 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD21    Filter bits
: CAN1_F8DATA1_FD22   %1 22 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD22    Filter bits
: CAN1_F8DATA1_FD23   %1 23 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD23    Filter bits
: CAN1_F8DATA1_FD24   %1 24 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD24    Filter bits
: CAN1_F8DATA1_FD25   %1 25 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD25    Filter bits
: CAN1_F8DATA1_FD26   %1 26 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD26    Filter bits
: CAN1_F8DATA1_FD27   %1 27 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD27    Filter bits
: CAN1_F8DATA1_FD28   %1 28 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD28    Filter bits
: CAN1_F8DATA1_FD29   %1 29 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD29    Filter bits
: CAN1_F8DATA1_FD30   %1 30 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD30    Filter bits
: CAN1_F8DATA1_FD31   %1 31 lshift CAN1_F8DATA1 bis! ;  \ CAN1_F8DATA1_FD31    Filter bits

\ CAN1_F9DATA0 (read-write)
: CAN1_F9DATA0_FD0   %1 0 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD0    Filter bits
: CAN1_F9DATA0_FD1   %1 1 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD1    Filter bits
: CAN1_F9DATA0_FD2   %1 2 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD2    Filter bits
: CAN1_F9DATA0_FD3   %1 3 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD3    Filter bits
: CAN1_F9DATA0_FD4   %1 4 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD4    Filter bits
: CAN1_F9DATA0_FD5   %1 5 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD5    Filter bits
: CAN1_F9DATA0_FD6   %1 6 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD6    Filter bits
: CAN1_F9DATA0_FD7   %1 7 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD7    Filter bits
: CAN1_F9DATA0_FD8   %1 8 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD8    Filter bits
: CAN1_F9DATA0_FD9   %1 9 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD9    Filter bits
: CAN1_F9DATA0_FD10   %1 10 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD10    Filter bits
: CAN1_F9DATA0_FD11   %1 11 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD11    Filter bits
: CAN1_F9DATA0_FD12   %1 12 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD12    Filter bits
: CAN1_F9DATA0_FD13   %1 13 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD13    Filter bits
: CAN1_F9DATA0_FD14   %1 14 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD14    Filter bits
: CAN1_F9DATA0_FD15   %1 15 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD15    Filter bits
: CAN1_F9DATA0_FD16   %1 16 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD16    Filter bits
: CAN1_F9DATA0_FD17   %1 17 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD17    Filter bits
: CAN1_F9DATA0_FD18   %1 18 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD18    Filter bits
: CAN1_F9DATA0_FD19   %1 19 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD19    Filter bits
: CAN1_F9DATA0_FD20   %1 20 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD20    Filter bits
: CAN1_F9DATA0_FD21   %1 21 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD21    Filter bits
: CAN1_F9DATA0_FD22   %1 22 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD22    Filter bits
: CAN1_F9DATA0_FD23   %1 23 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD23    Filter bits
: CAN1_F9DATA0_FD24   %1 24 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD24    Filter bits
: CAN1_F9DATA0_FD25   %1 25 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD25    Filter bits
: CAN1_F9DATA0_FD26   %1 26 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD26    Filter bits
: CAN1_F9DATA0_FD27   %1 27 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD27    Filter bits
: CAN1_F9DATA0_FD28   %1 28 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD28    Filter bits
: CAN1_F9DATA0_FD29   %1 29 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD29    Filter bits
: CAN1_F9DATA0_FD30   %1 30 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD30    Filter bits
: CAN1_F9DATA0_FD31   %1 31 lshift CAN1_F9DATA0 bis! ;  \ CAN1_F9DATA0_FD31    Filter bits

\ CAN1_F9DATA1 (read-write)
: CAN1_F9DATA1_FD0   %1 0 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD0    Filter bits
: CAN1_F9DATA1_FD1   %1 1 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD1    Filter bits
: CAN1_F9DATA1_FD2   %1 2 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD2    Filter bits
: CAN1_F9DATA1_FD3   %1 3 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD3    Filter bits
: CAN1_F9DATA1_FD4   %1 4 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD4    Filter bits
: CAN1_F9DATA1_FD5   %1 5 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD5    Filter bits
: CAN1_F9DATA1_FD6   %1 6 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD6    Filter bits
: CAN1_F9DATA1_FD7   %1 7 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD7    Filter bits
: CAN1_F9DATA1_FD8   %1 8 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD8    Filter bits
: CAN1_F9DATA1_FD9   %1 9 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD9    Filter bits
: CAN1_F9DATA1_FD10   %1 10 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD10    Filter bits
: CAN1_F9DATA1_FD11   %1 11 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD11    Filter bits
: CAN1_F9DATA1_FD12   %1 12 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD12    Filter bits
: CAN1_F9DATA1_FD13   %1 13 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD13    Filter bits
: CAN1_F9DATA1_FD14   %1 14 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD14    Filter bits
: CAN1_F9DATA1_FD15   %1 15 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD15    Filter bits
: CAN1_F9DATA1_FD16   %1 16 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD16    Filter bits
: CAN1_F9DATA1_FD17   %1 17 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD17    Filter bits
: CAN1_F9DATA1_FD18   %1 18 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD18    Filter bits
: CAN1_F9DATA1_FD19   %1 19 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD19    Filter bits
: CAN1_F9DATA1_FD20   %1 20 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD20    Filter bits
: CAN1_F9DATA1_FD21   %1 21 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD21    Filter bits
: CAN1_F9DATA1_FD22   %1 22 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD22    Filter bits
: CAN1_F9DATA1_FD23   %1 23 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD23    Filter bits
: CAN1_F9DATA1_FD24   %1 24 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD24    Filter bits
: CAN1_F9DATA1_FD25   %1 25 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD25    Filter bits
: CAN1_F9DATA1_FD26   %1 26 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD26    Filter bits
: CAN1_F9DATA1_FD27   %1 27 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD27    Filter bits
: CAN1_F9DATA1_FD28   %1 28 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD28    Filter bits
: CAN1_F9DATA1_FD29   %1 29 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD29    Filter bits
: CAN1_F9DATA1_FD30   %1 30 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD30    Filter bits
: CAN1_F9DATA1_FD31   %1 31 lshift CAN1_F9DATA1 bis! ;  \ CAN1_F9DATA1_FD31    Filter bits

\ CAN1_F10DATA0 (read-write)
: CAN1_F10DATA0_FD0   %1 0 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD0    Filter bits
: CAN1_F10DATA0_FD1   %1 1 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD1    Filter bits
: CAN1_F10DATA0_FD2   %1 2 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD2    Filter bits
: CAN1_F10DATA0_FD3   %1 3 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD3    Filter bits
: CAN1_F10DATA0_FD4   %1 4 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD4    Filter bits
: CAN1_F10DATA0_FD5   %1 5 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD5    Filter bits
: CAN1_F10DATA0_FD6   %1 6 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD6    Filter bits
: CAN1_F10DATA0_FD7   %1 7 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD7    Filter bits
: CAN1_F10DATA0_FD8   %1 8 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD8    Filter bits
: CAN1_F10DATA0_FD9   %1 9 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD9    Filter bits
: CAN1_F10DATA0_FD10   %1 10 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD10    Filter bits
: CAN1_F10DATA0_FD11   %1 11 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD11    Filter bits
: CAN1_F10DATA0_FD12   %1 12 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD12    Filter bits
: CAN1_F10DATA0_FD13   %1 13 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD13    Filter bits
: CAN1_F10DATA0_FD14   %1 14 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD14    Filter bits
: CAN1_F10DATA0_FD15   %1 15 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD15    Filter bits
: CAN1_F10DATA0_FD16   %1 16 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD16    Filter bits
: CAN1_F10DATA0_FD17   %1 17 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD17    Filter bits
: CAN1_F10DATA0_FD18   %1 18 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD18    Filter bits
: CAN1_F10DATA0_FD19   %1 19 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD19    Filter bits
: CAN1_F10DATA0_FD20   %1 20 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD20    Filter bits
: CAN1_F10DATA0_FD21   %1 21 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD21    Filter bits
: CAN1_F10DATA0_FD22   %1 22 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD22    Filter bits
: CAN1_F10DATA0_FD23   %1 23 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD23    Filter bits
: CAN1_F10DATA0_FD24   %1 24 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD24    Filter bits
: CAN1_F10DATA0_FD25   %1 25 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD25    Filter bits
: CAN1_F10DATA0_FD26   %1 26 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD26    Filter bits
: CAN1_F10DATA0_FD27   %1 27 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD27    Filter bits
: CAN1_F10DATA0_FD28   %1 28 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD28    Filter bits
: CAN1_F10DATA0_FD29   %1 29 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD29    Filter bits
: CAN1_F10DATA0_FD30   %1 30 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD30    Filter bits
: CAN1_F10DATA0_FD31   %1 31 lshift CAN1_F10DATA0 bis! ;  \ CAN1_F10DATA0_FD31    Filter bits

\ CAN1_F10DATA1 (read-write)
: CAN1_F10DATA1_FD0   %1 0 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD0    Filter bits
: CAN1_F10DATA1_FD1   %1 1 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD1    Filter bits
: CAN1_F10DATA1_FD2   %1 2 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD2    Filter bits
: CAN1_F10DATA1_FD3   %1 3 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD3    Filter bits
: CAN1_F10DATA1_FD4   %1 4 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD4    Filter bits
: CAN1_F10DATA1_FD5   %1 5 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD5    Filter bits
: CAN1_F10DATA1_FD6   %1 6 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD6    Filter bits
: CAN1_F10DATA1_FD7   %1 7 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD7    Filter bits
: CAN1_F10DATA1_FD8   %1 8 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD8    Filter bits
: CAN1_F10DATA1_FD9   %1 9 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD9    Filter bits
: CAN1_F10DATA1_FD10   %1 10 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD10    Filter bits
: CAN1_F10DATA1_FD11   %1 11 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD11    Filter bits
: CAN1_F10DATA1_FD12   %1 12 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD12    Filter bits
: CAN1_F10DATA1_FD13   %1 13 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD13    Filter bits
: CAN1_F10DATA1_FD14   %1 14 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD14    Filter bits
: CAN1_F10DATA1_FD15   %1 15 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD15    Filter bits
: CAN1_F10DATA1_FD16   %1 16 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD16    Filter bits
: CAN1_F10DATA1_FD17   %1 17 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD17    Filter bits
: CAN1_F10DATA1_FD18   %1 18 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD18    Filter bits
: CAN1_F10DATA1_FD19   %1 19 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD19    Filter bits
: CAN1_F10DATA1_FD20   %1 20 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD20    Filter bits
: CAN1_F10DATA1_FD21   %1 21 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD21    Filter bits
: CAN1_F10DATA1_FD22   %1 22 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD22    Filter bits
: CAN1_F10DATA1_FD23   %1 23 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD23    Filter bits
: CAN1_F10DATA1_FD24   %1 24 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD24    Filter bits
: CAN1_F10DATA1_FD25   %1 25 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD25    Filter bits
: CAN1_F10DATA1_FD26   %1 26 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD26    Filter bits
: CAN1_F10DATA1_FD27   %1 27 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD27    Filter bits
: CAN1_F10DATA1_FD28   %1 28 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD28    Filter bits
: CAN1_F10DATA1_FD29   %1 29 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD29    Filter bits
: CAN1_F10DATA1_FD30   %1 30 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD30    Filter bits
: CAN1_F10DATA1_FD31   %1 31 lshift CAN1_F10DATA1 bis! ;  \ CAN1_F10DATA1_FD31    Filter bits

\ CAN1_F11DATA0 (read-write)
: CAN1_F11DATA0_FD0   %1 0 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD0    Filter bits
: CAN1_F11DATA0_FD1   %1 1 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD1    Filter bits
: CAN1_F11DATA0_FD2   %1 2 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD2    Filter bits
: CAN1_F11DATA0_FD3   %1 3 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD3    Filter bits
: CAN1_F11DATA0_FD4   %1 4 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD4    Filter bits
: CAN1_F11DATA0_FD5   %1 5 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD5    Filter bits
: CAN1_F11DATA0_FD6   %1 6 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD6    Filter bits
: CAN1_F11DATA0_FD7   %1 7 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD7    Filter bits
: CAN1_F11DATA0_FD8   %1 8 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD8    Filter bits
: CAN1_F11DATA0_FD9   %1 9 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD9    Filter bits
: CAN1_F11DATA0_FD10   %1 10 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD10    Filter bits
: CAN1_F11DATA0_FD11   %1 11 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD11    Filter bits
: CAN1_F11DATA0_FD12   %1 12 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD12    Filter bits
: CAN1_F11DATA0_FD13   %1 13 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD13    Filter bits
: CAN1_F11DATA0_FD14   %1 14 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD14    Filter bits
: CAN1_F11DATA0_FD15   %1 15 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD15    Filter bits
: CAN1_F11DATA0_FD16   %1 16 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD16    Filter bits
: CAN1_F11DATA0_FD17   %1 17 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD17    Filter bits
: CAN1_F11DATA0_FD18   %1 18 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD18    Filter bits
: CAN1_F11DATA0_FD19   %1 19 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD19    Filter bits
: CAN1_F11DATA0_FD20   %1 20 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD20    Filter bits
: CAN1_F11DATA0_FD21   %1 21 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD21    Filter bits
: CAN1_F11DATA0_FD22   %1 22 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD22    Filter bits
: CAN1_F11DATA0_FD23   %1 23 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD23    Filter bits
: CAN1_F11DATA0_FD24   %1 24 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD24    Filter bits
: CAN1_F11DATA0_FD25   %1 25 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD25    Filter bits
: CAN1_F11DATA0_FD26   %1 26 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD26    Filter bits
: CAN1_F11DATA0_FD27   %1 27 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD27    Filter bits
: CAN1_F11DATA0_FD28   %1 28 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD28    Filter bits
: CAN1_F11DATA0_FD29   %1 29 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD29    Filter bits
: CAN1_F11DATA0_FD30   %1 30 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD30    Filter bits
: CAN1_F11DATA0_FD31   %1 31 lshift CAN1_F11DATA0 bis! ;  \ CAN1_F11DATA0_FD31    Filter bits

\ CAN1_F11DATA1 (read-write)
: CAN1_F11DATA1_FD0   %1 0 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD0    Filter bits
: CAN1_F11DATA1_FD1   %1 1 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD1    Filter bits
: CAN1_F11DATA1_FD2   %1 2 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD2    Filter bits
: CAN1_F11DATA1_FD3   %1 3 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD3    Filter bits
: CAN1_F11DATA1_FD4   %1 4 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD4    Filter bits
: CAN1_F11DATA1_FD5   %1 5 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD5    Filter bits
: CAN1_F11DATA1_FD6   %1 6 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD6    Filter bits
: CAN1_F11DATA1_FD7   %1 7 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD7    Filter bits
: CAN1_F11DATA1_FD8   %1 8 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD8    Filter bits
: CAN1_F11DATA1_FD9   %1 9 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD9    Filter bits
: CAN1_F11DATA1_FD10   %1 10 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD10    Filter bits
: CAN1_F11DATA1_FD11   %1 11 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD11    Filter bits
: CAN1_F11DATA1_FD12   %1 12 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD12    Filter bits
: CAN1_F11DATA1_FD13   %1 13 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD13    Filter bits
: CAN1_F11DATA1_FD14   %1 14 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD14    Filter bits
: CAN1_F11DATA1_FD15   %1 15 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD15    Filter bits
: CAN1_F11DATA1_FD16   %1 16 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD16    Filter bits
: CAN1_F11DATA1_FD17   %1 17 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD17    Filter bits
: CAN1_F11DATA1_FD18   %1 18 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD18    Filter bits
: CAN1_F11DATA1_FD19   %1 19 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD19    Filter bits
: CAN1_F11DATA1_FD20   %1 20 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD20    Filter bits
: CAN1_F11DATA1_FD21   %1 21 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD21    Filter bits
: CAN1_F11DATA1_FD22   %1 22 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD22    Filter bits
: CAN1_F11DATA1_FD23   %1 23 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD23    Filter bits
: CAN1_F11DATA1_FD24   %1 24 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD24    Filter bits
: CAN1_F11DATA1_FD25   %1 25 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD25    Filter bits
: CAN1_F11DATA1_FD26   %1 26 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD26    Filter bits
: CAN1_F11DATA1_FD27   %1 27 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD27    Filter bits
: CAN1_F11DATA1_FD28   %1 28 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD28    Filter bits
: CAN1_F11DATA1_FD29   %1 29 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD29    Filter bits
: CAN1_F11DATA1_FD30   %1 30 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD30    Filter bits
: CAN1_F11DATA1_FD31   %1 31 lshift CAN1_F11DATA1 bis! ;  \ CAN1_F11DATA1_FD31    Filter bits

\ CAN1_F12DATA0 (read-write)
: CAN1_F12DATA0_FD0   %1 0 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD0    Filter bits
: CAN1_F12DATA0_FD1   %1 1 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD1    Filter bits
: CAN1_F12DATA0_FD2   %1 2 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD2    Filter bits
: CAN1_F12DATA0_FD3   %1 3 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD3    Filter bits
: CAN1_F12DATA0_FD4   %1 4 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD4    Filter bits
: CAN1_F12DATA0_FD5   %1 5 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD5    Filter bits
: CAN1_F12DATA0_FD6   %1 6 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD6    Filter bits
: CAN1_F12DATA0_FD7   %1 7 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD7    Filter bits
: CAN1_F12DATA0_FD8   %1 8 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD8    Filter bits
: CAN1_F12DATA0_FD9   %1 9 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD9    Filter bits
: CAN1_F12DATA0_FD10   %1 10 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD10    Filter bits
: CAN1_F12DATA0_FD11   %1 11 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD11    Filter bits
: CAN1_F12DATA0_FD12   %1 12 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD12    Filter bits
: CAN1_F12DATA0_FD13   %1 13 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD13    Filter bits
: CAN1_F12DATA0_FD14   %1 14 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD14    Filter bits
: CAN1_F12DATA0_FD15   %1 15 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD15    Filter bits
: CAN1_F12DATA0_FD16   %1 16 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD16    Filter bits
: CAN1_F12DATA0_FD17   %1 17 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD17    Filter bits
: CAN1_F12DATA0_FD18   %1 18 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD18    Filter bits
: CAN1_F12DATA0_FD19   %1 19 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD19    Filter bits
: CAN1_F12DATA0_FD20   %1 20 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD20    Filter bits
: CAN1_F12DATA0_FD21   %1 21 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD21    Filter bits
: CAN1_F12DATA0_FD22   %1 22 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD22    Filter bits
: CAN1_F12DATA0_FD23   %1 23 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD23    Filter bits
: CAN1_F12DATA0_FD24   %1 24 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD24    Filter bits
: CAN1_F12DATA0_FD25   %1 25 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD25    Filter bits
: CAN1_F12DATA0_FD26   %1 26 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD26    Filter bits
: CAN1_F12DATA0_FD27   %1 27 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD27    Filter bits
: CAN1_F12DATA0_FD28   %1 28 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD28    Filter bits
: CAN1_F12DATA0_FD29   %1 29 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD29    Filter bits
: CAN1_F12DATA0_FD30   %1 30 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD30    Filter bits
: CAN1_F12DATA0_FD31   %1 31 lshift CAN1_F12DATA0 bis! ;  \ CAN1_F12DATA0_FD31    Filter bits

\ CAN1_F12DATA1 (read-write)
: CAN1_F12DATA1_FD0   %1 0 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD0    Filter bits
: CAN1_F12DATA1_FD1   %1 1 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD1    Filter bits
: CAN1_F12DATA1_FD2   %1 2 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD2    Filter bits
: CAN1_F12DATA1_FD3   %1 3 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD3    Filter bits
: CAN1_F12DATA1_FD4   %1 4 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD4    Filter bits
: CAN1_F12DATA1_FD5   %1 5 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD5    Filter bits
: CAN1_F12DATA1_FD6   %1 6 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD6    Filter bits
: CAN1_F12DATA1_FD7   %1 7 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD7    Filter bits
: CAN1_F12DATA1_FD8   %1 8 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD8    Filter bits
: CAN1_F12DATA1_FD9   %1 9 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD9    Filter bits
: CAN1_F12DATA1_FD10   %1 10 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD10    Filter bits
: CAN1_F12DATA1_FD11   %1 11 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD11    Filter bits
: CAN1_F12DATA1_FD12   %1 12 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD12    Filter bits
: CAN1_F12DATA1_FD13   %1 13 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD13    Filter bits
: CAN1_F12DATA1_FD14   %1 14 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD14    Filter bits
: CAN1_F12DATA1_FD15   %1 15 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD15    Filter bits
: CAN1_F12DATA1_FD16   %1 16 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD16    Filter bits
: CAN1_F12DATA1_FD17   %1 17 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD17    Filter bits
: CAN1_F12DATA1_FD18   %1 18 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD18    Filter bits
: CAN1_F12DATA1_FD19   %1 19 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD19    Filter bits
: CAN1_F12DATA1_FD20   %1 20 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD20    Filter bits
: CAN1_F12DATA1_FD21   %1 21 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD21    Filter bits
: CAN1_F12DATA1_FD22   %1 22 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD22    Filter bits
: CAN1_F12DATA1_FD23   %1 23 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD23    Filter bits
: CAN1_F12DATA1_FD24   %1 24 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD24    Filter bits
: CAN1_F12DATA1_FD25   %1 25 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD25    Filter bits
: CAN1_F12DATA1_FD26   %1 26 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD26    Filter bits
: CAN1_F12DATA1_FD27   %1 27 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD27    Filter bits
: CAN1_F12DATA1_FD28   %1 28 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD28    Filter bits
: CAN1_F12DATA1_FD29   %1 29 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD29    Filter bits
: CAN1_F12DATA1_FD30   %1 30 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD30    Filter bits
: CAN1_F12DATA1_FD31   %1 31 lshift CAN1_F12DATA1 bis! ;  \ CAN1_F12DATA1_FD31    Filter bits

\ CAN1_F13DATA0 (read-write)
: CAN1_F13DATA0_FD0   %1 0 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD0    Filter bits
: CAN1_F13DATA0_FD1   %1 1 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD1    Filter bits
: CAN1_F13DATA0_FD2   %1 2 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD2    Filter bits
: CAN1_F13DATA0_FD3   %1 3 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD3    Filter bits
: CAN1_F13DATA0_FD4   %1 4 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD4    Filter bits
: CAN1_F13DATA0_FD5   %1 5 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD5    Filter bits
: CAN1_F13DATA0_FD6   %1 6 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD6    Filter bits
: CAN1_F13DATA0_FD7   %1 7 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD7    Filter bits
: CAN1_F13DATA0_FD8   %1 8 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD8    Filter bits
: CAN1_F13DATA0_FD9   %1 9 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD9    Filter bits
: CAN1_F13DATA0_FD10   %1 10 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD10    Filter bits
: CAN1_F13DATA0_FD11   %1 11 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD11    Filter bits
: CAN1_F13DATA0_FD12   %1 12 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD12    Filter bits
: CAN1_F13DATA0_FD13   %1 13 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD13    Filter bits
: CAN1_F13DATA0_FD14   %1 14 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD14    Filter bits
: CAN1_F13DATA0_FD15   %1 15 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD15    Filter bits
: CAN1_F13DATA0_FD16   %1 16 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD16    Filter bits
: CAN1_F13DATA0_FD17   %1 17 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD17    Filter bits
: CAN1_F13DATA0_FD18   %1 18 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD18    Filter bits
: CAN1_F13DATA0_FD19   %1 19 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD19    Filter bits
: CAN1_F13DATA0_FD20   %1 20 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD20    Filter bits
: CAN1_F13DATA0_FD21   %1 21 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD21    Filter bits
: CAN1_F13DATA0_FD22   %1 22 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD22    Filter bits
: CAN1_F13DATA0_FD23   %1 23 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD23    Filter bits
: CAN1_F13DATA0_FD24   %1 24 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD24    Filter bits
: CAN1_F13DATA0_FD25   %1 25 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD25    Filter bits
: CAN1_F13DATA0_FD26   %1 26 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD26    Filter bits
: CAN1_F13DATA0_FD27   %1 27 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD27    Filter bits
: CAN1_F13DATA0_FD28   %1 28 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD28    Filter bits
: CAN1_F13DATA0_FD29   %1 29 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD29    Filter bits
: CAN1_F13DATA0_FD30   %1 30 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD30    Filter bits
: CAN1_F13DATA0_FD31   %1 31 lshift CAN1_F13DATA0 bis! ;  \ CAN1_F13DATA0_FD31    Filter bits

\ CAN1_F13DATA1 (read-write)
: CAN1_F13DATA1_FD0   %1 0 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD0    Filter bits
: CAN1_F13DATA1_FD1   %1 1 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD1    Filter bits
: CAN1_F13DATA1_FD2   %1 2 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD2    Filter bits
: CAN1_F13DATA1_FD3   %1 3 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD3    Filter bits
: CAN1_F13DATA1_FD4   %1 4 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD4    Filter bits
: CAN1_F13DATA1_FD5   %1 5 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD5    Filter bits
: CAN1_F13DATA1_FD6   %1 6 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD6    Filter bits
: CAN1_F13DATA1_FD7   %1 7 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD7    Filter bits
: CAN1_F13DATA1_FD8   %1 8 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD8    Filter bits
: CAN1_F13DATA1_FD9   %1 9 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD9    Filter bits
: CAN1_F13DATA1_FD10   %1 10 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD10    Filter bits
: CAN1_F13DATA1_FD11   %1 11 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD11    Filter bits
: CAN1_F13DATA1_FD12   %1 12 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD12    Filter bits
: CAN1_F13DATA1_FD13   %1 13 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD13    Filter bits
: CAN1_F13DATA1_FD14   %1 14 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD14    Filter bits
: CAN1_F13DATA1_FD15   %1 15 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD15    Filter bits
: CAN1_F13DATA1_FD16   %1 16 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD16    Filter bits
: CAN1_F13DATA1_FD17   %1 17 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD17    Filter bits
: CAN1_F13DATA1_FD18   %1 18 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD18    Filter bits
: CAN1_F13DATA1_FD19   %1 19 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD19    Filter bits
: CAN1_F13DATA1_FD20   %1 20 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD20    Filter bits
: CAN1_F13DATA1_FD21   %1 21 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD21    Filter bits
: CAN1_F13DATA1_FD22   %1 22 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD22    Filter bits
: CAN1_F13DATA1_FD23   %1 23 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD23    Filter bits
: CAN1_F13DATA1_FD24   %1 24 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD24    Filter bits
: CAN1_F13DATA1_FD25   %1 25 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD25    Filter bits
: CAN1_F13DATA1_FD26   %1 26 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD26    Filter bits
: CAN1_F13DATA1_FD27   %1 27 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD27    Filter bits
: CAN1_F13DATA1_FD28   %1 28 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD28    Filter bits
: CAN1_F13DATA1_FD29   %1 29 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD29    Filter bits
: CAN1_F13DATA1_FD30   %1 30 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD30    Filter bits
: CAN1_F13DATA1_FD31   %1 31 lshift CAN1_F13DATA1 bis! ;  \ CAN1_F13DATA1_FD31    Filter bits

\ CAN1_F14DATA0 (read-write)
: CAN1_F14DATA0_FD0   %1 0 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD0    Filter bits
: CAN1_F14DATA0_FD1   %1 1 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD1    Filter bits
: CAN1_F14DATA0_FD2   %1 2 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD2    Filter bits
: CAN1_F14DATA0_FD3   %1 3 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD3    Filter bits
: CAN1_F14DATA0_FD4   %1 4 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD4    Filter bits
: CAN1_F14DATA0_FD5   %1 5 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD5    Filter bits
: CAN1_F14DATA0_FD6   %1 6 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD6    Filter bits
: CAN1_F14DATA0_FD7   %1 7 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD7    Filter bits
: CAN1_F14DATA0_FD8   %1 8 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD8    Filter bits
: CAN1_F14DATA0_FD9   %1 9 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD9    Filter bits
: CAN1_F14DATA0_FD10   %1 10 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD10    Filter bits
: CAN1_F14DATA0_FD11   %1 11 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD11    Filter bits
: CAN1_F14DATA0_FD12   %1 12 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD12    Filter bits
: CAN1_F14DATA0_FD13   %1 13 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD13    Filter bits
: CAN1_F14DATA0_FD14   %1 14 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD14    Filter bits
: CAN1_F14DATA0_FD15   %1 15 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD15    Filter bits
: CAN1_F14DATA0_FD16   %1 16 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD16    Filter bits
: CAN1_F14DATA0_FD17   %1 17 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD17    Filter bits
: CAN1_F14DATA0_FD18   %1 18 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD18    Filter bits
: CAN1_F14DATA0_FD19   %1 19 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD19    Filter bits
: CAN1_F14DATA0_FD20   %1 20 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD20    Filter bits
: CAN1_F14DATA0_FD21   %1 21 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD21    Filter bits
: CAN1_F14DATA0_FD22   %1 22 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD22    Filter bits
: CAN1_F14DATA0_FD23   %1 23 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD23    Filter bits
: CAN1_F14DATA0_FD24   %1 24 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD24    Filter bits
: CAN1_F14DATA0_FD25   %1 25 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD25    Filter bits
: CAN1_F14DATA0_FD26   %1 26 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD26    Filter bits
: CAN1_F14DATA0_FD27   %1 27 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD27    Filter bits
: CAN1_F14DATA0_FD28   %1 28 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD28    Filter bits
: CAN1_F14DATA0_FD29   %1 29 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD29    Filter bits
: CAN1_F14DATA0_FD30   %1 30 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD30    Filter bits
: CAN1_F14DATA0_FD31   %1 31 lshift CAN1_F14DATA0 bis! ;  \ CAN1_F14DATA0_FD31    Filter bits

\ CAN1_F14DATA1 (read-write)
: CAN1_F14DATA1_FD0   %1 0 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD0    Filter bits
: CAN1_F14DATA1_FD1   %1 1 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD1    Filter bits
: CAN1_F14DATA1_FD2   %1 2 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD2    Filter bits
: CAN1_F14DATA1_FD3   %1 3 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD3    Filter bits
: CAN1_F14DATA1_FD4   %1 4 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD4    Filter bits
: CAN1_F14DATA1_FD5   %1 5 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD5    Filter bits
: CAN1_F14DATA1_FD6   %1 6 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD6    Filter bits
: CAN1_F14DATA1_FD7   %1 7 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD7    Filter bits
: CAN1_F14DATA1_FD8   %1 8 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD8    Filter bits
: CAN1_F14DATA1_FD9   %1 9 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD9    Filter bits
: CAN1_F14DATA1_FD10   %1 10 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD10    Filter bits
: CAN1_F14DATA1_FD11   %1 11 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD11    Filter bits
: CAN1_F14DATA1_FD12   %1 12 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD12    Filter bits
: CAN1_F14DATA1_FD13   %1 13 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD13    Filter bits
: CAN1_F14DATA1_FD14   %1 14 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD14    Filter bits
: CAN1_F14DATA1_FD15   %1 15 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD15    Filter bits
: CAN1_F14DATA1_FD16   %1 16 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD16    Filter bits
: CAN1_F14DATA1_FD17   %1 17 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD17    Filter bits
: CAN1_F14DATA1_FD18   %1 18 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD18    Filter bits
: CAN1_F14DATA1_FD19   %1 19 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD19    Filter bits
: CAN1_F14DATA1_FD20   %1 20 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD20    Filter bits
: CAN1_F14DATA1_FD21   %1 21 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD21    Filter bits
: CAN1_F14DATA1_FD22   %1 22 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD22    Filter bits
: CAN1_F14DATA1_FD23   %1 23 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD23    Filter bits
: CAN1_F14DATA1_FD24   %1 24 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD24    Filter bits
: CAN1_F14DATA1_FD25   %1 25 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD25    Filter bits
: CAN1_F14DATA1_FD26   %1 26 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD26    Filter bits
: CAN1_F14DATA1_FD27   %1 27 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD27    Filter bits
: CAN1_F14DATA1_FD28   %1 28 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD28    Filter bits
: CAN1_F14DATA1_FD29   %1 29 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD29    Filter bits
: CAN1_F14DATA1_FD30   %1 30 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD30    Filter bits
: CAN1_F14DATA1_FD31   %1 31 lshift CAN1_F14DATA1 bis! ;  \ CAN1_F14DATA1_FD31    Filter bits

\ CAN1_F15DATA0 (read-write)
: CAN1_F15DATA0_FD0   %1 0 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD0    Filter bits
: CAN1_F15DATA0_FD1   %1 1 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD1    Filter bits
: CAN1_F15DATA0_FD2   %1 2 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD2    Filter bits
: CAN1_F15DATA0_FD3   %1 3 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD3    Filter bits
: CAN1_F15DATA0_FD4   %1 4 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD4    Filter bits
: CAN1_F15DATA0_FD5   %1 5 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD5    Filter bits
: CAN1_F15DATA0_FD6   %1 6 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD6    Filter bits
: CAN1_F15DATA0_FD7   %1 7 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD7    Filter bits
: CAN1_F15DATA0_FD8   %1 8 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD8    Filter bits
: CAN1_F15DATA0_FD9   %1 9 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD9    Filter bits
: CAN1_F15DATA0_FD10   %1 10 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD10    Filter bits
: CAN1_F15DATA0_FD11   %1 11 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD11    Filter bits
: CAN1_F15DATA0_FD12   %1 12 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD12    Filter bits
: CAN1_F15DATA0_FD13   %1 13 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD13    Filter bits
: CAN1_F15DATA0_FD14   %1 14 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD14    Filter bits
: CAN1_F15DATA0_FD15   %1 15 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD15    Filter bits
: CAN1_F15DATA0_FD16   %1 16 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD16    Filter bits
: CAN1_F15DATA0_FD17   %1 17 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD17    Filter bits
: CAN1_F15DATA0_FD18   %1 18 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD18    Filter bits
: CAN1_F15DATA0_FD19   %1 19 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD19    Filter bits
: CAN1_F15DATA0_FD20   %1 20 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD20    Filter bits
: CAN1_F15DATA0_FD21   %1 21 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD21    Filter bits
: CAN1_F15DATA0_FD22   %1 22 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD22    Filter bits
: CAN1_F15DATA0_FD23   %1 23 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD23    Filter bits
: CAN1_F15DATA0_FD24   %1 24 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD24    Filter bits
: CAN1_F15DATA0_FD25   %1 25 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD25    Filter bits
: CAN1_F15DATA0_FD26   %1 26 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD26    Filter bits
: CAN1_F15DATA0_FD27   %1 27 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD27    Filter bits
: CAN1_F15DATA0_FD28   %1 28 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD28    Filter bits
: CAN1_F15DATA0_FD29   %1 29 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD29    Filter bits
: CAN1_F15DATA0_FD30   %1 30 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD30    Filter bits
: CAN1_F15DATA0_FD31   %1 31 lshift CAN1_F15DATA0 bis! ;  \ CAN1_F15DATA0_FD31    Filter bits

\ CAN1_F15DATA1 (read-write)
: CAN1_F15DATA1_FD0   %1 0 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD0    Filter bits
: CAN1_F15DATA1_FD1   %1 1 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD1    Filter bits
: CAN1_F15DATA1_FD2   %1 2 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD2    Filter bits
: CAN1_F15DATA1_FD3   %1 3 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD3    Filter bits
: CAN1_F15DATA1_FD4   %1 4 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD4    Filter bits
: CAN1_F15DATA1_FD5   %1 5 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD5    Filter bits
: CAN1_F15DATA1_FD6   %1 6 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD6    Filter bits
: CAN1_F15DATA1_FD7   %1 7 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD7    Filter bits
: CAN1_F15DATA1_FD8   %1 8 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD8    Filter bits
: CAN1_F15DATA1_FD9   %1 9 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD9    Filter bits
: CAN1_F15DATA1_FD10   %1 10 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD10    Filter bits
: CAN1_F15DATA1_FD11   %1 11 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD11    Filter bits
: CAN1_F15DATA1_FD12   %1 12 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD12    Filter bits
: CAN1_F15DATA1_FD13   %1 13 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD13    Filter bits
: CAN1_F15DATA1_FD14   %1 14 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD14    Filter bits
: CAN1_F15DATA1_FD15   %1 15 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD15    Filter bits
: CAN1_F15DATA1_FD16   %1 16 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD16    Filter bits
: CAN1_F15DATA1_FD17   %1 17 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD17    Filter bits
: CAN1_F15DATA1_FD18   %1 18 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD18    Filter bits
: CAN1_F15DATA1_FD19   %1 19 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD19    Filter bits
: CAN1_F15DATA1_FD20   %1 20 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD20    Filter bits
: CAN1_F15DATA1_FD21   %1 21 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD21    Filter bits
: CAN1_F15DATA1_FD22   %1 22 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD22    Filter bits
: CAN1_F15DATA1_FD23   %1 23 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD23    Filter bits
: CAN1_F15DATA1_FD24   %1 24 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD24    Filter bits
: CAN1_F15DATA1_FD25   %1 25 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD25    Filter bits
: CAN1_F15DATA1_FD26   %1 26 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD26    Filter bits
: CAN1_F15DATA1_FD27   %1 27 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD27    Filter bits
: CAN1_F15DATA1_FD28   %1 28 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD28    Filter bits
: CAN1_F15DATA1_FD29   %1 29 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD29    Filter bits
: CAN1_F15DATA1_FD30   %1 30 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD30    Filter bits
: CAN1_F15DATA1_FD31   %1 31 lshift CAN1_F15DATA1 bis! ;  \ CAN1_F15DATA1_FD31    Filter bits

\ CAN1_F16DATA0 (read-write)
: CAN1_F16DATA0_FD0   %1 0 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD0    Filter bits
: CAN1_F16DATA0_FD1   %1 1 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD1    Filter bits
: CAN1_F16DATA0_FD2   %1 2 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD2    Filter bits
: CAN1_F16DATA0_FD3   %1 3 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD3    Filter bits
: CAN1_F16DATA0_FD4   %1 4 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD4    Filter bits
: CAN1_F16DATA0_FD5   %1 5 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD5    Filter bits
: CAN1_F16DATA0_FD6   %1 6 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD6    Filter bits
: CAN1_F16DATA0_FD7   %1 7 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD7    Filter bits
: CAN1_F16DATA0_FD8   %1 8 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD8    Filter bits
: CAN1_F16DATA0_FD9   %1 9 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD9    Filter bits
: CAN1_F16DATA0_FD10   %1 10 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD10    Filter bits
: CAN1_F16DATA0_FD11   %1 11 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD11    Filter bits
: CAN1_F16DATA0_FD12   %1 12 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD12    Filter bits
: CAN1_F16DATA0_FD13   %1 13 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD13    Filter bits
: CAN1_F16DATA0_FD14   %1 14 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD14    Filter bits
: CAN1_F16DATA0_FD15   %1 15 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD15    Filter bits
: CAN1_F16DATA0_FD16   %1 16 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD16    Filter bits
: CAN1_F16DATA0_FD17   %1 17 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD17    Filter bits
: CAN1_F16DATA0_FD18   %1 18 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD18    Filter bits
: CAN1_F16DATA0_FD19   %1 19 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD19    Filter bits
: CAN1_F16DATA0_FD20   %1 20 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD20    Filter bits
: CAN1_F16DATA0_FD21   %1 21 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD21    Filter bits
: CAN1_F16DATA0_FD22   %1 22 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD22    Filter bits
: CAN1_F16DATA0_FD23   %1 23 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD23    Filter bits
: CAN1_F16DATA0_FD24   %1 24 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD24    Filter bits
: CAN1_F16DATA0_FD25   %1 25 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD25    Filter bits
: CAN1_F16DATA0_FD26   %1 26 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD26    Filter bits
: CAN1_F16DATA0_FD27   %1 27 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD27    Filter bits
: CAN1_F16DATA0_FD28   %1 28 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD28    Filter bits
: CAN1_F16DATA0_FD29   %1 29 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD29    Filter bits
: CAN1_F16DATA0_FD30   %1 30 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD30    Filter bits
: CAN1_F16DATA0_FD31   %1 31 lshift CAN1_F16DATA0 bis! ;  \ CAN1_F16DATA0_FD31    Filter bits

\ CAN1_F16DATA1 (read-write)
: CAN1_F16DATA1_FD0   %1 0 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD0    Filter bits
: CAN1_F16DATA1_FD1   %1 1 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD1    Filter bits
: CAN1_F16DATA1_FD2   %1 2 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD2    Filter bits
: CAN1_F16DATA1_FD3   %1 3 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD3    Filter bits
: CAN1_F16DATA1_FD4   %1 4 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD4    Filter bits
: CAN1_F16DATA1_FD5   %1 5 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD5    Filter bits
: CAN1_F16DATA1_FD6   %1 6 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD6    Filter bits
: CAN1_F16DATA1_FD7   %1 7 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD7    Filter bits
: CAN1_F16DATA1_FD8   %1 8 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD8    Filter bits
: CAN1_F16DATA1_FD9   %1 9 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD9    Filter bits
: CAN1_F16DATA1_FD10   %1 10 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD10    Filter bits
: CAN1_F16DATA1_FD11   %1 11 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD11    Filter bits
: CAN1_F16DATA1_FD12   %1 12 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD12    Filter bits
: CAN1_F16DATA1_FD13   %1 13 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD13    Filter bits
: CAN1_F16DATA1_FD14   %1 14 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD14    Filter bits
: CAN1_F16DATA1_FD15   %1 15 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD15    Filter bits
: CAN1_F16DATA1_FD16   %1 16 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD16    Filter bits
: CAN1_F16DATA1_FD17   %1 17 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD17    Filter bits
: CAN1_F16DATA1_FD18   %1 18 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD18    Filter bits
: CAN1_F16DATA1_FD19   %1 19 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD19    Filter bits
: CAN1_F16DATA1_FD20   %1 20 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD20    Filter bits
: CAN1_F16DATA1_FD21   %1 21 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD21    Filter bits
: CAN1_F16DATA1_FD22   %1 22 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD22    Filter bits
: CAN1_F16DATA1_FD23   %1 23 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD23    Filter bits
: CAN1_F16DATA1_FD24   %1 24 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD24    Filter bits
: CAN1_F16DATA1_FD25   %1 25 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD25    Filter bits
: CAN1_F16DATA1_FD26   %1 26 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD26    Filter bits
: CAN1_F16DATA1_FD27   %1 27 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD27    Filter bits
: CAN1_F16DATA1_FD28   %1 28 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD28    Filter bits
: CAN1_F16DATA1_FD29   %1 29 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD29    Filter bits
: CAN1_F16DATA1_FD30   %1 30 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD30    Filter bits
: CAN1_F16DATA1_FD31   %1 31 lshift CAN1_F16DATA1 bis! ;  \ CAN1_F16DATA1_FD31    Filter bits

\ CAN1_F17DATA0 (read-write)
: CAN1_F17DATA0_FD0   %1 0 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD0    Filter bits
: CAN1_F17DATA0_FD1   %1 1 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD1    Filter bits
: CAN1_F17DATA0_FD2   %1 2 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD2    Filter bits
: CAN1_F17DATA0_FD3   %1 3 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD3    Filter bits
: CAN1_F17DATA0_FD4   %1 4 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD4    Filter bits
: CAN1_F17DATA0_FD5   %1 5 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD5    Filter bits
: CAN1_F17DATA0_FD6   %1 6 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD6    Filter bits
: CAN1_F17DATA0_FD7   %1 7 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD7    Filter bits
: CAN1_F17DATA0_FD8   %1 8 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD8    Filter bits
: CAN1_F17DATA0_FD9   %1 9 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD9    Filter bits
: CAN1_F17DATA0_FD10   %1 10 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD10    Filter bits
: CAN1_F17DATA0_FD11   %1 11 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD11    Filter bits
: CAN1_F17DATA0_FD12   %1 12 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD12    Filter bits
: CAN1_F17DATA0_FD13   %1 13 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD13    Filter bits
: CAN1_F17DATA0_FD14   %1 14 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD14    Filter bits
: CAN1_F17DATA0_FD15   %1 15 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD15    Filter bits
: CAN1_F17DATA0_FD16   %1 16 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD16    Filter bits
: CAN1_F17DATA0_FD17   %1 17 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD17    Filter bits
: CAN1_F17DATA0_FD18   %1 18 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD18    Filter bits
: CAN1_F17DATA0_FD19   %1 19 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD19    Filter bits
: CAN1_F17DATA0_FD20   %1 20 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD20    Filter bits
: CAN1_F17DATA0_FD21   %1 21 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD21    Filter bits
: CAN1_F17DATA0_FD22   %1 22 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD22    Filter bits
: CAN1_F17DATA0_FD23   %1 23 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD23    Filter bits
: CAN1_F17DATA0_FD24   %1 24 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD24    Filter bits
: CAN1_F17DATA0_FD25   %1 25 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD25    Filter bits
: CAN1_F17DATA0_FD26   %1 26 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD26    Filter bits
: CAN1_F17DATA0_FD27   %1 27 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD27    Filter bits
: CAN1_F17DATA0_FD28   %1 28 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD28    Filter bits
: CAN1_F17DATA0_FD29   %1 29 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD29    Filter bits
: CAN1_F17DATA0_FD30   %1 30 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD30    Filter bits
: CAN1_F17DATA0_FD31   %1 31 lshift CAN1_F17DATA0 bis! ;  \ CAN1_F17DATA0_FD31    Filter bits

\ CAN1_F17DATA1 (read-write)
: CAN1_F17DATA1_FD0   %1 0 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD0    Filter bits
: CAN1_F17DATA1_FD1   %1 1 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD1    Filter bits
: CAN1_F17DATA1_FD2   %1 2 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD2    Filter bits
: CAN1_F17DATA1_FD3   %1 3 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD3    Filter bits
: CAN1_F17DATA1_FD4   %1 4 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD4    Filter bits
: CAN1_F17DATA1_FD5   %1 5 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD5    Filter bits
: CAN1_F17DATA1_FD6   %1 6 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD6    Filter bits
: CAN1_F17DATA1_FD7   %1 7 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD7    Filter bits
: CAN1_F17DATA1_FD8   %1 8 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD8    Filter bits
: CAN1_F17DATA1_FD9   %1 9 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD9    Filter bits
: CAN1_F17DATA1_FD10   %1 10 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD10    Filter bits
: CAN1_F17DATA1_FD11   %1 11 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD11    Filter bits
: CAN1_F17DATA1_FD12   %1 12 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD12    Filter bits
: CAN1_F17DATA1_FD13   %1 13 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD13    Filter bits
: CAN1_F17DATA1_FD14   %1 14 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD14    Filter bits
: CAN1_F17DATA1_FD15   %1 15 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD15    Filter bits
: CAN1_F17DATA1_FD16   %1 16 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD16    Filter bits
: CAN1_F17DATA1_FD17   %1 17 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD17    Filter bits
: CAN1_F17DATA1_FD18   %1 18 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD18    Filter bits
: CAN1_F17DATA1_FD19   %1 19 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD19    Filter bits
: CAN1_F17DATA1_FD20   %1 20 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD20    Filter bits
: CAN1_F17DATA1_FD21   %1 21 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD21    Filter bits
: CAN1_F17DATA1_FD22   %1 22 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD22    Filter bits
: CAN1_F17DATA1_FD23   %1 23 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD23    Filter bits
: CAN1_F17DATA1_FD24   %1 24 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD24    Filter bits
: CAN1_F17DATA1_FD25   %1 25 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD25    Filter bits
: CAN1_F17DATA1_FD26   %1 26 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD26    Filter bits
: CAN1_F17DATA1_FD27   %1 27 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD27    Filter bits
: CAN1_F17DATA1_FD28   %1 28 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD28    Filter bits
: CAN1_F17DATA1_FD29   %1 29 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD29    Filter bits
: CAN1_F17DATA1_FD30   %1 30 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD30    Filter bits
: CAN1_F17DATA1_FD31   %1 31 lshift CAN1_F17DATA1 bis! ;  \ CAN1_F17DATA1_FD31    Filter bits

\ CAN1_F18DATA0 (read-write)
: CAN1_F18DATA0_FD0   %1 0 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD0    Filter bits
: CAN1_F18DATA0_FD1   %1 1 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD1    Filter bits
: CAN1_F18DATA0_FD2   %1 2 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD2    Filter bits
: CAN1_F18DATA0_FD3   %1 3 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD3    Filter bits
: CAN1_F18DATA0_FD4   %1 4 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD4    Filter bits
: CAN1_F18DATA0_FD5   %1 5 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD5    Filter bits
: CAN1_F18DATA0_FD6   %1 6 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD6    Filter bits
: CAN1_F18DATA0_FD7   %1 7 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD7    Filter bits
: CAN1_F18DATA0_FD8   %1 8 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD8    Filter bits
: CAN1_F18DATA0_FD9   %1 9 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD9    Filter bits
: CAN1_F18DATA0_FD10   %1 10 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD10    Filter bits
: CAN1_F18DATA0_FD11   %1 11 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD11    Filter bits
: CAN1_F18DATA0_FD12   %1 12 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD12    Filter bits
: CAN1_F18DATA0_FD13   %1 13 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD13    Filter bits
: CAN1_F18DATA0_FD14   %1 14 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD14    Filter bits
: CAN1_F18DATA0_FD15   %1 15 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD15    Filter bits
: CAN1_F18DATA0_FD16   %1 16 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD16    Filter bits
: CAN1_F18DATA0_FD17   %1 17 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD17    Filter bits
: CAN1_F18DATA0_FD18   %1 18 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD18    Filter bits
: CAN1_F18DATA0_FD19   %1 19 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD19    Filter bits
: CAN1_F18DATA0_FD20   %1 20 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD20    Filter bits
: CAN1_F18DATA0_FD21   %1 21 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD21    Filter bits
: CAN1_F18DATA0_FD22   %1 22 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD22    Filter bits
: CAN1_F18DATA0_FD23   %1 23 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD23    Filter bits
: CAN1_F18DATA0_FD24   %1 24 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD24    Filter bits
: CAN1_F18DATA0_FD25   %1 25 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD25    Filter bits
: CAN1_F18DATA0_FD26   %1 26 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD26    Filter bits
: CAN1_F18DATA0_FD27   %1 27 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD27    Filter bits
: CAN1_F18DATA0_FD28   %1 28 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD28    Filter bits
: CAN1_F18DATA0_FD29   %1 29 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD29    Filter bits
: CAN1_F18DATA0_FD30   %1 30 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD30    Filter bits
: CAN1_F18DATA0_FD31   %1 31 lshift CAN1_F18DATA0 bis! ;  \ CAN1_F18DATA0_FD31    Filter bits

\ CAN1_F18DATA1 (read-write)
: CAN1_F18DATA1_FD0   %1 0 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD0    Filter bits
: CAN1_F18DATA1_FD1   %1 1 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD1    Filter bits
: CAN1_F18DATA1_FD2   %1 2 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD2    Filter bits
: CAN1_F18DATA1_FD3   %1 3 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD3    Filter bits
: CAN1_F18DATA1_FD4   %1 4 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD4    Filter bits
: CAN1_F18DATA1_FD5   %1 5 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD5    Filter bits
: CAN1_F18DATA1_FD6   %1 6 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD6    Filter bits
: CAN1_F18DATA1_FD7   %1 7 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD7    Filter bits
: CAN1_F18DATA1_FD8   %1 8 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD8    Filter bits
: CAN1_F18DATA1_FD9   %1 9 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD9    Filter bits
: CAN1_F18DATA1_FD10   %1 10 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD10    Filter bits
: CAN1_F18DATA1_FD11   %1 11 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD11    Filter bits
: CAN1_F18DATA1_FD12   %1 12 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD12    Filter bits
: CAN1_F18DATA1_FD13   %1 13 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD13    Filter bits
: CAN1_F18DATA1_FD14   %1 14 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD14    Filter bits
: CAN1_F18DATA1_FD15   %1 15 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD15    Filter bits
: CAN1_F18DATA1_FD16   %1 16 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD16    Filter bits
: CAN1_F18DATA1_FD17   %1 17 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD17    Filter bits
: CAN1_F18DATA1_FD18   %1 18 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD18    Filter bits
: CAN1_F18DATA1_FD19   %1 19 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD19    Filter bits
: CAN1_F18DATA1_FD20   %1 20 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD20    Filter bits
: CAN1_F18DATA1_FD21   %1 21 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD21    Filter bits
: CAN1_F18DATA1_FD22   %1 22 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD22    Filter bits
: CAN1_F18DATA1_FD23   %1 23 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD23    Filter bits
: CAN1_F18DATA1_FD24   %1 24 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD24    Filter bits
: CAN1_F18DATA1_FD25   %1 25 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD25    Filter bits
: CAN1_F18DATA1_FD26   %1 26 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD26    Filter bits
: CAN1_F18DATA1_FD27   %1 27 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD27    Filter bits
: CAN1_F18DATA1_FD28   %1 28 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD28    Filter bits
: CAN1_F18DATA1_FD29   %1 29 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD29    Filter bits
: CAN1_F18DATA1_FD30   %1 30 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD30    Filter bits
: CAN1_F18DATA1_FD31   %1 31 lshift CAN1_F18DATA1 bis! ;  \ CAN1_F18DATA1_FD31    Filter bits

\ CAN1_F19DATA0 (read-write)
: CAN1_F19DATA0_FD0   %1 0 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD0    Filter bits
: CAN1_F19DATA0_FD1   %1 1 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD1    Filter bits
: CAN1_F19DATA0_FD2   %1 2 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD2    Filter bits
: CAN1_F19DATA0_FD3   %1 3 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD3    Filter bits
: CAN1_F19DATA0_FD4   %1 4 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD4    Filter bits
: CAN1_F19DATA0_FD5   %1 5 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD5    Filter bits
: CAN1_F19DATA0_FD6   %1 6 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD6    Filter bits
: CAN1_F19DATA0_FD7   %1 7 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD7    Filter bits
: CAN1_F19DATA0_FD8   %1 8 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD8    Filter bits
: CAN1_F19DATA0_FD9   %1 9 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD9    Filter bits
: CAN1_F19DATA0_FD10   %1 10 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD10    Filter bits
: CAN1_F19DATA0_FD11   %1 11 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD11    Filter bits
: CAN1_F19DATA0_FD12   %1 12 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD12    Filter bits
: CAN1_F19DATA0_FD13   %1 13 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD13    Filter bits
: CAN1_F19DATA0_FD14   %1 14 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD14    Filter bits
: CAN1_F19DATA0_FD15   %1 15 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD15    Filter bits
: CAN1_F19DATA0_FD16   %1 16 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD16    Filter bits
: CAN1_F19DATA0_FD17   %1 17 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD17    Filter bits
: CAN1_F19DATA0_FD18   %1 18 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD18    Filter bits
: CAN1_F19DATA0_FD19   %1 19 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD19    Filter bits
: CAN1_F19DATA0_FD20   %1 20 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD20    Filter bits
: CAN1_F19DATA0_FD21   %1 21 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD21    Filter bits
: CAN1_F19DATA0_FD22   %1 22 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD22    Filter bits
: CAN1_F19DATA0_FD23   %1 23 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD23    Filter bits
: CAN1_F19DATA0_FD24   %1 24 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD24    Filter bits
: CAN1_F19DATA0_FD25   %1 25 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD25    Filter bits
: CAN1_F19DATA0_FD26   %1 26 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD26    Filter bits
: CAN1_F19DATA0_FD27   %1 27 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD27    Filter bits
: CAN1_F19DATA0_FD28   %1 28 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD28    Filter bits
: CAN1_F19DATA0_FD29   %1 29 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD29    Filter bits
: CAN1_F19DATA0_FD30   %1 30 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD30    Filter bits
: CAN1_F19DATA0_FD31   %1 31 lshift CAN1_F19DATA0 bis! ;  \ CAN1_F19DATA0_FD31    Filter bits

\ CAN1_F19DATA1 (read-write)
: CAN1_F19DATA1_FD0   %1 0 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD0    Filter bits
: CAN1_F19DATA1_FD1   %1 1 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD1    Filter bits
: CAN1_F19DATA1_FD2   %1 2 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD2    Filter bits
: CAN1_F19DATA1_FD3   %1 3 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD3    Filter bits
: CAN1_F19DATA1_FD4   %1 4 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD4    Filter bits
: CAN1_F19DATA1_FD5   %1 5 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD5    Filter bits
: CAN1_F19DATA1_FD6   %1 6 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD6    Filter bits
: CAN1_F19DATA1_FD7   %1 7 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD7    Filter bits
: CAN1_F19DATA1_FD8   %1 8 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD8    Filter bits
: CAN1_F19DATA1_FD9   %1 9 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD9    Filter bits
: CAN1_F19DATA1_FD10   %1 10 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD10    Filter bits
: CAN1_F19DATA1_FD11   %1 11 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD11    Filter bits
: CAN1_F19DATA1_FD12   %1 12 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD12    Filter bits
: CAN1_F19DATA1_FD13   %1 13 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD13    Filter bits
: CAN1_F19DATA1_FD14   %1 14 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD14    Filter bits
: CAN1_F19DATA1_FD15   %1 15 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD15    Filter bits
: CAN1_F19DATA1_FD16   %1 16 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD16    Filter bits
: CAN1_F19DATA1_FD17   %1 17 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD17    Filter bits
: CAN1_F19DATA1_FD18   %1 18 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD18    Filter bits
: CAN1_F19DATA1_FD19   %1 19 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD19    Filter bits
: CAN1_F19DATA1_FD20   %1 20 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD20    Filter bits
: CAN1_F19DATA1_FD21   %1 21 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD21    Filter bits
: CAN1_F19DATA1_FD22   %1 22 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD22    Filter bits
: CAN1_F19DATA1_FD23   %1 23 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD23    Filter bits
: CAN1_F19DATA1_FD24   %1 24 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD24    Filter bits
: CAN1_F19DATA1_FD25   %1 25 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD25    Filter bits
: CAN1_F19DATA1_FD26   %1 26 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD26    Filter bits
: CAN1_F19DATA1_FD27   %1 27 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD27    Filter bits
: CAN1_F19DATA1_FD28   %1 28 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD28    Filter bits
: CAN1_F19DATA1_FD29   %1 29 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD29    Filter bits
: CAN1_F19DATA1_FD30   %1 30 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD30    Filter bits
: CAN1_F19DATA1_FD31   %1 31 lshift CAN1_F19DATA1 bis! ;  \ CAN1_F19DATA1_FD31    Filter bits

\ CAN1_F20DATA0 (read-write)
: CAN1_F20DATA0_FD0   %1 0 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD0    Filter bits
: CAN1_F20DATA0_FD1   %1 1 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD1    Filter bits
: CAN1_F20DATA0_FD2   %1 2 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD2    Filter bits
: CAN1_F20DATA0_FD3   %1 3 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD3    Filter bits
: CAN1_F20DATA0_FD4   %1 4 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD4    Filter bits
: CAN1_F20DATA0_FD5   %1 5 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD5    Filter bits
: CAN1_F20DATA0_FD6   %1 6 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD6    Filter bits
: CAN1_F20DATA0_FD7   %1 7 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD7    Filter bits
: CAN1_F20DATA0_FD8   %1 8 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD8    Filter bits
: CAN1_F20DATA0_FD9   %1 9 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD9    Filter bits
: CAN1_F20DATA0_FD10   %1 10 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD10    Filter bits
: CAN1_F20DATA0_FD11   %1 11 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD11    Filter bits
: CAN1_F20DATA0_FD12   %1 12 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD12    Filter bits
: CAN1_F20DATA0_FD13   %1 13 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD13    Filter bits
: CAN1_F20DATA0_FD14   %1 14 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD14    Filter bits
: CAN1_F20DATA0_FD15   %1 15 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD15    Filter bits
: CAN1_F20DATA0_FD16   %1 16 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD16    Filter bits
: CAN1_F20DATA0_FD17   %1 17 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD17    Filter bits
: CAN1_F20DATA0_FD18   %1 18 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD18    Filter bits
: CAN1_F20DATA0_FD19   %1 19 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD19    Filter bits
: CAN1_F20DATA0_FD20   %1 20 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD20    Filter bits
: CAN1_F20DATA0_FD21   %1 21 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD21    Filter bits
: CAN1_F20DATA0_FD22   %1 22 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD22    Filter bits
: CAN1_F20DATA0_FD23   %1 23 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD23    Filter bits
: CAN1_F20DATA0_FD24   %1 24 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD24    Filter bits
: CAN1_F20DATA0_FD25   %1 25 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD25    Filter bits
: CAN1_F20DATA0_FD26   %1 26 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD26    Filter bits
: CAN1_F20DATA0_FD27   %1 27 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD27    Filter bits
: CAN1_F20DATA0_FD28   %1 28 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD28    Filter bits
: CAN1_F20DATA0_FD29   %1 29 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD29    Filter bits
: CAN1_F20DATA0_FD30   %1 30 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD30    Filter bits
: CAN1_F20DATA0_FD31   %1 31 lshift CAN1_F20DATA0 bis! ;  \ CAN1_F20DATA0_FD31    Filter bits

\ CAN1_F20DATA1 (read-write)
: CAN1_F20DATA1_FD0   %1 0 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD0    Filter bits
: CAN1_F20DATA1_FD1   %1 1 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD1    Filter bits
: CAN1_F20DATA1_FD2   %1 2 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD2    Filter bits
: CAN1_F20DATA1_FD3   %1 3 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD3    Filter bits
: CAN1_F20DATA1_FD4   %1 4 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD4    Filter bits
: CAN1_F20DATA1_FD5   %1 5 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD5    Filter bits
: CAN1_F20DATA1_FD6   %1 6 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD6    Filter bits
: CAN1_F20DATA1_FD7   %1 7 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD7    Filter bits
: CAN1_F20DATA1_FD8   %1 8 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD8    Filter bits
: CAN1_F20DATA1_FD9   %1 9 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD9    Filter bits
: CAN1_F20DATA1_FD10   %1 10 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD10    Filter bits
: CAN1_F20DATA1_FD11   %1 11 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD11    Filter bits
: CAN1_F20DATA1_FD12   %1 12 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD12    Filter bits
: CAN1_F20DATA1_FD13   %1 13 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD13    Filter bits
: CAN1_F20DATA1_FD14   %1 14 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD14    Filter bits
: CAN1_F20DATA1_FD15   %1 15 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD15    Filter bits
: CAN1_F20DATA1_FD16   %1 16 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD16    Filter bits
: CAN1_F20DATA1_FD17   %1 17 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD17    Filter bits
: CAN1_F20DATA1_FD18   %1 18 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD18    Filter bits
: CAN1_F20DATA1_FD19   %1 19 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD19    Filter bits
: CAN1_F20DATA1_FD20   %1 20 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD20    Filter bits
: CAN1_F20DATA1_FD21   %1 21 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD21    Filter bits
: CAN1_F20DATA1_FD22   %1 22 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD22    Filter bits
: CAN1_F20DATA1_FD23   %1 23 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD23    Filter bits
: CAN1_F20DATA1_FD24   %1 24 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD24    Filter bits
: CAN1_F20DATA1_FD25   %1 25 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD25    Filter bits
: CAN1_F20DATA1_FD26   %1 26 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD26    Filter bits
: CAN1_F20DATA1_FD27   %1 27 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD27    Filter bits
: CAN1_F20DATA1_FD28   %1 28 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD28    Filter bits
: CAN1_F20DATA1_FD29   %1 29 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD29    Filter bits
: CAN1_F20DATA1_FD30   %1 30 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD30    Filter bits
: CAN1_F20DATA1_FD31   %1 31 lshift CAN1_F20DATA1 bis! ;  \ CAN1_F20DATA1_FD31    Filter bits

\ CAN1_F21DATA0 (read-write)
: CAN1_F21DATA0_FD0   %1 0 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD0    Filter bits
: CAN1_F21DATA0_FD1   %1 1 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD1    Filter bits
: CAN1_F21DATA0_FD2   %1 2 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD2    Filter bits
: CAN1_F21DATA0_FD3   %1 3 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD3    Filter bits
: CAN1_F21DATA0_FD4   %1 4 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD4    Filter bits
: CAN1_F21DATA0_FD5   %1 5 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD5    Filter bits
: CAN1_F21DATA0_FD6   %1 6 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD6    Filter bits
: CAN1_F21DATA0_FD7   %1 7 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD7    Filter bits
: CAN1_F21DATA0_FD8   %1 8 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD8    Filter bits
: CAN1_F21DATA0_FD9   %1 9 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD9    Filter bits
: CAN1_F21DATA0_FD10   %1 10 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD10    Filter bits
: CAN1_F21DATA0_FD11   %1 11 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD11    Filter bits
: CAN1_F21DATA0_FD12   %1 12 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD12    Filter bits
: CAN1_F21DATA0_FD13   %1 13 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD13    Filter bits
: CAN1_F21DATA0_FD14   %1 14 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD14    Filter bits
: CAN1_F21DATA0_FD15   %1 15 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD15    Filter bits
: CAN1_F21DATA0_FD16   %1 16 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD16    Filter bits
: CAN1_F21DATA0_FD17   %1 17 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD17    Filter bits
: CAN1_F21DATA0_FD18   %1 18 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD18    Filter bits
: CAN1_F21DATA0_FD19   %1 19 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD19    Filter bits
: CAN1_F21DATA0_FD20   %1 20 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD20    Filter bits
: CAN1_F21DATA0_FD21   %1 21 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD21    Filter bits
: CAN1_F21DATA0_FD22   %1 22 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD22    Filter bits
: CAN1_F21DATA0_FD23   %1 23 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD23    Filter bits
: CAN1_F21DATA0_FD24   %1 24 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD24    Filter bits
: CAN1_F21DATA0_FD25   %1 25 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD25    Filter bits
: CAN1_F21DATA0_FD26   %1 26 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD26    Filter bits
: CAN1_F21DATA0_FD27   %1 27 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD27    Filter bits
: CAN1_F21DATA0_FD28   %1 28 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD28    Filter bits
: CAN1_F21DATA0_FD29   %1 29 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD29    Filter bits
: CAN1_F21DATA0_FD30   %1 30 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD30    Filter bits
: CAN1_F21DATA0_FD31   %1 31 lshift CAN1_F21DATA0 bis! ;  \ CAN1_F21DATA0_FD31    Filter bits

\ CAN1_F21DATA1 (read-write)
: CAN1_F21DATA1_FD0   %1 0 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD0    Filter bits
: CAN1_F21DATA1_FD1   %1 1 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD1    Filter bits
: CAN1_F21DATA1_FD2   %1 2 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD2    Filter bits
: CAN1_F21DATA1_FD3   %1 3 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD3    Filter bits
: CAN1_F21DATA1_FD4   %1 4 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD4    Filter bits
: CAN1_F21DATA1_FD5   %1 5 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD5    Filter bits
: CAN1_F21DATA1_FD6   %1 6 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD6    Filter bits
: CAN1_F21DATA1_FD7   %1 7 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD7    Filter bits
: CAN1_F21DATA1_FD8   %1 8 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD8    Filter bits
: CAN1_F21DATA1_FD9   %1 9 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD9    Filter bits
: CAN1_F21DATA1_FD10   %1 10 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD10    Filter bits
: CAN1_F21DATA1_FD11   %1 11 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD11    Filter bits
: CAN1_F21DATA1_FD12   %1 12 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD12    Filter bits
: CAN1_F21DATA1_FD13   %1 13 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD13    Filter bits
: CAN1_F21DATA1_FD14   %1 14 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD14    Filter bits
: CAN1_F21DATA1_FD15   %1 15 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD15    Filter bits
: CAN1_F21DATA1_FD16   %1 16 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD16    Filter bits
: CAN1_F21DATA1_FD17   %1 17 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD17    Filter bits
: CAN1_F21DATA1_FD18   %1 18 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD18    Filter bits
: CAN1_F21DATA1_FD19   %1 19 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD19    Filter bits
: CAN1_F21DATA1_FD20   %1 20 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD20    Filter bits
: CAN1_F21DATA1_FD21   %1 21 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD21    Filter bits
: CAN1_F21DATA1_FD22   %1 22 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD22    Filter bits
: CAN1_F21DATA1_FD23   %1 23 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD23    Filter bits
: CAN1_F21DATA1_FD24   %1 24 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD24    Filter bits
: CAN1_F21DATA1_FD25   %1 25 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD25    Filter bits
: CAN1_F21DATA1_FD26   %1 26 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD26    Filter bits
: CAN1_F21DATA1_FD27   %1 27 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD27    Filter bits
: CAN1_F21DATA1_FD28   %1 28 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD28    Filter bits
: CAN1_F21DATA1_FD29   %1 29 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD29    Filter bits
: CAN1_F21DATA1_FD30   %1 30 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD30    Filter bits
: CAN1_F21DATA1_FD31   %1 31 lshift CAN1_F21DATA1 bis! ;  \ CAN1_F21DATA1_FD31    Filter bits

\ CAN1_F22DATA0 (read-write)
: CAN1_F22DATA0_FD0   %1 0 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD0    Filter bits
: CAN1_F22DATA0_FD1   %1 1 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD1    Filter bits
: CAN1_F22DATA0_FD2   %1 2 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD2    Filter bits
: CAN1_F22DATA0_FD3   %1 3 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD3    Filter bits
: CAN1_F22DATA0_FD4   %1 4 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD4    Filter bits
: CAN1_F22DATA0_FD5   %1 5 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD5    Filter bits
: CAN1_F22DATA0_FD6   %1 6 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD6    Filter bits
: CAN1_F22DATA0_FD7   %1 7 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD7    Filter bits
: CAN1_F22DATA0_FD8   %1 8 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD8    Filter bits
: CAN1_F22DATA0_FD9   %1 9 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD9    Filter bits
: CAN1_F22DATA0_FD10   %1 10 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD10    Filter bits
: CAN1_F22DATA0_FD11   %1 11 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD11    Filter bits
: CAN1_F22DATA0_FD12   %1 12 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD12    Filter bits
: CAN1_F22DATA0_FD13   %1 13 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD13    Filter bits
: CAN1_F22DATA0_FD14   %1 14 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD14    Filter bits
: CAN1_F22DATA0_FD15   %1 15 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD15    Filter bits
: CAN1_F22DATA0_FD16   %1 16 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD16    Filter bits
: CAN1_F22DATA0_FD17   %1 17 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD17    Filter bits
: CAN1_F22DATA0_FD18   %1 18 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD18    Filter bits
: CAN1_F22DATA0_FD19   %1 19 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD19    Filter bits
: CAN1_F22DATA0_FD20   %1 20 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD20    Filter bits
: CAN1_F22DATA0_FD21   %1 21 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD21    Filter bits
: CAN1_F22DATA0_FD22   %1 22 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD22    Filter bits
: CAN1_F22DATA0_FD23   %1 23 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD23    Filter bits
: CAN1_F22DATA0_FD24   %1 24 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD24    Filter bits
: CAN1_F22DATA0_FD25   %1 25 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD25    Filter bits
: CAN1_F22DATA0_FD26   %1 26 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD26    Filter bits
: CAN1_F22DATA0_FD27   %1 27 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD27    Filter bits
: CAN1_F22DATA0_FD28   %1 28 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD28    Filter bits
: CAN1_F22DATA0_FD29   %1 29 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD29    Filter bits
: CAN1_F22DATA0_FD30   %1 30 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD30    Filter bits
: CAN1_F22DATA0_FD31   %1 31 lshift CAN1_F22DATA0 bis! ;  \ CAN1_F22DATA0_FD31    Filter bits

\ CAN1_F22DATA1 (read-write)
: CAN1_F22DATA1_FD0   %1 0 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD0    Filter bits
: CAN1_F22DATA1_FD1   %1 1 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD1    Filter bits
: CAN1_F22DATA1_FD2   %1 2 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD2    Filter bits
: CAN1_F22DATA1_FD3   %1 3 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD3    Filter bits
: CAN1_F22DATA1_FD4   %1 4 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD4    Filter bits
: CAN1_F22DATA1_FD5   %1 5 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD5    Filter bits
: CAN1_F22DATA1_FD6   %1 6 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD6    Filter bits
: CAN1_F22DATA1_FD7   %1 7 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD7    Filter bits
: CAN1_F22DATA1_FD8   %1 8 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD8    Filter bits
: CAN1_F22DATA1_FD9   %1 9 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD9    Filter bits
: CAN1_F22DATA1_FD10   %1 10 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD10    Filter bits
: CAN1_F22DATA1_FD11   %1 11 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD11    Filter bits
: CAN1_F22DATA1_FD12   %1 12 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD12    Filter bits
: CAN1_F22DATA1_FD13   %1 13 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD13    Filter bits
: CAN1_F22DATA1_FD14   %1 14 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD14    Filter bits
: CAN1_F22DATA1_FD15   %1 15 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD15    Filter bits
: CAN1_F22DATA1_FD16   %1 16 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD16    Filter bits
: CAN1_F22DATA1_FD17   %1 17 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD17    Filter bits
: CAN1_F22DATA1_FD18   %1 18 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD18    Filter bits
: CAN1_F22DATA1_FD19   %1 19 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD19    Filter bits
: CAN1_F22DATA1_FD20   %1 20 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD20    Filter bits
: CAN1_F22DATA1_FD21   %1 21 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD21    Filter bits
: CAN1_F22DATA1_FD22   %1 22 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD22    Filter bits
: CAN1_F22DATA1_FD23   %1 23 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD23    Filter bits
: CAN1_F22DATA1_FD24   %1 24 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD24    Filter bits
: CAN1_F22DATA1_FD25   %1 25 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD25    Filter bits
: CAN1_F22DATA1_FD26   %1 26 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD26    Filter bits
: CAN1_F22DATA1_FD27   %1 27 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD27    Filter bits
: CAN1_F22DATA1_FD28   %1 28 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD28    Filter bits
: CAN1_F22DATA1_FD29   %1 29 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD29    Filter bits
: CAN1_F22DATA1_FD30   %1 30 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD30    Filter bits
: CAN1_F22DATA1_FD31   %1 31 lshift CAN1_F22DATA1 bis! ;  \ CAN1_F22DATA1_FD31    Filter bits

\ CAN1_F23DATA0 (read-write)
: CAN1_F23DATA0_FD0   %1 0 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD0    Filter bits
: CAN1_F23DATA0_FD1   %1 1 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD1    Filter bits
: CAN1_F23DATA0_FD2   %1 2 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD2    Filter bits
: CAN1_F23DATA0_FD3   %1 3 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD3    Filter bits
: CAN1_F23DATA0_FD4   %1 4 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD4    Filter bits
: CAN1_F23DATA0_FD5   %1 5 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD5    Filter bits
: CAN1_F23DATA0_FD6   %1 6 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD6    Filter bits
: CAN1_F23DATA0_FD7   %1 7 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD7    Filter bits
: CAN1_F23DATA0_FD8   %1 8 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD8    Filter bits
: CAN1_F23DATA0_FD9   %1 9 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD9    Filter bits
: CAN1_F23DATA0_FD10   %1 10 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD10    Filter bits
: CAN1_F23DATA0_FD11   %1 11 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD11    Filter bits
: CAN1_F23DATA0_FD12   %1 12 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD12    Filter bits
: CAN1_F23DATA0_FD13   %1 13 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD13    Filter bits
: CAN1_F23DATA0_FD14   %1 14 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD14    Filter bits
: CAN1_F23DATA0_FD15   %1 15 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD15    Filter bits
: CAN1_F23DATA0_FD16   %1 16 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD16    Filter bits
: CAN1_F23DATA0_FD17   %1 17 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD17    Filter bits
: CAN1_F23DATA0_FD18   %1 18 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD18    Filter bits
: CAN1_F23DATA0_FD19   %1 19 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD19    Filter bits
: CAN1_F23DATA0_FD20   %1 20 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD20    Filter bits
: CAN1_F23DATA0_FD21   %1 21 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD21    Filter bits
: CAN1_F23DATA0_FD22   %1 22 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD22    Filter bits
: CAN1_F23DATA0_FD23   %1 23 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD23    Filter bits
: CAN1_F23DATA0_FD24   %1 24 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD24    Filter bits
: CAN1_F23DATA0_FD25   %1 25 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD25    Filter bits
: CAN1_F23DATA0_FD26   %1 26 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD26    Filter bits
: CAN1_F23DATA0_FD27   %1 27 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD27    Filter bits
: CAN1_F23DATA0_FD28   %1 28 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD28    Filter bits
: CAN1_F23DATA0_FD29   %1 29 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD29    Filter bits
: CAN1_F23DATA0_FD30   %1 30 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD30    Filter bits
: CAN1_F23DATA0_FD31   %1 31 lshift CAN1_F23DATA0 bis! ;  \ CAN1_F23DATA0_FD31    Filter bits

\ CAN1_F23DATA1 (read-write)
: CAN1_F23DATA1_FD0   %1 0 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD0    Filter bits
: CAN1_F23DATA1_FD1   %1 1 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD1    Filter bits
: CAN1_F23DATA1_FD2   %1 2 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD2    Filter bits
: CAN1_F23DATA1_FD3   %1 3 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD3    Filter bits
: CAN1_F23DATA1_FD4   %1 4 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD4    Filter bits
: CAN1_F23DATA1_FD5   %1 5 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD5    Filter bits
: CAN1_F23DATA1_FD6   %1 6 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD6    Filter bits
: CAN1_F23DATA1_FD7   %1 7 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD7    Filter bits
: CAN1_F23DATA1_FD8   %1 8 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD8    Filter bits
: CAN1_F23DATA1_FD9   %1 9 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD9    Filter bits
: CAN1_F23DATA1_FD10   %1 10 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD10    Filter bits
: CAN1_F23DATA1_FD11   %1 11 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD11    Filter bits
: CAN1_F23DATA1_FD12   %1 12 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD12    Filter bits
: CAN1_F23DATA1_FD13   %1 13 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD13    Filter bits
: CAN1_F23DATA1_FD14   %1 14 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD14    Filter bits
: CAN1_F23DATA1_FD15   %1 15 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD15    Filter bits
: CAN1_F23DATA1_FD16   %1 16 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD16    Filter bits
: CAN1_F23DATA1_FD17   %1 17 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD17    Filter bits
: CAN1_F23DATA1_FD18   %1 18 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD18    Filter bits
: CAN1_F23DATA1_FD19   %1 19 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD19    Filter bits
: CAN1_F23DATA1_FD20   %1 20 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD20    Filter bits
: CAN1_F23DATA1_FD21   %1 21 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD21    Filter bits
: CAN1_F23DATA1_FD22   %1 22 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD22    Filter bits
: CAN1_F23DATA1_FD23   %1 23 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD23    Filter bits
: CAN1_F23DATA1_FD24   %1 24 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD24    Filter bits
: CAN1_F23DATA1_FD25   %1 25 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD25    Filter bits
: CAN1_F23DATA1_FD26   %1 26 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD26    Filter bits
: CAN1_F23DATA1_FD27   %1 27 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD27    Filter bits
: CAN1_F23DATA1_FD28   %1 28 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD28    Filter bits
: CAN1_F23DATA1_FD29   %1 29 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD29    Filter bits
: CAN1_F23DATA1_FD30   %1 30 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD30    Filter bits
: CAN1_F23DATA1_FD31   %1 31 lshift CAN1_F23DATA1 bis! ;  \ CAN1_F23DATA1_FD31    Filter bits

\ CAN1_F24DATA0 (read-write)
: CAN1_F24DATA0_FD0   %1 0 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD0    Filter bits
: CAN1_F24DATA0_FD1   %1 1 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD1    Filter bits
: CAN1_F24DATA0_FD2   %1 2 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD2    Filter bits
: CAN1_F24DATA0_FD3   %1 3 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD3    Filter bits
: CAN1_F24DATA0_FD4   %1 4 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD4    Filter bits
: CAN1_F24DATA0_FD5   %1 5 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD5    Filter bits
: CAN1_F24DATA0_FD6   %1 6 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD6    Filter bits
: CAN1_F24DATA0_FD7   %1 7 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD7    Filter bits
: CAN1_F24DATA0_FD8   %1 8 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD8    Filter bits
: CAN1_F24DATA0_FD9   %1 9 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD9    Filter bits
: CAN1_F24DATA0_FD10   %1 10 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD10    Filter bits
: CAN1_F24DATA0_FD11   %1 11 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD11    Filter bits
: CAN1_F24DATA0_FD12   %1 12 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD12    Filter bits
: CAN1_F24DATA0_FD13   %1 13 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD13    Filter bits
: CAN1_F24DATA0_FD14   %1 14 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD14    Filter bits
: CAN1_F24DATA0_FD15   %1 15 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD15    Filter bits
: CAN1_F24DATA0_FD16   %1 16 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD16    Filter bits
: CAN1_F24DATA0_FD17   %1 17 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD17    Filter bits
: CAN1_F24DATA0_FD18   %1 18 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD18    Filter bits
: CAN1_F24DATA0_FD19   %1 19 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD19    Filter bits
: CAN1_F24DATA0_FD20   %1 20 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD20    Filter bits
: CAN1_F24DATA0_FD21   %1 21 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD21    Filter bits
: CAN1_F24DATA0_FD22   %1 22 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD22    Filter bits
: CAN1_F24DATA0_FD23   %1 23 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD23    Filter bits
: CAN1_F24DATA0_FD24   %1 24 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD24    Filter bits
: CAN1_F24DATA0_FD25   %1 25 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD25    Filter bits
: CAN1_F24DATA0_FD26   %1 26 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD26    Filter bits
: CAN1_F24DATA0_FD27   %1 27 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD27    Filter bits
: CAN1_F24DATA0_FD28   %1 28 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD28    Filter bits
: CAN1_F24DATA0_FD29   %1 29 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD29    Filter bits
: CAN1_F24DATA0_FD30   %1 30 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD30    Filter bits
: CAN1_F24DATA0_FD31   %1 31 lshift CAN1_F24DATA0 bis! ;  \ CAN1_F24DATA0_FD31    Filter bits

\ CAN1_F24DATA1 (read-write)
: CAN1_F24DATA1_FD0   %1 0 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD0    Filter bits
: CAN1_F24DATA1_FD1   %1 1 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD1    Filter bits
: CAN1_F24DATA1_FD2   %1 2 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD2    Filter bits
: CAN1_F24DATA1_FD3   %1 3 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD3    Filter bits
: CAN1_F24DATA1_FD4   %1 4 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD4    Filter bits
: CAN1_F24DATA1_FD5   %1 5 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD5    Filter bits
: CAN1_F24DATA1_FD6   %1 6 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD6    Filter bits
: CAN1_F24DATA1_FD7   %1 7 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD7    Filter bits
: CAN1_F24DATA1_FD8   %1 8 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD8    Filter bits
: CAN1_F24DATA1_FD9   %1 9 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD9    Filter bits
: CAN1_F24DATA1_FD10   %1 10 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD10    Filter bits
: CAN1_F24DATA1_FD11   %1 11 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD11    Filter bits
: CAN1_F24DATA1_FD12   %1 12 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD12    Filter bits
: CAN1_F24DATA1_FD13   %1 13 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD13    Filter bits
: CAN1_F24DATA1_FD14   %1 14 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD14    Filter bits
: CAN1_F24DATA1_FD15   %1 15 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD15    Filter bits
: CAN1_F24DATA1_FD16   %1 16 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD16    Filter bits
: CAN1_F24DATA1_FD17   %1 17 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD17    Filter bits
: CAN1_F24DATA1_FD18   %1 18 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD18    Filter bits
: CAN1_F24DATA1_FD19   %1 19 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD19    Filter bits
: CAN1_F24DATA1_FD20   %1 20 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD20    Filter bits
: CAN1_F24DATA1_FD21   %1 21 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD21    Filter bits
: CAN1_F24DATA1_FD22   %1 22 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD22    Filter bits
: CAN1_F24DATA1_FD23   %1 23 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD23    Filter bits
: CAN1_F24DATA1_FD24   %1 24 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD24    Filter bits
: CAN1_F24DATA1_FD25   %1 25 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD25    Filter bits
: CAN1_F24DATA1_FD26   %1 26 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD26    Filter bits
: CAN1_F24DATA1_FD27   %1 27 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD27    Filter bits
: CAN1_F24DATA1_FD28   %1 28 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD28    Filter bits
: CAN1_F24DATA1_FD29   %1 29 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD29    Filter bits
: CAN1_F24DATA1_FD30   %1 30 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD30    Filter bits
: CAN1_F24DATA1_FD31   %1 31 lshift CAN1_F24DATA1 bis! ;  \ CAN1_F24DATA1_FD31    Filter bits

\ CAN1_F25DATA0 (read-write)
: CAN1_F25DATA0_FD0   %1 0 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD0    Filter bits
: CAN1_F25DATA0_FD1   %1 1 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD1    Filter bits
: CAN1_F25DATA0_FD2   %1 2 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD2    Filter bits
: CAN1_F25DATA0_FD3   %1 3 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD3    Filter bits
: CAN1_F25DATA0_FD4   %1 4 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD4    Filter bits
: CAN1_F25DATA0_FD5   %1 5 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD5    Filter bits
: CAN1_F25DATA0_FD6   %1 6 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD6    Filter bits
: CAN1_F25DATA0_FD7   %1 7 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD7    Filter bits
: CAN1_F25DATA0_FD8   %1 8 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD8    Filter bits
: CAN1_F25DATA0_FD9   %1 9 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD9    Filter bits
: CAN1_F25DATA0_FD10   %1 10 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD10    Filter bits
: CAN1_F25DATA0_FD11   %1 11 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD11    Filter bits
: CAN1_F25DATA0_FD12   %1 12 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD12    Filter bits
: CAN1_F25DATA0_FD13   %1 13 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD13    Filter bits
: CAN1_F25DATA0_FD14   %1 14 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD14    Filter bits
: CAN1_F25DATA0_FD15   %1 15 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD15    Filter bits
: CAN1_F25DATA0_FD16   %1 16 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD16    Filter bits
: CAN1_F25DATA0_FD17   %1 17 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD17    Filter bits
: CAN1_F25DATA0_FD18   %1 18 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD18    Filter bits
: CAN1_F25DATA0_FD19   %1 19 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD19    Filter bits
: CAN1_F25DATA0_FD20   %1 20 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD20    Filter bits
: CAN1_F25DATA0_FD21   %1 21 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD21    Filter bits
: CAN1_F25DATA0_FD22   %1 22 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD22    Filter bits
: CAN1_F25DATA0_FD23   %1 23 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD23    Filter bits
: CAN1_F25DATA0_FD24   %1 24 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD24    Filter bits
: CAN1_F25DATA0_FD25   %1 25 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD25    Filter bits
: CAN1_F25DATA0_FD26   %1 26 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD26    Filter bits
: CAN1_F25DATA0_FD27   %1 27 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD27    Filter bits
: CAN1_F25DATA0_FD28   %1 28 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD28    Filter bits
: CAN1_F25DATA0_FD29   %1 29 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD29    Filter bits
: CAN1_F25DATA0_FD30   %1 30 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD30    Filter bits
: CAN1_F25DATA0_FD31   %1 31 lshift CAN1_F25DATA0 bis! ;  \ CAN1_F25DATA0_FD31    Filter bits

\ CAN1_F25DATA1 (read-write)
: CAN1_F25DATA1_FD0   %1 0 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD0    Filter bits
: CAN1_F25DATA1_FD1   %1 1 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD1    Filter bits
: CAN1_F25DATA1_FD2   %1 2 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD2    Filter bits
: CAN1_F25DATA1_FD3   %1 3 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD3    Filter bits
: CAN1_F25DATA1_FD4   %1 4 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD4    Filter bits
: CAN1_F25DATA1_FD5   %1 5 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD5    Filter bits
: CAN1_F25DATA1_FD6   %1 6 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD6    Filter bits
: CAN1_F25DATA1_FD7   %1 7 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD7    Filter bits
: CAN1_F25DATA1_FD8   %1 8 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD8    Filter bits
: CAN1_F25DATA1_FD9   %1 9 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD9    Filter bits
: CAN1_F25DATA1_FD10   %1 10 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD10    Filter bits
: CAN1_F25DATA1_FD11   %1 11 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD11    Filter bits
: CAN1_F25DATA1_FD12   %1 12 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD12    Filter bits
: CAN1_F25DATA1_FD13   %1 13 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD13    Filter bits
: CAN1_F25DATA1_FD14   %1 14 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD14    Filter bits
: CAN1_F25DATA1_FD15   %1 15 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD15    Filter bits
: CAN1_F25DATA1_FD16   %1 16 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD16    Filter bits
: CAN1_F25DATA1_FD17   %1 17 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD17    Filter bits
: CAN1_F25DATA1_FD18   %1 18 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD18    Filter bits
: CAN1_F25DATA1_FD19   %1 19 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD19    Filter bits
: CAN1_F25DATA1_FD20   %1 20 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD20    Filter bits
: CAN1_F25DATA1_FD21   %1 21 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD21    Filter bits
: CAN1_F25DATA1_FD22   %1 22 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD22    Filter bits
: CAN1_F25DATA1_FD23   %1 23 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD23    Filter bits
: CAN1_F25DATA1_FD24   %1 24 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD24    Filter bits
: CAN1_F25DATA1_FD25   %1 25 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD25    Filter bits
: CAN1_F25DATA1_FD26   %1 26 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD26    Filter bits
: CAN1_F25DATA1_FD27   %1 27 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD27    Filter bits
: CAN1_F25DATA1_FD28   %1 28 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD28    Filter bits
: CAN1_F25DATA1_FD29   %1 29 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD29    Filter bits
: CAN1_F25DATA1_FD30   %1 30 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD30    Filter bits
: CAN1_F25DATA1_FD31   %1 31 lshift CAN1_F25DATA1 bis! ;  \ CAN1_F25DATA1_FD31    Filter bits

\ CAN1_F26DATA0 (read-write)
: CAN1_F26DATA0_FD0   %1 0 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD0    Filter bits
: CAN1_F26DATA0_FD1   %1 1 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD1    Filter bits
: CAN1_F26DATA0_FD2   %1 2 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD2    Filter bits
: CAN1_F26DATA0_FD3   %1 3 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD3    Filter bits
: CAN1_F26DATA0_FD4   %1 4 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD4    Filter bits
: CAN1_F26DATA0_FD5   %1 5 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD5    Filter bits
: CAN1_F26DATA0_FD6   %1 6 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD6    Filter bits
: CAN1_F26DATA0_FD7   %1 7 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD7    Filter bits
: CAN1_F26DATA0_FD8   %1 8 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD8    Filter bits
: CAN1_F26DATA0_FD9   %1 9 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD9    Filter bits
: CAN1_F26DATA0_FD10   %1 10 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD10    Filter bits
: CAN1_F26DATA0_FD11   %1 11 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD11    Filter bits
: CAN1_F26DATA0_FD12   %1 12 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD12    Filter bits
: CAN1_F26DATA0_FD13   %1 13 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD13    Filter bits
: CAN1_F26DATA0_FD14   %1 14 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD14    Filter bits
: CAN1_F26DATA0_FD15   %1 15 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD15    Filter bits
: CAN1_F26DATA0_FD16   %1 16 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD16    Filter bits
: CAN1_F26DATA0_FD17   %1 17 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD17    Filter bits
: CAN1_F26DATA0_FD18   %1 18 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD18    Filter bits
: CAN1_F26DATA0_FD19   %1 19 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD19    Filter bits
: CAN1_F26DATA0_FD20   %1 20 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD20    Filter bits
: CAN1_F26DATA0_FD21   %1 21 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD21    Filter bits
: CAN1_F26DATA0_FD22   %1 22 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD22    Filter bits
: CAN1_F26DATA0_FD23   %1 23 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD23    Filter bits
: CAN1_F26DATA0_FD24   %1 24 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD24    Filter bits
: CAN1_F26DATA0_FD25   %1 25 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD25    Filter bits
: CAN1_F26DATA0_FD26   %1 26 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD26    Filter bits
: CAN1_F26DATA0_FD27   %1 27 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD27    Filter bits
: CAN1_F26DATA0_FD28   %1 28 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD28    Filter bits
: CAN1_F26DATA0_FD29   %1 29 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD29    Filter bits
: CAN1_F26DATA0_FD30   %1 30 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD30    Filter bits
: CAN1_F26DATA0_FD31   %1 31 lshift CAN1_F26DATA0 bis! ;  \ CAN1_F26DATA0_FD31    Filter bits

\ CAN1_F26DATA1 (read-write)
: CAN1_F26DATA1_FD0   %1 0 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD0    Filter bits
: CAN1_F26DATA1_FD1   %1 1 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD1    Filter bits
: CAN1_F26DATA1_FD2   %1 2 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD2    Filter bits
: CAN1_F26DATA1_FD3   %1 3 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD3    Filter bits
: CAN1_F26DATA1_FD4   %1 4 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD4    Filter bits
: CAN1_F26DATA1_FD5   %1 5 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD5    Filter bits
: CAN1_F26DATA1_FD6   %1 6 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD6    Filter bits
: CAN1_F26DATA1_FD7   %1 7 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD7    Filter bits
: CAN1_F26DATA1_FD8   %1 8 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD8    Filter bits
: CAN1_F26DATA1_FD9   %1 9 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD9    Filter bits
: CAN1_F26DATA1_FD10   %1 10 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD10    Filter bits
: CAN1_F26DATA1_FD11   %1 11 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD11    Filter bits
: CAN1_F26DATA1_FD12   %1 12 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD12    Filter bits
: CAN1_F26DATA1_FD13   %1 13 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD13    Filter bits
: CAN1_F26DATA1_FD14   %1 14 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD14    Filter bits
: CAN1_F26DATA1_FD15   %1 15 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD15    Filter bits
: CAN1_F26DATA1_FD16   %1 16 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD16    Filter bits
: CAN1_F26DATA1_FD17   %1 17 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD17    Filter bits
: CAN1_F26DATA1_FD18   %1 18 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD18    Filter bits
: CAN1_F26DATA1_FD19   %1 19 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD19    Filter bits
: CAN1_F26DATA1_FD20   %1 20 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD20    Filter bits
: CAN1_F26DATA1_FD21   %1 21 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD21    Filter bits
: CAN1_F26DATA1_FD22   %1 22 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD22    Filter bits
: CAN1_F26DATA1_FD23   %1 23 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD23    Filter bits
: CAN1_F26DATA1_FD24   %1 24 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD24    Filter bits
: CAN1_F26DATA1_FD25   %1 25 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD25    Filter bits
: CAN1_F26DATA1_FD26   %1 26 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD26    Filter bits
: CAN1_F26DATA1_FD27   %1 27 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD27    Filter bits
: CAN1_F26DATA1_FD28   %1 28 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD28    Filter bits
: CAN1_F26DATA1_FD29   %1 29 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD29    Filter bits
: CAN1_F26DATA1_FD30   %1 30 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD30    Filter bits
: CAN1_F26DATA1_FD31   %1 31 lshift CAN1_F26DATA1 bis! ;  \ CAN1_F26DATA1_FD31    Filter bits

\ CAN1_F27DATA0 (read-write)
: CAN1_F27DATA0_FD0   %1 0 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD0    Filter bits
: CAN1_F27DATA0_FD1   %1 1 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD1    Filter bits
: CAN1_F27DATA0_FD2   %1 2 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD2    Filter bits
: CAN1_F27DATA0_FD3   %1 3 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD3    Filter bits
: CAN1_F27DATA0_FD4   %1 4 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD4    Filter bits
: CAN1_F27DATA0_FD5   %1 5 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD5    Filter bits
: CAN1_F27DATA0_FD6   %1 6 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD6    Filter bits
: CAN1_F27DATA0_FD7   %1 7 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD7    Filter bits
: CAN1_F27DATA0_FD8   %1 8 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD8    Filter bits
: CAN1_F27DATA0_FD9   %1 9 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD9    Filter bits
: CAN1_F27DATA0_FD10   %1 10 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD10    Filter bits
: CAN1_F27DATA0_FD11   %1 11 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD11    Filter bits
: CAN1_F27DATA0_FD12   %1 12 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD12    Filter bits
: CAN1_F27DATA0_FD13   %1 13 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD13    Filter bits
: CAN1_F27DATA0_FD14   %1 14 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD14    Filter bits
: CAN1_F27DATA0_FD15   %1 15 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD15    Filter bits
: CAN1_F27DATA0_FD16   %1 16 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD16    Filter bits
: CAN1_F27DATA0_FD17   %1 17 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD17    Filter bits
: CAN1_F27DATA0_FD18   %1 18 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD18    Filter bits
: CAN1_F27DATA0_FD19   %1 19 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD19    Filter bits
: CAN1_F27DATA0_FD20   %1 20 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD20    Filter bits
: CAN1_F27DATA0_FD21   %1 21 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD21    Filter bits
: CAN1_F27DATA0_FD22   %1 22 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD22    Filter bits
: CAN1_F27DATA0_FD23   %1 23 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD23    Filter bits
: CAN1_F27DATA0_FD24   %1 24 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD24    Filter bits
: CAN1_F27DATA0_FD25   %1 25 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD25    Filter bits
: CAN1_F27DATA0_FD26   %1 26 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD26    Filter bits
: CAN1_F27DATA0_FD27   %1 27 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD27    Filter bits
: CAN1_F27DATA0_FD28   %1 28 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD28    Filter bits
: CAN1_F27DATA0_FD29   %1 29 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD29    Filter bits
: CAN1_F27DATA0_FD30   %1 30 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD30    Filter bits
: CAN1_F27DATA0_FD31   %1 31 lshift CAN1_F27DATA0 bis! ;  \ CAN1_F27DATA0_FD31    Filter bits

\ CAN1_F27DATA1 (read-write)
: CAN1_F27DATA1_FD0   %1 0 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD0    Filter bits
: CAN1_F27DATA1_FD1   %1 1 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD1    Filter bits
: CAN1_F27DATA1_FD2   %1 2 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD2    Filter bits
: CAN1_F27DATA1_FD3   %1 3 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD3    Filter bits
: CAN1_F27DATA1_FD4   %1 4 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD4    Filter bits
: CAN1_F27DATA1_FD5   %1 5 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD5    Filter bits
: CAN1_F27DATA1_FD6   %1 6 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD6    Filter bits
: CAN1_F27DATA1_FD7   %1 7 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD7    Filter bits
: CAN1_F27DATA1_FD8   %1 8 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD8    Filter bits
: CAN1_F27DATA1_FD9   %1 9 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD9    Filter bits
: CAN1_F27DATA1_FD10   %1 10 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD10    Filter bits
: CAN1_F27DATA1_FD11   %1 11 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD11    Filter bits
: CAN1_F27DATA1_FD12   %1 12 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD12    Filter bits
: CAN1_F27DATA1_FD13   %1 13 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD13    Filter bits
: CAN1_F27DATA1_FD14   %1 14 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD14    Filter bits
: CAN1_F27DATA1_FD15   %1 15 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD15    Filter bits
: CAN1_F27DATA1_FD16   %1 16 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD16    Filter bits
: CAN1_F27DATA1_FD17   %1 17 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD17    Filter bits
: CAN1_F27DATA1_FD18   %1 18 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD18    Filter bits
: CAN1_F27DATA1_FD19   %1 19 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD19    Filter bits
: CAN1_F27DATA1_FD20   %1 20 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD20    Filter bits
: CAN1_F27DATA1_FD21   %1 21 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD21    Filter bits
: CAN1_F27DATA1_FD22   %1 22 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD22    Filter bits
: CAN1_F27DATA1_FD23   %1 23 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD23    Filter bits
: CAN1_F27DATA1_FD24   %1 24 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD24    Filter bits
: CAN1_F27DATA1_FD25   %1 25 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD25    Filter bits
: CAN1_F27DATA1_FD26   %1 26 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD26    Filter bits
: CAN1_F27DATA1_FD27   %1 27 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD27    Filter bits
: CAN1_F27DATA1_FD28   %1 28 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD28    Filter bits
: CAN1_F27DATA1_FD29   %1 29 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD29    Filter bits
: CAN1_F27DATA1_FD30   %1 30 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD30    Filter bits
: CAN1_F27DATA1_FD31   %1 31 lshift CAN1_F27DATA1 bis! ;  \ CAN1_F27DATA1_FD31    Filter bits

\ CRC_DATA (read-write)
: CRC_DATA_DATA   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift CRC_DATA bis! ;  \ CRC_DATA_DATA    CRC calculation result bits

\ CRC_FDATA (read-write)
: CRC_FDATA_FDATA   ( %XXXXXXXX -- ) 0 lshift CRC_FDATA bis! ;  \ CRC_FDATA_FDATA    Free Data Register bits

\ CRC_CTL (read-write)
: CRC_CTL_RST   %1 0 lshift CRC_CTL bis! ;  \ CRC_CTL_RST    reset bit

\ DAC_CTL (read-write)
: DAC_CTL_DEN0   %1 0 lshift DAC_CTL bis! ;  \ DAC_CTL_DEN0    DAC0 enable
: DAC_CTL_DBOFF0   %1 1 lshift DAC_CTL bis! ;  \ DAC_CTL_DBOFF0    DAC0 output buffer turn off
: DAC_CTL_DTEN0   %1 2 lshift DAC_CTL bis! ;  \ DAC_CTL_DTEN0    DAC0 trigger enable
: DAC_CTL_DTSEL0   ( %XXX -- ) 3 lshift DAC_CTL bis! ;  \ DAC_CTL_DTSEL0    DAC0 trigger selection
: DAC_CTL_DWM0   ( %XX -- ) 6 lshift DAC_CTL bis! ;  \ DAC_CTL_DWM0    DAC0 noise wave mode
: DAC_CTL_DWBW0   ( %XXXX -- ) 8 lshift DAC_CTL bis! ;  \ DAC_CTL_DWBW0    DAC0 noise wave bit width
: DAC_CTL_DDMAEN0   %1 12 lshift DAC_CTL bis! ;  \ DAC_CTL_DDMAEN0    DAC0 DMA enable
: DAC_CTL_DEN1   %1 16 lshift DAC_CTL bis! ;  \ DAC_CTL_DEN1    DAC1 enable
: DAC_CTL_DBOFF1   %1 17 lshift DAC_CTL bis! ;  \ DAC_CTL_DBOFF1    DAC1 output buffer turn off
: DAC_CTL_DTEN1   %1 18 lshift DAC_CTL bis! ;  \ DAC_CTL_DTEN1    DAC1 trigger enable
: DAC_CTL_DTSEL1   ( %XXX -- ) 19 lshift DAC_CTL bis! ;  \ DAC_CTL_DTSEL1    DAC1 trigger selection
: DAC_CTL_DWM1   ( %XX -- ) 22 lshift DAC_CTL bis! ;  \ DAC_CTL_DWM1    DAC1 noise wave mode
: DAC_CTL_DWBW1   ( %XXXX -- ) 24 lshift DAC_CTL bis! ;  \ DAC_CTL_DWBW1    DAC1 noise wave bit width
: DAC_CTL_DDMAEN1   %1 28 lshift DAC_CTL bis! ;  \ DAC_CTL_DDMAEN1    DAC1 DMA enable

\ DAC_SWT (write-only)
: DAC_SWT_SWTR0   %1 0 lshift DAC_SWT bis! ;  \ DAC_SWT_SWTR0    DAC0 software trigger
: DAC_SWT_SWTR1   %1 1 lshift DAC_SWT bis! ;  \ DAC_SWT_SWTR1    DAC1 software trigger

\ DAC_DAC0_R12DH (read-write)
: DAC_DAC0_R12DH_DAC0_DH   ( %XXXXXXXXXXX -- ) 0 lshift DAC_DAC0_R12DH bis! ;  \ DAC_DAC0_R12DH_DAC0_DH    DAC0 12-bit right-aligned  data

\ DAC_DAC0_L12DH (read-write)
: DAC_DAC0_L12DH_DAC0_DH   ( %XXXXXXXXXXX -- ) 4 lshift DAC_DAC0_L12DH bis! ;  \ DAC_DAC0_L12DH_DAC0_DH    DAC0 12-bit left-aligned  data

\ DAC_DAC0_R8DH (read-write)
: DAC_DAC0_R8DH_DAC0_DH   ( %XXXXXXXX -- ) 0 lshift DAC_DAC0_R8DH bis! ;  \ DAC_DAC0_R8DH_DAC0_DH    DAC0 8-bit right-aligned  data

\ DAC_DAC1_R12DH (read-write)
: DAC_DAC1_R12DH_DAC1_DH   ( %XXXXXXXXXXX -- ) 0 lshift DAC_DAC1_R12DH bis! ;  \ DAC_DAC1_R12DH_DAC1_DH    DAC1 12-bit right-aligned  data

\ DAC_DAC1_L12DH (read-write)
: DAC_DAC1_L12DH_DAC1_DH   ( %XXXXXXXXXXX -- ) 4 lshift DAC_DAC1_L12DH bis! ;  \ DAC_DAC1_L12DH_DAC1_DH    DAC1 12-bit left-aligned  data

\ DAC_DAC1_R8DH (read-write)
: DAC_DAC1_R8DH_DAC1_DH   ( %XXXXXXXX -- ) 0 lshift DAC_DAC1_R8DH bis! ;  \ DAC_DAC1_R8DH_DAC1_DH    DAC1 8-bit right-aligned  data

\ DAC_DACC_R12DH (read-write)
: DAC_DACC_R12DH_DAC0_DH   ( %XXXXXXXXXXX -- ) 0 lshift DAC_DACC_R12DH bis! ;  \ DAC_DACC_R12DH_DAC0_DH    DAC0 12-bit right-aligned  data
: DAC_DACC_R12DH_DAC1_DH   ( %XXXXXXXXXXX -- ) 16 lshift DAC_DACC_R12DH bis! ;  \ DAC_DACC_R12DH_DAC1_DH    DAC1 12-bit right-aligned  data

\ DAC_DACC_L12DH (read-write)
: DAC_DACC_L12DH_DAC0_DH   ( %XXXXXXXXXXX -- ) 4 lshift DAC_DACC_L12DH bis! ;  \ DAC_DACC_L12DH_DAC0_DH    DAC0 12-bit left-aligned  data
: DAC_DACC_L12DH_DAC1_DH   ( %XXXXXXXXXXX -- ) 20 lshift DAC_DACC_L12DH bis! ;  \ DAC_DACC_L12DH_DAC1_DH    DAC1 12-bit left-aligned  data

\ DAC_DACC_R8DH (read-write)
: DAC_DACC_R8DH_DAC0_DH   ( %XXXXXXXX -- ) 0 lshift DAC_DACC_R8DH bis! ;  \ DAC_DACC_R8DH_DAC0_DH    DAC0 8-bit right-aligned  data
: DAC_DACC_R8DH_DAC1_DH   ( %XXXXXXXX -- ) 8 lshift DAC_DACC_R8DH bis! ;  \ DAC_DACC_R8DH_DAC1_DH    DAC1 8-bit right-aligned  data

\ DAC_DAC0_DO (read-only)
: DAC_DAC0_DO_DAC0_DO   ( %XXXXXXXXXXX -- ) 0 lshift DAC_DAC0_DO bis! ;  \ DAC_DAC0_DO_DAC0_DO    DAC0 data output

\ DAC_DAC1_DO (read-only)
: DAC_DAC1_DO_DAC1_DO   ( %XXXXXXXXXXX -- ) 0 lshift DAC_DAC1_DO bis! ;  \ DAC_DAC1_DO_DAC1_DO    DAC1 data output

\ DBG_ID (read-only)
: DBG_ID_ID_CODE   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DBG_ID bis! ;  \ DBG_ID_ID_CODE    DBG ID code register

\ DBG_CTL (read-write)
: DBG_CTL_SLP_HOLD   %1 0 lshift DBG_CTL bis! ;  \ DBG_CTL_SLP_HOLD    Sleep mode hold register
: DBG_CTL_DSLP_HOLD   %1 1 lshift DBG_CTL bis! ;  \ DBG_CTL_DSLP_HOLD    Deep-sleep mode hold register
: DBG_CTL_STB_HOLD   %1 2 lshift DBG_CTL bis! ;  \ DBG_CTL_STB_HOLD    Standby mode hold register
: DBG_CTL_FWDGT_HOLD   %1 8 lshift DBG_CTL bis! ;  \ DBG_CTL_FWDGT_HOLD    FWDGT hold bit
: DBG_CTL_WWDGT_HOLD   %1 9 lshift DBG_CTL bis! ;  \ DBG_CTL_WWDGT_HOLD    WWDGT hold bit
: DBG_CTL_TIMER0_HOLD   %1 10 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER0_HOLD    TIMER 0 hold bit
: DBG_CTL_TIMER1_HOLD   %1 11 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER1_HOLD    TIMER 1 hold bit
: DBG_CTL_TIMER2_HOLD   %1 12 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER2_HOLD    TIMER 2 hold bit
: DBG_CTL_TIMER3_HOLD   %1 13 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER3_HOLD    TIMER 23 hold bit
: DBG_CTL_CAN0_HOLD   %1 14 lshift DBG_CTL bis! ;  \ DBG_CTL_CAN0_HOLD    CAN0 hold bit
: DBG_CTL_I2C0_HOLD   %1 15 lshift DBG_CTL bis! ;  \ DBG_CTL_I2C0_HOLD    I2C0 hold bit
: DBG_CTL_I2C1_HOLD   %1 16 lshift DBG_CTL bis! ;  \ DBG_CTL_I2C1_HOLD    I2C1 hold bit
: DBG_CTL_TIMER4_HOLD   %1 18 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER4_HOLD    TIMER4_HOLD
: DBG_CTL_TIMER5_HOLD   %1 19 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER5_HOLD    TIMER 5 hold bit
: DBG_CTL_TIMER6_HOLD   %1 20 lshift DBG_CTL bis! ;  \ DBG_CTL_TIMER6_HOLD    TIMER 6 hold bit
: DBG_CTL_CAN1_HOLD   %1 21 lshift DBG_CTL bis! ;  \ DBG_CTL_CAN1_HOLD    CAN1 hold bit

\ DMA0_INTF (read-only)
: DMA0_INTF_GIF0   %1 0 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF0    Global interrupt flag of channel 0
: DMA0_INTF_FTFIF0   %1 1 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF0    Full Transfer finish flag of channe 0
: DMA0_INTF_HTFIF0   %1 2 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF0    Half transfer finish flag of channel 0
: DMA0_INTF_ERRIF0   %1 3 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF0    Error flag of channel 0
: DMA0_INTF_GIF1   %1 4 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF1    Global interrupt flag of channel 1
: DMA0_INTF_FTFIF1   %1 5 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF1    Full Transfer finish flag of channe 1
: DMA0_INTF_HTFIF1   %1 6 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF1    Half transfer finish flag of channel 1
: DMA0_INTF_ERRIF1   %1 7 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF1    Error flag of channel 1
: DMA0_INTF_GIF2   %1 8 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF2    Global interrupt flag of channel 2
: DMA0_INTF_FTFIF2   %1 9 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF2    Full Transfer finish flag of channe 2
: DMA0_INTF_HTFIF2   %1 10 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF2    Half transfer finish flag of channel 2
: DMA0_INTF_ERRIF2   %1 11 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF2    Error flag of channel 2
: DMA0_INTF_GIF3   %1 12 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF3    Global interrupt flag of channel 3
: DMA0_INTF_FTFIF3   %1 13 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF3    Full Transfer finish flag of channe 3
: DMA0_INTF_HTFIF3   %1 14 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF3    Half transfer finish flag of channel 3
: DMA0_INTF_ERRIF3   %1 15 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF3    Error flag of channel 3
: DMA0_INTF_GIF4   %1 16 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF4    Global interrupt flag of channel 4
: DMA0_INTF_FTFIF4   %1 17 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF4    Full Transfer finish flag of channe 4
: DMA0_INTF_HTFIF4   %1 18 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF4    Half transfer finish flag of channel 4
: DMA0_INTF_ERRIF4   %1 19 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF4    Error flag of channel 4
: DMA0_INTF_GIF5   %1 20 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF5    Global interrupt flag of channel 5
: DMA0_INTF_FTFIF5   %1 21 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF5    Full Transfer finish flag of channe 5
: DMA0_INTF_HTFIF5   %1 22 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF5    Half transfer finish flag of channel 5
: DMA0_INTF_ERRIF5   %1 23 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF5    Error flag of channel 5
: DMA0_INTF_GIF6   %1 24 lshift DMA0_INTF bis! ;  \ DMA0_INTF_GIF6    Global interrupt flag of channel 6
: DMA0_INTF_FTFIF6   %1 25 lshift DMA0_INTF bis! ;  \ DMA0_INTF_FTFIF6    Full Transfer finish flag of channe 6
: DMA0_INTF_HTFIF6   %1 26 lshift DMA0_INTF bis! ;  \ DMA0_INTF_HTFIF6    Half transfer finish flag of channel 6
: DMA0_INTF_ERRIF6   %1 27 lshift DMA0_INTF bis! ;  \ DMA0_INTF_ERRIF6    Error flag of channel 6

\ DMA0_INTC (write-only)
: DMA0_INTC_GIFC0   %1 0 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC0    Clear global interrupt flag of channel 0
: DMA0_INTC_FTFIFC0   %1 1 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC0    Clear bit for full transfer finish flag of channel 0
: DMA0_INTC_HTFIFC0   %1 2 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC0    Clear bit for half transfer finish flag of channel 0
: DMA0_INTC_ERRIFC0   %1 3 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC0    Clear bit for error flag of channel 0
: DMA0_INTC_GIFC1   %1 4 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC1    Clear global interrupt flag of channel 1
: DMA0_INTC_FTFIFC1   %1 5 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC1    Clear bit for full transfer finish flag of channel 1
: DMA0_INTC_HTFIFC1   %1 6 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC1    Clear bit for half transfer finish flag of channel 1
: DMA0_INTC_ERRIFC1   %1 7 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC1    Clear bit for error flag of channel 1
: DMA0_INTC_GIFC2   %1 8 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC2    Clear global interrupt flag of channel 2
: DMA0_INTC_FTFIFC2   %1 9 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC2    Clear bit for full transfer finish flag of channel 2
: DMA0_INTC_HTFIFC2   %1 10 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC2    Clear bit for half transfer finish flag of channel 2
: DMA0_INTC_ERRIFC2   %1 11 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC2    Clear bit for error flag of channel 2
: DMA0_INTC_GIFC3   %1 12 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC3    Clear global interrupt flag of channel 3
: DMA0_INTC_FTFIFC3   %1 13 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC3    Clear bit for full transfer finish flag of channel 3
: DMA0_INTC_HTFIFC3   %1 14 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC3    Clear bit for half transfer finish flag of channel 3
: DMA0_INTC_ERRIFC3   %1 15 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC3    Clear bit for error flag of channel 3
: DMA0_INTC_GIFC4   %1 16 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC4    Clear global interrupt flag of channel 4
: DMA0_INTC_FTFIFC4   %1 17 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC4    Clear bit for full transfer finish flag of channel 4
: DMA0_INTC_HTFIFC4   %1 18 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC4    Clear bit for half transfer finish flag of channel 4
: DMA0_INTC_ERRIFC4   %1 19 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC4    Clear bit for error flag of channel 4
: DMA0_INTC_GIFC5   %1 20 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC5    Clear global interrupt flag of channel 5
: DMA0_INTC_FTFIFC5   %1 21 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC5    Clear bit for full transfer finish flag of channel 5
: DMA0_INTC_HTFIFC5   %1 22 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC5    Clear bit for half transfer finish flag of channel 5
: DMA0_INTC_ERRIFC5   %1 23 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC5    Clear bit for error flag of channel 5
: DMA0_INTC_GIFC6   %1 24 lshift DMA0_INTC bis! ;  \ DMA0_INTC_GIFC6    Clear global interrupt flag of channel 6
: DMA0_INTC_FTFIFC6   %1 25 lshift DMA0_INTC bis! ;  \ DMA0_INTC_FTFIFC6    Clear bit for full transfer finish flag of channel 6
: DMA0_INTC_HTFIFC6   %1 26 lshift DMA0_INTC bis! ;  \ DMA0_INTC_HTFIFC6    Clear bit for half transfer finish flag of channel 6
: DMA0_INTC_ERRIFC6   %1 27 lshift DMA0_INTC bis! ;  \ DMA0_INTC_ERRIFC6    Clear bit for error flag of channel 6

\ DMA0_CH0CTL (read-write)
: DMA0_CH0CTL_CHEN   %1 0 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_CHEN    Channel enable
: DMA0_CH0CTL_FTFIE   %1 1 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH0CTL_HTFIE   %1 2 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH0CTL_ERRIE   %1 3 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH0CTL_DIR   %1 4 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_DIR    Transfer direction
: DMA0_CH0CTL_CMEN   %1 5 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_CMEN    Circular mode enable
: DMA0_CH0CTL_PNAGA   %1 6 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH0CTL_MNAGA   %1 7 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH0CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH0CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_MWIDTH    Transfer data size of memory
: DMA0_CH0CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_PRIO    Priority level
: DMA0_CH0CTL_M2M   %1 14 lshift DMA0_CH0CTL bis! ;  \ DMA0_CH0CTL_M2M    Memory to Memory Mode

\ DMA0_CH0CNT (read-write)
: DMA0_CH0CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH0CNT bis! ;  \ DMA0_CH0CNT_CNT    Transfer counter

\ DMA0_CH0PADDR (read-write)
: DMA0_CH0PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH0PADDR bis! ;  \ DMA0_CH0PADDR_PADDR    Peripheral base address

\ DMA0_CH0MADDR (read-write)
: DMA0_CH0MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH0MADDR bis! ;  \ DMA0_CH0MADDR_MADDR    Memory base address

\ DMA0_CH1CTL (read-write)
: DMA0_CH1CTL_CHEN   %1 0 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_CHEN    Channel enable
: DMA0_CH1CTL_FTFIE   %1 1 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH1CTL_HTFIE   %1 2 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH1CTL_ERRIE   %1 3 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH1CTL_DIR   %1 4 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_DIR    Transfer direction
: DMA0_CH1CTL_CMEN   %1 5 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_CMEN    Circular mode enable
: DMA0_CH1CTL_PNAGA   %1 6 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH1CTL_MNAGA   %1 7 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH1CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH1CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_MWIDTH    Transfer data size of memory
: DMA0_CH1CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_PRIO    Priority level
: DMA0_CH1CTL_M2M   %1 14 lshift DMA0_CH1CTL bis! ;  \ DMA0_CH1CTL_M2M    Memory to Memory Mode

\ DMA0_CH1CNT (read-write)
: DMA0_CH1CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH1CNT bis! ;  \ DMA0_CH1CNT_CNT    Transfer counter

\ DMA0_CH1PADDR (read-write)
: DMA0_CH1PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH1PADDR bis! ;  \ DMA0_CH1PADDR_PADDR    Peripheral base address

\ DMA0_CH1MADDR (read-write)
: DMA0_CH1MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH1MADDR bis! ;  \ DMA0_CH1MADDR_MADDR    Memory base address

\ DMA0_CH2CTL (read-write)
: DMA0_CH2CTL_CHEN   %1 0 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_CHEN    Channel enable
: DMA0_CH2CTL_FTFIE   %1 1 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH2CTL_HTFIE   %1 2 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH2CTL_ERRIE   %1 3 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH2CTL_DIR   %1 4 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_DIR    Transfer direction
: DMA0_CH2CTL_CMEN   %1 5 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_CMEN    Circular mode enable
: DMA0_CH2CTL_PNAGA   %1 6 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH2CTL_MNAGA   %1 7 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH2CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH2CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_MWIDTH    Transfer data size of memory
: DMA0_CH2CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_PRIO    Priority level
: DMA0_CH2CTL_M2M   %1 14 lshift DMA0_CH2CTL bis! ;  \ DMA0_CH2CTL_M2M    Memory to Memory Mode

\ DMA0_CH2CNT (read-write)
: DMA0_CH2CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH2CNT bis! ;  \ DMA0_CH2CNT_CNT    Transfer counter

\ DMA0_CH2PADDR (read-write)
: DMA0_CH2PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH2PADDR bis! ;  \ DMA0_CH2PADDR_PADDR    Peripheral base address

\ DMA0_CH2MADDR (read-write)
: DMA0_CH2MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH2MADDR bis! ;  \ DMA0_CH2MADDR_MADDR    Memory base address

\ DMA0_CH3CTL (read-write)
: DMA0_CH3CTL_CHEN   %1 0 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_CHEN    Channel enable
: DMA0_CH3CTL_FTFIE   %1 1 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH3CTL_HTFIE   %1 2 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH3CTL_ERRIE   %1 3 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH3CTL_DIR   %1 4 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_DIR    Transfer direction
: DMA0_CH3CTL_CMEN   %1 5 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_CMEN    Circular mode enable
: DMA0_CH3CTL_PNAGA   %1 6 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH3CTL_MNAGA   %1 7 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH3CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH3CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_MWIDTH    Transfer data size of memory
: DMA0_CH3CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_PRIO    Priority level
: DMA0_CH3CTL_M2M   %1 14 lshift DMA0_CH3CTL bis! ;  \ DMA0_CH3CTL_M2M    Memory to Memory Mode

\ DMA0_CH3CNT (read-write)
: DMA0_CH3CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH3CNT bis! ;  \ DMA0_CH3CNT_CNT    Transfer counter

\ DMA0_CH3PADDR (read-write)
: DMA0_CH3PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH3PADDR bis! ;  \ DMA0_CH3PADDR_PADDR    Peripheral base address

\ DMA0_CH3MADDR (read-write)
: DMA0_CH3MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH3MADDR bis! ;  \ DMA0_CH3MADDR_MADDR    Memory base address

\ DMA0_CH4CTL (read-write)
: DMA0_CH4CTL_CHEN   %1 0 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_CHEN    Channel enable
: DMA0_CH4CTL_FTFIE   %1 1 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH4CTL_HTFIE   %1 2 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH4CTL_ERRIE   %1 3 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH4CTL_DIR   %1 4 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_DIR    Transfer direction
: DMA0_CH4CTL_CMEN   %1 5 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_CMEN    Circular mode enable
: DMA0_CH4CTL_PNAGA   %1 6 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH4CTL_MNAGA   %1 7 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH4CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH4CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_MWIDTH    Transfer data size of memory
: DMA0_CH4CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_PRIO    Priority level
: DMA0_CH4CTL_M2M   %1 14 lshift DMA0_CH4CTL bis! ;  \ DMA0_CH4CTL_M2M    Memory to Memory Mode

\ DMA0_CH4CNT (read-write)
: DMA0_CH4CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH4CNT bis! ;  \ DMA0_CH4CNT_CNT    Transfer counter

\ DMA0_CH4PADDR (read-write)
: DMA0_CH4PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH4PADDR bis! ;  \ DMA0_CH4PADDR_PADDR    Peripheral base address

\ DMA0_CH4MADDR (read-write)
: DMA0_CH4MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH4MADDR bis! ;  \ DMA0_CH4MADDR_MADDR    Memory base address

\ DMA0_CH5CTL (read-write)
: DMA0_CH5CTL_CHEN   %1 0 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_CHEN    Channel enable
: DMA0_CH5CTL_FTFIE   %1 1 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH5CTL_HTFIE   %1 2 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH5CTL_ERRIE   %1 3 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH5CTL_DIR   %1 4 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_DIR    Transfer direction
: DMA0_CH5CTL_CMEN   %1 5 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_CMEN    Circular mode enable
: DMA0_CH5CTL_PNAGA   %1 6 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH5CTL_MNAGA   %1 7 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH5CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH5CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_MWIDTH    Transfer data size of memory
: DMA0_CH5CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_PRIO    Priority level
: DMA0_CH5CTL_M2M   %1 14 lshift DMA0_CH5CTL bis! ;  \ DMA0_CH5CTL_M2M    Memory to Memory Mode

\ DMA0_CH5CNT (read-write)
: DMA0_CH5CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH5CNT bis! ;  \ DMA0_CH5CNT_CNT    Transfer counter

\ DMA0_CH5PADDR (read-write)
: DMA0_CH5PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH5PADDR bis! ;  \ DMA0_CH5PADDR_PADDR    Peripheral base address

\ DMA0_CH5MADDR (read-write)
: DMA0_CH5MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH5MADDR bis! ;  \ DMA0_CH5MADDR_MADDR    Memory base address

\ DMA0_CH6CTL (read-write)
: DMA0_CH6CTL_CHEN   %1 0 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_CHEN    Channel enable
: DMA0_CH6CTL_FTFIE   %1 1 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA0_CH6CTL_HTFIE   %1 2 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA0_CH6CTL_ERRIE   %1 3 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_ERRIE    Enable bit for channel error interrupt
: DMA0_CH6CTL_DIR   %1 4 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_DIR    Transfer direction
: DMA0_CH6CTL_CMEN   %1 5 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_CMEN    Circular mode enable
: DMA0_CH6CTL_PNAGA   %1 6 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_PNAGA    Next address generation algorithm of peripheral
: DMA0_CH6CTL_MNAGA   %1 7 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_MNAGA    Next address generation algorithm of memory
: DMA0_CH6CTL_PWIDTH   ( %XX -- ) 8 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_PWIDTH    Transfer data size of peripheral
: DMA0_CH6CTL_MWIDTH   ( %XX -- ) 10 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_MWIDTH    Transfer data size of memory
: DMA0_CH6CTL_PRIO   ( %XX -- ) 12 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_PRIO    Priority level
: DMA0_CH6CTL_M2M   %1 14 lshift DMA0_CH6CTL bis! ;  \ DMA0_CH6CTL_M2M    Memory to Memory Mode

\ DMA0_CH6CNT (read-write)
: DMA0_CH6CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH6CNT bis! ;  \ DMA0_CH6CNT_CNT    Transfer counter

\ DMA0_CH6PADDR (read-write)
: DMA0_CH6PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH6PADDR bis! ;  \ DMA0_CH6PADDR_PADDR    Peripheral base address

\ DMA0_CH6MADDR (read-write)
: DMA0_CH6MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA0_CH6MADDR bis! ;  \ DMA0_CH6MADDR_MADDR    Memory base address

\ DMA1_INTF (read-only)
: DMA1_INTF_GIF0   %1 0 lshift DMA1_INTF bis! ;  \ DMA1_INTF_GIF0    Global interrupt flag of channel 0
: DMA1_INTF_FTFIF0   %1 1 lshift DMA1_INTF bis! ;  \ DMA1_INTF_FTFIF0    Full Transfer finish flag of channe 0
: DMA1_INTF_HTFIF0   %1 2 lshift DMA1_INTF bis! ;  \ DMA1_INTF_HTFIF0    Half transfer finish flag of channel 0
: DMA1_INTF_ERRIF0   %1 3 lshift DMA1_INTF bis! ;  \ DMA1_INTF_ERRIF0    Error flag of channel 0
: DMA1_INTF_GIF1   %1 4 lshift DMA1_INTF bis! ;  \ DMA1_INTF_GIF1    Global interrupt flag of channel 1
: DMA1_INTF_FTFIF1   %1 5 lshift DMA1_INTF bis! ;  \ DMA1_INTF_FTFIF1    Full Transfer finish flag of channe 1
: DMA1_INTF_HTFIF1   %1 6 lshift DMA1_INTF bis! ;  \ DMA1_INTF_HTFIF1    Half transfer finish flag of channel 1
: DMA1_INTF_ERRIF1   %1 7 lshift DMA1_INTF bis! ;  \ DMA1_INTF_ERRIF1    Error flag of channel 1
: DMA1_INTF_GIF2   %1 8 lshift DMA1_INTF bis! ;  \ DMA1_INTF_GIF2    Global interrupt flag of channel 2
: DMA1_INTF_FTFIF2   %1 9 lshift DMA1_INTF bis! ;  \ DMA1_INTF_FTFIF2    Full Transfer finish flag of channe 2
: DMA1_INTF_HTFIF2   %1 10 lshift DMA1_INTF bis! ;  \ DMA1_INTF_HTFIF2    Half transfer finish flag of channel 2
: DMA1_INTF_ERRIF2   %1 11 lshift DMA1_INTF bis! ;  \ DMA1_INTF_ERRIF2    Error flag of channel 2
: DMA1_INTF_GIF3   %1 12 lshift DMA1_INTF bis! ;  \ DMA1_INTF_GIF3    Global interrupt flag of channel 3
: DMA1_INTF_FTFIF3   %1 13 lshift DMA1_INTF bis! ;  \ DMA1_INTF_FTFIF3    Full Transfer finish flag of channe 3
: DMA1_INTF_HTFIF3   %1 14 lshift DMA1_INTF bis! ;  \ DMA1_INTF_HTFIF3    Half transfer finish flag of channel 3
: DMA1_INTF_ERRIF3   %1 15 lshift DMA1_INTF bis! ;  \ DMA1_INTF_ERRIF3    Error flag of channel 3
: DMA1_INTF_GIF4   %1 16 lshift DMA1_INTF bis! ;  \ DMA1_INTF_GIF4    Global interrupt flag of channel 4
: DMA1_INTF_FTFIF4   %1 17 lshift DMA1_INTF bis! ;  \ DMA1_INTF_FTFIF4    Full Transfer finish flag of channe 4
: DMA1_INTF_HTFIF4   %1 18 lshift DMA1_INTF bis! ;  \ DMA1_INTF_HTFIF4    Half transfer finish flag of channel 4
: DMA1_INTF_ERRIF4   %1 19 lshift DMA1_INTF bis! ;  \ DMA1_INTF_ERRIF4    Error flag of channel 4

\ DMA1_INTC (write-only)
: DMA1_INTC_GIFC0   %1 0 lshift DMA1_INTC bis! ;  \ DMA1_INTC_GIFC0    Clear global interrupt flag of channel 0
: DMA1_INTC_FTFIFC0   %1 1 lshift DMA1_INTC bis! ;  \ DMA1_INTC_FTFIFC0    Clear bit for full transfer finish flag of channel 0
: DMA1_INTC_HTFIFC0   %1 2 lshift DMA1_INTC bis! ;  \ DMA1_INTC_HTFIFC0    Clear bit for half transfer finish flag of channel 0
: DMA1_INTC_ERRIFC0   %1 3 lshift DMA1_INTC bis! ;  \ DMA1_INTC_ERRIFC0    Clear bit for error flag of channel 0
: DMA1_INTC_GIFC1   %1 4 lshift DMA1_INTC bis! ;  \ DMA1_INTC_GIFC1    Clear global interrupt flag of channel 1
: DMA1_INTC_FTFIFC1   %1 5 lshift DMA1_INTC bis! ;  \ DMA1_INTC_FTFIFC1    Clear bit for full transfer finish flag of channel 1
: DMA1_INTC_HTFIFC1   %1 6 lshift DMA1_INTC bis! ;  \ DMA1_INTC_HTFIFC1    Clear bit for half transfer finish flag of channel 1
: DMA1_INTC_ERRIFC1   %1 7 lshift DMA1_INTC bis! ;  \ DMA1_INTC_ERRIFC1    Clear bit for error flag of channel 1
: DMA1_INTC_GIFC2   %1 8 lshift DMA1_INTC bis! ;  \ DMA1_INTC_GIFC2    Clear global interrupt flag of channel 2
: DMA1_INTC_FTFIFC2   %1 9 lshift DMA1_INTC bis! ;  \ DMA1_INTC_FTFIFC2    Clear bit for full transfer finish flag of channel 2
: DMA1_INTC_HTFIFC2   %1 10 lshift DMA1_INTC bis! ;  \ DMA1_INTC_HTFIFC2    Clear bit for half transfer finish flag of channel 2
: DMA1_INTC_ERRIFC2   %1 11 lshift DMA1_INTC bis! ;  \ DMA1_INTC_ERRIFC2    Clear bit for error flag of channel 2
: DMA1_INTC_GIFC3   %1 12 lshift DMA1_INTC bis! ;  \ DMA1_INTC_GIFC3    Clear global interrupt flag of channel 3
: DMA1_INTC_FTFIFC3   %1 13 lshift DMA1_INTC bis! ;  \ DMA1_INTC_FTFIFC3    Clear bit for full transfer finish flag of channel 3
: DMA1_INTC_HTFIFC3   %1 14 lshift DMA1_INTC bis! ;  \ DMA1_INTC_HTFIFC3    Clear bit for half transfer finish flag of channel 3
: DMA1_INTC_ERRIFC3   %1 15 lshift DMA1_INTC bis! ;  \ DMA1_INTC_ERRIFC3    Clear bit for error flag of channel 3
: DMA1_INTC_GIFC4   %1 16 lshift DMA1_INTC bis! ;  \ DMA1_INTC_GIFC4    Clear global interrupt flag of channel 4
: DMA1_INTC_FTFIFC4   %1 17 lshift DMA1_INTC bis! ;  \ DMA1_INTC_FTFIFC4    Clear bit for full transfer finish flag of channel 4
: DMA1_INTC_HTFIFC4   %1 18 lshift DMA1_INTC bis! ;  \ DMA1_INTC_HTFIFC4    Clear bit for half transfer finish flag of channel 4
: DMA1_INTC_ERRIFC4   %1 19 lshift DMA1_INTC bis! ;  \ DMA1_INTC_ERRIFC4    Clear bit for error flag of channel 4

\ DMA1_CH0CTL (read-write)
: DMA1_CH0CTL_CHEN   %1 0 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_CHEN    Channel enable
: DMA1_CH0CTL_FTFIE   %1 1 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA1_CH0CTL_HTFIE   %1 2 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA1_CH0CTL_ERRIE   %1 3 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_ERRIE    Enable bit for channel error interrupt
: DMA1_CH0CTL_DIR   %1 4 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_DIR    Transfer direction
: DMA1_CH0CTL_CMEN   %1 5 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_CMEN    Circular mode enable
: DMA1_CH0CTL_PNAGA   %1 6 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_PNAGA    Next address generation algorithm of peripheral
: DMA1_CH0CTL_MNAGA   %1 7 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_MNAGA    Next address generation algorithm of memory
: DMA1_CH0CTL_PWIDTH   ( %XX -- ) 8 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_PWIDTH    Transfer data size of peripheral
: DMA1_CH0CTL_MWIDTH   ( %XX -- ) 10 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_MWIDTH    Transfer data size of memory
: DMA1_CH0CTL_PRIO   ( %XX -- ) 12 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_PRIO    Priority level
: DMA1_CH0CTL_M2M   %1 14 lshift DMA1_CH0CTL bis! ;  \ DMA1_CH0CTL_M2M    Memory to Memory Mode

\ DMA1_CH0CNT (read-write)
: DMA1_CH0CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH0CNT bis! ;  \ DMA1_CH0CNT_CNT    Transfer counter

\ DMA1_CH0PADDR (read-write)
: DMA1_CH0PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH0PADDR bis! ;  \ DMA1_CH0PADDR_PADDR    Peripheral base address

\ DMA1_CH0MADDR (read-write)
: DMA1_CH0MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH0MADDR bis! ;  \ DMA1_CH0MADDR_MADDR    Memory base address

\ DMA1_CH1CTL (read-write)
: DMA1_CH1CTL_CHEN   %1 0 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_CHEN    Channel enable
: DMA1_CH1CTL_FTFIE   %1 1 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA1_CH1CTL_HTFIE   %1 2 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA1_CH1CTL_ERRIE   %1 3 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_ERRIE    Enable bit for channel error interrupt
: DMA1_CH1CTL_DIR   %1 4 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_DIR    Transfer direction
: DMA1_CH1CTL_CMEN   %1 5 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_CMEN    Circular mode enable
: DMA1_CH1CTL_PNAGA   %1 6 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_PNAGA    Next address generation algorithm of peripheral
: DMA1_CH1CTL_MNAGA   %1 7 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_MNAGA    Next address generation algorithm of memory
: DMA1_CH1CTL_PWIDTH   ( %XX -- ) 8 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_PWIDTH    Transfer data size of peripheral
: DMA1_CH1CTL_MWIDTH   ( %XX -- ) 10 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_MWIDTH    Transfer data size of memory
: DMA1_CH1CTL_PRIO   ( %XX -- ) 12 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_PRIO    Priority level
: DMA1_CH1CTL_M2M   %1 14 lshift DMA1_CH1CTL bis! ;  \ DMA1_CH1CTL_M2M    Memory to Memory Mode

\ DMA1_CH1CNT (read-write)
: DMA1_CH1CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH1CNT bis! ;  \ DMA1_CH1CNT_CNT    Transfer counter

\ DMA1_CH1PADDR (read-write)
: DMA1_CH1PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH1PADDR bis! ;  \ DMA1_CH1PADDR_PADDR    Peripheral base address

\ DMA1_CH1MADDR (read-write)
: DMA1_CH1MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH1MADDR bis! ;  \ DMA1_CH1MADDR_MADDR    Memory base address

\ DMA1_CH2CTL (read-write)
: DMA1_CH2CTL_CHEN   %1 0 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_CHEN    Channel enable
: DMA1_CH2CTL_FTFIE   %1 1 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA1_CH2CTL_HTFIE   %1 2 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA1_CH2CTL_ERRIE   %1 3 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_ERRIE    Enable bit for channel error interrupt
: DMA1_CH2CTL_DIR   %1 4 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_DIR    Transfer direction
: DMA1_CH2CTL_CMEN   %1 5 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_CMEN    Circular mode enable
: DMA1_CH2CTL_PNAGA   %1 6 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_PNAGA    Next address generation algorithm of peripheral
: DMA1_CH2CTL_MNAGA   %1 7 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_MNAGA    Next address generation algorithm of memory
: DMA1_CH2CTL_PWIDTH   ( %XX -- ) 8 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_PWIDTH    Transfer data size of peripheral
: DMA1_CH2CTL_MWIDTH   ( %XX -- ) 10 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_MWIDTH    Transfer data size of memory
: DMA1_CH2CTL_PRIO   ( %XX -- ) 12 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_PRIO    Priority level
: DMA1_CH2CTL_M2M   %1 14 lshift DMA1_CH2CTL bis! ;  \ DMA1_CH2CTL_M2M    Memory to Memory Mode

\ DMA1_CH2CNT (read-write)
: DMA1_CH2CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH2CNT bis! ;  \ DMA1_CH2CNT_CNT    Transfer counter

\ DMA1_CH2PADDR (read-write)
: DMA1_CH2PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH2PADDR bis! ;  \ DMA1_CH2PADDR_PADDR    Peripheral base address

\ DMA1_CH2MADDR (read-write)
: DMA1_CH2MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH2MADDR bis! ;  \ DMA1_CH2MADDR_MADDR    Memory base address

\ DMA1_CH3CTL (read-write)
: DMA1_CH3CTL_CHEN   %1 0 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_CHEN    Channel enable
: DMA1_CH3CTL_FTFIE   %1 1 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA1_CH3CTL_HTFIE   %1 2 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA1_CH3CTL_ERRIE   %1 3 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_ERRIE    Enable bit for channel error interrupt
: DMA1_CH3CTL_DIR   %1 4 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_DIR    Transfer direction
: DMA1_CH3CTL_CMEN   %1 5 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_CMEN    Circular mode enable
: DMA1_CH3CTL_PNAGA   %1 6 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_PNAGA    Next address generation algorithm of peripheral
: DMA1_CH3CTL_MNAGA   %1 7 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_MNAGA    Next address generation algorithm of memory
: DMA1_CH3CTL_PWIDTH   ( %XX -- ) 8 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_PWIDTH    Transfer data size of peripheral
: DMA1_CH3CTL_MWIDTH   ( %XX -- ) 10 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_MWIDTH    Transfer data size of memory
: DMA1_CH3CTL_PRIO   ( %XX -- ) 12 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_PRIO    Priority level
: DMA1_CH3CTL_M2M   %1 14 lshift DMA1_CH3CTL bis! ;  \ DMA1_CH3CTL_M2M    Memory to Memory Mode

\ DMA1_CH3CNT (read-write)
: DMA1_CH3CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH3CNT bis! ;  \ DMA1_CH3CNT_CNT    Transfer counter

\ DMA1_CH3PADDR (read-write)
: DMA1_CH3PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH3PADDR bis! ;  \ DMA1_CH3PADDR_PADDR    Peripheral base address

\ DMA1_CH3MADDR (read-write)
: DMA1_CH3MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH3MADDR bis! ;  \ DMA1_CH3MADDR_MADDR    Memory base address

\ DMA1_CH4CTL (read-write)
: DMA1_CH4CTL_CHEN   %1 0 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_CHEN    Channel enable
: DMA1_CH4CTL_FTFIE   %1 1 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_FTFIE    Enable bit for channel full transfer finish interrupt
: DMA1_CH4CTL_HTFIE   %1 2 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_HTFIE    Enable bit for channel half transfer finish interrupt
: DMA1_CH4CTL_ERRIE   %1 3 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_ERRIE    Enable bit for channel error interrupt
: DMA1_CH4CTL_DIR   %1 4 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_DIR    Transfer direction
: DMA1_CH4CTL_CMEN   %1 5 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_CMEN    Circular mode enable
: DMA1_CH4CTL_PNAGA   %1 6 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_PNAGA    Next address generation algorithm of peripheral
: DMA1_CH4CTL_MNAGA   %1 7 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_MNAGA    Next address generation algorithm of memory
: DMA1_CH4CTL_PWIDTH   ( %XX -- ) 8 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_PWIDTH    Transfer data size of peripheral
: DMA1_CH4CTL_MWIDTH   ( %XX -- ) 10 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_MWIDTH    Transfer data size of memory
: DMA1_CH4CTL_PRIO   ( %XX -- ) 12 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_PRIO    Priority level
: DMA1_CH4CTL_M2M   %1 14 lshift DMA1_CH4CTL bis! ;  \ DMA1_CH4CTL_M2M    Memory to Memory Mode

\ DMA1_CH4CNT (read-write)
: DMA1_CH4CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH4CNT bis! ;  \ DMA1_CH4CNT_CNT    Transfer counter

\ DMA1_CH4PADDR (read-write)
: DMA1_CH4PADDR_PADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH4PADDR bis! ;  \ DMA1_CH4PADDR_PADDR    Peripheral base address

\ DMA1_CH4MADDR (read-write)
: DMA1_CH4MADDR_MADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift DMA1_CH4MADDR bis! ;  \ DMA1_CH4MADDR_MADDR    Memory base address

\ EXMC_SNCTL0 (read-write)
: EXMC_SNCTL0_ASYNCWAIT   %1 15 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_ASYNCWAIT    Asynchronous wait
: EXMC_SNCTL0_NRWTEN   %1 13 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NRWTEN    NWAIT signal enable
: EXMC_SNCTL0_WREN   %1 12 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_WREN    Write enable
: EXMC_SNCTL0_NRWTPOL   %1 9 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NRWTPOL    NWAIT signal polarity
: EXMC_SNCTL0_NREN   %1 6 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NREN    NOR Flash access enable
: EXMC_SNCTL0_NRW   ( %XX -- ) 4 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NRW    NOR bank memory data bus width
: EXMC_SNCTL0_NRTP   ( %XX -- ) 2 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NRTP    NOR bank memory type
: EXMC_SNCTL0_NRMUX   %1 1 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NRMUX    NOR bank memory address/data multiplexing
: EXMC_SNCTL0_NRBKEN   %1 0 lshift EXMC_SNCTL0 bis! ;  \ EXMC_SNCTL0_NRBKEN    NOR bank enable

\ EXMC_SNTCFG0 (read-write)
: EXMC_SNTCFG0_BUSLAT   ( %XXXX -- ) 16 lshift EXMC_SNTCFG0 bis! ;  \ EXMC_SNTCFG0_BUSLAT    Bus latency
: EXMC_SNTCFG0_DSET   ( %XXXXXXXX -- ) 8 lshift EXMC_SNTCFG0 bis! ;  \ EXMC_SNTCFG0_DSET    Data setup time
: EXMC_SNTCFG0_AHLD   ( %XXXX -- ) 4 lshift EXMC_SNTCFG0 bis! ;  \ EXMC_SNTCFG0_AHLD    Address hold time
: EXMC_SNTCFG0_ASET   ( %XXXX -- ) 0 lshift EXMC_SNTCFG0 bis! ;  \ EXMC_SNTCFG0_ASET    Address setup time

\ EXMC_SNCTL1 (read-write)
: EXMC_SNCTL1_ASYNCWAIT   %1 15 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_ASYNCWAIT    Asynchronous wait
: EXMC_SNCTL1_NRWTEN   %1 13 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NRWTEN    NWAIT signal enable
: EXMC_SNCTL1_WREN   %1 12 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_WREN    Write enable
: EXMC_SNCTL1_NRWTPOL   %1 9 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NRWTPOL    NWAIT signal polarity
: EXMC_SNCTL1_NREN   %1 6 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NREN    NOR Flash access enable
: EXMC_SNCTL1_NRW   ( %XX -- ) 4 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NRW    NOR bank memory data bus width
: EXMC_SNCTL1_NRTP   ( %XX -- ) 2 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NRTP    NOR bank memory type
: EXMC_SNCTL1_NRMUX   %1 1 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NRMUX    NOR bank memory address/data multiplexing
: EXMC_SNCTL1_NRBKEN   %1 0 lshift EXMC_SNCTL1 bis! ;  \ EXMC_SNCTL1_NRBKEN    NOR bank enable

\ EXTI_INTEN (read-write)
: EXTI_INTEN_INTEN0   %1 0 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN0    Enable Interrupt on line 0
: EXTI_INTEN_INTEN1   %1 1 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN1    Enable Interrupt on line 1
: EXTI_INTEN_INTEN2   %1 2 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN2    Enable Interrupt on line 2
: EXTI_INTEN_INTEN3   %1 3 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN3    Enable Interrupt on line 3
: EXTI_INTEN_INTEN4   %1 4 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN4    Enable Interrupt on line 4
: EXTI_INTEN_INTEN5   %1 5 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN5    Enable Interrupt on line 5
: EXTI_INTEN_INTEN6   %1 6 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN6    Enable Interrupt on line 6
: EXTI_INTEN_INTEN7   %1 7 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN7    Enable Interrupt on line 7
: EXTI_INTEN_INTEN8   %1 8 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN8    Enable Interrupt on line 8
: EXTI_INTEN_INTEN9   %1 9 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN9    Enable Interrupt on line 9
: EXTI_INTEN_INTEN10   %1 10 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN10    Enable Interrupt on line 10
: EXTI_INTEN_INTEN11   %1 11 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN11    Enable Interrupt on line 11
: EXTI_INTEN_INTEN12   %1 12 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN12    Enable Interrupt on line 12
: EXTI_INTEN_INTEN13   %1 13 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN13    Enable Interrupt on line 13
: EXTI_INTEN_INTEN14   %1 14 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN14    Enable Interrupt on line 14
: EXTI_INTEN_INTEN15   %1 15 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN15    Enable Interrupt on line 15
: EXTI_INTEN_INTEN16   %1 16 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN16    Enable Interrupt on line 16
: EXTI_INTEN_INTEN17   %1 17 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN17    Enable Interrupt on line 17
: EXTI_INTEN_INTEN18   %1 18 lshift EXTI_INTEN bis! ;  \ EXTI_INTEN_INTEN18    Enable Interrupt on line 18

\ EXTI_EVEN (read-write)
: EXTI_EVEN_EVEN0   %1 0 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN0    Enable Event on line 0
: EXTI_EVEN_EVEN1   %1 1 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN1    Enable Event on line 1
: EXTI_EVEN_EVEN2   %1 2 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN2    Enable Event on line 2
: EXTI_EVEN_EVEN3   %1 3 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN3    Enable Event on line 3
: EXTI_EVEN_EVEN4   %1 4 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN4    Enable Event on line 4
: EXTI_EVEN_EVEN5   %1 5 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN5    Enable Event on line 5
: EXTI_EVEN_EVEN6   %1 6 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN6    Enable Event on line 6
: EXTI_EVEN_EVEN7   %1 7 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN7    Enable Event on line 7
: EXTI_EVEN_EVEN8   %1 8 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN8    Enable Event on line 8
: EXTI_EVEN_EVEN9   %1 9 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN9    Enable Event on line 9
: EXTI_EVEN_EVEN10   %1 10 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN10    Enable Event on line 10
: EXTI_EVEN_EVEN11   %1 11 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN11    Enable Event on line 11
: EXTI_EVEN_EVEN12   %1 12 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN12    Enable Event on line 12
: EXTI_EVEN_EVEN13   %1 13 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN13    Enable Event on line 13
: EXTI_EVEN_EVEN14   %1 14 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN14    Enable Event on line 14
: EXTI_EVEN_EVEN15   %1 15 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN15    Enable Event on line 15
: EXTI_EVEN_EVEN16   %1 16 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN16    Enable Event on line 16
: EXTI_EVEN_EVEN17   %1 17 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN17    Enable Event on line 17
: EXTI_EVEN_EVEN18   %1 18 lshift EXTI_EVEN bis! ;  \ EXTI_EVEN_EVEN18    Enable Event on line 18

\ EXTI_RTEN (read-write)
: EXTI_RTEN_RTEN0   %1 0 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN0    Rising edge trigger enable of  line 0
: EXTI_RTEN_RTEN1   %1 1 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN1    Rising edge trigger enable of  line 1
: EXTI_RTEN_RTEN2   %1 2 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN2    Rising edge trigger enable of  line 2
: EXTI_RTEN_RTEN3   %1 3 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN3    Rising edge trigger enable of  line 3
: EXTI_RTEN_RTEN4   %1 4 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN4    Rising edge trigger enable of  line 4
: EXTI_RTEN_RTEN5   %1 5 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN5    Rising edge trigger enable of  line 5
: EXTI_RTEN_RTEN6   %1 6 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN6    Rising edge trigger enable of  line 6
: EXTI_RTEN_RTEN7   %1 7 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN7    Rising edge trigger enable of  line 7
: EXTI_RTEN_RTEN8   %1 8 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN8    Rising edge trigger enable of  line 8
: EXTI_RTEN_RTEN9   %1 9 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN9    Rising edge trigger enable of  line 9
: EXTI_RTEN_RTEN10   %1 10 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN10    Rising edge trigger enable of  line 10
: EXTI_RTEN_RTEN11   %1 11 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN11    Rising edge trigger enable of  line 11
: EXTI_RTEN_RTEN12   %1 12 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN12    Rising edge trigger enable of  line 12
: EXTI_RTEN_RTEN13   %1 13 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN13    Rising edge trigger enable of  line 13
: EXTI_RTEN_RTEN14   %1 14 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN14    Rising edge trigger enable of  line 14
: EXTI_RTEN_RTEN15   %1 15 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN15    Rising edge trigger enable of  line 15
: EXTI_RTEN_RTEN16   %1 16 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN16    Rising edge trigger enable of  line 16
: EXTI_RTEN_RTEN17   %1 17 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN17    Rising edge trigger enable of  line 17
: EXTI_RTEN_RTEN18   %1 18 lshift EXTI_RTEN bis! ;  \ EXTI_RTEN_RTEN18    Rising edge trigger enable of  line 18

\ EXTI_FTEN (read-write)
: EXTI_FTEN_FTEN0   %1 0 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN0    Falling edge trigger enable of  line 0
: EXTI_FTEN_FTEN1   %1 1 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN1    Falling edge trigger enable of  line 1
: EXTI_FTEN_FTEN2   %1 2 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN2    Falling edge trigger enable of  line 2
: EXTI_FTEN_FTEN3   %1 3 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN3    Falling edge trigger enable of  line 3
: EXTI_FTEN_FTEN4   %1 4 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN4    Falling edge trigger enable of  line 4
: EXTI_FTEN_FTEN5   %1 5 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN5    Falling edge trigger enable of  line 5
: EXTI_FTEN_FTEN6   %1 6 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN6    Falling edge trigger enable of  line 6
: EXTI_FTEN_FTEN7   %1 7 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN7    Falling edge trigger enable of  line 7
: EXTI_FTEN_FTEN8   %1 8 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN8    Falling edge trigger enable of  line 8
: EXTI_FTEN_FTEN9   %1 9 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN9    Falling edge trigger enable of  line 9
: EXTI_FTEN_FTEN10   %1 10 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN10    Falling edge trigger enable of  line 10
: EXTI_FTEN_FTEN11   %1 11 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN11    Falling edge trigger enable of  line 11
: EXTI_FTEN_FTEN12   %1 12 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN12    Falling edge trigger enable of  line 12
: EXTI_FTEN_FTEN13   %1 13 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN13    Falling edge trigger enable of  line 13
: EXTI_FTEN_FTEN14   %1 14 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN14    Falling edge trigger enable of  line 14
: EXTI_FTEN_FTEN15   %1 15 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN15    Falling edge trigger enable of  line 15
: EXTI_FTEN_FTEN16   %1 16 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN16    Falling edge trigger enable of  line 16
: EXTI_FTEN_FTEN17   %1 17 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN17    Falling edge trigger enable of  line 17
: EXTI_FTEN_FTEN18   %1 18 lshift EXTI_FTEN bis! ;  \ EXTI_FTEN_FTEN18    Falling edge trigger enable of  line 18

\ EXTI_SWIEV (read-write)
: EXTI_SWIEV_SWIEV0   %1 0 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV0    Interrupt/Event software trigger on line  0
: EXTI_SWIEV_SWIEV1   %1 1 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV1    Interrupt/Event software trigger on line  1
: EXTI_SWIEV_SWIEV2   %1 2 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV2    Interrupt/Event software trigger on line  2
: EXTI_SWIEV_SWIEV3   %1 3 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV3    Interrupt/Event software trigger on line  3
: EXTI_SWIEV_SWIEV4   %1 4 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV4    Interrupt/Event software trigger on line  4
: EXTI_SWIEV_SWIEV5   %1 5 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV5    Interrupt/Event software trigger on line  5
: EXTI_SWIEV_SWIEV6   %1 6 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV6    Interrupt/Event software trigger on line  6
: EXTI_SWIEV_SWIEV7   %1 7 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV7    Interrupt/Event software trigger on line  7
: EXTI_SWIEV_SWIEV8   %1 8 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV8    Interrupt/Event software trigger on line  8
: EXTI_SWIEV_SWIEV9   %1 9 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV9    Interrupt/Event software trigger on line  9
: EXTI_SWIEV_SWIEV10   %1 10 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV10    Interrupt/Event software trigger on line  10
: EXTI_SWIEV_SWIEV11   %1 11 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV11    Interrupt/Event software trigger on line  11
: EXTI_SWIEV_SWIEV12   %1 12 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV12    Interrupt/Event software trigger on line  12
: EXTI_SWIEV_SWIEV13   %1 13 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV13    Interrupt/Event software trigger on line  13
: EXTI_SWIEV_SWIEV14   %1 14 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV14    Interrupt/Event software trigger on line  14
: EXTI_SWIEV_SWIEV15   %1 15 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV15    Interrupt/Event software trigger on line  15
: EXTI_SWIEV_SWIEV16   %1 16 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV16    Interrupt/Event software trigger on line  16
: EXTI_SWIEV_SWIEV17   %1 17 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV17    Interrupt/Event software trigger on line  17
: EXTI_SWIEV_SWIEV18   %1 18 lshift EXTI_SWIEV bis! ;  \ EXTI_SWIEV_SWIEV18    Interrupt/Event software trigger on line  18

\ EXTI_PD (read-write)
: EXTI_PD_PD0   %1 0 lshift EXTI_PD bis! ;  \ EXTI_PD_PD0    Interrupt pending status of line 0
: EXTI_PD_PD1   %1 1 lshift EXTI_PD bis! ;  \ EXTI_PD_PD1    Interrupt pending status of line 1
: EXTI_PD_PD2   %1 2 lshift EXTI_PD bis! ;  \ EXTI_PD_PD2    Interrupt pending status of line 2
: EXTI_PD_PD3   %1 3 lshift EXTI_PD bis! ;  \ EXTI_PD_PD3    Interrupt pending status of line 3
: EXTI_PD_PD4   %1 4 lshift EXTI_PD bis! ;  \ EXTI_PD_PD4    Interrupt pending status of line 4
: EXTI_PD_PD5   %1 5 lshift EXTI_PD bis! ;  \ EXTI_PD_PD5    Interrupt pending status of line 5
: EXTI_PD_PD6   %1 6 lshift EXTI_PD bis! ;  \ EXTI_PD_PD6    Interrupt pending status of line 6
: EXTI_PD_PD7   %1 7 lshift EXTI_PD bis! ;  \ EXTI_PD_PD7    Interrupt pending status of line 7
: EXTI_PD_PD8   %1 8 lshift EXTI_PD bis! ;  \ EXTI_PD_PD8    Interrupt pending status of line 8
: EXTI_PD_PD9   %1 9 lshift EXTI_PD bis! ;  \ EXTI_PD_PD9    Interrupt pending status of line 9
: EXTI_PD_PD10   %1 10 lshift EXTI_PD bis! ;  \ EXTI_PD_PD10    Interrupt pending status of line 10
: EXTI_PD_PD11   %1 11 lshift EXTI_PD bis! ;  \ EXTI_PD_PD11    Interrupt pending status of line 11
: EXTI_PD_PD12   %1 12 lshift EXTI_PD bis! ;  \ EXTI_PD_PD12    Interrupt pending status of line 12
: EXTI_PD_PD13   %1 13 lshift EXTI_PD bis! ;  \ EXTI_PD_PD13    Interrupt pending status of line 13
: EXTI_PD_PD14   %1 14 lshift EXTI_PD bis! ;  \ EXTI_PD_PD14    Interrupt pending status of line 14
: EXTI_PD_PD15   %1 15 lshift EXTI_PD bis! ;  \ EXTI_PD_PD15    Interrupt pending status of line 15
: EXTI_PD_PD16   %1 16 lshift EXTI_PD bis! ;  \ EXTI_PD_PD16    Interrupt pending status of line 16
: EXTI_PD_PD17   %1 17 lshift EXTI_PD bis! ;  \ EXTI_PD_PD17    Interrupt pending status of line 17
: EXTI_PD_PD18   %1 18 lshift EXTI_PD bis! ;  \ EXTI_PD_PD18    Interrupt pending status of line 18

\ FMC_WS (read-write)
: FMC_WS_WSCNT   ( %XXX -- ) 0 lshift FMC_WS bis! ;  \ FMC_WS_WSCNT    wait state counter register

\ FMC_KEY0 (write-only)
: FMC_KEY0_KEY   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FMC_KEY0 bis! ;  \ FMC_KEY0_KEY    FMC_CTL0 unlock key

\ FMC_OBKEY (write-only)
: FMC_OBKEY_OBKEY   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FMC_OBKEY bis! ;  \ FMC_OBKEY_OBKEY    FMC_ CTL0 option byte operation unlock register

\ FMC_STAT0 ()
: FMC_STAT0_ENDF   %1 5 lshift FMC_STAT0 bis! ;  \ FMC_STAT0_ENDF    End of operation flag bit
: FMC_STAT0_WPERR   %1 4 lshift FMC_STAT0 bis! ;  \ FMC_STAT0_WPERR    Erase/Program protection error flag bit
: FMC_STAT0_PGERR   %1 2 lshift FMC_STAT0 bis! ;  \ FMC_STAT0_PGERR    Program error flag bit
: FMC_STAT0_BUSY   %1 0 lshift FMC_STAT0 bis! ;  \ FMC_STAT0_BUSY    The flash is busy bit

\ FMC_CTL0 (read-write)
: FMC_CTL0_ENDIE   %1 12 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_ENDIE    End of operation interrupt enable bit
: FMC_CTL0_ERRIE   %1 10 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_ERRIE    Error interrupt enable bit
: FMC_CTL0_OBWEN   %1 9 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_OBWEN    Option byte erase/program enable bit
: FMC_CTL0_LK   %1 7 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_LK    FMC_CTL0 lock bit
: FMC_CTL0_START   %1 6 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_START    Send erase command to FMC bit
: FMC_CTL0_OBER   %1 5 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_OBER    Option bytes erase command bit
: FMC_CTL0_OBPG   %1 4 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_OBPG    Option bytes program command bit
: FMC_CTL0_MER   %1 2 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_MER    Main flash mass erase for bank0 command bit
: FMC_CTL0_PER   %1 1 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_PER    Main flash page erase for bank0 command bit
: FMC_CTL0_PG   %1 0 lshift FMC_CTL0 bis! ;  \ FMC_CTL0_PG    Main flash program for bank0 command bit

\ FMC_ADDR0 (write-only)
: FMC_ADDR0_ADDR   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FMC_ADDR0 bis! ;  \ FMC_ADDR0_ADDR    Flash erase/program command address bits

\ FMC_OBSTAT (read-only)
: FMC_OBSTAT_OBERR   %1 0 lshift FMC_OBSTAT bis! ;  \ FMC_OBSTAT_OBERR    Option bytes read error bit
: FMC_OBSTAT_SPC   %1 1 lshift FMC_OBSTAT bis! ;  \ FMC_OBSTAT_SPC    Option bytes security protection code
: FMC_OBSTAT_USER   ( %XXXXXXXX -- ) 2 lshift FMC_OBSTAT bis! ;  \ FMC_OBSTAT_USER    Store USER of option bytes block after system reset
: FMC_OBSTAT_DATA   ( %XXXXXXXXXXXXXXXX -- ) 10 lshift FMC_OBSTAT bis! ;  \ FMC_OBSTAT_DATA    Store DATA[15:0] of option bytes block after system reset

\ FMC_WP (read-only)
: FMC_WP_WP   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FMC_WP bis! ;  \ FMC_WP_WP    Store WP[31:0] of option bytes block after system reset

\ FMC_PID (read-only)
: FMC_PID_PID   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FMC_PID bis! ;  \ FMC_PID_PID    Product reserved ID code register

\ FWDGT_CTL (write-only)
: FWDGT_CTL_CMD   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift FWDGT_CTL bis! ;  \ FWDGT_CTL_CMD    Key value

\ FWDGT_PSC (read-write)
: FWDGT_PSC_PSC   ( %XXX -- ) 0 lshift FWDGT_PSC bis! ;  \ FWDGT_PSC_PSC    Free watchdog timer prescaler selection

\ FWDGT_RLD (read-write)
: FWDGT_RLD_RLD   ( %XXXXXXXXXXX -- ) 0 lshift FWDGT_RLD bis! ;  \ FWDGT_RLD_RLD    Free watchdog timer counter reload value

\ FWDGT_STAT (read-only)
: FWDGT_STAT_PUD   %1 0 lshift FWDGT_STAT bis! ;  \ FWDGT_STAT_PUD    Free watchdog timer prescaler value update
: FWDGT_STAT_RUD   %1 1 lshift FWDGT_STAT bis! ;  \ FWDGT_STAT_RUD    Free watchdog timer counter reload value update

\ GPIOA_CTL0 (read-write)
: GPIOA_CTL0_CTL7   ( %XX -- ) 30 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL7    Port x configuration bits x =  7
: GPIOA_CTL0_MD7   ( %XX -- ) 28 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD7    Port x mode bits x =  7
: GPIOA_CTL0_CTL6   ( %XX -- ) 26 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL6    Port x configuration bits x =  6
: GPIOA_CTL0_MD6   ( %XX -- ) 24 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD6    Port x mode bits x =  6
: GPIOA_CTL0_CTL5   ( %XX -- ) 22 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL5    Port x configuration bits x =  5
: GPIOA_CTL0_MD5   ( %XX -- ) 20 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD5    Port x mode bits x =  5
: GPIOA_CTL0_CTL4   ( %XX -- ) 18 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL4    Port x configuration bits x =  4
: GPIOA_CTL0_MD4   ( %XX -- ) 16 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD4    Port x mode bits x =  4
: GPIOA_CTL0_CTL3   ( %XX -- ) 14 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL3    Port x configuration bits x =  3
: GPIOA_CTL0_MD3   ( %XX -- ) 12 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD3    Port x mode bits x =  3 
: GPIOA_CTL0_CTL2   ( %XX -- ) 10 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL2    Port x configuration bits x =  2
: GPIOA_CTL0_MD2   ( %XX -- ) 8 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD2    Port x mode bits x =  2 
: GPIOA_CTL0_CTL1   ( %XX -- ) 6 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL1    Port x configuration bits x =  1
: GPIOA_CTL0_MD1   ( %XX -- ) 4 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD1    Port x mode bits x =  1
: GPIOA_CTL0_CTL0   ( %XX -- ) 2 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_CTL0    Port x configuration bits x =  0
: GPIOA_CTL0_MD0   ( %XX -- ) 0 lshift GPIOA_CTL0 bis! ;  \ GPIOA_CTL0_MD0    Port x mode bits x =  0

\ GPIOA_CTL1 (read-write)
: GPIOA_CTL1_CTL15   ( %XX -- ) 30 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL15    Port x configuration bits x =  15
: GPIOA_CTL1_MD15   ( %XX -- ) 28 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD15    Port x mode bits x =  15
: GPIOA_CTL1_CTL14   ( %XX -- ) 26 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL14    Port x configuration bits x =  14
: GPIOA_CTL1_MD14   ( %XX -- ) 24 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD14    Port x mode bits x =  14
: GPIOA_CTL1_CTL13   ( %XX -- ) 22 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL13    Port x configuration bits x =  13
: GPIOA_CTL1_MD13   ( %XX -- ) 20 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD13    Port x mode bits x =  13
: GPIOA_CTL1_CTL12   ( %XX -- ) 18 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL12    Port x configuration bits x =  12
: GPIOA_CTL1_MD12   ( %XX -- ) 16 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD12    Port x mode bits x =  12
: GPIOA_CTL1_CTL11   ( %XX -- ) 14 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL11    Port x configuration bits x =  11
: GPIOA_CTL1_MD11   ( %XX -- ) 12 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD11    Port x mode bits x =  11 
: GPIOA_CTL1_CTL10   ( %XX -- ) 10 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL10    Port x configuration bits x =  10
: GPIOA_CTL1_MD10   ( %XX -- ) 8 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD10    Port x mode bits x =  10 
: GPIOA_CTL1_CTL9   ( %XX -- ) 6 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL9    Port x configuration bits x =  9
: GPIOA_CTL1_MD9   ( %XX -- ) 4 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD9    Port x mode bits x =  9
: GPIOA_CTL1_CTL8   ( %XX -- ) 2 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_CTL8    Port x configuration bits x =  8
: GPIOA_CTL1_MD8   ( %XX -- ) 0 lshift GPIOA_CTL1 bis! ;  \ GPIOA_CTL1_MD8    Port x mode bits x =  8

\ GPIOA_ISTAT (read-only)
: GPIOA_ISTAT_ISTAT15   %1 15 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT15    Port input status
: GPIOA_ISTAT_ISTAT14   %1 14 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT14    Port input status
: GPIOA_ISTAT_ISTAT13   %1 13 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT13    Port input status
: GPIOA_ISTAT_ISTAT12   %1 12 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT12    Port input status
: GPIOA_ISTAT_ISTAT11   %1 11 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT11    Port input status
: GPIOA_ISTAT_ISTAT10   %1 10 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT10    Port input status
: GPIOA_ISTAT_ISTAT9   %1 9 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT9    Port input status
: GPIOA_ISTAT_ISTAT8   %1 8 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT8    Port input status
: GPIOA_ISTAT_ISTAT7   %1 7 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT7    Port input status
: GPIOA_ISTAT_ISTAT6   %1 6 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT6    Port input status
: GPIOA_ISTAT_ISTAT5   %1 5 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT5    Port input status
: GPIOA_ISTAT_ISTAT4   %1 4 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT4    Port input status
: GPIOA_ISTAT_ISTAT3   %1 3 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT3    Port input status
: GPIOA_ISTAT_ISTAT2   %1 2 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT2    Port input status
: GPIOA_ISTAT_ISTAT1   %1 1 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT1    Port input status
: GPIOA_ISTAT_ISTAT0   %1 0 lshift GPIOA_ISTAT bis! ;  \ GPIOA_ISTAT_ISTAT0    Port input status

\ GPIOA_OCTL (read-write)
: GPIOA_OCTL_OCTL15   %1 15 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL15    Port output control
: GPIOA_OCTL_OCTL14   %1 14 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL14    Port output control
: GPIOA_OCTL_OCTL13   %1 13 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL13    Port output control
: GPIOA_OCTL_OCTL12   %1 12 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL12    Port output control
: GPIOA_OCTL_OCTL11   %1 11 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL11    Port output control
: GPIOA_OCTL_OCTL10   %1 10 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL10    Port output control
: GPIOA_OCTL_OCTL9   %1 9 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL9    Port output control
: GPIOA_OCTL_OCTL8   %1 8 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL8    Port output control
: GPIOA_OCTL_OCTL7   %1 7 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL7    Port output control
: GPIOA_OCTL_OCTL6   %1 6 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL6    Port output control
: GPIOA_OCTL_OCTL5   %1 5 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL5    Port output control
: GPIOA_OCTL_OCTL4   %1 4 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL4    Port output control
: GPIOA_OCTL_OCTL3   %1 3 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL3    Port output control
: GPIOA_OCTL_OCTL2   %1 2 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL2    Port output control
: GPIOA_OCTL_OCTL1   %1 1 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL1    Port output control
: GPIOA_OCTL_OCTL0   %1 0 lshift GPIOA_OCTL bis! ;  \ GPIOA_OCTL_OCTL0    Port output control

\ GPIOA_BOP (write-only)
: GPIOA_BOP_CR15   %1 31 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR15    Port 15 Clear bit
: GPIOA_BOP_CR14   %1 30 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR14    Port 14 Clear bit
: GPIOA_BOP_CR13   %1 29 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR13    Port 13 Clear bit
: GPIOA_BOP_CR12   %1 28 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR12    Port 12 Clear bit
: GPIOA_BOP_CR11   %1 27 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR11    Port 11 Clear bit
: GPIOA_BOP_CR10   %1 26 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR10    Port 10 Clear bit
: GPIOA_BOP_CR9   %1 25 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR9    Port 9 Clear bit
: GPIOA_BOP_CR8   %1 24 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR8    Port 8 Clear bit
: GPIOA_BOP_CR7   %1 23 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR7    Port 7 Clear bit
: GPIOA_BOP_CR6   %1 22 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR6    Port 6 Clear bit
: GPIOA_BOP_CR5   %1 21 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR5    Port 5 Clear bit
: GPIOA_BOP_CR4   %1 20 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR4    Port 4 Clear bit
: GPIOA_BOP_CR3   %1 19 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR3    Port 3 Clear bit
: GPIOA_BOP_CR2   %1 18 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR2    Port 2 Clear bit
: GPIOA_BOP_CR1   %1 17 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR1    Port 1 Clear bit
: GPIOA_BOP_CR0   %1 16 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_CR0    Port 0 Clear bit
: GPIOA_BOP_BOP15   %1 15 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP15    Port 15 Set bit
: GPIOA_BOP_BOP14   %1 14 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP14    Port 14 Set bit
: GPIOA_BOP_BOP13   %1 13 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP13    Port 13 Set bit
: GPIOA_BOP_BOP12   %1 12 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP12    Port 12 Set bit
: GPIOA_BOP_BOP11   %1 11 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP11    Port 11 Set bit
: GPIOA_BOP_BOP10   %1 10 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP10    Port 10 Set bit
: GPIOA_BOP_BOP9   %1 9 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP9    Port 9 Set bit
: GPIOA_BOP_BOP8   %1 8 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP8    Port 8 Set bit
: GPIOA_BOP_BOP7   %1 7 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP7    Port 7 Set bit
: GPIOA_BOP_BOP6   %1 6 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP6    Port 6 Set bit
: GPIOA_BOP_BOP5   %1 5 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP5    Port 5 Set bit
: GPIOA_BOP_BOP4   %1 4 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP4    Port 4 Set bit
: GPIOA_BOP_BOP3   %1 3 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP3    Port 3 Set bit
: GPIOA_BOP_BOP2   %1 2 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP2    Port 2 Set bit
: GPIOA_BOP_BOP1   %1 1 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP1    Port 1 Set bit
: GPIOA_BOP_BOP0   %1 0 lshift GPIOA_BOP bis! ;  \ GPIOA_BOP_BOP0    Port 0 Set bit

\ GPIOA_BC (write-only)
: GPIOA_BC_CR15   %1 15 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR15    Port 15 Clear bit
: GPIOA_BC_CR14   %1 14 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR14    Port 14 Clear bit
: GPIOA_BC_CR13   %1 13 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR13    Port 13 Clear bit
: GPIOA_BC_CR12   %1 12 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR12    Port 12 Clear bit
: GPIOA_BC_CR11   %1 11 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR11    Port 11 Clear bit
: GPIOA_BC_CR10   %1 10 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR10    Port 10 Clear bit
: GPIOA_BC_CR9   %1 9 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR9    Port 9 Clear bit
: GPIOA_BC_CR8   %1 8 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR8    Port 8 Clear bit
: GPIOA_BC_CR7   %1 7 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR7    Port 7 Clear bit
: GPIOA_BC_CR6   %1 6 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR6    Port 6 Clear bit
: GPIOA_BC_CR5   %1 5 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR5    Port 5 Clear bit
: GPIOA_BC_CR4   %1 4 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR4    Port 4 Clear bit
: GPIOA_BC_CR3   %1 3 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR3    Port 3 Clear bit
: GPIOA_BC_CR2   %1 2 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR2    Port 2 Clear bit
: GPIOA_BC_CR1   %1 1 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR1    Port 1 Clear bit
: GPIOA_BC_CR0   %1 0 lshift GPIOA_BC bis! ;  \ GPIOA_BC_CR0    Port 0 Clear bit

\ GPIOA_LOCK (read-write)
: GPIOA_LOCK_LKK   %1 16 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LKK    Lock sequence key  
: GPIOA_LOCK_LK15   %1 15 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK15    Port Lock bit 15
: GPIOA_LOCK_LK14   %1 14 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK14    Port Lock bit 14
: GPIOA_LOCK_LK13   %1 13 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK13    Port Lock bit 13
: GPIOA_LOCK_LK12   %1 12 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK12    Port Lock bit 12
: GPIOA_LOCK_LK11   %1 11 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK11    Port Lock bit 11
: GPIOA_LOCK_LK10   %1 10 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK10    Port Lock bit 10
: GPIOA_LOCK_LK9   %1 9 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK9    Port Lock bit 9
: GPIOA_LOCK_LK8   %1 8 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK8    Port Lock bit 8
: GPIOA_LOCK_LK7   %1 7 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK7    Port Lock bit 7
: GPIOA_LOCK_LK6   %1 6 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK6    Port Lock bit 6
: GPIOA_LOCK_LK5   %1 5 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK5    Port Lock bit 5
: GPIOA_LOCK_LK4   %1 4 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK4    Port Lock bit 4
: GPIOA_LOCK_LK3   %1 3 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK3    Port Lock bit 3
: GPIOA_LOCK_LK2   %1 2 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK2    Port Lock bit 2
: GPIOA_LOCK_LK1   %1 1 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK1    Port Lock bit 1
: GPIOA_LOCK_LK0   %1 0 lshift GPIOA_LOCK bis! ;  \ GPIOA_LOCK_LK0    Port Lock bit 0

\ GPIOB_CTL0 (read-write)
: GPIOB_CTL0_CTL7   ( %XX -- ) 30 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL7    Port x configuration bits x =  7
: GPIOB_CTL0_MD7   ( %XX -- ) 28 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD7    Port x mode bits x =  7
: GPIOB_CTL0_CTL6   ( %XX -- ) 26 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL6    Port x configuration bits x =  6
: GPIOB_CTL0_MD6   ( %XX -- ) 24 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD6    Port x mode bits x =  6
: GPIOB_CTL0_CTL5   ( %XX -- ) 22 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL5    Port x configuration bits x =  5
: GPIOB_CTL0_MD5   ( %XX -- ) 20 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD5    Port x mode bits x =  5
: GPIOB_CTL0_CTL4   ( %XX -- ) 18 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL4    Port x configuration bits x =  4
: GPIOB_CTL0_MD4   ( %XX -- ) 16 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD4    Port x mode bits x =  4
: GPIOB_CTL0_CTL3   ( %XX -- ) 14 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL3    Port x configuration bits x =  3
: GPIOB_CTL0_MD3   ( %XX -- ) 12 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD3    Port x mode bits x =  3 
: GPIOB_CTL0_CTL2   ( %XX -- ) 10 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL2    Port x configuration bits x =  2
: GPIOB_CTL0_MD2   ( %XX -- ) 8 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD2    Port x mode bits x =  2 
: GPIOB_CTL0_CTL1   ( %XX -- ) 6 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL1    Port x configuration bits x =  1
: GPIOB_CTL0_MD1   ( %XX -- ) 4 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD1    Port x mode bits x =  1
: GPIOB_CTL0_CTL0   ( %XX -- ) 2 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_CTL0    Port x configuration bits x =  0
: GPIOB_CTL0_MD0   ( %XX -- ) 0 lshift GPIOB_CTL0 bis! ;  \ GPIOB_CTL0_MD0    Port x mode bits x =  0

\ GPIOB_CTL1 (read-write)
: GPIOB_CTL1_CTL15   ( %XX -- ) 30 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL15    Port x configuration bits x =  15
: GPIOB_CTL1_MD15   ( %XX -- ) 28 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD15    Port x mode bits x =  15
: GPIOB_CTL1_CTL14   ( %XX -- ) 26 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL14    Port x configuration bits x =  14
: GPIOB_CTL1_MD14   ( %XX -- ) 24 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD14    Port x mode bits x =  14
: GPIOB_CTL1_CTL13   ( %XX -- ) 22 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL13    Port x configuration bits x =  13
: GPIOB_CTL1_MD13   ( %XX -- ) 20 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD13    Port x mode bits x =  13
: GPIOB_CTL1_CTL12   ( %XX -- ) 18 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL12    Port x configuration bits x =  12
: GPIOB_CTL1_MD12   ( %XX -- ) 16 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD12    Port x mode bits x =  12
: GPIOB_CTL1_CTL11   ( %XX -- ) 14 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL11    Port x configuration bits x =  11
: GPIOB_CTL1_MD11   ( %XX -- ) 12 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD11    Port x mode bits x =  11 
: GPIOB_CTL1_CTL10   ( %XX -- ) 10 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL10    Port x configuration bits x =  10
: GPIOB_CTL1_MD10   ( %XX -- ) 8 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD10    Port x mode bits x =  10 
: GPIOB_CTL1_CTL9   ( %XX -- ) 6 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL9    Port x configuration bits x =  9
: GPIOB_CTL1_MD9   ( %XX -- ) 4 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD9    Port x mode bits x =  9
: GPIOB_CTL1_CTL8   ( %XX -- ) 2 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_CTL8    Port x configuration bits x =  8
: GPIOB_CTL1_MD8   ( %XX -- ) 0 lshift GPIOB_CTL1 bis! ;  \ GPIOB_CTL1_MD8    Port x mode bits x =  8

\ GPIOB_ISTAT (read-only)
: GPIOB_ISTAT_ISTAT15   %1 15 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT15    Port input status
: GPIOB_ISTAT_ISTAT14   %1 14 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT14    Port input status
: GPIOB_ISTAT_ISTAT13   %1 13 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT13    Port input status
: GPIOB_ISTAT_ISTAT12   %1 12 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT12    Port input status
: GPIOB_ISTAT_ISTAT11   %1 11 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT11    Port input status
: GPIOB_ISTAT_ISTAT10   %1 10 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT10    Port input status
: GPIOB_ISTAT_ISTAT9   %1 9 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT9    Port input status
: GPIOB_ISTAT_ISTAT8   %1 8 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT8    Port input status
: GPIOB_ISTAT_ISTAT7   %1 7 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT7    Port input status
: GPIOB_ISTAT_ISTAT6   %1 6 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT6    Port input status
: GPIOB_ISTAT_ISTAT5   %1 5 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT5    Port input status
: GPIOB_ISTAT_ISTAT4   %1 4 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT4    Port input status
: GPIOB_ISTAT_ISTAT3   %1 3 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT3    Port input status
: GPIOB_ISTAT_ISTAT2   %1 2 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT2    Port input status
: GPIOB_ISTAT_ISTAT1   %1 1 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT1    Port input status
: GPIOB_ISTAT_ISTAT0   %1 0 lshift GPIOB_ISTAT bis! ;  \ GPIOB_ISTAT_ISTAT0    Port input status

\ GPIOB_OCTL (read-write)
: GPIOB_OCTL_OCTL15   %1 15 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL15    Port output control
: GPIOB_OCTL_OCTL14   %1 14 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL14    Port output control
: GPIOB_OCTL_OCTL13   %1 13 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL13    Port output control
: GPIOB_OCTL_OCTL12   %1 12 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL12    Port output control
: GPIOB_OCTL_OCTL11   %1 11 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL11    Port output control
: GPIOB_OCTL_OCTL10   %1 10 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL10    Port output control
: GPIOB_OCTL_OCTL9   %1 9 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL9    Port output control
: GPIOB_OCTL_OCTL8   %1 8 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL8    Port output control
: GPIOB_OCTL_OCTL7   %1 7 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL7    Port output control
: GPIOB_OCTL_OCTL6   %1 6 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL6    Port output control
: GPIOB_OCTL_OCTL5   %1 5 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL5    Port output control
: GPIOB_OCTL_OCTL4   %1 4 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL4    Port output control
: GPIOB_OCTL_OCTL3   %1 3 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL3    Port output control
: GPIOB_OCTL_OCTL2   %1 2 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL2    Port output control
: GPIOB_OCTL_OCTL1   %1 1 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL1    Port output control
: GPIOB_OCTL_OCTL0   %1 0 lshift GPIOB_OCTL bis! ;  \ GPIOB_OCTL_OCTL0    Port output control

\ GPIOB_BOP (write-only)
: GPIOB_BOP_CR15   %1 31 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR15    Port 15 Clear bit
: GPIOB_BOP_CR14   %1 30 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR14    Port 14 Clear bit
: GPIOB_BOP_CR13   %1 29 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR13    Port 13 Clear bit
: GPIOB_BOP_CR12   %1 28 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR12    Port 12 Clear bit
: GPIOB_BOP_CR11   %1 27 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR11    Port 11 Clear bit
: GPIOB_BOP_CR10   %1 26 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR10    Port 10 Clear bit
: GPIOB_BOP_CR9   %1 25 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR9    Port 9 Clear bit
: GPIOB_BOP_CR8   %1 24 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR8    Port 8 Clear bit
: GPIOB_BOP_CR7   %1 23 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR7    Port 7 Clear bit
: GPIOB_BOP_CR6   %1 22 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR6    Port 6 Clear bit
: GPIOB_BOP_CR5   %1 21 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR5    Port 5 Clear bit
: GPIOB_BOP_CR4   %1 20 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR4    Port 4 Clear bit
: GPIOB_BOP_CR3   %1 19 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR3    Port 3 Clear bit
: GPIOB_BOP_CR2   %1 18 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR2    Port 2 Clear bit
: GPIOB_BOP_CR1   %1 17 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR1    Port 1 Clear bit
: GPIOB_BOP_CR0   %1 16 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_CR0    Port 0 Clear bit
: GPIOB_BOP_BOP15   %1 15 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP15    Port 15 Set bit
: GPIOB_BOP_BOP14   %1 14 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP14    Port 14 Set bit
: GPIOB_BOP_BOP13   %1 13 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP13    Port 13 Set bit
: GPIOB_BOP_BOP12   %1 12 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP12    Port 12 Set bit
: GPIOB_BOP_BOP11   %1 11 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP11    Port 11 Set bit
: GPIOB_BOP_BOP10   %1 10 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP10    Port 10 Set bit
: GPIOB_BOP_BOP9   %1 9 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP9    Port 9 Set bit
: GPIOB_BOP_BOP8   %1 8 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP8    Port 8 Set bit
: GPIOB_BOP_BOP7   %1 7 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP7    Port 7 Set bit
: GPIOB_BOP_BOP6   %1 6 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP6    Port 6 Set bit
: GPIOB_BOP_BOP5   %1 5 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP5    Port 5 Set bit
: GPIOB_BOP_BOP4   %1 4 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP4    Port 4 Set bit
: GPIOB_BOP_BOP3   %1 3 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP3    Port 3 Set bit
: GPIOB_BOP_BOP2   %1 2 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP2    Port 2 Set bit
: GPIOB_BOP_BOP1   %1 1 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP1    Port 1 Set bit
: GPIOB_BOP_BOP0   %1 0 lshift GPIOB_BOP bis! ;  \ GPIOB_BOP_BOP0    Port 0 Set bit

\ GPIOB_BC (write-only)
: GPIOB_BC_CR15   %1 15 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR15    Port 15 Clear bit
: GPIOB_BC_CR14   %1 14 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR14    Port 14 Clear bit
: GPIOB_BC_CR13   %1 13 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR13    Port 13 Clear bit
: GPIOB_BC_CR12   %1 12 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR12    Port 12 Clear bit
: GPIOB_BC_CR11   %1 11 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR11    Port 11 Clear bit
: GPIOB_BC_CR10   %1 10 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR10    Port 10 Clear bit
: GPIOB_BC_CR9   %1 9 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR9    Port 9 Clear bit
: GPIOB_BC_CR8   %1 8 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR8    Port 8 Clear bit
: GPIOB_BC_CR7   %1 7 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR7    Port 7 Clear bit
: GPIOB_BC_CR6   %1 6 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR6    Port 6 Clear bit
: GPIOB_BC_CR5   %1 5 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR5    Port 5 Clear bit
: GPIOB_BC_CR4   %1 4 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR4    Port 4 Clear bit
: GPIOB_BC_CR3   %1 3 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR3    Port 3 Clear bit
: GPIOB_BC_CR2   %1 2 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR2    Port 2 Clear bit
: GPIOB_BC_CR1   %1 1 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR1    Port 1 Clear bit
: GPIOB_BC_CR0   %1 0 lshift GPIOB_BC bis! ;  \ GPIOB_BC_CR0    Port 0 Clear bit

\ GPIOB_LOCK (read-write)
: GPIOB_LOCK_LKK   %1 16 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LKK    Lock sequence key  
: GPIOB_LOCK_LK15   %1 15 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK15    Port Lock bit 15
: GPIOB_LOCK_LK14   %1 14 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK14    Port Lock bit 14
: GPIOB_LOCK_LK13   %1 13 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK13    Port Lock bit 13
: GPIOB_LOCK_LK12   %1 12 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK12    Port Lock bit 12
: GPIOB_LOCK_LK11   %1 11 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK11    Port Lock bit 11
: GPIOB_LOCK_LK10   %1 10 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK10    Port Lock bit 10
: GPIOB_LOCK_LK9   %1 9 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK9    Port Lock bit 9
: GPIOB_LOCK_LK8   %1 8 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK8    Port Lock bit 8
: GPIOB_LOCK_LK7   %1 7 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK7    Port Lock bit 7
: GPIOB_LOCK_LK6   %1 6 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK6    Port Lock bit 6
: GPIOB_LOCK_LK5   %1 5 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK5    Port Lock bit 5
: GPIOB_LOCK_LK4   %1 4 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK4    Port Lock bit 4
: GPIOB_LOCK_LK3   %1 3 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK3    Port Lock bit 3
: GPIOB_LOCK_LK2   %1 2 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK2    Port Lock bit 2
: GPIOB_LOCK_LK1   %1 1 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK1    Port Lock bit 1
: GPIOB_LOCK_LK0   %1 0 lshift GPIOB_LOCK bis! ;  \ GPIOB_LOCK_LK0    Port Lock bit 0

\ GPIOC_CTL0 (read-write)
: GPIOC_CTL0_CTL7   ( %XX -- ) 30 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL7    Port x configuration bits x =  7
: GPIOC_CTL0_MD7   ( %XX -- ) 28 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD7    Port x mode bits x =  7
: GPIOC_CTL0_CTL6   ( %XX -- ) 26 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL6    Port x configuration bits x =  6
: GPIOC_CTL0_MD6   ( %XX -- ) 24 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD6    Port x mode bits x =  6
: GPIOC_CTL0_CTL5   ( %XX -- ) 22 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL5    Port x configuration bits x =  5
: GPIOC_CTL0_MD5   ( %XX -- ) 20 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD5    Port x mode bits x =  5
: GPIOC_CTL0_CTL4   ( %XX -- ) 18 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL4    Port x configuration bits x =  4
: GPIOC_CTL0_MD4   ( %XX -- ) 16 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD4    Port x mode bits x =  4
: GPIOC_CTL0_CTL3   ( %XX -- ) 14 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL3    Port x configuration bits x =  3
: GPIOC_CTL0_MD3   ( %XX -- ) 12 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD3    Port x mode bits x =  3 
: GPIOC_CTL0_CTL2   ( %XX -- ) 10 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL2    Port x configuration bits x =  2
: GPIOC_CTL0_MD2   ( %XX -- ) 8 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD2    Port x mode bits x =  2 
: GPIOC_CTL0_CTL1   ( %XX -- ) 6 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL1    Port x configuration bits x =  1
: GPIOC_CTL0_MD1   ( %XX -- ) 4 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD1    Port x mode bits x =  1
: GPIOC_CTL0_CTL0   ( %XX -- ) 2 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_CTL0    Port x configuration bits x =  0
: GPIOC_CTL0_MD0   ( %XX -- ) 0 lshift GPIOC_CTL0 bis! ;  \ GPIOC_CTL0_MD0    Port x mode bits x =  0

\ GPIOC_CTL1 (read-write)
: GPIOC_CTL1_CTL15   ( %XX -- ) 30 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL15    Port x configuration bits x =  15
: GPIOC_CTL1_MD15   ( %XX -- ) 28 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD15    Port x mode bits x =  15
: GPIOC_CTL1_CTL14   ( %XX -- ) 26 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL14    Port x configuration bits x =  14
: GPIOC_CTL1_MD14   ( %XX -- ) 24 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD14    Port x mode bits x =  14
: GPIOC_CTL1_CTL13   ( %XX -- ) 22 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL13    Port x configuration bits x =  13
: GPIOC_CTL1_MD13   ( %XX -- ) 20 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD13    Port x mode bits x =  13
: GPIOC_CTL1_CTL12   ( %XX -- ) 18 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL12    Port x configuration bits x =  12
: GPIOC_CTL1_MD12   ( %XX -- ) 16 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD12    Port x mode bits x =  12
: GPIOC_CTL1_CTL11   ( %XX -- ) 14 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL11    Port x configuration bits x =  11
: GPIOC_CTL1_MD11   ( %XX -- ) 12 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD11    Port x mode bits x =  11 
: GPIOC_CTL1_CTL10   ( %XX -- ) 10 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL10    Port x configuration bits x =  10
: GPIOC_CTL1_MD10   ( %XX -- ) 8 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD10    Port x mode bits x =  10 
: GPIOC_CTL1_CTL9   ( %XX -- ) 6 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL9    Port x configuration bits x =  9
: GPIOC_CTL1_MD9   ( %XX -- ) 4 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD9    Port x mode bits x =  9
: GPIOC_CTL1_CTL8   ( %XX -- ) 2 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_CTL8    Port x configuration bits x =  8
: GPIOC_CTL1_MD8   ( %XX -- ) 0 lshift GPIOC_CTL1 bis! ;  \ GPIOC_CTL1_MD8    Port x mode bits x =  8

\ GPIOC_ISTAT (read-only)
: GPIOC_ISTAT_ISTAT15   %1 15 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT15    Port input status
: GPIOC_ISTAT_ISTAT14   %1 14 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT14    Port input status
: GPIOC_ISTAT_ISTAT13   %1 13 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT13    Port input status
: GPIOC_ISTAT_ISTAT12   %1 12 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT12    Port input status
: GPIOC_ISTAT_ISTAT11   %1 11 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT11    Port input status
: GPIOC_ISTAT_ISTAT10   %1 10 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT10    Port input status
: GPIOC_ISTAT_ISTAT9   %1 9 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT9    Port input status
: GPIOC_ISTAT_ISTAT8   %1 8 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT8    Port input status
: GPIOC_ISTAT_ISTAT7   %1 7 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT7    Port input status
: GPIOC_ISTAT_ISTAT6   %1 6 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT6    Port input status
: GPIOC_ISTAT_ISTAT5   %1 5 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT5    Port input status
: GPIOC_ISTAT_ISTAT4   %1 4 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT4    Port input status
: GPIOC_ISTAT_ISTAT3   %1 3 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT3    Port input status
: GPIOC_ISTAT_ISTAT2   %1 2 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT2    Port input status
: GPIOC_ISTAT_ISTAT1   %1 1 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT1    Port input status
: GPIOC_ISTAT_ISTAT0   %1 0 lshift GPIOC_ISTAT bis! ;  \ GPIOC_ISTAT_ISTAT0    Port input status

\ GPIOC_OCTL (read-write)
: GPIOC_OCTL_OCTL15   %1 15 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL15    Port output control
: GPIOC_OCTL_OCTL14   %1 14 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL14    Port output control
: GPIOC_OCTL_OCTL13   %1 13 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL13    Port output control
: GPIOC_OCTL_OCTL12   %1 12 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL12    Port output control
: GPIOC_OCTL_OCTL11   %1 11 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL11    Port output control
: GPIOC_OCTL_OCTL10   %1 10 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL10    Port output control
: GPIOC_OCTL_OCTL9   %1 9 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL9    Port output control
: GPIOC_OCTL_OCTL8   %1 8 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL8    Port output control
: GPIOC_OCTL_OCTL7   %1 7 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL7    Port output control
: GPIOC_OCTL_OCTL6   %1 6 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL6    Port output control
: GPIOC_OCTL_OCTL5   %1 5 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL5    Port output control
: GPIOC_OCTL_OCTL4   %1 4 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL4    Port output control
: GPIOC_OCTL_OCTL3   %1 3 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL3    Port output control
: GPIOC_OCTL_OCTL2   %1 2 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL2    Port output control
: GPIOC_OCTL_OCTL1   %1 1 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL1    Port output control
: GPIOC_OCTL_OCTL0   %1 0 lshift GPIOC_OCTL bis! ;  \ GPIOC_OCTL_OCTL0    Port output control

\ GPIOC_BOP (write-only)
: GPIOC_BOP_CR15   %1 31 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR15    Port 15 Clear bit
: GPIOC_BOP_CR14   %1 30 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR14    Port 14 Clear bit
: GPIOC_BOP_CR13   %1 29 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR13    Port 13 Clear bit
: GPIOC_BOP_CR12   %1 28 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR12    Port 12 Clear bit
: GPIOC_BOP_CR11   %1 27 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR11    Port 11 Clear bit
: GPIOC_BOP_CR10   %1 26 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR10    Port 10 Clear bit
: GPIOC_BOP_CR9   %1 25 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR9    Port 9 Clear bit
: GPIOC_BOP_CR8   %1 24 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR8    Port 8 Clear bit
: GPIOC_BOP_CR7   %1 23 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR7    Port 7 Clear bit
: GPIOC_BOP_CR6   %1 22 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR6    Port 6 Clear bit
: GPIOC_BOP_CR5   %1 21 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR5    Port 5 Clear bit
: GPIOC_BOP_CR4   %1 20 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR4    Port 4 Clear bit
: GPIOC_BOP_CR3   %1 19 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR3    Port 3 Clear bit
: GPIOC_BOP_CR2   %1 18 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR2    Port 2 Clear bit
: GPIOC_BOP_CR1   %1 17 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR1    Port 1 Clear bit
: GPIOC_BOP_CR0   %1 16 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_CR0    Port 0 Clear bit
: GPIOC_BOP_BOP15   %1 15 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP15    Port 15 Set bit
: GPIOC_BOP_BOP14   %1 14 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP14    Port 14 Set bit
: GPIOC_BOP_BOP13   %1 13 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP13    Port 13 Set bit
: GPIOC_BOP_BOP12   %1 12 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP12    Port 12 Set bit
: GPIOC_BOP_BOP11   %1 11 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP11    Port 11 Set bit
: GPIOC_BOP_BOP10   %1 10 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP10    Port 10 Set bit
: GPIOC_BOP_BOP9   %1 9 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP9    Port 9 Set bit
: GPIOC_BOP_BOP8   %1 8 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP8    Port 8 Set bit
: GPIOC_BOP_BOP7   %1 7 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP7    Port 7 Set bit
: GPIOC_BOP_BOP6   %1 6 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP6    Port 6 Set bit
: GPIOC_BOP_BOP5   %1 5 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP5    Port 5 Set bit
: GPIOC_BOP_BOP4   %1 4 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP4    Port 4 Set bit
: GPIOC_BOP_BOP3   %1 3 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP3    Port 3 Set bit
: GPIOC_BOP_BOP2   %1 2 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP2    Port 2 Set bit
: GPIOC_BOP_BOP1   %1 1 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP1    Port 1 Set bit
: GPIOC_BOP_BOP0   %1 0 lshift GPIOC_BOP bis! ;  \ GPIOC_BOP_BOP0    Port 0 Set bit

\ GPIOC_BC (write-only)
: GPIOC_BC_CR15   %1 15 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR15    Port 15 Clear bit
: GPIOC_BC_CR14   %1 14 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR14    Port 14 Clear bit
: GPIOC_BC_CR13   %1 13 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR13    Port 13 Clear bit
: GPIOC_BC_CR12   %1 12 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR12    Port 12 Clear bit
: GPIOC_BC_CR11   %1 11 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR11    Port 11 Clear bit
: GPIOC_BC_CR10   %1 10 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR10    Port 10 Clear bit
: GPIOC_BC_CR9   %1 9 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR9    Port 9 Clear bit
: GPIOC_BC_CR8   %1 8 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR8    Port 8 Clear bit
: GPIOC_BC_CR7   %1 7 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR7    Port 7 Clear bit
: GPIOC_BC_CR6   %1 6 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR6    Port 6 Clear bit
: GPIOC_BC_CR5   %1 5 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR5    Port 5 Clear bit
: GPIOC_BC_CR4   %1 4 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR4    Port 4 Clear bit
: GPIOC_BC_CR3   %1 3 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR3    Port 3 Clear bit
: GPIOC_BC_CR2   %1 2 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR2    Port 2 Clear bit
: GPIOC_BC_CR1   %1 1 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR1    Port 1 Clear bit
: GPIOC_BC_CR0   %1 0 lshift GPIOC_BC bis! ;  \ GPIOC_BC_CR0    Port 0 Clear bit

\ GPIOC_LOCK (read-write)
: GPIOC_LOCK_LKK   %1 16 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LKK    Lock sequence key  
: GPIOC_LOCK_LK15   %1 15 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK15    Port Lock bit 15
: GPIOC_LOCK_LK14   %1 14 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK14    Port Lock bit 14
: GPIOC_LOCK_LK13   %1 13 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK13    Port Lock bit 13
: GPIOC_LOCK_LK12   %1 12 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK12    Port Lock bit 12
: GPIOC_LOCK_LK11   %1 11 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK11    Port Lock bit 11
: GPIOC_LOCK_LK10   %1 10 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK10    Port Lock bit 10
: GPIOC_LOCK_LK9   %1 9 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK9    Port Lock bit 9
: GPIOC_LOCK_LK8   %1 8 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK8    Port Lock bit 8
: GPIOC_LOCK_LK7   %1 7 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK7    Port Lock bit 7
: GPIOC_LOCK_LK6   %1 6 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK6    Port Lock bit 6
: GPIOC_LOCK_LK5   %1 5 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK5    Port Lock bit 5
: GPIOC_LOCK_LK4   %1 4 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK4    Port Lock bit 4
: GPIOC_LOCK_LK3   %1 3 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK3    Port Lock bit 3
: GPIOC_LOCK_LK2   %1 2 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK2    Port Lock bit 2
: GPIOC_LOCK_LK1   %1 1 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK1    Port Lock bit 1
: GPIOC_LOCK_LK0   %1 0 lshift GPIOC_LOCK bis! ;  \ GPIOC_LOCK_LK0    Port Lock bit 0

\ GPIOD_CTL0 (read-write)
: GPIOD_CTL0_CTL7   ( %XX -- ) 30 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL7    Port x configuration bits x =  7
: GPIOD_CTL0_MD7   ( %XX -- ) 28 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD7    Port x mode bits x =  7
: GPIOD_CTL0_CTL6   ( %XX -- ) 26 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL6    Port x configuration bits x =  6
: GPIOD_CTL0_MD6   ( %XX -- ) 24 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD6    Port x mode bits x =  6
: GPIOD_CTL0_CTL5   ( %XX -- ) 22 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL5    Port x configuration bits x =  5
: GPIOD_CTL0_MD5   ( %XX -- ) 20 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD5    Port x mode bits x =  5
: GPIOD_CTL0_CTL4   ( %XX -- ) 18 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL4    Port x configuration bits x =  4
: GPIOD_CTL0_MD4   ( %XX -- ) 16 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD4    Port x mode bits x =  4
: GPIOD_CTL0_CTL3   ( %XX -- ) 14 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL3    Port x configuration bits x =  3
: GPIOD_CTL0_MD3   ( %XX -- ) 12 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD3    Port x mode bits x =  3 
: GPIOD_CTL0_CTL2   ( %XX -- ) 10 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL2    Port x configuration bits x =  2
: GPIOD_CTL0_MD2   ( %XX -- ) 8 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD2    Port x mode bits x =  2 
: GPIOD_CTL0_CTL1   ( %XX -- ) 6 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL1    Port x configuration bits x =  1
: GPIOD_CTL0_MD1   ( %XX -- ) 4 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD1    Port x mode bits x =  1
: GPIOD_CTL0_CTL0   ( %XX -- ) 2 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_CTL0    Port x configuration bits x =  0
: GPIOD_CTL0_MD0   ( %XX -- ) 0 lshift GPIOD_CTL0 bis! ;  \ GPIOD_CTL0_MD0    Port x mode bits x =  0

\ GPIOD_CTL1 (read-write)
: GPIOD_CTL1_CTL15   ( %XX -- ) 30 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL15    Port x configuration bits x =  15
: GPIOD_CTL1_MD15   ( %XX -- ) 28 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD15    Port x mode bits x =  15
: GPIOD_CTL1_CTL14   ( %XX -- ) 26 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL14    Port x configuration bits x =  14
: GPIOD_CTL1_MD14   ( %XX -- ) 24 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD14    Port x mode bits x =  14
: GPIOD_CTL1_CTL13   ( %XX -- ) 22 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL13    Port x configuration bits x =  13
: GPIOD_CTL1_MD13   ( %XX -- ) 20 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD13    Port x mode bits x =  13
: GPIOD_CTL1_CTL12   ( %XX -- ) 18 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL12    Port x configuration bits x =  12
: GPIOD_CTL1_MD12   ( %XX -- ) 16 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD12    Port x mode bits x =  12
: GPIOD_CTL1_CTL11   ( %XX -- ) 14 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL11    Port x configuration bits x =  11
: GPIOD_CTL1_MD11   ( %XX -- ) 12 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD11    Port x mode bits x =  11 
: GPIOD_CTL1_CTL10   ( %XX -- ) 10 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL10    Port x configuration bits x =  10
: GPIOD_CTL1_MD10   ( %XX -- ) 8 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD10    Port x mode bits x =  10 
: GPIOD_CTL1_CTL9   ( %XX -- ) 6 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL9    Port x configuration bits x =  9
: GPIOD_CTL1_MD9   ( %XX -- ) 4 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD9    Port x mode bits x =  9
: GPIOD_CTL1_CTL8   ( %XX -- ) 2 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_CTL8    Port x configuration bits x =  8
: GPIOD_CTL1_MD8   ( %XX -- ) 0 lshift GPIOD_CTL1 bis! ;  \ GPIOD_CTL1_MD8    Port x mode bits x =  8

\ GPIOD_ISTAT (read-only)
: GPIOD_ISTAT_ISTAT15   %1 15 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT15    Port input status
: GPIOD_ISTAT_ISTAT14   %1 14 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT14    Port input status
: GPIOD_ISTAT_ISTAT13   %1 13 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT13    Port input status
: GPIOD_ISTAT_ISTAT12   %1 12 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT12    Port input status
: GPIOD_ISTAT_ISTAT11   %1 11 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT11    Port input status
: GPIOD_ISTAT_ISTAT10   %1 10 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT10    Port input status
: GPIOD_ISTAT_ISTAT9   %1 9 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT9    Port input status
: GPIOD_ISTAT_ISTAT8   %1 8 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT8    Port input status
: GPIOD_ISTAT_ISTAT7   %1 7 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT7    Port input status
: GPIOD_ISTAT_ISTAT6   %1 6 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT6    Port input status
: GPIOD_ISTAT_ISTAT5   %1 5 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT5    Port input status
: GPIOD_ISTAT_ISTAT4   %1 4 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT4    Port input status
: GPIOD_ISTAT_ISTAT3   %1 3 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT3    Port input status
: GPIOD_ISTAT_ISTAT2   %1 2 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT2    Port input status
: GPIOD_ISTAT_ISTAT1   %1 1 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT1    Port input status
: GPIOD_ISTAT_ISTAT0   %1 0 lshift GPIOD_ISTAT bis! ;  \ GPIOD_ISTAT_ISTAT0    Port input status

\ GPIOD_OCTL (read-write)
: GPIOD_OCTL_OCTL15   %1 15 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL15    Port output control
: GPIOD_OCTL_OCTL14   %1 14 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL14    Port output control
: GPIOD_OCTL_OCTL13   %1 13 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL13    Port output control
: GPIOD_OCTL_OCTL12   %1 12 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL12    Port output control
: GPIOD_OCTL_OCTL11   %1 11 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL11    Port output control
: GPIOD_OCTL_OCTL10   %1 10 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL10    Port output control
: GPIOD_OCTL_OCTL9   %1 9 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL9    Port output control
: GPIOD_OCTL_OCTL8   %1 8 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL8    Port output control
: GPIOD_OCTL_OCTL7   %1 7 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL7    Port output control
: GPIOD_OCTL_OCTL6   %1 6 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL6    Port output control
: GPIOD_OCTL_OCTL5   %1 5 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL5    Port output control
: GPIOD_OCTL_OCTL4   %1 4 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL4    Port output control
: GPIOD_OCTL_OCTL3   %1 3 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL3    Port output control
: GPIOD_OCTL_OCTL2   %1 2 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL2    Port output control
: GPIOD_OCTL_OCTL1   %1 1 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL1    Port output control
: GPIOD_OCTL_OCTL0   %1 0 lshift GPIOD_OCTL bis! ;  \ GPIOD_OCTL_OCTL0    Port output control

\ GPIOD_BOP (write-only)
: GPIOD_BOP_CR15   %1 31 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR15    Port 15 Clear bit
: GPIOD_BOP_CR14   %1 30 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR14    Port 14 Clear bit
: GPIOD_BOP_CR13   %1 29 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR13    Port 13 Clear bit
: GPIOD_BOP_CR12   %1 28 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR12    Port 12 Clear bit
: GPIOD_BOP_CR11   %1 27 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR11    Port 11 Clear bit
: GPIOD_BOP_CR10   %1 26 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR10    Port 10 Clear bit
: GPIOD_BOP_CR9   %1 25 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR9    Port 9 Clear bit
: GPIOD_BOP_CR8   %1 24 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR8    Port 8 Clear bit
: GPIOD_BOP_CR7   %1 23 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR7    Port 7 Clear bit
: GPIOD_BOP_CR6   %1 22 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR6    Port 6 Clear bit
: GPIOD_BOP_CR5   %1 21 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR5    Port 5 Clear bit
: GPIOD_BOP_CR4   %1 20 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR4    Port 4 Clear bit
: GPIOD_BOP_CR3   %1 19 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR3    Port 3 Clear bit
: GPIOD_BOP_CR2   %1 18 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR2    Port 2 Clear bit
: GPIOD_BOP_CR1   %1 17 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR1    Port 1 Clear bit
: GPIOD_BOP_CR0   %1 16 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_CR0    Port 0 Clear bit
: GPIOD_BOP_BOP15   %1 15 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP15    Port 15 Set bit
: GPIOD_BOP_BOP14   %1 14 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP14    Port 14 Set bit
: GPIOD_BOP_BOP13   %1 13 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP13    Port 13 Set bit
: GPIOD_BOP_BOP12   %1 12 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP12    Port 12 Set bit
: GPIOD_BOP_BOP11   %1 11 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP11    Port 11 Set bit
: GPIOD_BOP_BOP10   %1 10 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP10    Port 10 Set bit
: GPIOD_BOP_BOP9   %1 9 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP9    Port 9 Set bit
: GPIOD_BOP_BOP8   %1 8 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP8    Port 8 Set bit
: GPIOD_BOP_BOP7   %1 7 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP7    Port 7 Set bit
: GPIOD_BOP_BOP6   %1 6 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP6    Port 6 Set bit
: GPIOD_BOP_BOP5   %1 5 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP5    Port 5 Set bit
: GPIOD_BOP_BOP4   %1 4 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP4    Port 4 Set bit
: GPIOD_BOP_BOP3   %1 3 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP3    Port 3 Set bit
: GPIOD_BOP_BOP2   %1 2 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP2    Port 2 Set bit
: GPIOD_BOP_BOP1   %1 1 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP1    Port 1 Set bit
: GPIOD_BOP_BOP0   %1 0 lshift GPIOD_BOP bis! ;  \ GPIOD_BOP_BOP0    Port 0 Set bit

\ GPIOD_BC (write-only)
: GPIOD_BC_CR15   %1 15 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR15    Port 15 Clear bit
: GPIOD_BC_CR14   %1 14 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR14    Port 14 Clear bit
: GPIOD_BC_CR13   %1 13 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR13    Port 13 Clear bit
: GPIOD_BC_CR12   %1 12 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR12    Port 12 Clear bit
: GPIOD_BC_CR11   %1 11 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR11    Port 11 Clear bit
: GPIOD_BC_CR10   %1 10 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR10    Port 10 Clear bit
: GPIOD_BC_CR9   %1 9 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR9    Port 9 Clear bit
: GPIOD_BC_CR8   %1 8 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR8    Port 8 Clear bit
: GPIOD_BC_CR7   %1 7 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR7    Port 7 Clear bit
: GPIOD_BC_CR6   %1 6 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR6    Port 6 Clear bit
: GPIOD_BC_CR5   %1 5 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR5    Port 5 Clear bit
: GPIOD_BC_CR4   %1 4 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR4    Port 4 Clear bit
: GPIOD_BC_CR3   %1 3 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR3    Port 3 Clear bit
: GPIOD_BC_CR2   %1 2 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR2    Port 2 Clear bit
: GPIOD_BC_CR1   %1 1 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR1    Port 1 Clear bit
: GPIOD_BC_CR0   %1 0 lshift GPIOD_BC bis! ;  \ GPIOD_BC_CR0    Port 0 Clear bit

\ GPIOD_LOCK (read-write)
: GPIOD_LOCK_LKK   %1 16 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LKK    Lock sequence key  
: GPIOD_LOCK_LK15   %1 15 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK15    Port Lock bit 15
: GPIOD_LOCK_LK14   %1 14 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK14    Port Lock bit 14
: GPIOD_LOCK_LK13   %1 13 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK13    Port Lock bit 13
: GPIOD_LOCK_LK12   %1 12 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK12    Port Lock bit 12
: GPIOD_LOCK_LK11   %1 11 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK11    Port Lock bit 11
: GPIOD_LOCK_LK10   %1 10 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK10    Port Lock bit 10
: GPIOD_LOCK_LK9   %1 9 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK9    Port Lock bit 9
: GPIOD_LOCK_LK8   %1 8 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK8    Port Lock bit 8
: GPIOD_LOCK_LK7   %1 7 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK7    Port Lock bit 7
: GPIOD_LOCK_LK6   %1 6 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK6    Port Lock bit 6
: GPIOD_LOCK_LK5   %1 5 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK5    Port Lock bit 5
: GPIOD_LOCK_LK4   %1 4 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK4    Port Lock bit 4
: GPIOD_LOCK_LK3   %1 3 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK3    Port Lock bit 3
: GPIOD_LOCK_LK2   %1 2 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK2    Port Lock bit 2
: GPIOD_LOCK_LK1   %1 1 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK1    Port Lock bit 1
: GPIOD_LOCK_LK0   %1 0 lshift GPIOD_LOCK bis! ;  \ GPIOD_LOCK_LK0    Port Lock bit 0

\ GPIOE_CTL0 (read-write)
: GPIOE_CTL0_CTL7   ( %XX -- ) 30 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL7    Port x configuration bits x =  7
: GPIOE_CTL0_MD7   ( %XX -- ) 28 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD7    Port x mode bits x =  7
: GPIOE_CTL0_CTL6   ( %XX -- ) 26 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL6    Port x configuration bits x =  6
: GPIOE_CTL0_MD6   ( %XX -- ) 24 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD6    Port x mode bits x =  6
: GPIOE_CTL0_CTL5   ( %XX -- ) 22 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL5    Port x configuration bits x =  5
: GPIOE_CTL0_MD5   ( %XX -- ) 20 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD5    Port x mode bits x =  5
: GPIOE_CTL0_CTL4   ( %XX -- ) 18 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL4    Port x configuration bits x =  4
: GPIOE_CTL0_MD4   ( %XX -- ) 16 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD4    Port x mode bits x =  4
: GPIOE_CTL0_CTL3   ( %XX -- ) 14 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL3    Port x configuration bits x =  3
: GPIOE_CTL0_MD3   ( %XX -- ) 12 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD3    Port x mode bits x =  3 
: GPIOE_CTL0_CTL2   ( %XX -- ) 10 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL2    Port x configuration bits x =  2
: GPIOE_CTL0_MD2   ( %XX -- ) 8 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD2    Port x mode bits x =  2 
: GPIOE_CTL0_CTL1   ( %XX -- ) 6 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL1    Port x configuration bits x =  1
: GPIOE_CTL0_MD1   ( %XX -- ) 4 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD1    Port x mode bits x =  1
: GPIOE_CTL0_CTL0   ( %XX -- ) 2 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_CTL0    Port x configuration bits x =  0
: GPIOE_CTL0_MD0   ( %XX -- ) 0 lshift GPIOE_CTL0 bis! ;  \ GPIOE_CTL0_MD0    Port x mode bits x =  0

\ GPIOE_CTL1 (read-write)
: GPIOE_CTL1_CTL15   ( %XX -- ) 30 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL15    Port x configuration bits x =  15
: GPIOE_CTL1_MD15   ( %XX -- ) 28 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD15    Port x mode bits x =  15
: GPIOE_CTL1_CTL14   ( %XX -- ) 26 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL14    Port x configuration bits x =  14
: GPIOE_CTL1_MD14   ( %XX -- ) 24 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD14    Port x mode bits x =  14
: GPIOE_CTL1_CTL13   ( %XX -- ) 22 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL13    Port x configuration bits x =  13
: GPIOE_CTL1_MD13   ( %XX -- ) 20 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD13    Port x mode bits x =  13
: GPIOE_CTL1_CTL12   ( %XX -- ) 18 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL12    Port x configuration bits x =  12
: GPIOE_CTL1_MD12   ( %XX -- ) 16 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD12    Port x mode bits x =  12
: GPIOE_CTL1_CTL11   ( %XX -- ) 14 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL11    Port x configuration bits x =  11
: GPIOE_CTL1_MD11   ( %XX -- ) 12 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD11    Port x mode bits x =  11 
: GPIOE_CTL1_CTL10   ( %XX -- ) 10 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL10    Port x configuration bits x =  10
: GPIOE_CTL1_MD10   ( %XX -- ) 8 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD10    Port x mode bits x =  10 
: GPIOE_CTL1_CTL9   ( %XX -- ) 6 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL9    Port x configuration bits x =  9
: GPIOE_CTL1_MD9   ( %XX -- ) 4 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD9    Port x mode bits x =  9
: GPIOE_CTL1_CTL8   ( %XX -- ) 2 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_CTL8    Port x configuration bits x =  8
: GPIOE_CTL1_MD8   ( %XX -- ) 0 lshift GPIOE_CTL1 bis! ;  \ GPIOE_CTL1_MD8    Port x mode bits x =  8

\ GPIOE_ISTAT (read-only)
: GPIOE_ISTAT_ISTAT15   %1 15 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT15    Port input status
: GPIOE_ISTAT_ISTAT14   %1 14 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT14    Port input status
: GPIOE_ISTAT_ISTAT13   %1 13 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT13    Port input status
: GPIOE_ISTAT_ISTAT12   %1 12 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT12    Port input status
: GPIOE_ISTAT_ISTAT11   %1 11 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT11    Port input status
: GPIOE_ISTAT_ISTAT10   %1 10 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT10    Port input status
: GPIOE_ISTAT_ISTAT9   %1 9 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT9    Port input status
: GPIOE_ISTAT_ISTAT8   %1 8 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT8    Port input status
: GPIOE_ISTAT_ISTAT7   %1 7 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT7    Port input status
: GPIOE_ISTAT_ISTAT6   %1 6 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT6    Port input status
: GPIOE_ISTAT_ISTAT5   %1 5 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT5    Port input status
: GPIOE_ISTAT_ISTAT4   %1 4 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT4    Port input status
: GPIOE_ISTAT_ISTAT3   %1 3 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT3    Port input status
: GPIOE_ISTAT_ISTAT2   %1 2 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT2    Port input status
: GPIOE_ISTAT_ISTAT1   %1 1 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT1    Port input status
: GPIOE_ISTAT_ISTAT0   %1 0 lshift GPIOE_ISTAT bis! ;  \ GPIOE_ISTAT_ISTAT0    Port input status

\ GPIOE_OCTL (read-write)
: GPIOE_OCTL_OCTL15   %1 15 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL15    Port output control
: GPIOE_OCTL_OCTL14   %1 14 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL14    Port output control
: GPIOE_OCTL_OCTL13   %1 13 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL13    Port output control
: GPIOE_OCTL_OCTL12   %1 12 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL12    Port output control
: GPIOE_OCTL_OCTL11   %1 11 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL11    Port output control
: GPIOE_OCTL_OCTL10   %1 10 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL10    Port output control
: GPIOE_OCTL_OCTL9   %1 9 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL9    Port output control
: GPIOE_OCTL_OCTL8   %1 8 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL8    Port output control
: GPIOE_OCTL_OCTL7   %1 7 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL7    Port output control
: GPIOE_OCTL_OCTL6   %1 6 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL6    Port output control
: GPIOE_OCTL_OCTL5   %1 5 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL5    Port output control
: GPIOE_OCTL_OCTL4   %1 4 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL4    Port output control
: GPIOE_OCTL_OCTL3   %1 3 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL3    Port output control
: GPIOE_OCTL_OCTL2   %1 2 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL2    Port output control
: GPIOE_OCTL_OCTL1   %1 1 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL1    Port output control
: GPIOE_OCTL_OCTL0   %1 0 lshift GPIOE_OCTL bis! ;  \ GPIOE_OCTL_OCTL0    Port output control

\ GPIOE_BOP (write-only)
: GPIOE_BOP_CR15   %1 31 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR15    Port 15 Clear bit
: GPIOE_BOP_CR14   %1 30 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR14    Port 14 Clear bit
: GPIOE_BOP_CR13   %1 29 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR13    Port 13 Clear bit
: GPIOE_BOP_CR12   %1 28 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR12    Port 12 Clear bit
: GPIOE_BOP_CR11   %1 27 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR11    Port 11 Clear bit
: GPIOE_BOP_CR10   %1 26 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR10    Port 10 Clear bit
: GPIOE_BOP_CR9   %1 25 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR9    Port 9 Clear bit
: GPIOE_BOP_CR8   %1 24 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR8    Port 8 Clear bit
: GPIOE_BOP_CR7   %1 23 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR7    Port 7 Clear bit
: GPIOE_BOP_CR6   %1 22 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR6    Port 6 Clear bit
: GPIOE_BOP_CR5   %1 21 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR5    Port 5 Clear bit
: GPIOE_BOP_CR4   %1 20 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR4    Port 4 Clear bit
: GPIOE_BOP_CR3   %1 19 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR3    Port 3 Clear bit
: GPIOE_BOP_CR2   %1 18 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR2    Port 2 Clear bit
: GPIOE_BOP_CR1   %1 17 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR1    Port 1 Clear bit
: GPIOE_BOP_CR0   %1 16 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_CR0    Port 0 Clear bit
: GPIOE_BOP_BOP15   %1 15 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP15    Port 15 Set bit
: GPIOE_BOP_BOP14   %1 14 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP14    Port 14 Set bit
: GPIOE_BOP_BOP13   %1 13 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP13    Port 13 Set bit
: GPIOE_BOP_BOP12   %1 12 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP12    Port 12 Set bit
: GPIOE_BOP_BOP11   %1 11 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP11    Port 11 Set bit
: GPIOE_BOP_BOP10   %1 10 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP10    Port 10 Set bit
: GPIOE_BOP_BOP9   %1 9 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP9    Port 9 Set bit
: GPIOE_BOP_BOP8   %1 8 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP8    Port 8 Set bit
: GPIOE_BOP_BOP7   %1 7 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP7    Port 7 Set bit
: GPIOE_BOP_BOP6   %1 6 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP6    Port 6 Set bit
: GPIOE_BOP_BOP5   %1 5 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP5    Port 5 Set bit
: GPIOE_BOP_BOP4   %1 4 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP4    Port 4 Set bit
: GPIOE_BOP_BOP3   %1 3 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP3    Port 3 Set bit
: GPIOE_BOP_BOP2   %1 2 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP2    Port 2 Set bit
: GPIOE_BOP_BOP1   %1 1 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP1    Port 1 Set bit
: GPIOE_BOP_BOP0   %1 0 lshift GPIOE_BOP bis! ;  \ GPIOE_BOP_BOP0    Port 0 Set bit

\ GPIOE_BC (write-only)
: GPIOE_BC_CR15   %1 15 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR15    Port 15 Clear bit
: GPIOE_BC_CR14   %1 14 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR14    Port 14 Clear bit
: GPIOE_BC_CR13   %1 13 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR13    Port 13 Clear bit
: GPIOE_BC_CR12   %1 12 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR12    Port 12 Clear bit
: GPIOE_BC_CR11   %1 11 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR11    Port 11 Clear bit
: GPIOE_BC_CR10   %1 10 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR10    Port 10 Clear bit
: GPIOE_BC_CR9   %1 9 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR9    Port 9 Clear bit
: GPIOE_BC_CR8   %1 8 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR8    Port 8 Clear bit
: GPIOE_BC_CR7   %1 7 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR7    Port 7 Clear bit
: GPIOE_BC_CR6   %1 6 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR6    Port 6 Clear bit
: GPIOE_BC_CR5   %1 5 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR5    Port 5 Clear bit
: GPIOE_BC_CR4   %1 4 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR4    Port 4 Clear bit
: GPIOE_BC_CR3   %1 3 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR3    Port 3 Clear bit
: GPIOE_BC_CR2   %1 2 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR2    Port 2 Clear bit
: GPIOE_BC_CR1   %1 1 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR1    Port 1 Clear bit
: GPIOE_BC_CR0   %1 0 lshift GPIOE_BC bis! ;  \ GPIOE_BC_CR0    Port 0 Clear bit

\ GPIOE_LOCK (read-write)
: GPIOE_LOCK_LKK   %1 16 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LKK    Lock sequence key  
: GPIOE_LOCK_LK15   %1 15 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK15    Port Lock bit 15
: GPIOE_LOCK_LK14   %1 14 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK14    Port Lock bit 14
: GPIOE_LOCK_LK13   %1 13 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK13    Port Lock bit 13
: GPIOE_LOCK_LK12   %1 12 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK12    Port Lock bit 12
: GPIOE_LOCK_LK11   %1 11 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK11    Port Lock bit 11
: GPIOE_LOCK_LK10   %1 10 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK10    Port Lock bit 10
: GPIOE_LOCK_LK9   %1 9 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK9    Port Lock bit 9
: GPIOE_LOCK_LK8   %1 8 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK8    Port Lock bit 8
: GPIOE_LOCK_LK7   %1 7 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK7    Port Lock bit 7
: GPIOE_LOCK_LK6   %1 6 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK6    Port Lock bit 6
: GPIOE_LOCK_LK5   %1 5 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK5    Port Lock bit 5
: GPIOE_LOCK_LK4   %1 4 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK4    Port Lock bit 4
: GPIOE_LOCK_LK3   %1 3 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK3    Port Lock bit 3
: GPIOE_LOCK_LK2   %1 2 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK2    Port Lock bit 2
: GPIOE_LOCK_LK1   %1 1 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK1    Port Lock bit 1
: GPIOE_LOCK_LK0   %1 0 lshift GPIOE_LOCK bis! ;  \ GPIOE_LOCK_LK0    Port Lock bit 0

\ I2C0_CTL0 (read-write)
: I2C0_CTL0_SRESET   %1 15 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_SRESET    Software reset
: I2C0_CTL0_SALT   %1 13 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_SALT    SMBus alert
: I2C0_CTL0_PECTRANS   %1 12 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_PECTRANS    PEC Transfer
: I2C0_CTL0_POAP   %1 11 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_POAP    Position of ACK and PEC when receiving
: I2C0_CTL0_ACKEN   %1 10 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_ACKEN    Whether or not to send an ACK
: I2C0_CTL0_STOP   %1 9 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_STOP    Generate a STOP condition on I2C bus
: I2C0_CTL0_START   %1 8 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_START    Generate a START condition on I2C bus
: I2C0_CTL0_SS   %1 7 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_SS    Whether to stretch SCL low when data is not ready in slave mode
: I2C0_CTL0_GCEN   %1 6 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_GCEN    Whether or not to response to a General Call $00
: I2C0_CTL0_PECEN   %1 5 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_PECEN    PEC Calculation Switch
: I2C0_CTL0_ARPEN   %1 4 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_ARPEN    ARP protocol in SMBus switch
: I2C0_CTL0_SMBSEL   %1 3 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_SMBSEL    SMBusType Selection
: I2C0_CTL0_SMBEN   %1 1 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_SMBEN    SMBus/I2C mode switch
: I2C0_CTL0_I2CEN   %1 0 lshift I2C0_CTL0 bis! ;  \ I2C0_CTL0_I2CEN    I2C peripheral enable

\ I2C0_CTL1 (read-write)
: I2C0_CTL1_DMALST   %1 12 lshift I2C0_CTL1 bis! ;  \ I2C0_CTL1_DMALST    Flag indicating DMA last transfer
: I2C0_CTL1_DMAON   %1 11 lshift I2C0_CTL1 bis! ;  \ I2C0_CTL1_DMAON    DMA mode switch
: I2C0_CTL1_BUFIE   %1 10 lshift I2C0_CTL1 bis! ;  \ I2C0_CTL1_BUFIE    Buffer interrupt enable
: I2C0_CTL1_EVIE   %1 9 lshift I2C0_CTL1 bis! ;  \ I2C0_CTL1_EVIE    Event interrupt enable
: I2C0_CTL1_ERRIE   %1 8 lshift I2C0_CTL1 bis! ;  \ I2C0_CTL1_ERRIE    Error interrupt enable
: I2C0_CTL1_I2CCLK   ( %XXXXXX -- ) 0 lshift I2C0_CTL1 bis! ;  \ I2C0_CTL1_I2CCLK    I2C Peripheral clock frequency

\ I2C0_SADDR0 (read-write)
: I2C0_SADDR0_ADDFORMAT   %1 15 lshift I2C0_SADDR0 bis! ;  \ I2C0_SADDR0_ADDFORMAT    Address mode for the I2C slave
: I2C0_SADDR0_ADDRESS9_8   ( %XX -- ) 8 lshift I2C0_SADDR0 bis! ;  \ I2C0_SADDR0_ADDRESS9_8    Highest two bits of a 10-bit address
: I2C0_SADDR0_ADDRESS7_1   ( %XXXXXXX -- ) 1 lshift I2C0_SADDR0 bis! ;  \ I2C0_SADDR0_ADDRESS7_1    7-bit address or bits 7:1 of a 10-bit address
: I2C0_SADDR0_ADDRESS0   %1 0 lshift I2C0_SADDR0 bis! ;  \ I2C0_SADDR0_ADDRESS0    Bit 0 of a 10-bit address

\ I2C0_SADDR1 (read-write)
: I2C0_SADDR1_ADDRESS2   ( %XXXXXXX -- ) 1 lshift I2C0_SADDR1 bis! ;  \ I2C0_SADDR1_ADDRESS2    Second I2C address for the slave in Dual-Address mode
: I2C0_SADDR1_DUADEN   %1 0 lshift I2C0_SADDR1 bis! ;  \ I2C0_SADDR1_DUADEN    Dual-Address mode switch

\ I2C0_DATA (read-write)
: I2C0_DATA_TRB   ( %XXXXXXXX -- ) 0 lshift I2C0_DATA bis! ;  \ I2C0_DATA_TRB    Transmission or reception data buffer register

\ I2C0_STAT0 ()
: I2C0_STAT0_SMBALT   %1 15 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_SMBALT    SMBus Alert status
: I2C0_STAT0_SMBTO   %1 14 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_SMBTO    Timeout signal in SMBus mode
: I2C0_STAT0_PECERR   %1 12 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_PECERR    PEC error when receiving data
: I2C0_STAT0_OUERR   %1 11 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_OUERR    Over-run or under-run situation occurs in slave mode
: I2C0_STAT0_AERR   %1 10 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_AERR    Acknowledge error
: I2C0_STAT0_LOSTARB   %1 9 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_LOSTARB    Arbitration Lost in master mode
: I2C0_STAT0_BERR   %1 8 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_BERR    A bus error occurs indication a unexpected START or STOP condition on I2C bus
: I2C0_STAT0_TBE   %1 7 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_TBE    I2C_DATA is Empty during transmitting
: I2C0_STAT0_RBNE   %1 6 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_RBNE    I2C_DATA is not Empty during receiving
: I2C0_STAT0_STPDET   %1 4 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_STPDET    STOP condition detected in slave mode
: I2C0_STAT0_ADD10SEND   %1 3 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_ADD10SEND    Header of 10-bit address is sent in master mode
: I2C0_STAT0_BTC   %1 2 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_BTC    Byte transmission completed
: I2C0_STAT0_ADDSEND   %1 1 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_ADDSEND    Address is sent in master mode or received and matches in slave mode
: I2C0_STAT0_SBSEND   %1 0 lshift I2C0_STAT0 bis! ;  \ I2C0_STAT0_SBSEND    START condition sent out in master mode

\ I2C0_STAT1 (read-only)
: I2C0_STAT1_PECV   ( %XXXXXXXX -- ) 8 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_PECV    Packet Error Checking Value that calculated by hardware when PEC is enabled
: I2C0_STAT1_DUMODF   %1 7 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_DUMODF    Dual Flag in slave mode
: I2C0_STAT1_HSTSMB   %1 6 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_HSTSMB    SMBus Host Header detected in slave mode
: I2C0_STAT1_DEFSMB   %1 5 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_DEFSMB    Default address of SMBusDevice
: I2C0_STAT1_RXGC   %1 4 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_RXGC    General call address 00h received
: I2C0_STAT1_TR   %1 2 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_TR    Whether the I2C is a transmitter or a receiver
: I2C0_STAT1_I2CBSY   %1 1 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_I2CBSY    Busy flag
: I2C0_STAT1_MASTER   %1 0 lshift I2C0_STAT1 bis! ;  \ I2C0_STAT1_MASTER    A flag indicating whether I2C block is in master or slave mode

\ I2C0_CKCFG (read-write)
: I2C0_CKCFG_FAST   %1 15 lshift I2C0_CKCFG bis! ;  \ I2C0_CKCFG_FAST    I2C speed selection in master mode
: I2C0_CKCFG_DTCY   %1 14 lshift I2C0_CKCFG bis! ;  \ I2C0_CKCFG_DTCY    Duty cycle in fast mode
: I2C0_CKCFG_CLKC   ( %XXXXXXXXXXX -- ) 0 lshift I2C0_CKCFG bis! ;  \ I2C0_CKCFG_CLKC    I2C Clock control in master mode

\ I2C0_RT (read-write)
: I2C0_RT_RISETIME   ( %XXXXXX -- ) 0 lshift I2C0_RT bis! ;  \ I2C0_RT_RISETIME    Maximum rise time in master mode

\ I2C1_CTL0 (read-write)
: I2C1_CTL0_SRESET   %1 15 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_SRESET    Software reset
: I2C1_CTL0_SALT   %1 13 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_SALT    SMBus alert
: I2C1_CTL0_PECTRANS   %1 12 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_PECTRANS    PEC Transfer
: I2C1_CTL0_POAP   %1 11 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_POAP    Position of ACK and PEC when receiving
: I2C1_CTL0_ACKEN   %1 10 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_ACKEN    Whether or not to send an ACK
: I2C1_CTL0_STOP   %1 9 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_STOP    Generate a STOP condition on I2C bus
: I2C1_CTL0_START   %1 8 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_START    Generate a START condition on I2C bus
: I2C1_CTL0_SS   %1 7 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_SS    Whether to stretch SCL low when data is not ready in slave mode
: I2C1_CTL0_GCEN   %1 6 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_GCEN    Whether or not to response to a General Call $00
: I2C1_CTL0_PECEN   %1 5 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_PECEN    PEC Calculation Switch
: I2C1_CTL0_ARPEN   %1 4 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_ARPEN    ARP protocol in SMBus switch
: I2C1_CTL0_SMBSEL   %1 3 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_SMBSEL    SMBusType Selection
: I2C1_CTL0_SMBEN   %1 1 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_SMBEN    SMBus/I2C mode switch
: I2C1_CTL0_I2CEN   %1 0 lshift I2C1_CTL0 bis! ;  \ I2C1_CTL0_I2CEN    I2C peripheral enable

\ I2C1_CTL1 (read-write)
: I2C1_CTL1_DMALST   %1 12 lshift I2C1_CTL1 bis! ;  \ I2C1_CTL1_DMALST    Flag indicating DMA last transfer
: I2C1_CTL1_DMAON   %1 11 lshift I2C1_CTL1 bis! ;  \ I2C1_CTL1_DMAON    DMA mode switch
: I2C1_CTL1_BUFIE   %1 10 lshift I2C1_CTL1 bis! ;  \ I2C1_CTL1_BUFIE    Buffer interrupt enable
: I2C1_CTL1_EVIE   %1 9 lshift I2C1_CTL1 bis! ;  \ I2C1_CTL1_EVIE    Event interrupt enable
: I2C1_CTL1_ERRIE   %1 8 lshift I2C1_CTL1 bis! ;  \ I2C1_CTL1_ERRIE    Error interrupt enable
: I2C1_CTL1_I2CCLK   ( %XXXXXX -- ) 0 lshift I2C1_CTL1 bis! ;  \ I2C1_CTL1_I2CCLK    I2C Peripheral clock frequency

\ I2C1_SADDR0 (read-write)
: I2C1_SADDR0_ADDFORMAT   %1 15 lshift I2C1_SADDR0 bis! ;  \ I2C1_SADDR0_ADDFORMAT    Address mode for the I2C slave
: I2C1_SADDR0_ADDRESS9_8   ( %XX -- ) 8 lshift I2C1_SADDR0 bis! ;  \ I2C1_SADDR0_ADDRESS9_8    Highest two bits of a 10-bit address
: I2C1_SADDR0_ADDRESS7_1   ( %XXXXXXX -- ) 1 lshift I2C1_SADDR0 bis! ;  \ I2C1_SADDR0_ADDRESS7_1    7-bit address or bits 7:1 of a 10-bit address
: I2C1_SADDR0_ADDRESS0   %1 0 lshift I2C1_SADDR0 bis! ;  \ I2C1_SADDR0_ADDRESS0    Bit 0 of a 10-bit address

\ I2C1_SADDR1 (read-write)
: I2C1_SADDR1_ADDRESS2   ( %XXXXXXX -- ) 1 lshift I2C1_SADDR1 bis! ;  \ I2C1_SADDR1_ADDRESS2    Second I2C address for the slave in Dual-Address mode
: I2C1_SADDR1_DUADEN   %1 0 lshift I2C1_SADDR1 bis! ;  \ I2C1_SADDR1_DUADEN    Dual-Address mode switch

\ I2C1_DATA (read-write)
: I2C1_DATA_TRB   ( %XXXXXXXX -- ) 0 lshift I2C1_DATA bis! ;  \ I2C1_DATA_TRB    Transmission or reception data buffer register

\ I2C1_STAT0 ()
: I2C1_STAT0_SMBALT   %1 15 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_SMBALT    SMBus Alert status
: I2C1_STAT0_SMBTO   %1 14 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_SMBTO    Timeout signal in SMBus mode
: I2C1_STAT0_PECERR   %1 12 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_PECERR    PEC error when receiving data
: I2C1_STAT0_OUERR   %1 11 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_OUERR    Over-run or under-run situation occurs in slave mode
: I2C1_STAT0_AERR   %1 10 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_AERR    Acknowledge error
: I2C1_STAT0_LOSTARB   %1 9 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_LOSTARB    Arbitration Lost in master mode
: I2C1_STAT0_BERR   %1 8 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_BERR    A bus error occurs indication a unexpected START or STOP condition on I2C bus
: I2C1_STAT0_TBE   %1 7 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_TBE    I2C_DATA is Empty during transmitting
: I2C1_STAT0_RBNE   %1 6 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_RBNE    I2C_DATA is not Empty during receiving
: I2C1_STAT0_STPDET   %1 4 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_STPDET    STOP condition detected in slave mode
: I2C1_STAT0_ADD10SEND   %1 3 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_ADD10SEND    Header of 10-bit address is sent in master mode
: I2C1_STAT0_BTC   %1 2 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_BTC    Byte transmission completed
: I2C1_STAT0_ADDSEND   %1 1 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_ADDSEND    Address is sent in master mode or received and matches in slave mode
: I2C1_STAT0_SBSEND   %1 0 lshift I2C1_STAT0 bis! ;  \ I2C1_STAT0_SBSEND    START condition sent out in master mode

\ I2C1_STAT1 (read-only)
: I2C1_STAT1_PECV   ( %XXXXXXXX -- ) 8 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_PECV    Packet Error Checking Value that calculated by hardware when PEC is enabled
: I2C1_STAT1_DUMODF   %1 7 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_DUMODF    Dual Flag in slave mode
: I2C1_STAT1_HSTSMB   %1 6 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_HSTSMB    SMBus Host Header detected in slave mode
: I2C1_STAT1_DEFSMB   %1 5 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_DEFSMB    Default address of SMBusDevice
: I2C1_STAT1_RXGC   %1 4 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_RXGC    General call address 00h received
: I2C1_STAT1_TR   %1 2 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_TR    Whether the I2C is a transmitter or a receiver
: I2C1_STAT1_I2CBSY   %1 1 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_I2CBSY    Busy flag
: I2C1_STAT1_MASTER   %1 0 lshift I2C1_STAT1 bis! ;  \ I2C1_STAT1_MASTER    A flag indicating whether I2C block is in master or slave mode

\ I2C1_CKCFG (read-write)
: I2C1_CKCFG_FAST   %1 15 lshift I2C1_CKCFG bis! ;  \ I2C1_CKCFG_FAST    I2C speed selection in master mode
: I2C1_CKCFG_DTCY   %1 14 lshift I2C1_CKCFG bis! ;  \ I2C1_CKCFG_DTCY    Duty cycle in fast mode
: I2C1_CKCFG_CLKC   ( %XXXXXXXXXXX -- ) 0 lshift I2C1_CKCFG bis! ;  \ I2C1_CKCFG_CLKC    I2C Clock control in master mode

\ I2C1_RT (read-write)
: I2C1_RT_RISETIME   ( %XXXXXX -- ) 0 lshift I2C1_RT bis! ;  \ I2C1_RT_RISETIME    Maximum rise time in master mode

\ ECLIC_CLICCFG (read-write)
: ECLIC_CLICCFG_NLBITS   ( %XXXX -- ) 1 lshift ECLIC_CLICCFG bis! ;  \ ECLIC_CLICCFG_NLBITS    NLBITS

\ ECLIC_CLICINFO (read-only)
: ECLIC_CLICINFO_NUM_INTERRUPT  0 lshift ECLIC_CLICINFO bis! ;  \ ECLIC_CLICINFO_NUM_INTERRUPT    NUM_INTERRUPT
: ECLIC_CLICINFO_VERSION   ( %XXXXXXXX -- ) 13 lshift ECLIC_CLICINFO bis! ;  \ ECLIC_CLICINFO_VERSION    VERSION
: ECLIC_CLICINFO_CLICINTCTLBITS   ( %XXXX -- ) 21 lshift ECLIC_CLICINFO bis! ;  \ ECLIC_CLICINFO_CLICINTCTLBITS    CLICINTCTLBITS

\ ECLIC_MTH (read-write)
: ECLIC_MTH_MTH   ( %XXXXXXXX -- ) 0 lshift ECLIC_MTH bis! ;  \ ECLIC_MTH_MTH    MTH

\ ECLIC_CLICINTIP_0 (read-write)
: ECLIC_CLICINTIP_0_IP   %1 0 lshift ECLIC_CLICINTIP_0 bis! ;  \ ECLIC_CLICINTIP_0_IP    IP

\ ECLIC_CLICINTIP_1 (read-write)
: ECLIC_CLICINTIP_1_IP   %1 0 lshift ECLIC_CLICINTIP_1 bis! ;  \ ECLIC_CLICINTIP_1_IP    IP

\ ECLIC_CLICINTIP_2 (read-write)
: ECLIC_CLICINTIP_2_IP   %1 0 lshift ECLIC_CLICINTIP_2 bis! ;  \ ECLIC_CLICINTIP_2_IP    IP

\ ECLIC_CLICINTIP_3 (read-write)
: ECLIC_CLICINTIP_3_IP   %1 0 lshift ECLIC_CLICINTIP_3 bis! ;  \ ECLIC_CLICINTIP_3_IP    IP

\ ECLIC_CLICINTIP_4 (read-write)
: ECLIC_CLICINTIP_4_IP   %1 0 lshift ECLIC_CLICINTIP_4 bis! ;  \ ECLIC_CLICINTIP_4_IP    IP

\ ECLIC_CLICINTIP_5 (read-write)
: ECLIC_CLICINTIP_5_IP   %1 0 lshift ECLIC_CLICINTIP_5 bis! ;  \ ECLIC_CLICINTIP_5_IP    IP

\ ECLIC_CLICINTIP_6 (read-write)
: ECLIC_CLICINTIP_6_IP   %1 0 lshift ECLIC_CLICINTIP_6 bis! ;  \ ECLIC_CLICINTIP_6_IP    IP

\ ECLIC_CLICINTIP_7 (read-write)
: ECLIC_CLICINTIP_7_IP   %1 0 lshift ECLIC_CLICINTIP_7 bis! ;  \ ECLIC_CLICINTIP_7_IP    IP

\ ECLIC_CLICINTIP_8 (read-write)
: ECLIC_CLICINTIP_8_IP   %1 0 lshift ECLIC_CLICINTIP_8 bis! ;  \ ECLIC_CLICINTIP_8_IP    IP

\ ECLIC_CLICINTIP_9 (read-write)
: ECLIC_CLICINTIP_9_IP   %1 0 lshift ECLIC_CLICINTIP_9 bis! ;  \ ECLIC_CLICINTIP_9_IP    IP

\ ECLIC_CLICINTIP_10 (read-write)
: ECLIC_CLICINTIP_10_IP   %1 0 lshift ECLIC_CLICINTIP_10 bis! ;  \ ECLIC_CLICINTIP_10_IP    IP

\ ECLIC_CLICINTIP_11 (read-write)
: ECLIC_CLICINTIP_11_IP   %1 0 lshift ECLIC_CLICINTIP_11 bis! ;  \ ECLIC_CLICINTIP_11_IP    IP

\ ECLIC_CLICINTIP_12 (read-write)
: ECLIC_CLICINTIP_12_IP   %1 0 lshift ECLIC_CLICINTIP_12 bis! ;  \ ECLIC_CLICINTIP_12_IP    IP

\ ECLIC_CLICINTIP_13 (read-write)
: ECLIC_CLICINTIP_13_IP   %1 0 lshift ECLIC_CLICINTIP_13 bis! ;  \ ECLIC_CLICINTIP_13_IP    IP

\ ECLIC_CLICINTIP_14 (read-write)
: ECLIC_CLICINTIP_14_IP   %1 0 lshift ECLIC_CLICINTIP_14 bis! ;  \ ECLIC_CLICINTIP_14_IP    IP

\ ECLIC_CLICINTIP_15 (read-write)
: ECLIC_CLICINTIP_15_IP   %1 0 lshift ECLIC_CLICINTIP_15 bis! ;  \ ECLIC_CLICINTIP_15_IP    IP

\ ECLIC_CLICINTIP_16 (read-write)
: ECLIC_CLICINTIP_16_IP   %1 0 lshift ECLIC_CLICINTIP_16 bis! ;  \ ECLIC_CLICINTIP_16_IP    IP

\ ECLIC_CLICINTIP_17 (read-write)
: ECLIC_CLICINTIP_17_IP   %1 0 lshift ECLIC_CLICINTIP_17 bis! ;  \ ECLIC_CLICINTIP_17_IP    IP

\ ECLIC_CLICINTIP_18 (read-write)
: ECLIC_CLICINTIP_18_IP   %1 0 lshift ECLIC_CLICINTIP_18 bis! ;  \ ECLIC_CLICINTIP_18_IP    IP

\ ECLIC_CLICINTIP_19 (read-write)
: ECLIC_CLICINTIP_19_IP   %1 0 lshift ECLIC_CLICINTIP_19 bis! ;  \ ECLIC_CLICINTIP_19_IP    IP

\ ECLIC_CLICINTIP_20 (read-write)
: ECLIC_CLICINTIP_20_IP   %1 0 lshift ECLIC_CLICINTIP_20 bis! ;  \ ECLIC_CLICINTIP_20_IP    IP

\ ECLIC_CLICINTIP_21 (read-write)
: ECLIC_CLICINTIP_21_IP   %1 0 lshift ECLIC_CLICINTIP_21 bis! ;  \ ECLIC_CLICINTIP_21_IP    IP

\ ECLIC_CLICINTIP_22 (read-write)
: ECLIC_CLICINTIP_22_IP   %1 0 lshift ECLIC_CLICINTIP_22 bis! ;  \ ECLIC_CLICINTIP_22_IP    IP

\ ECLIC_CLICINTIP_23 (read-write)
: ECLIC_CLICINTIP_23_IP   %1 0 lshift ECLIC_CLICINTIP_23 bis! ;  \ ECLIC_CLICINTIP_23_IP    IP

\ ECLIC_CLICINTIP_24 (read-write)
: ECLIC_CLICINTIP_24_IP   %1 0 lshift ECLIC_CLICINTIP_24 bis! ;  \ ECLIC_CLICINTIP_24_IP    IP

\ ECLIC_CLICINTIP_25 (read-write)
: ECLIC_CLICINTIP_25_IP   %1 0 lshift ECLIC_CLICINTIP_25 bis! ;  \ ECLIC_CLICINTIP_25_IP    IP

\ ECLIC_CLICINTIP_26 (read-write)
: ECLIC_CLICINTIP_26_IP   %1 0 lshift ECLIC_CLICINTIP_26 bis! ;  \ ECLIC_CLICINTIP_26_IP    IP

\ ECLIC_CLICINTIP_27 (read-write)
: ECLIC_CLICINTIP_27_IP   %1 0 lshift ECLIC_CLICINTIP_27 bis! ;  \ ECLIC_CLICINTIP_27_IP    IP

\ ECLIC_CLICINTIP_28 (read-write)
: ECLIC_CLICINTIP_28_IP   %1 0 lshift ECLIC_CLICINTIP_28 bis! ;  \ ECLIC_CLICINTIP_28_IP    IP

\ ECLIC_CLICINTIP_29 (read-write)
: ECLIC_CLICINTIP_29_IP   %1 0 lshift ECLIC_CLICINTIP_29 bis! ;  \ ECLIC_CLICINTIP_29_IP    IP

\ ECLIC_CLICINTIP_30 (read-write)
: ECLIC_CLICINTIP_30_IP   %1 0 lshift ECLIC_CLICINTIP_30 bis! ;  \ ECLIC_CLICINTIP_30_IP    IP

\ ECLIC_CLICINTIP_31 (read-write)
: ECLIC_CLICINTIP_31_IP   %1 0 lshift ECLIC_CLICINTIP_31 bis! ;  \ ECLIC_CLICINTIP_31_IP    IP

\ ECLIC_CLICINTIP_32 (read-write)
: ECLIC_CLICINTIP_32_IP   %1 0 lshift ECLIC_CLICINTIP_32 bis! ;  \ ECLIC_CLICINTIP_32_IP    IP

\ ECLIC_CLICINTIP_33 (read-write)
: ECLIC_CLICINTIP_33_IP   %1 0 lshift ECLIC_CLICINTIP_33 bis! ;  \ ECLIC_CLICINTIP_33_IP    IP

\ ECLIC_CLICINTIP_34 (read-write)
: ECLIC_CLICINTIP_34_IP   %1 0 lshift ECLIC_CLICINTIP_34 bis! ;  \ ECLIC_CLICINTIP_34_IP    IP

\ ECLIC_CLICINTIP_35 (read-write)
: ECLIC_CLICINTIP_35_IP   %1 0 lshift ECLIC_CLICINTIP_35 bis! ;  \ ECLIC_CLICINTIP_35_IP    IP

\ ECLIC_CLICINTIP_36 (read-write)
: ECLIC_CLICINTIP_36_IP   %1 0 lshift ECLIC_CLICINTIP_36 bis! ;  \ ECLIC_CLICINTIP_36_IP    IP

\ ECLIC_CLICINTIP_37 (read-write)
: ECLIC_CLICINTIP_37_IP   %1 0 lshift ECLIC_CLICINTIP_37 bis! ;  \ ECLIC_CLICINTIP_37_IP    IP

\ ECLIC_CLICINTIP_38 (read-write)
: ECLIC_CLICINTIP_38_IP   %1 0 lshift ECLIC_CLICINTIP_38 bis! ;  \ ECLIC_CLICINTIP_38_IP    IP

\ ECLIC_CLICINTIP_39 (read-write)
: ECLIC_CLICINTIP_39_IP   %1 0 lshift ECLIC_CLICINTIP_39 bis! ;  \ ECLIC_CLICINTIP_39_IP    IP

\ ECLIC_CLICINTIP_40 (read-write)
: ECLIC_CLICINTIP_40_IP   %1 0 lshift ECLIC_CLICINTIP_40 bis! ;  \ ECLIC_CLICINTIP_40_IP    IP

\ ECLIC_CLICINTIP_41 (read-write)
: ECLIC_CLICINTIP_41_IP   %1 0 lshift ECLIC_CLICINTIP_41 bis! ;  \ ECLIC_CLICINTIP_41_IP    IP

\ ECLIC_CLICINTIP_42 (read-write)
: ECLIC_CLICINTIP_42_IP   %1 0 lshift ECLIC_CLICINTIP_42 bis! ;  \ ECLIC_CLICINTIP_42_IP    IP

\ ECLIC_CLICINTIP_43 (read-write)
: ECLIC_CLICINTIP_43_IP   %1 0 lshift ECLIC_CLICINTIP_43 bis! ;  \ ECLIC_CLICINTIP_43_IP    IP

\ ECLIC_CLICINTIP_44 (read-write)
: ECLIC_CLICINTIP_44_IP   %1 0 lshift ECLIC_CLICINTIP_44 bis! ;  \ ECLIC_CLICINTIP_44_IP    IP

\ ECLIC_CLICINTIP_45 (read-write)
: ECLIC_CLICINTIP_45_IP   %1 0 lshift ECLIC_CLICINTIP_45 bis! ;  \ ECLIC_CLICINTIP_45_IP    IP

\ ECLIC_CLICINTIP_46 (read-write)
: ECLIC_CLICINTIP_46_IP   %1 0 lshift ECLIC_CLICINTIP_46 bis! ;  \ ECLIC_CLICINTIP_46_IP    IP

\ ECLIC_CLICINTIP_47 (read-write)
: ECLIC_CLICINTIP_47_IP   %1 0 lshift ECLIC_CLICINTIP_47 bis! ;  \ ECLIC_CLICINTIP_47_IP    IP

\ ECLIC_CLICINTIP_48 (read-write)
: ECLIC_CLICINTIP_48_IP   %1 0 lshift ECLIC_CLICINTIP_48 bis! ;  \ ECLIC_CLICINTIP_48_IP    IP

\ ECLIC_CLICINTIP_49 (read-write)
: ECLIC_CLICINTIP_49_IP   %1 0 lshift ECLIC_CLICINTIP_49 bis! ;  \ ECLIC_CLICINTIP_49_IP    IP

\ ECLIC_CLICINTIP_50 (read-write)
: ECLIC_CLICINTIP_50_IP   %1 0 lshift ECLIC_CLICINTIP_50 bis! ;  \ ECLIC_CLICINTIP_50_IP    IP

\ ECLIC_CLICINTIP_51 (read-write)
: ECLIC_CLICINTIP_51_IP   %1 0 lshift ECLIC_CLICINTIP_51 bis! ;  \ ECLIC_CLICINTIP_51_IP    IP

\ ECLIC_CLICINTIP_52 (read-write)
: ECLIC_CLICINTIP_52_IP   %1 0 lshift ECLIC_CLICINTIP_52 bis! ;  \ ECLIC_CLICINTIP_52_IP    IP

\ ECLIC_CLICINTIP_53 (read-write)
: ECLIC_CLICINTIP_53_IP   %1 0 lshift ECLIC_CLICINTIP_53 bis! ;  \ ECLIC_CLICINTIP_53_IP    IP

\ ECLIC_CLICINTIP_54 (read-write)
: ECLIC_CLICINTIP_54_IP   %1 0 lshift ECLIC_CLICINTIP_54 bis! ;  \ ECLIC_CLICINTIP_54_IP    IP

\ ECLIC_CLICINTIP_55 (read-write)
: ECLIC_CLICINTIP_55_IP   %1 0 lshift ECLIC_CLICINTIP_55 bis! ;  \ ECLIC_CLICINTIP_55_IP    IP

\ ECLIC_CLICINTIP_56 (read-write)
: ECLIC_CLICINTIP_56_IP   %1 0 lshift ECLIC_CLICINTIP_56 bis! ;  \ ECLIC_CLICINTIP_56_IP    IP

\ ECLIC_CLICINTIP_57 (read-write)
: ECLIC_CLICINTIP_57_IP   %1 0 lshift ECLIC_CLICINTIP_57 bis! ;  \ ECLIC_CLICINTIP_57_IP    IP

\ ECLIC_CLICINTIP_58 (read-write)
: ECLIC_CLICINTIP_58_IP   %1 0 lshift ECLIC_CLICINTIP_58 bis! ;  \ ECLIC_CLICINTIP_58_IP    IP

\ ECLIC_CLICINTIP_59 (read-write)
: ECLIC_CLICINTIP_59_IP   %1 0 lshift ECLIC_CLICINTIP_59 bis! ;  \ ECLIC_CLICINTIP_59_IP    IP

\ ECLIC_CLICINTIP_60 (read-write)
: ECLIC_CLICINTIP_60_IP   %1 0 lshift ECLIC_CLICINTIP_60 bis! ;  \ ECLIC_CLICINTIP_60_IP    IP

\ ECLIC_CLICINTIP_61 (read-write)
: ECLIC_CLICINTIP_61_IP   %1 0 lshift ECLIC_CLICINTIP_61 bis! ;  \ ECLIC_CLICINTIP_61_IP    IP

\ ECLIC_CLICINTIP_62 (read-write)
: ECLIC_CLICINTIP_62_IP   %1 0 lshift ECLIC_CLICINTIP_62 bis! ;  \ ECLIC_CLICINTIP_62_IP    IP

\ ECLIC_CLICINTIP_63 (read-write)
: ECLIC_CLICINTIP_63_IP   %1 0 lshift ECLIC_CLICINTIP_63 bis! ;  \ ECLIC_CLICINTIP_63_IP    IP

\ ECLIC_CLICINTIP_64 (read-write)
: ECLIC_CLICINTIP_64_IP   %1 0 lshift ECLIC_CLICINTIP_64 bis! ;  \ ECLIC_CLICINTIP_64_IP    IP

\ ECLIC_CLICINTIP_65 (read-write)
: ECLIC_CLICINTIP_65_IP   %1 0 lshift ECLIC_CLICINTIP_65 bis! ;  \ ECLIC_CLICINTIP_65_IP    IP

\ ECLIC_CLICINTIP_66 (read-write)
: ECLIC_CLICINTIP_66_IP   %1 0 lshift ECLIC_CLICINTIP_66 bis! ;  \ ECLIC_CLICINTIP_66_IP    IP

\ ECLIC_CLICINTIP_67 (read-write)
: ECLIC_CLICINTIP_67_IP   %1 0 lshift ECLIC_CLICINTIP_67 bis! ;  \ ECLIC_CLICINTIP_67_IP    IP

\ ECLIC_CLICINTIP_68 (read-write)
: ECLIC_CLICINTIP_68_IP   %1 0 lshift ECLIC_CLICINTIP_68 bis! ;  \ ECLIC_CLICINTIP_68_IP    IP

\ ECLIC_CLICINTIP_69 (read-write)
: ECLIC_CLICINTIP_69_IP   %1 0 lshift ECLIC_CLICINTIP_69 bis! ;  \ ECLIC_CLICINTIP_69_IP    IP

\ ECLIC_CLICINTIP_70 (read-write)
: ECLIC_CLICINTIP_70_IP   %1 0 lshift ECLIC_CLICINTIP_70 bis! ;  \ ECLIC_CLICINTIP_70_IP    IP

\ ECLIC_CLICINTIP_71 (read-write)
: ECLIC_CLICINTIP_71_IP   %1 0 lshift ECLIC_CLICINTIP_71 bis! ;  \ ECLIC_CLICINTIP_71_IP    IP

\ ECLIC_CLICINTIP_72 (read-write)
: ECLIC_CLICINTIP_72_IP   %1 0 lshift ECLIC_CLICINTIP_72 bis! ;  \ ECLIC_CLICINTIP_72_IP    IP

\ ECLIC_CLICINTIP_73 (read-write)
: ECLIC_CLICINTIP_73_IP   %1 0 lshift ECLIC_CLICINTIP_73 bis! ;  \ ECLIC_CLICINTIP_73_IP    IP

\ ECLIC_CLICINTIP_74 (read-write)
: ECLIC_CLICINTIP_74_IP   %1 0 lshift ECLIC_CLICINTIP_74 bis! ;  \ ECLIC_CLICINTIP_74_IP    IP

\ ECLIC_CLICINTIP_75 (read-write)
: ECLIC_CLICINTIP_75_IP   %1 0 lshift ECLIC_CLICINTIP_75 bis! ;  \ ECLIC_CLICINTIP_75_IP    IP

\ ECLIC_CLICINTIP_76 (read-write)
: ECLIC_CLICINTIP_76_IP   %1 0 lshift ECLIC_CLICINTIP_76 bis! ;  \ ECLIC_CLICINTIP_76_IP    IP

\ ECLIC_CLICINTIP_77 (read-write)
: ECLIC_CLICINTIP_77_IP   %1 0 lshift ECLIC_CLICINTIP_77 bis! ;  \ ECLIC_CLICINTIP_77_IP    IP

\ ECLIC_CLICINTIP_78 (read-write)
: ECLIC_CLICINTIP_78_IP   %1 0 lshift ECLIC_CLICINTIP_78 bis! ;  \ ECLIC_CLICINTIP_78_IP    IP

\ ECLIC_CLICINTIP_79 (read-write)
: ECLIC_CLICINTIP_79_IP   %1 0 lshift ECLIC_CLICINTIP_79 bis! ;  \ ECLIC_CLICINTIP_79_IP    IP

\ ECLIC_CLICINTIP_80 (read-write)
: ECLIC_CLICINTIP_80_IP   %1 0 lshift ECLIC_CLICINTIP_80 bis! ;  \ ECLIC_CLICINTIP_80_IP    IP

\ ECLIC_CLICINTIP_81 (read-write)
: ECLIC_CLICINTIP_81_IP   %1 0 lshift ECLIC_CLICINTIP_81 bis! ;  \ ECLIC_CLICINTIP_81_IP    IP

\ ECLIC_CLICINTIP_82 (read-write)
: ECLIC_CLICINTIP_82_IP   %1 0 lshift ECLIC_CLICINTIP_82 bis! ;  \ ECLIC_CLICINTIP_82_IP    IP

\ ECLIC_CLICINTIP_83 (read-write)
: ECLIC_CLICINTIP_83_IP   %1 0 lshift ECLIC_CLICINTIP_83 bis! ;  \ ECLIC_CLICINTIP_83_IP    IP

\ ECLIC_CLICINTIP_84 (read-write)
: ECLIC_CLICINTIP_84_IP   %1 0 lshift ECLIC_CLICINTIP_84 bis! ;  \ ECLIC_CLICINTIP_84_IP    IP

\ ECLIC_CLICINTIP_85 (read-write)
: ECLIC_CLICINTIP_85_IP   %1 0 lshift ECLIC_CLICINTIP_85 bis! ;  \ ECLIC_CLICINTIP_85_IP    IP

\ ECLIC_CLICINTIP_86 (read-write)
: ECLIC_CLICINTIP_86_IP   %1 0 lshift ECLIC_CLICINTIP_86 bis! ;  \ ECLIC_CLICINTIP_86_IP    IP

\ ECLIC_CLICINTIE_0 (read-write)
: ECLIC_CLICINTIE_0_IE   %1 0 lshift ECLIC_CLICINTIE_0 bis! ;  \ ECLIC_CLICINTIE_0_IE    IE

\ ECLIC_CLICINTIE_1 (read-write)
: ECLIC_CLICINTIE_1_IE   %1 0 lshift ECLIC_CLICINTIE_1 bis! ;  \ ECLIC_CLICINTIE_1_IE    IE

\ ECLIC_CLICINTIE_2 (read-write)
: ECLIC_CLICINTIE_2_IE   %1 0 lshift ECLIC_CLICINTIE_2 bis! ;  \ ECLIC_CLICINTIE_2_IE    IE

\ ECLIC_CLICINTIE_3 (read-write)
: ECLIC_CLICINTIE_3_IE   %1 0 lshift ECLIC_CLICINTIE_3 bis! ;  \ ECLIC_CLICINTIE_3_IE    IE

\ ECLIC_CLICINTIE_4 (read-write)
: ECLIC_CLICINTIE_4_IE   %1 0 lshift ECLIC_CLICINTIE_4 bis! ;  \ ECLIC_CLICINTIE_4_IE    IE

\ ECLIC_CLICINTIE_5 (read-write)
: ECLIC_CLICINTIE_5_IE   %1 0 lshift ECLIC_CLICINTIE_5 bis! ;  \ ECLIC_CLICINTIE_5_IE    IE

\ ECLIC_CLICINTIE_6 (read-write)
: ECLIC_CLICINTIE_6_IE   %1 0 lshift ECLIC_CLICINTIE_6 bis! ;  \ ECLIC_CLICINTIE_6_IE    IE

\ ECLIC_CLICINTIE_7 (read-write)
: ECLIC_CLICINTIE_7_IE   %1 0 lshift ECLIC_CLICINTIE_7 bis! ;  \ ECLIC_CLICINTIE_7_IE    IE

\ ECLIC_CLICINTIE_8 (read-write)
: ECLIC_CLICINTIE_8_IE   %1 0 lshift ECLIC_CLICINTIE_8 bis! ;  \ ECLIC_CLICINTIE_8_IE    IE

\ ECLIC_CLICINTIE_9 (read-write)
: ECLIC_CLICINTIE_9_IE   %1 0 lshift ECLIC_CLICINTIE_9 bis! ;  \ ECLIC_CLICINTIE_9_IE    IE

\ ECLIC_CLICINTIE_10 (read-write)
: ECLIC_CLICINTIE_10_IE   %1 0 lshift ECLIC_CLICINTIE_10 bis! ;  \ ECLIC_CLICINTIE_10_IE    IE

\ ECLIC_CLICINTIE_11 (read-write)
: ECLIC_CLICINTIE_11_IE   %1 0 lshift ECLIC_CLICINTIE_11 bis! ;  \ ECLIC_CLICINTIE_11_IE    IE

\ ECLIC_CLICINTIE_12 (read-write)
: ECLIC_CLICINTIE_12_IE   %1 0 lshift ECLIC_CLICINTIE_12 bis! ;  \ ECLIC_CLICINTIE_12_IE    IE

\ ECLIC_CLICINTIE_13 (read-write)
: ECLIC_CLICINTIE_13_IE   %1 0 lshift ECLIC_CLICINTIE_13 bis! ;  \ ECLIC_CLICINTIE_13_IE    IE

\ ECLIC_CLICINTIE_14 (read-write)
: ECLIC_CLICINTIE_14_IE   %1 0 lshift ECLIC_CLICINTIE_14 bis! ;  \ ECLIC_CLICINTIE_14_IE    IE

\ ECLIC_CLICINTIE_15 (read-write)
: ECLIC_CLICINTIE_15_IE   %1 0 lshift ECLIC_CLICINTIE_15 bis! ;  \ ECLIC_CLICINTIE_15_IE    IE

\ ECLIC_CLICINTIE_16 (read-write)
: ECLIC_CLICINTIE_16_IE   %1 0 lshift ECLIC_CLICINTIE_16 bis! ;  \ ECLIC_CLICINTIE_16_IE    IE

\ ECLIC_CLICINTIE_17 (read-write)
: ECLIC_CLICINTIE_17_IE   %1 0 lshift ECLIC_CLICINTIE_17 bis! ;  \ ECLIC_CLICINTIE_17_IE    IE

\ ECLIC_CLICINTIE_18 (read-write)
: ECLIC_CLICINTIE_18_IE   %1 0 lshift ECLIC_CLICINTIE_18 bis! ;  \ ECLIC_CLICINTIE_18_IE    IE

\ ECLIC_CLICINTIE_19 (read-write)
: ECLIC_CLICINTIE_19_IE   %1 0 lshift ECLIC_CLICINTIE_19 bis! ;  \ ECLIC_CLICINTIE_19_IE    IE

\ ECLIC_CLICINTIE_20 (read-write)
: ECLIC_CLICINTIE_20_IE   %1 0 lshift ECLIC_CLICINTIE_20 bis! ;  \ ECLIC_CLICINTIE_20_IE    IE

\ ECLIC_CLICINTIE_21 (read-write)
: ECLIC_CLICINTIE_21_IE   %1 0 lshift ECLIC_CLICINTIE_21 bis! ;  \ ECLIC_CLICINTIE_21_IE    IE

\ ECLIC_CLICINTIE_22 (read-write)
: ECLIC_CLICINTIE_22_IE   %1 0 lshift ECLIC_CLICINTIE_22 bis! ;  \ ECLIC_CLICINTIE_22_IE    IE

\ ECLIC_CLICINTIE_23 (read-write)
: ECLIC_CLICINTIE_23_IE   %1 0 lshift ECLIC_CLICINTIE_23 bis! ;  \ ECLIC_CLICINTIE_23_IE    IE

\ ECLIC_CLICINTIE_24 (read-write)
: ECLIC_CLICINTIE_24_IE   %1 0 lshift ECLIC_CLICINTIE_24 bis! ;  \ ECLIC_CLICINTIE_24_IE    IE

\ ECLIC_CLICINTIE_25 (read-write)
: ECLIC_CLICINTIE_25_IE   %1 0 lshift ECLIC_CLICINTIE_25 bis! ;  \ ECLIC_CLICINTIE_25_IE    IE

\ ECLIC_CLICINTIE_26 (read-write)
: ECLIC_CLICINTIE_26_IE   %1 0 lshift ECLIC_CLICINTIE_26 bis! ;  \ ECLIC_CLICINTIE_26_IE    IE

\ ECLIC_CLICINTIE_27 (read-write)
: ECLIC_CLICINTIE_27_IE   %1 0 lshift ECLIC_CLICINTIE_27 bis! ;  \ ECLIC_CLICINTIE_27_IE    IE

\ ECLIC_CLICINTIE_28 (read-write)
: ECLIC_CLICINTIE_28_IE   %1 0 lshift ECLIC_CLICINTIE_28 bis! ;  \ ECLIC_CLICINTIE_28_IE    IE

\ ECLIC_CLICINTIE_29 (read-write)
: ECLIC_CLICINTIE_29_IE   %1 0 lshift ECLIC_CLICINTIE_29 bis! ;  \ ECLIC_CLICINTIE_29_IE    IE

\ ECLIC_CLICINTIE_30 (read-write)
: ECLIC_CLICINTIE_30_IE   %1 0 lshift ECLIC_CLICINTIE_30 bis! ;  \ ECLIC_CLICINTIE_30_IE    IE

\ ECLIC_CLICINTIE_31 (read-write)
: ECLIC_CLICINTIE_31_IE   %1 0 lshift ECLIC_CLICINTIE_31 bis! ;  \ ECLIC_CLICINTIE_31_IE    IE

\ ECLIC_CLICINTIE_32 (read-write)
: ECLIC_CLICINTIE_32_IE   %1 0 lshift ECLIC_CLICINTIE_32 bis! ;  \ ECLIC_CLICINTIE_32_IE    IE

\ ECLIC_CLICINTIE_33 (read-write)
: ECLIC_CLICINTIE_33_IE   %1 0 lshift ECLIC_CLICINTIE_33 bis! ;  \ ECLIC_CLICINTIE_33_IE    IE

\ ECLIC_CLICINTIE_34 (read-write)
: ECLIC_CLICINTIE_34_IE   %1 0 lshift ECLIC_CLICINTIE_34 bis! ;  \ ECLIC_CLICINTIE_34_IE    IE

\ ECLIC_CLICINTIE_35 (read-write)
: ECLIC_CLICINTIE_35_IE   %1 0 lshift ECLIC_CLICINTIE_35 bis! ;  \ ECLIC_CLICINTIE_35_IE    IE

\ ECLIC_CLICINTIE_36 (read-write)
: ECLIC_CLICINTIE_36_IE   %1 0 lshift ECLIC_CLICINTIE_36 bis! ;  \ ECLIC_CLICINTIE_36_IE    IE

\ ECLIC_CLICINTIE_37 (read-write)
: ECLIC_CLICINTIE_37_IE   %1 0 lshift ECLIC_CLICINTIE_37 bis! ;  \ ECLIC_CLICINTIE_37_IE    IE

\ ECLIC_CLICINTIE_38 (read-write)
: ECLIC_CLICINTIE_38_IE   %1 0 lshift ECLIC_CLICINTIE_38 bis! ;  \ ECLIC_CLICINTIE_38_IE    IE

\ ECLIC_CLICINTIE_39 (read-write)
: ECLIC_CLICINTIE_39_IE   %1 0 lshift ECLIC_CLICINTIE_39 bis! ;  \ ECLIC_CLICINTIE_39_IE    IE

\ ECLIC_CLICINTIE_40 (read-write)
: ECLIC_CLICINTIE_40_IE   %1 0 lshift ECLIC_CLICINTIE_40 bis! ;  \ ECLIC_CLICINTIE_40_IE    IE

\ ECLIC_CLICINTIE_41 (read-write)
: ECLIC_CLICINTIE_41_IE   %1 0 lshift ECLIC_CLICINTIE_41 bis! ;  \ ECLIC_CLICINTIE_41_IE    IE

\ ECLIC_CLICINTIE_42 (read-write)
: ECLIC_CLICINTIE_42_IE   %1 0 lshift ECLIC_CLICINTIE_42 bis! ;  \ ECLIC_CLICINTIE_42_IE    IE

\ ECLIC_CLICINTIE_43 (read-write)
: ECLIC_CLICINTIE_43_IE   %1 0 lshift ECLIC_CLICINTIE_43 bis! ;  \ ECLIC_CLICINTIE_43_IE    IE

\ ECLIC_CLICINTIE_44 (read-write)
: ECLIC_CLICINTIE_44_IE   %1 0 lshift ECLIC_CLICINTIE_44 bis! ;  \ ECLIC_CLICINTIE_44_IE    IE

\ ECLIC_CLICINTIE_45 (read-write)
: ECLIC_CLICINTIE_45_IE   %1 0 lshift ECLIC_CLICINTIE_45 bis! ;  \ ECLIC_CLICINTIE_45_IE    IE

\ ECLIC_CLICINTIE_46 (read-write)
: ECLIC_CLICINTIE_46_IE   %1 0 lshift ECLIC_CLICINTIE_46 bis! ;  \ ECLIC_CLICINTIE_46_IE    IE

\ ECLIC_CLICINTIE_47 (read-write)
: ECLIC_CLICINTIE_47_IE   %1 0 lshift ECLIC_CLICINTIE_47 bis! ;  \ ECLIC_CLICINTIE_47_IE    IE

\ ECLIC_CLICINTIE_48 (read-write)
: ECLIC_CLICINTIE_48_IE   %1 0 lshift ECLIC_CLICINTIE_48 bis! ;  \ ECLIC_CLICINTIE_48_IE    IE

\ ECLIC_CLICINTIE_49 (read-write)
: ECLIC_CLICINTIE_49_IE   %1 0 lshift ECLIC_CLICINTIE_49 bis! ;  \ ECLIC_CLICINTIE_49_IE    IE

\ ECLIC_CLICINTIE_50 (read-write)
: ECLIC_CLICINTIE_50_IE   %1 0 lshift ECLIC_CLICINTIE_50 bis! ;  \ ECLIC_CLICINTIE_50_IE    IE

\ ECLIC_CLICINTIE_51 (read-write)
: ECLIC_CLICINTIE_51_IE   %1 0 lshift ECLIC_CLICINTIE_51 bis! ;  \ ECLIC_CLICINTIE_51_IE    IE

\ ECLIC_CLICINTIE_52 (read-write)
: ECLIC_CLICINTIE_52_IE   %1 0 lshift ECLIC_CLICINTIE_52 bis! ;  \ ECLIC_CLICINTIE_52_IE    IE

\ ECLIC_CLICINTIE_53 (read-write)
: ECLIC_CLICINTIE_53_IE   %1 0 lshift ECLIC_CLICINTIE_53 bis! ;  \ ECLIC_CLICINTIE_53_IE    IE

\ ECLIC_CLICINTIE_54 (read-write)
: ECLIC_CLICINTIE_54_IE   %1 0 lshift ECLIC_CLICINTIE_54 bis! ;  \ ECLIC_CLICINTIE_54_IE    IE

\ ECLIC_CLICINTIE_55 (read-write)
: ECLIC_CLICINTIE_55_IE   %1 0 lshift ECLIC_CLICINTIE_55 bis! ;  \ ECLIC_CLICINTIE_55_IE    IE

\ ECLIC_CLICINTIE_56 (read-write)
: ECLIC_CLICINTIE_56_IE   %1 0 lshift ECLIC_CLICINTIE_56 bis! ;  \ ECLIC_CLICINTIE_56_IE    IE

\ ECLIC_CLICINTIE_57 (read-write)
: ECLIC_CLICINTIE_57_IE   %1 0 lshift ECLIC_CLICINTIE_57 bis! ;  \ ECLIC_CLICINTIE_57_IE    IE

\ ECLIC_CLICINTIE_58 (read-write)
: ECLIC_CLICINTIE_58_IE   %1 0 lshift ECLIC_CLICINTIE_58 bis! ;  \ ECLIC_CLICINTIE_58_IE    IE

\ ECLIC_CLICINTIE_59 (read-write)
: ECLIC_CLICINTIE_59_IE   %1 0 lshift ECLIC_CLICINTIE_59 bis! ;  \ ECLIC_CLICINTIE_59_IE    IE

\ ECLIC_CLICINTIE_60 (read-write)
: ECLIC_CLICINTIE_60_IE   %1 0 lshift ECLIC_CLICINTIE_60 bis! ;  \ ECLIC_CLICINTIE_60_IE    IE

\ ECLIC_CLICINTIE_61 (read-write)
: ECLIC_CLICINTIE_61_IE   %1 0 lshift ECLIC_CLICINTIE_61 bis! ;  \ ECLIC_CLICINTIE_61_IE    IE

\ ECLIC_CLICINTIE_62 (read-write)
: ECLIC_CLICINTIE_62_IE   %1 0 lshift ECLIC_CLICINTIE_62 bis! ;  \ ECLIC_CLICINTIE_62_IE    IE

\ ECLIC_CLICINTIE_63 (read-write)
: ECLIC_CLICINTIE_63_IE   %1 0 lshift ECLIC_CLICINTIE_63 bis! ;  \ ECLIC_CLICINTIE_63_IE    IE

\ ECLIC_CLICINTIE_64 (read-write)
: ECLIC_CLICINTIE_64_IE   %1 0 lshift ECLIC_CLICINTIE_64 bis! ;  \ ECLIC_CLICINTIE_64_IE    IE

\ ECLIC_CLICINTIE_65 (read-write)
: ECLIC_CLICINTIE_65_IE   %1 0 lshift ECLIC_CLICINTIE_65 bis! ;  \ ECLIC_CLICINTIE_65_IE    IE

\ ECLIC_CLICINTIE_66 (read-write)
: ECLIC_CLICINTIE_66_IE   %1 0 lshift ECLIC_CLICINTIE_66 bis! ;  \ ECLIC_CLICINTIE_66_IE    IE

\ ECLIC_CLICINTIE_67 (read-write)
: ECLIC_CLICINTIE_67_IE   %1 0 lshift ECLIC_CLICINTIE_67 bis! ;  \ ECLIC_CLICINTIE_67_IE    IE

\ ECLIC_CLICINTIE_68 (read-write)
: ECLIC_CLICINTIE_68_IE   %1 0 lshift ECLIC_CLICINTIE_68 bis! ;  \ ECLIC_CLICINTIE_68_IE    IE

\ ECLIC_CLICINTIE_69 (read-write)
: ECLIC_CLICINTIE_69_IE   %1 0 lshift ECLIC_CLICINTIE_69 bis! ;  \ ECLIC_CLICINTIE_69_IE    IE

\ ECLIC_CLICINTIE_70 (read-write)
: ECLIC_CLICINTIE_70_IE   %1 0 lshift ECLIC_CLICINTIE_70 bis! ;  \ ECLIC_CLICINTIE_70_IE    IE

\ ECLIC_CLICINTIE_71 (read-write)
: ECLIC_CLICINTIE_71_IE   %1 0 lshift ECLIC_CLICINTIE_71 bis! ;  \ ECLIC_CLICINTIE_71_IE    IE

\ ECLIC_CLICINTIE_72 (read-write)
: ECLIC_CLICINTIE_72_IE   %1 0 lshift ECLIC_CLICINTIE_72 bis! ;  \ ECLIC_CLICINTIE_72_IE    IE

\ ECLIC_CLICINTIE_73 (read-write)
: ECLIC_CLICINTIE_73_IE   %1 0 lshift ECLIC_CLICINTIE_73 bis! ;  \ ECLIC_CLICINTIE_73_IE    IE

\ ECLIC_CLICINTIE_74 (read-write)
: ECLIC_CLICINTIE_74_IE   %1 0 lshift ECLIC_CLICINTIE_74 bis! ;  \ ECLIC_CLICINTIE_74_IE    IE

\ ECLIC_CLICINTIE_75 (read-write)
: ECLIC_CLICINTIE_75_IE   %1 0 lshift ECLIC_CLICINTIE_75 bis! ;  \ ECLIC_CLICINTIE_75_IE    IE

\ ECLIC_CLICINTIE_76 (read-write)
: ECLIC_CLICINTIE_76_IE   %1 0 lshift ECLIC_CLICINTIE_76 bis! ;  \ ECLIC_CLICINTIE_76_IE    IE

\ ECLIC_CLICINTIE_77 (read-write)
: ECLIC_CLICINTIE_77_IE   %1 0 lshift ECLIC_CLICINTIE_77 bis! ;  \ ECLIC_CLICINTIE_77_IE    IE

\ ECLIC_CLICINTIE_78 (read-write)
: ECLIC_CLICINTIE_78_IE   %1 0 lshift ECLIC_CLICINTIE_78 bis! ;  \ ECLIC_CLICINTIE_78_IE    IE

\ ECLIC_CLICINTIE_79 (read-write)
: ECLIC_CLICINTIE_79_IE   %1 0 lshift ECLIC_CLICINTIE_79 bis! ;  \ ECLIC_CLICINTIE_79_IE    IE

\ ECLIC_CLICINTIE_80 (read-write)
: ECLIC_CLICINTIE_80_IE   %1 0 lshift ECLIC_CLICINTIE_80 bis! ;  \ ECLIC_CLICINTIE_80_IE    IE

\ ECLIC_CLICINTIE_81 (read-write)
: ECLIC_CLICINTIE_81_IE   %1 0 lshift ECLIC_CLICINTIE_81 bis! ;  \ ECLIC_CLICINTIE_81_IE    IE

\ ECLIC_CLICINTIE_82 (read-write)
: ECLIC_CLICINTIE_82_IE   %1 0 lshift ECLIC_CLICINTIE_82 bis! ;  \ ECLIC_CLICINTIE_82_IE    IE

\ ECLIC_CLICINTIE_83 (read-write)
: ECLIC_CLICINTIE_83_IE   %1 0 lshift ECLIC_CLICINTIE_83 bis! ;  \ ECLIC_CLICINTIE_83_IE    IE

\ ECLIC_CLICINTIE_84 (read-write)
: ECLIC_CLICINTIE_84_IE   %1 0 lshift ECLIC_CLICINTIE_84 bis! ;  \ ECLIC_CLICINTIE_84_IE    IE

\ ECLIC_CLICINTIE_85 (read-write)
: ECLIC_CLICINTIE_85_IE   %1 0 lshift ECLIC_CLICINTIE_85 bis! ;  \ ECLIC_CLICINTIE_85_IE    IE

\ ECLIC_CLICINTIE_86 (read-write)
: ECLIC_CLICINTIE_86_IE   %1 0 lshift ECLIC_CLICINTIE_86 bis! ;  \ ECLIC_CLICINTIE_86_IE    IE

\ ECLIC_CLICINTATTR_0 (read-write)
: ECLIC_CLICINTATTR_0_SHV   %1 0 lshift ECLIC_CLICINTATTR_0 bis! ;  \ ECLIC_CLICINTATTR_0_SHV    SHV
: ECLIC_CLICINTATTR_0_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_0 bis! ;  \ ECLIC_CLICINTATTR_0_TRIG    TRIG

\ ECLIC_CLICINTATTR_1 (read-write)
: ECLIC_CLICINTATTR_1_SHV   %1 0 lshift ECLIC_CLICINTATTR_1 bis! ;  \ ECLIC_CLICINTATTR_1_SHV    SHV
: ECLIC_CLICINTATTR_1_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_1 bis! ;  \ ECLIC_CLICINTATTR_1_TRIG    TRIG

\ ECLIC_CLICINTATTR_2 (read-write)
: ECLIC_CLICINTATTR_2_SHV   %1 0 lshift ECLIC_CLICINTATTR_2 bis! ;  \ ECLIC_CLICINTATTR_2_SHV    SHV
: ECLIC_CLICINTATTR_2_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_2 bis! ;  \ ECLIC_CLICINTATTR_2_TRIG    TRIG

\ ECLIC_CLICINTATTR_3 (read-write)
: ECLIC_CLICINTATTR_3_SHV   %1 0 lshift ECLIC_CLICINTATTR_3 bis! ;  \ ECLIC_CLICINTATTR_3_SHV    SHV
: ECLIC_CLICINTATTR_3_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_3 bis! ;  \ ECLIC_CLICINTATTR_3_TRIG    TRIG

\ ECLIC_CLICINTATTR_4 (read-write)
: ECLIC_CLICINTATTR_4_SHV   %1 0 lshift ECLIC_CLICINTATTR_4 bis! ;  \ ECLIC_CLICINTATTR_4_SHV    SHV
: ECLIC_CLICINTATTR_4_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_4 bis! ;  \ ECLIC_CLICINTATTR_4_TRIG    TRIG

\ ECLIC_CLICINTATTR_5 (read-write)
: ECLIC_CLICINTATTR_5_SHV   %1 0 lshift ECLIC_CLICINTATTR_5 bis! ;  \ ECLIC_CLICINTATTR_5_SHV    SHV
: ECLIC_CLICINTATTR_5_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_5 bis! ;  \ ECLIC_CLICINTATTR_5_TRIG    TRIG

\ ECLIC_CLICINTATTR_6 (read-write)
: ECLIC_CLICINTATTR_6_SHV   %1 0 lshift ECLIC_CLICINTATTR_6 bis! ;  \ ECLIC_CLICINTATTR_6_SHV    SHV
: ECLIC_CLICINTATTR_6_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_6 bis! ;  \ ECLIC_CLICINTATTR_6_TRIG    TRIG

\ ECLIC_CLICINTATTR_7 (read-write)
: ECLIC_CLICINTATTR_7_SHV   %1 0 lshift ECLIC_CLICINTATTR_7 bis! ;  \ ECLIC_CLICINTATTR_7_SHV    SHV
: ECLIC_CLICINTATTR_7_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_7 bis! ;  \ ECLIC_CLICINTATTR_7_TRIG    TRIG

\ ECLIC_CLICINTATTR_8 (read-write)
: ECLIC_CLICINTATTR_8_SHV   %1 0 lshift ECLIC_CLICINTATTR_8 bis! ;  \ ECLIC_CLICINTATTR_8_SHV    SHV
: ECLIC_CLICINTATTR_8_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_8 bis! ;  \ ECLIC_CLICINTATTR_8_TRIG    TRIG

\ ECLIC_CLICINTATTR_9 (read-write)
: ECLIC_CLICINTATTR_9_SHV   %1 0 lshift ECLIC_CLICINTATTR_9 bis! ;  \ ECLIC_CLICINTATTR_9_SHV    SHV
: ECLIC_CLICINTATTR_9_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_9 bis! ;  \ ECLIC_CLICINTATTR_9_TRIG    TRIG

\ ECLIC_CLICINTATTR_10 (read-write)
: ECLIC_CLICINTATTR_10_SHV   %1 0 lshift ECLIC_CLICINTATTR_10 bis! ;  \ ECLIC_CLICINTATTR_10_SHV    SHV
: ECLIC_CLICINTATTR_10_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_10 bis! ;  \ ECLIC_CLICINTATTR_10_TRIG    TRIG

\ ECLIC_CLICINTATTR_11 (read-write)
: ECLIC_CLICINTATTR_11_SHV   %1 0 lshift ECLIC_CLICINTATTR_11 bis! ;  \ ECLIC_CLICINTATTR_11_SHV    SHV
: ECLIC_CLICINTATTR_11_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_11 bis! ;  \ ECLIC_CLICINTATTR_11_TRIG    TRIG

\ ECLIC_CLICINTATTR_12 (read-write)
: ECLIC_CLICINTATTR_12_SHV   %1 0 lshift ECLIC_CLICINTATTR_12 bis! ;  \ ECLIC_CLICINTATTR_12_SHV    SHV
: ECLIC_CLICINTATTR_12_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_12 bis! ;  \ ECLIC_CLICINTATTR_12_TRIG    TRIG

\ ECLIC_CLICINTATTR_13 (read-write)
: ECLIC_CLICINTATTR_13_SHV   %1 0 lshift ECLIC_CLICINTATTR_13 bis! ;  \ ECLIC_CLICINTATTR_13_SHV    SHV
: ECLIC_CLICINTATTR_13_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_13 bis! ;  \ ECLIC_CLICINTATTR_13_TRIG    TRIG

\ ECLIC_CLICINTATTR_14 (read-write)
: ECLIC_CLICINTATTR_14_SHV   %1 0 lshift ECLIC_CLICINTATTR_14 bis! ;  \ ECLIC_CLICINTATTR_14_SHV    SHV
: ECLIC_CLICINTATTR_14_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_14 bis! ;  \ ECLIC_CLICINTATTR_14_TRIG    TRIG

\ ECLIC_CLICINTATTR_15 (read-write)
: ECLIC_CLICINTATTR_15_SHV   %1 0 lshift ECLIC_CLICINTATTR_15 bis! ;  \ ECLIC_CLICINTATTR_15_SHV    SHV
: ECLIC_CLICINTATTR_15_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_15 bis! ;  \ ECLIC_CLICINTATTR_15_TRIG    TRIG

\ ECLIC_CLICINTATTR_16 (read-write)
: ECLIC_CLICINTATTR_16_SHV   %1 0 lshift ECLIC_CLICINTATTR_16 bis! ;  \ ECLIC_CLICINTATTR_16_SHV    SHV
: ECLIC_CLICINTATTR_16_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_16 bis! ;  \ ECLIC_CLICINTATTR_16_TRIG    TRIG

\ ECLIC_CLICINTATTR_17 (read-write)
: ECLIC_CLICINTATTR_17_SHV   %1 0 lshift ECLIC_CLICINTATTR_17 bis! ;  \ ECLIC_CLICINTATTR_17_SHV    SHV
: ECLIC_CLICINTATTR_17_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_17 bis! ;  \ ECLIC_CLICINTATTR_17_TRIG    TRIG

\ ECLIC_CLICINTATTR_18 (read-write)
: ECLIC_CLICINTATTR_18_SHV   %1 0 lshift ECLIC_CLICINTATTR_18 bis! ;  \ ECLIC_CLICINTATTR_18_SHV    SHV
: ECLIC_CLICINTATTR_18_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_18 bis! ;  \ ECLIC_CLICINTATTR_18_TRIG    TRIG

\ ECLIC_CLICINTATTR_19 (read-write)
: ECLIC_CLICINTATTR_19_SHV   %1 0 lshift ECLIC_CLICINTATTR_19 bis! ;  \ ECLIC_CLICINTATTR_19_SHV    SHV
: ECLIC_CLICINTATTR_19_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_19 bis! ;  \ ECLIC_CLICINTATTR_19_TRIG    TRIG

\ ECLIC_CLICINTATTR_20 (read-write)
: ECLIC_CLICINTATTR_20_SHV   %1 0 lshift ECLIC_CLICINTATTR_20 bis! ;  \ ECLIC_CLICINTATTR_20_SHV    SHV
: ECLIC_CLICINTATTR_20_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_20 bis! ;  \ ECLIC_CLICINTATTR_20_TRIG    TRIG

\ ECLIC_CLICINTATTR_21 (read-write)
: ECLIC_CLICINTATTR_21_SHV   %1 0 lshift ECLIC_CLICINTATTR_21 bis! ;  \ ECLIC_CLICINTATTR_21_SHV    SHV
: ECLIC_CLICINTATTR_21_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_21 bis! ;  \ ECLIC_CLICINTATTR_21_TRIG    TRIG

\ ECLIC_CLICINTATTR_22 (read-write)
: ECLIC_CLICINTATTR_22_SHV   %1 0 lshift ECLIC_CLICINTATTR_22 bis! ;  \ ECLIC_CLICINTATTR_22_SHV    SHV
: ECLIC_CLICINTATTR_22_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_22 bis! ;  \ ECLIC_CLICINTATTR_22_TRIG    TRIG

\ ECLIC_CLICINTATTR_23 (read-write)
: ECLIC_CLICINTATTR_23_SHV   %1 0 lshift ECLIC_CLICINTATTR_23 bis! ;  \ ECLIC_CLICINTATTR_23_SHV    SHV
: ECLIC_CLICINTATTR_23_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_23 bis! ;  \ ECLIC_CLICINTATTR_23_TRIG    TRIG

\ ECLIC_CLICINTATTR_24 (read-write)
: ECLIC_CLICINTATTR_24_SHV   %1 0 lshift ECLIC_CLICINTATTR_24 bis! ;  \ ECLIC_CLICINTATTR_24_SHV    SHV
: ECLIC_CLICINTATTR_24_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_24 bis! ;  \ ECLIC_CLICINTATTR_24_TRIG    TRIG

\ ECLIC_CLICINTATTR_25 (read-write)
: ECLIC_CLICINTATTR_25_SHV   %1 0 lshift ECLIC_CLICINTATTR_25 bis! ;  \ ECLIC_CLICINTATTR_25_SHV    SHV
: ECLIC_CLICINTATTR_25_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_25 bis! ;  \ ECLIC_CLICINTATTR_25_TRIG    TRIG

\ ECLIC_CLICINTATTR_26 (read-write)
: ECLIC_CLICINTATTR_26_SHV   %1 0 lshift ECLIC_CLICINTATTR_26 bis! ;  \ ECLIC_CLICINTATTR_26_SHV    SHV
: ECLIC_CLICINTATTR_26_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_26 bis! ;  \ ECLIC_CLICINTATTR_26_TRIG    TRIG

\ ECLIC_CLICINTATTR_27 (read-write)
: ECLIC_CLICINTATTR_27_SHV   %1 0 lshift ECLIC_CLICINTATTR_27 bis! ;  \ ECLIC_CLICINTATTR_27_SHV    SHV
: ECLIC_CLICINTATTR_27_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_27 bis! ;  \ ECLIC_CLICINTATTR_27_TRIG    TRIG

\ ECLIC_CLICINTATTR_28 (read-write)
: ECLIC_CLICINTATTR_28_SHV   %1 0 lshift ECLIC_CLICINTATTR_28 bis! ;  \ ECLIC_CLICINTATTR_28_SHV    SHV
: ECLIC_CLICINTATTR_28_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_28 bis! ;  \ ECLIC_CLICINTATTR_28_TRIG    TRIG

\ ECLIC_CLICINTATTR_29 (read-write)
: ECLIC_CLICINTATTR_29_SHV   %1 0 lshift ECLIC_CLICINTATTR_29 bis! ;  \ ECLIC_CLICINTATTR_29_SHV    SHV
: ECLIC_CLICINTATTR_29_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_29 bis! ;  \ ECLIC_CLICINTATTR_29_TRIG    TRIG

\ ECLIC_CLICINTATTR_30 (read-write)
: ECLIC_CLICINTATTR_30_SHV   %1 0 lshift ECLIC_CLICINTATTR_30 bis! ;  \ ECLIC_CLICINTATTR_30_SHV    SHV
: ECLIC_CLICINTATTR_30_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_30 bis! ;  \ ECLIC_CLICINTATTR_30_TRIG    TRIG

\ ECLIC_CLICINTATTR_31 (read-write)
: ECLIC_CLICINTATTR_31_SHV   %1 0 lshift ECLIC_CLICINTATTR_31 bis! ;  \ ECLIC_CLICINTATTR_31_SHV    SHV
: ECLIC_CLICINTATTR_31_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_31 bis! ;  \ ECLIC_CLICINTATTR_31_TRIG    TRIG

\ ECLIC_CLICINTATTR_32 (read-write)
: ECLIC_CLICINTATTR_32_SHV   %1 0 lshift ECLIC_CLICINTATTR_32 bis! ;  \ ECLIC_CLICINTATTR_32_SHV    SHV
: ECLIC_CLICINTATTR_32_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_32 bis! ;  \ ECLIC_CLICINTATTR_32_TRIG    TRIG

\ ECLIC_CLICINTATTR_33 (read-write)
: ECLIC_CLICINTATTR_33_SHV   %1 0 lshift ECLIC_CLICINTATTR_33 bis! ;  \ ECLIC_CLICINTATTR_33_SHV    SHV
: ECLIC_CLICINTATTR_33_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_33 bis! ;  \ ECLIC_CLICINTATTR_33_TRIG    TRIG

\ ECLIC_CLICINTATTR_34 (read-write)
: ECLIC_CLICINTATTR_34_SHV   %1 0 lshift ECLIC_CLICINTATTR_34 bis! ;  \ ECLIC_CLICINTATTR_34_SHV    SHV
: ECLIC_CLICINTATTR_34_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_34 bis! ;  \ ECLIC_CLICINTATTR_34_TRIG    TRIG

\ ECLIC_CLICINTATTR_35 (read-write)
: ECLIC_CLICINTATTR_35_SHV   %1 0 lshift ECLIC_CLICINTATTR_35 bis! ;  \ ECLIC_CLICINTATTR_35_SHV    SHV
: ECLIC_CLICINTATTR_35_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_35 bis! ;  \ ECLIC_CLICINTATTR_35_TRIG    TRIG

\ ECLIC_CLICINTATTR_36 (read-write)
: ECLIC_CLICINTATTR_36_SHV   %1 0 lshift ECLIC_CLICINTATTR_36 bis! ;  \ ECLIC_CLICINTATTR_36_SHV    SHV
: ECLIC_CLICINTATTR_36_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_36 bis! ;  \ ECLIC_CLICINTATTR_36_TRIG    TRIG

\ ECLIC_CLICINTATTR_37 (read-write)
: ECLIC_CLICINTATTR_37_SHV   %1 0 lshift ECLIC_CLICINTATTR_37 bis! ;  \ ECLIC_CLICINTATTR_37_SHV    SHV
: ECLIC_CLICINTATTR_37_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_37 bis! ;  \ ECLIC_CLICINTATTR_37_TRIG    TRIG

\ ECLIC_CLICINTATTR_38 (read-write)
: ECLIC_CLICINTATTR_38_SHV   %1 0 lshift ECLIC_CLICINTATTR_38 bis! ;  \ ECLIC_CLICINTATTR_38_SHV    SHV
: ECLIC_CLICINTATTR_38_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_38 bis! ;  \ ECLIC_CLICINTATTR_38_TRIG    TRIG

\ ECLIC_CLICINTATTR_39 (read-write)
: ECLIC_CLICINTATTR_39_SHV   %1 0 lshift ECLIC_CLICINTATTR_39 bis! ;  \ ECLIC_CLICINTATTR_39_SHV    SHV
: ECLIC_CLICINTATTR_39_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_39 bis! ;  \ ECLIC_CLICINTATTR_39_TRIG    TRIG

\ ECLIC_CLICINTATTR_40 (read-write)
: ECLIC_CLICINTATTR_40_SHV   %1 0 lshift ECLIC_CLICINTATTR_40 bis! ;  \ ECLIC_CLICINTATTR_40_SHV    SHV
: ECLIC_CLICINTATTR_40_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_40 bis! ;  \ ECLIC_CLICINTATTR_40_TRIG    TRIG

\ ECLIC_CLICINTATTR_41 (read-write)
: ECLIC_CLICINTATTR_41_SHV   %1 0 lshift ECLIC_CLICINTATTR_41 bis! ;  \ ECLIC_CLICINTATTR_41_SHV    SHV
: ECLIC_CLICINTATTR_41_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_41 bis! ;  \ ECLIC_CLICINTATTR_41_TRIG    TRIG

\ ECLIC_CLICINTATTR_42 (read-write)
: ECLIC_CLICINTATTR_42_SHV   %1 0 lshift ECLIC_CLICINTATTR_42 bis! ;  \ ECLIC_CLICINTATTR_42_SHV    SHV
: ECLIC_CLICINTATTR_42_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_42 bis! ;  \ ECLIC_CLICINTATTR_42_TRIG    TRIG

\ ECLIC_CLICINTATTR_43 (read-write)
: ECLIC_CLICINTATTR_43_SHV   %1 0 lshift ECLIC_CLICINTATTR_43 bis! ;  \ ECLIC_CLICINTATTR_43_SHV    SHV
: ECLIC_CLICINTATTR_43_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_43 bis! ;  \ ECLIC_CLICINTATTR_43_TRIG    TRIG

\ ECLIC_CLICINTATTR_44 (read-write)
: ECLIC_CLICINTATTR_44_SHV   %1 0 lshift ECLIC_CLICINTATTR_44 bis! ;  \ ECLIC_CLICINTATTR_44_SHV    SHV
: ECLIC_CLICINTATTR_44_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_44 bis! ;  \ ECLIC_CLICINTATTR_44_TRIG    TRIG

\ ECLIC_CLICINTATTR_45 (read-write)
: ECLIC_CLICINTATTR_45_SHV   %1 0 lshift ECLIC_CLICINTATTR_45 bis! ;  \ ECLIC_CLICINTATTR_45_SHV    SHV
: ECLIC_CLICINTATTR_45_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_45 bis! ;  \ ECLIC_CLICINTATTR_45_TRIG    TRIG

\ ECLIC_CLICINTATTR_46 (read-write)
: ECLIC_CLICINTATTR_46_SHV   %1 0 lshift ECLIC_CLICINTATTR_46 bis! ;  \ ECLIC_CLICINTATTR_46_SHV    SHV
: ECLIC_CLICINTATTR_46_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_46 bis! ;  \ ECLIC_CLICINTATTR_46_TRIG    TRIG

\ ECLIC_CLICINTATTR_47 (read-write)
: ECLIC_CLICINTATTR_47_SHV   %1 0 lshift ECLIC_CLICINTATTR_47 bis! ;  \ ECLIC_CLICINTATTR_47_SHV    SHV
: ECLIC_CLICINTATTR_47_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_47 bis! ;  \ ECLIC_CLICINTATTR_47_TRIG    TRIG

\ ECLIC_CLICINTATTR_48 (read-write)
: ECLIC_CLICINTATTR_48_SHV   %1 0 lshift ECLIC_CLICINTATTR_48 bis! ;  \ ECLIC_CLICINTATTR_48_SHV    SHV
: ECLIC_CLICINTATTR_48_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_48 bis! ;  \ ECLIC_CLICINTATTR_48_TRIG    TRIG

\ ECLIC_CLICINTATTR_49 (read-write)
: ECLIC_CLICINTATTR_49_SHV   %1 0 lshift ECLIC_CLICINTATTR_49 bis! ;  \ ECLIC_CLICINTATTR_49_SHV    SHV
: ECLIC_CLICINTATTR_49_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_49 bis! ;  \ ECLIC_CLICINTATTR_49_TRIG    TRIG

\ ECLIC_CLICINTATTR_50 (read-write)
: ECLIC_CLICINTATTR_50_SHV   %1 0 lshift ECLIC_CLICINTATTR_50 bis! ;  \ ECLIC_CLICINTATTR_50_SHV    SHV
: ECLIC_CLICINTATTR_50_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_50 bis! ;  \ ECLIC_CLICINTATTR_50_TRIG    TRIG

\ ECLIC_CLICINTATTR_51 (read-write)
: ECLIC_CLICINTATTR_51_SHV   %1 0 lshift ECLIC_CLICINTATTR_51 bis! ;  \ ECLIC_CLICINTATTR_51_SHV    SHV
: ECLIC_CLICINTATTR_51_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_51 bis! ;  \ ECLIC_CLICINTATTR_51_TRIG    TRIG

\ ECLIC_CLICINTATTR_52 (read-write)
: ECLIC_CLICINTATTR_52_SHV   %1 0 lshift ECLIC_CLICINTATTR_52 bis! ;  \ ECLIC_CLICINTATTR_52_SHV    SHV
: ECLIC_CLICINTATTR_52_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_52 bis! ;  \ ECLIC_CLICINTATTR_52_TRIG    TRIG

\ ECLIC_CLICINTATTR_53 (read-write)
: ECLIC_CLICINTATTR_53_SHV   %1 0 lshift ECLIC_CLICINTATTR_53 bis! ;  \ ECLIC_CLICINTATTR_53_SHV    SHV
: ECLIC_CLICINTATTR_53_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_53 bis! ;  \ ECLIC_CLICINTATTR_53_TRIG    TRIG

\ ECLIC_CLICINTATTR_54 (read-write)
: ECLIC_CLICINTATTR_54_SHV   %1 0 lshift ECLIC_CLICINTATTR_54 bis! ;  \ ECLIC_CLICINTATTR_54_SHV    SHV
: ECLIC_CLICINTATTR_54_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_54 bis! ;  \ ECLIC_CLICINTATTR_54_TRIG    TRIG

\ ECLIC_CLICINTATTR_55 (read-write)
: ECLIC_CLICINTATTR_55_SHV   %1 0 lshift ECLIC_CLICINTATTR_55 bis! ;  \ ECLIC_CLICINTATTR_55_SHV    SHV
: ECLIC_CLICINTATTR_55_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_55 bis! ;  \ ECLIC_CLICINTATTR_55_TRIG    TRIG

\ ECLIC_CLICINTATTR_56 (read-write)
: ECLIC_CLICINTATTR_56_SHV   %1 0 lshift ECLIC_CLICINTATTR_56 bis! ;  \ ECLIC_CLICINTATTR_56_SHV    SHV
: ECLIC_CLICINTATTR_56_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_56 bis! ;  \ ECLIC_CLICINTATTR_56_TRIG    TRIG

\ ECLIC_CLICINTATTR_57 (read-write)
: ECLIC_CLICINTATTR_57_SHV   %1 0 lshift ECLIC_CLICINTATTR_57 bis! ;  \ ECLIC_CLICINTATTR_57_SHV    SHV
: ECLIC_CLICINTATTR_57_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_57 bis! ;  \ ECLIC_CLICINTATTR_57_TRIG    TRIG

\ ECLIC_CLICINTATTR_58 (read-write)
: ECLIC_CLICINTATTR_58_SHV   %1 0 lshift ECLIC_CLICINTATTR_58 bis! ;  \ ECLIC_CLICINTATTR_58_SHV    SHV
: ECLIC_CLICINTATTR_58_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_58 bis! ;  \ ECLIC_CLICINTATTR_58_TRIG    TRIG

\ ECLIC_CLICINTATTR_59 (read-write)
: ECLIC_CLICINTATTR_59_SHV   %1 0 lshift ECLIC_CLICINTATTR_59 bis! ;  \ ECLIC_CLICINTATTR_59_SHV    SHV
: ECLIC_CLICINTATTR_59_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_59 bis! ;  \ ECLIC_CLICINTATTR_59_TRIG    TRIG

\ ECLIC_CLICINTATTR_60 (read-write)
: ECLIC_CLICINTATTR_60_SHV   %1 0 lshift ECLIC_CLICINTATTR_60 bis! ;  \ ECLIC_CLICINTATTR_60_SHV    SHV
: ECLIC_CLICINTATTR_60_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_60 bis! ;  \ ECLIC_CLICINTATTR_60_TRIG    TRIG

\ ECLIC_CLICINTATTR_61 (read-write)
: ECLIC_CLICINTATTR_61_SHV   %1 0 lshift ECLIC_CLICINTATTR_61 bis! ;  \ ECLIC_CLICINTATTR_61_SHV    SHV
: ECLIC_CLICINTATTR_61_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_61 bis! ;  \ ECLIC_CLICINTATTR_61_TRIG    TRIG

\ ECLIC_CLICINTATTR_62 (read-write)
: ECLIC_CLICINTATTR_62_SHV   %1 0 lshift ECLIC_CLICINTATTR_62 bis! ;  \ ECLIC_CLICINTATTR_62_SHV    SHV
: ECLIC_CLICINTATTR_62_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_62 bis! ;  \ ECLIC_CLICINTATTR_62_TRIG    TRIG

\ ECLIC_CLICINTATTR_63 (read-write)
: ECLIC_CLICINTATTR_63_SHV   %1 0 lshift ECLIC_CLICINTATTR_63 bis! ;  \ ECLIC_CLICINTATTR_63_SHV    SHV
: ECLIC_CLICINTATTR_63_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_63 bis! ;  \ ECLIC_CLICINTATTR_63_TRIG    TRIG

\ ECLIC_CLICINTATTR_64 (read-write)
: ECLIC_CLICINTATTR_64_SHV   %1 0 lshift ECLIC_CLICINTATTR_64 bis! ;  \ ECLIC_CLICINTATTR_64_SHV    SHV
: ECLIC_CLICINTATTR_64_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_64 bis! ;  \ ECLIC_CLICINTATTR_64_TRIG    TRIG

\ ECLIC_CLICINTATTR_65 (read-write)
: ECLIC_CLICINTATTR_65_SHV   %1 0 lshift ECLIC_CLICINTATTR_65 bis! ;  \ ECLIC_CLICINTATTR_65_SHV    SHV
: ECLIC_CLICINTATTR_65_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_65 bis! ;  \ ECLIC_CLICINTATTR_65_TRIG    TRIG

\ ECLIC_CLICINTATTR_66 (read-write)
: ECLIC_CLICINTATTR_66_SHV   %1 0 lshift ECLIC_CLICINTATTR_66 bis! ;  \ ECLIC_CLICINTATTR_66_SHV    SHV
: ECLIC_CLICINTATTR_66_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_66 bis! ;  \ ECLIC_CLICINTATTR_66_TRIG    TRIG

\ ECLIC_CLICINTATTR_67 (read-write)
: ECLIC_CLICINTATTR_67_SHV   %1 0 lshift ECLIC_CLICINTATTR_67 bis! ;  \ ECLIC_CLICINTATTR_67_SHV    SHV
: ECLIC_CLICINTATTR_67_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_67 bis! ;  \ ECLIC_CLICINTATTR_67_TRIG    TRIG

\ ECLIC_CLICINTATTR_68 (read-write)
: ECLIC_CLICINTATTR_68_SHV   %1 0 lshift ECLIC_CLICINTATTR_68 bis! ;  \ ECLIC_CLICINTATTR_68_SHV    SHV
: ECLIC_CLICINTATTR_68_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_68 bis! ;  \ ECLIC_CLICINTATTR_68_TRIG    TRIG

\ ECLIC_CLICINTATTR_69 (read-write)
: ECLIC_CLICINTATTR_69_SHV   %1 0 lshift ECLIC_CLICINTATTR_69 bis! ;  \ ECLIC_CLICINTATTR_69_SHV    SHV
: ECLIC_CLICINTATTR_69_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_69 bis! ;  \ ECLIC_CLICINTATTR_69_TRIG    TRIG

\ ECLIC_CLICINTATTR_70 (read-write)
: ECLIC_CLICINTATTR_70_SHV   %1 0 lshift ECLIC_CLICINTATTR_70 bis! ;  \ ECLIC_CLICINTATTR_70_SHV    SHV
: ECLIC_CLICINTATTR_70_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_70 bis! ;  \ ECLIC_CLICINTATTR_70_TRIG    TRIG

\ ECLIC_CLICINTATTR_71 (read-write)
: ECLIC_CLICINTATTR_71_SHV   %1 0 lshift ECLIC_CLICINTATTR_71 bis! ;  \ ECLIC_CLICINTATTR_71_SHV    SHV
: ECLIC_CLICINTATTR_71_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_71 bis! ;  \ ECLIC_CLICINTATTR_71_TRIG    TRIG

\ ECLIC_CLICINTATTR_72 (read-write)
: ECLIC_CLICINTATTR_72_SHV   %1 0 lshift ECLIC_CLICINTATTR_72 bis! ;  \ ECLIC_CLICINTATTR_72_SHV    SHV
: ECLIC_CLICINTATTR_72_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_72 bis! ;  \ ECLIC_CLICINTATTR_72_TRIG    TRIG

\ ECLIC_CLICINTATTR_73 (read-write)
: ECLIC_CLICINTATTR_73_SHV   %1 0 lshift ECLIC_CLICINTATTR_73 bis! ;  \ ECLIC_CLICINTATTR_73_SHV    SHV
: ECLIC_CLICINTATTR_73_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_73 bis! ;  \ ECLIC_CLICINTATTR_73_TRIG    TRIG

\ ECLIC_CLICINTATTR_74 (read-write)
: ECLIC_CLICINTATTR_74_SHV   %1 0 lshift ECLIC_CLICINTATTR_74 bis! ;  \ ECLIC_CLICINTATTR_74_SHV    SHV
: ECLIC_CLICINTATTR_74_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_74 bis! ;  \ ECLIC_CLICINTATTR_74_TRIG    TRIG

\ ECLIC_CLICINTATTR_75 (read-write)
: ECLIC_CLICINTATTR_75_SHV   %1 0 lshift ECLIC_CLICINTATTR_75 bis! ;  \ ECLIC_CLICINTATTR_75_SHV    SHV
: ECLIC_CLICINTATTR_75_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_75 bis! ;  \ ECLIC_CLICINTATTR_75_TRIG    TRIG

\ ECLIC_CLICINTATTR_76 (read-write)
: ECLIC_CLICINTATTR_76_SHV   %1 0 lshift ECLIC_CLICINTATTR_76 bis! ;  \ ECLIC_CLICINTATTR_76_SHV    SHV
: ECLIC_CLICINTATTR_76_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_76 bis! ;  \ ECLIC_CLICINTATTR_76_TRIG    TRIG

\ ECLIC_CLICINTATTR_77 (read-write)
: ECLIC_CLICINTATTR_77_SHV   %1 0 lshift ECLIC_CLICINTATTR_77 bis! ;  \ ECLIC_CLICINTATTR_77_SHV    SHV
: ECLIC_CLICINTATTR_77_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_77 bis! ;  \ ECLIC_CLICINTATTR_77_TRIG    TRIG

\ ECLIC_CLICINTATTR_78 (read-write)
: ECLIC_CLICINTATTR_78_SHV   %1 0 lshift ECLIC_CLICINTATTR_78 bis! ;  \ ECLIC_CLICINTATTR_78_SHV    SHV
: ECLIC_CLICINTATTR_78_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_78 bis! ;  \ ECLIC_CLICINTATTR_78_TRIG    TRIG

\ ECLIC_CLICINTATTR_79 (read-write)
: ECLIC_CLICINTATTR_79_SHV   %1 0 lshift ECLIC_CLICINTATTR_79 bis! ;  \ ECLIC_CLICINTATTR_79_SHV    SHV
: ECLIC_CLICINTATTR_79_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_79 bis! ;  \ ECLIC_CLICINTATTR_79_TRIG    TRIG

\ ECLIC_CLICINTATTR_80 (read-write)
: ECLIC_CLICINTATTR_80_SHV   %1 0 lshift ECLIC_CLICINTATTR_80 bis! ;  \ ECLIC_CLICINTATTR_80_SHV    SHV
: ECLIC_CLICINTATTR_80_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_80 bis! ;  \ ECLIC_CLICINTATTR_80_TRIG    TRIG

\ ECLIC_CLICINTATTR_81 (read-write)
: ECLIC_CLICINTATTR_81_SHV   %1 0 lshift ECLIC_CLICINTATTR_81 bis! ;  \ ECLIC_CLICINTATTR_81_SHV    SHV
: ECLIC_CLICINTATTR_81_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_81 bis! ;  \ ECLIC_CLICINTATTR_81_TRIG    TRIG

\ ECLIC_CLICINTATTR_82 (read-write)
: ECLIC_CLICINTATTR_82_SHV   %1 0 lshift ECLIC_CLICINTATTR_82 bis! ;  \ ECLIC_CLICINTATTR_82_SHV    SHV
: ECLIC_CLICINTATTR_82_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_82 bis! ;  \ ECLIC_CLICINTATTR_82_TRIG    TRIG

\ ECLIC_CLICINTATTR_83 (read-write)
: ECLIC_CLICINTATTR_83_SHV   %1 0 lshift ECLIC_CLICINTATTR_83 bis! ;  \ ECLIC_CLICINTATTR_83_SHV    SHV
: ECLIC_CLICINTATTR_83_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_83 bis! ;  \ ECLIC_CLICINTATTR_83_TRIG    TRIG

\ ECLIC_CLICINTATTR_84 (read-write)
: ECLIC_CLICINTATTR_84_SHV   %1 0 lshift ECLIC_CLICINTATTR_84 bis! ;  \ ECLIC_CLICINTATTR_84_SHV    SHV
: ECLIC_CLICINTATTR_84_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_84 bis! ;  \ ECLIC_CLICINTATTR_84_TRIG    TRIG

\ ECLIC_CLICINTATTR_85 (read-write)
: ECLIC_CLICINTATTR_85_SHV   %1 0 lshift ECLIC_CLICINTATTR_85 bis! ;  \ ECLIC_CLICINTATTR_85_SHV    SHV
: ECLIC_CLICINTATTR_85_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_85 bis! ;  \ ECLIC_CLICINTATTR_85_TRIG    TRIG

\ ECLIC_CLICINTATTR_86 (read-write)
: ECLIC_CLICINTATTR_86_SHV   %1 0 lshift ECLIC_CLICINTATTR_86 bis! ;  \ ECLIC_CLICINTATTR_86_SHV    SHV
: ECLIC_CLICINTATTR_86_TRIG   ( %XX -- ) 1 lshift ECLIC_CLICINTATTR_86 bis! ;  \ ECLIC_CLICINTATTR_86_TRIG    TRIG

\ ECLIC_CLICINTCTL_0 (read-write)
: ECLIC_CLICINTCTL_0_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_0 bis! ;  \ ECLIC_CLICINTCTL_0_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_1 (read-write)
: ECLIC_CLICINTCTL_1_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_1 bis! ;  \ ECLIC_CLICINTCTL_1_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_2 (read-write)
: ECLIC_CLICINTCTL_2_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_2 bis! ;  \ ECLIC_CLICINTCTL_2_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_3 (read-write)
: ECLIC_CLICINTCTL_3_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_3 bis! ;  \ ECLIC_CLICINTCTL_3_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_4 (read-write)
: ECLIC_CLICINTCTL_4_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_4 bis! ;  \ ECLIC_CLICINTCTL_4_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_5 (read-write)
: ECLIC_CLICINTCTL_5_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_5 bis! ;  \ ECLIC_CLICINTCTL_5_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_6 (read-write)
: ECLIC_CLICINTCTL_6_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_6 bis! ;  \ ECLIC_CLICINTCTL_6_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_7 (read-write)
: ECLIC_CLICINTCTL_7_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_7 bis! ;  \ ECLIC_CLICINTCTL_7_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_8 (read-write)
: ECLIC_CLICINTCTL_8_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_8 bis! ;  \ ECLIC_CLICINTCTL_8_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_9 (read-write)
: ECLIC_CLICINTCTL_9_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_9 bis! ;  \ ECLIC_CLICINTCTL_9_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_10 (read-write)
: ECLIC_CLICINTCTL_10_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_10 bis! ;  \ ECLIC_CLICINTCTL_10_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_11 (read-write)
: ECLIC_CLICINTCTL_11_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_11 bis! ;  \ ECLIC_CLICINTCTL_11_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_12 (read-write)
: ECLIC_CLICINTCTL_12_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_12 bis! ;  \ ECLIC_CLICINTCTL_12_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_13 (read-write)
: ECLIC_CLICINTCTL_13_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_13 bis! ;  \ ECLIC_CLICINTCTL_13_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_14 (read-write)
: ECLIC_CLICINTCTL_14_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_14 bis! ;  \ ECLIC_CLICINTCTL_14_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_15 (read-write)
: ECLIC_CLICINTCTL_15_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_15 bis! ;  \ ECLIC_CLICINTCTL_15_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_16 (read-write)
: ECLIC_CLICINTCTL_16_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_16 bis! ;  \ ECLIC_CLICINTCTL_16_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_17 (read-write)
: ECLIC_CLICINTCTL_17_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_17 bis! ;  \ ECLIC_CLICINTCTL_17_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_18 (read-write)
: ECLIC_CLICINTCTL_18_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_18 bis! ;  \ ECLIC_CLICINTCTL_18_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_19 (read-write)
: ECLIC_CLICINTCTL_19_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_19 bis! ;  \ ECLIC_CLICINTCTL_19_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_20 (read-write)
: ECLIC_CLICINTCTL_20_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_20 bis! ;  \ ECLIC_CLICINTCTL_20_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_21 (read-write)
: ECLIC_CLICINTCTL_21_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_21 bis! ;  \ ECLIC_CLICINTCTL_21_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_22 (read-write)
: ECLIC_CLICINTCTL_22_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_22 bis! ;  \ ECLIC_CLICINTCTL_22_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_23 (read-write)
: ECLIC_CLICINTCTL_23_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_23 bis! ;  \ ECLIC_CLICINTCTL_23_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_24 (read-write)
: ECLIC_CLICINTCTL_24_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_24 bis! ;  \ ECLIC_CLICINTCTL_24_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_25 (read-write)
: ECLIC_CLICINTCTL_25_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_25 bis! ;  \ ECLIC_CLICINTCTL_25_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_26 (read-write)
: ECLIC_CLICINTCTL_26_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_26 bis! ;  \ ECLIC_CLICINTCTL_26_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_27 (read-write)
: ECLIC_CLICINTCTL_27_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_27 bis! ;  \ ECLIC_CLICINTCTL_27_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_28 (read-write)
: ECLIC_CLICINTCTL_28_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_28 bis! ;  \ ECLIC_CLICINTCTL_28_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_29 (read-write)
: ECLIC_CLICINTCTL_29_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_29 bis! ;  \ ECLIC_CLICINTCTL_29_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_30 (read-write)
: ECLIC_CLICINTCTL_30_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_30 bis! ;  \ ECLIC_CLICINTCTL_30_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_31 (read-write)
: ECLIC_CLICINTCTL_31_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_31 bis! ;  \ ECLIC_CLICINTCTL_31_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_32 (read-write)
: ECLIC_CLICINTCTL_32_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_32 bis! ;  \ ECLIC_CLICINTCTL_32_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_33 (read-write)
: ECLIC_CLICINTCTL_33_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_33 bis! ;  \ ECLIC_CLICINTCTL_33_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_34 (read-write)
: ECLIC_CLICINTCTL_34_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_34 bis! ;  \ ECLIC_CLICINTCTL_34_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_35 (read-write)
: ECLIC_CLICINTCTL_35_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_35 bis! ;  \ ECLIC_CLICINTCTL_35_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_36 (read-write)
: ECLIC_CLICINTCTL_36_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_36 bis! ;  \ ECLIC_CLICINTCTL_36_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_37 (read-write)
: ECLIC_CLICINTCTL_37_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_37 bis! ;  \ ECLIC_CLICINTCTL_37_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_38 (read-write)
: ECLIC_CLICINTCTL_38_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_38 bis! ;  \ ECLIC_CLICINTCTL_38_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_39 (read-write)
: ECLIC_CLICINTCTL_39_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_39 bis! ;  \ ECLIC_CLICINTCTL_39_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_40 (read-write)
: ECLIC_CLICINTCTL_40_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_40 bis! ;  \ ECLIC_CLICINTCTL_40_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_41 (read-write)
: ECLIC_CLICINTCTL_41_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_41 bis! ;  \ ECLIC_CLICINTCTL_41_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_42 (read-write)
: ECLIC_CLICINTCTL_42_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_42 bis! ;  \ ECLIC_CLICINTCTL_42_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_43 (read-write)
: ECLIC_CLICINTCTL_43_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_43 bis! ;  \ ECLIC_CLICINTCTL_43_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_44 (read-write)
: ECLIC_CLICINTCTL_44_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_44 bis! ;  \ ECLIC_CLICINTCTL_44_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_45 (read-write)
: ECLIC_CLICINTCTL_45_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_45 bis! ;  \ ECLIC_CLICINTCTL_45_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_46 (read-write)
: ECLIC_CLICINTCTL_46_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_46 bis! ;  \ ECLIC_CLICINTCTL_46_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_47 (read-write)
: ECLIC_CLICINTCTL_47_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_47 bis! ;  \ ECLIC_CLICINTCTL_47_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_48 (read-write)
: ECLIC_CLICINTCTL_48_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_48 bis! ;  \ ECLIC_CLICINTCTL_48_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_49 (read-write)
: ECLIC_CLICINTCTL_49_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_49 bis! ;  \ ECLIC_CLICINTCTL_49_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_50 (read-write)
: ECLIC_CLICINTCTL_50_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_50 bis! ;  \ ECLIC_CLICINTCTL_50_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_51 (read-write)
: ECLIC_CLICINTCTL_51_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_51 bis! ;  \ ECLIC_CLICINTCTL_51_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_52 (read-write)
: ECLIC_CLICINTCTL_52_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_52 bis! ;  \ ECLIC_CLICINTCTL_52_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_53 (read-write)
: ECLIC_CLICINTCTL_53_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_53 bis! ;  \ ECLIC_CLICINTCTL_53_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_54 (read-write)
: ECLIC_CLICINTCTL_54_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_54 bis! ;  \ ECLIC_CLICINTCTL_54_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_55 (read-write)
: ECLIC_CLICINTCTL_55_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_55 bis! ;  \ ECLIC_CLICINTCTL_55_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_56 (read-write)
: ECLIC_CLICINTCTL_56_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_56 bis! ;  \ ECLIC_CLICINTCTL_56_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_57 (read-write)
: ECLIC_CLICINTCTL_57_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_57 bis! ;  \ ECLIC_CLICINTCTL_57_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_58 (read-write)
: ECLIC_CLICINTCTL_58_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_58 bis! ;  \ ECLIC_CLICINTCTL_58_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_59 (read-write)
: ECLIC_CLICINTCTL_59_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_59 bis! ;  \ ECLIC_CLICINTCTL_59_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_60 (read-write)
: ECLIC_CLICINTCTL_60_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_60 bis! ;  \ ECLIC_CLICINTCTL_60_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_61 (read-write)
: ECLIC_CLICINTCTL_61_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_61 bis! ;  \ ECLIC_CLICINTCTL_61_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_62 (read-write)
: ECLIC_CLICINTCTL_62_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_62 bis! ;  \ ECLIC_CLICINTCTL_62_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_63 (read-write)
: ECLIC_CLICINTCTL_63_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_63 bis! ;  \ ECLIC_CLICINTCTL_63_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_64 (read-write)
: ECLIC_CLICINTCTL_64_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_64 bis! ;  \ ECLIC_CLICINTCTL_64_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_65 (read-write)
: ECLIC_CLICINTCTL_65_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_65 bis! ;  \ ECLIC_CLICINTCTL_65_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_66 (read-write)
: ECLIC_CLICINTCTL_66_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_66 bis! ;  \ ECLIC_CLICINTCTL_66_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_67 (read-write)
: ECLIC_CLICINTCTL_67_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_67 bis! ;  \ ECLIC_CLICINTCTL_67_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_68 (read-write)
: ECLIC_CLICINTCTL_68_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_68 bis! ;  \ ECLIC_CLICINTCTL_68_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_69 (read-write)
: ECLIC_CLICINTCTL_69_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_69 bis! ;  \ ECLIC_CLICINTCTL_69_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_70 (read-write)
: ECLIC_CLICINTCTL_70_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_70 bis! ;  \ ECLIC_CLICINTCTL_70_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_71 (read-write)
: ECLIC_CLICINTCTL_71_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_71 bis! ;  \ ECLIC_CLICINTCTL_71_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_72 (read-write)
: ECLIC_CLICINTCTL_72_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_72 bis! ;  \ ECLIC_CLICINTCTL_72_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_73 (read-write)
: ECLIC_CLICINTCTL_73_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_73 bis! ;  \ ECLIC_CLICINTCTL_73_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_74 (read-write)
: ECLIC_CLICINTCTL_74_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_74 bis! ;  \ ECLIC_CLICINTCTL_74_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_75 (read-write)
: ECLIC_CLICINTCTL_75_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_75 bis! ;  \ ECLIC_CLICINTCTL_75_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_76 (read-write)
: ECLIC_CLICINTCTL_76_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_76 bis! ;  \ ECLIC_CLICINTCTL_76_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_77 (read-write)
: ECLIC_CLICINTCTL_77_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_77 bis! ;  \ ECLIC_CLICINTCTL_77_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_78 (read-write)
: ECLIC_CLICINTCTL_78_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_78 bis! ;  \ ECLIC_CLICINTCTL_78_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_79 (read-write)
: ECLIC_CLICINTCTL_79_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_79 bis! ;  \ ECLIC_CLICINTCTL_79_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_80 (read-write)
: ECLIC_CLICINTCTL_80_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_80 bis! ;  \ ECLIC_CLICINTCTL_80_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_81 (read-write)
: ECLIC_CLICINTCTL_81_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_81 bis! ;  \ ECLIC_CLICINTCTL_81_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_82 (read-write)
: ECLIC_CLICINTCTL_82_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_82 bis! ;  \ ECLIC_CLICINTCTL_82_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_83 (read-write)
: ECLIC_CLICINTCTL_83_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_83 bis! ;  \ ECLIC_CLICINTCTL_83_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_84 (read-write)
: ECLIC_CLICINTCTL_84_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_84 bis! ;  \ ECLIC_CLICINTCTL_84_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_85 (read-write)
: ECLIC_CLICINTCTL_85_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_85 bis! ;  \ ECLIC_CLICINTCTL_85_LEVEL_PRIORITY    LEVEL_PRIORITY

\ ECLIC_CLICINTCTL_86 (read-write)
: ECLIC_CLICINTCTL_86_LEVEL_PRIORITY   ( %XXXXXXXX -- ) 0 lshift ECLIC_CLICINTCTL_86 bis! ;  \ ECLIC_CLICINTCTL_86_LEVEL_PRIORITY    LEVEL_PRIORITY

\ PMU_CTL (read-write)
: PMU_CTL_BKPWEN   %1 8 lshift PMU_CTL bis! ;  \ PMU_CTL_BKPWEN    Backup Domain Write Enable
: PMU_CTL_LVDT   ( %XXX -- ) 5 lshift PMU_CTL bis! ;  \ PMU_CTL_LVDT    Low Voltage Detector Threshold
: PMU_CTL_LVDEN   %1 4 lshift PMU_CTL bis! ;  \ PMU_CTL_LVDEN    Low Voltage Detector Enable
: PMU_CTL_STBRST   %1 3 lshift PMU_CTL bis! ;  \ PMU_CTL_STBRST    Standby Flag Reset
: PMU_CTL_WURST   %1 2 lshift PMU_CTL bis! ;  \ PMU_CTL_WURST    Wakeup Flag Reset
: PMU_CTL_STBMOD   %1 1 lshift PMU_CTL bis! ;  \ PMU_CTL_STBMOD    Standby Mode
: PMU_CTL_LDOLP   %1 0 lshift PMU_CTL bis! ;  \ PMU_CTL_LDOLP    LDO Low Power Mode

\ PMU_CS ()
: PMU_CS_WUPEN   %1 8 lshift PMU_CS bis! ;  \ PMU_CS_WUPEN    Enable WKUP pin
: PMU_CS_LVDF   %1 2 lshift PMU_CS bis! ;  \ PMU_CS_LVDF    Low Voltage Detector Status Flag
: PMU_CS_STBF   %1 1 lshift PMU_CS bis! ;  \ PMU_CS_STBF    Standby flag
: PMU_CS_WUF   %1 0 lshift PMU_CS bis! ;  \ PMU_CS_WUF    Wakeup flag

\ RCU_CTL ()
: RCU_CTL_IRC8MEN   %1 0 lshift RCU_CTL bis! ;  \ RCU_CTL_IRC8MEN    Internal 8MHz RC oscillator Enable
: RCU_CTL_IRC8MSTB   %1 1 lshift RCU_CTL bis! ;  \ RCU_CTL_IRC8MSTB    IRC8M Internal 8MHz RC Oscillator stabilization Flag
: RCU_CTL_IRC8MADJ   ( %XXXXX -- ) 3 lshift RCU_CTL bis! ;  \ RCU_CTL_IRC8MADJ    Internal 8MHz RC Oscillator clock trim adjust value
: RCU_CTL_IRC8MCALIB   ( %XXXXXXXX -- ) 8 lshift RCU_CTL bis! ;  \ RCU_CTL_IRC8MCALIB    Internal 8MHz RC Oscillator calibration value register
: RCU_CTL_HXTALEN   %1 16 lshift RCU_CTL bis! ;  \ RCU_CTL_HXTALEN    External High Speed oscillator Enable
: RCU_CTL_HXTALSTB   %1 17 lshift RCU_CTL bis! ;  \ RCU_CTL_HXTALSTB    External crystal oscillator HXTAL clock stabilization flag
: RCU_CTL_HXTALBPS   %1 18 lshift RCU_CTL bis! ;  \ RCU_CTL_HXTALBPS    External crystal oscillator HXTAL clock bypass mode enable
: RCU_CTL_CKMEN   %1 19 lshift RCU_CTL bis! ;  \ RCU_CTL_CKMEN    HXTAL Clock Monitor Enable
: RCU_CTL_PLLEN   %1 24 lshift RCU_CTL bis! ;  \ RCU_CTL_PLLEN    PLL enable
: RCU_CTL_PLLSTB   %1 25 lshift RCU_CTL bis! ;  \ RCU_CTL_PLLSTB    PLL Clock Stabilization Flag
: RCU_CTL_PLL1EN   %1 26 lshift RCU_CTL bis! ;  \ RCU_CTL_PLL1EN    PLL1 enable
: RCU_CTL_PLL1STB   %1 27 lshift RCU_CTL bis! ;  \ RCU_CTL_PLL1STB    PLL1 Clock Stabilization Flag
: RCU_CTL_PLL2EN   %1 28 lshift RCU_CTL bis! ;  \ RCU_CTL_PLL2EN    PLL2 enable
: RCU_CTL_PLL2STB   %1 29 lshift RCU_CTL bis! ;  \ RCU_CTL_PLL2STB    PLL2 Clock Stabilization Flag

\ RCU_CFG0 ()
: RCU_CFG0_SCS   ( %XX -- ) 0 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_SCS    System clock switch
: RCU_CFG0_SCSS   ( %XX -- ) 2 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_SCSS    System clock switch status
: RCU_CFG0_AHBPSC   ( %XXXX -- ) 4 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_AHBPSC    AHB prescaler selection
: RCU_CFG0_APB1PSC   ( %XXX -- ) 8 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_APB1PSC    APB1 prescaler selection
: RCU_CFG0_APB2PSC   ( %XXX -- ) 11 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_APB2PSC    APB2 prescaler selection
: RCU_CFG0_ADCPSC_1_0   ( %XX -- ) 14 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_ADCPSC_1_0    ADC clock prescaler selection
: RCU_CFG0_PLLSEL   %1 16 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_PLLSEL    PLL Clock Source Selection
: RCU_CFG0_PREDV0_LSB   %1 17 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_PREDV0_LSB    The LSB of PREDV0 division factor
: RCU_CFG0_PLLMF_3_0   ( %XXXX -- ) 18 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_PLLMF_3_0    The PLL clock multiplication factor
: RCU_CFG0_USBFSPSC   ( %XX -- ) 22 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_USBFSPSC    USBFS clock prescaler selection
: RCU_CFG0_CKOUT0SEL   ( %XXXX -- ) 24 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_CKOUT0SEL    CKOUT0 Clock Source Selection
: RCU_CFG0_ADCPSC_2   %1 28 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_ADCPSC_2    Bit 2 of ADCPSC
: RCU_CFG0_PLLMF_4   %1 29 lshift RCU_CFG0 bis! ;  \ RCU_CFG0_PLLMF_4    Bit 4 of PLLMF

\ RCU_INT ()
: RCU_INT_IRC40KSTBIF   %1 0 lshift RCU_INT bis! ;  \ RCU_INT_IRC40KSTBIF    IRC40K stabilization interrupt flag
: RCU_INT_LXTALSTBIF   %1 1 lshift RCU_INT bis! ;  \ RCU_INT_LXTALSTBIF    LXTAL stabilization interrupt flag
: RCU_INT_IRC8MSTBIF   %1 2 lshift RCU_INT bis! ;  \ RCU_INT_IRC8MSTBIF    IRC8M stabilization interrupt flag
: RCU_INT_HXTALSTBIF   %1 3 lshift RCU_INT bis! ;  \ RCU_INT_HXTALSTBIF    HXTAL stabilization interrupt flag
: RCU_INT_PLLSTBIF   %1 4 lshift RCU_INT bis! ;  \ RCU_INT_PLLSTBIF    PLL stabilization interrupt flag
: RCU_INT_PLL1STBIF   %1 5 lshift RCU_INT bis! ;  \ RCU_INT_PLL1STBIF    PLL1 stabilization interrupt flag
: RCU_INT_PLL2STBIF   %1 6 lshift RCU_INT bis! ;  \ RCU_INT_PLL2STBIF    PLL2 stabilization interrupt flag
: RCU_INT_CKMIF   %1 7 lshift RCU_INT bis! ;  \ RCU_INT_CKMIF    HXTAL Clock Stuck Interrupt Flag
: RCU_INT_IRC40KSTBIE   %1 8 lshift RCU_INT bis! ;  \ RCU_INT_IRC40KSTBIE    IRC40K Stabilization interrupt enable
: RCU_INT_LXTALSTBIE   %1 9 lshift RCU_INT bis! ;  \ RCU_INT_LXTALSTBIE    LXTAL Stabilization Interrupt Enable
: RCU_INT_IRC8MSTBIE   %1 10 lshift RCU_INT bis! ;  \ RCU_INT_IRC8MSTBIE    IRC8M Stabilization Interrupt Enable
: RCU_INT_HXTALSTBIE   %1 11 lshift RCU_INT bis! ;  \ RCU_INT_HXTALSTBIE    HXTAL Stabilization Interrupt Enable
: RCU_INT_PLLSTBIE   %1 12 lshift RCU_INT bis! ;  \ RCU_INT_PLLSTBIE    PLL Stabilization Interrupt Enable
: RCU_INT_PLL1STBIE   %1 13 lshift RCU_INT bis! ;  \ RCU_INT_PLL1STBIE    PLL1 Stabilization Interrupt Enable
: RCU_INT_PLL2STBIE   %1 14 lshift RCU_INT bis! ;  \ RCU_INT_PLL2STBIE    PLL2 Stabilization Interrupt Enable
: RCU_INT_IRC40KSTBIC   %1 16 lshift RCU_INT bis! ;  \ RCU_INT_IRC40KSTBIC    IRC40K Stabilization Interrupt Clear
: RCU_INT_LXTALSTBIC   %1 17 lshift RCU_INT bis! ;  \ RCU_INT_LXTALSTBIC    LXTAL Stabilization Interrupt Clear
: RCU_INT_IRC8MSTBIC   %1 18 lshift RCU_INT bis! ;  \ RCU_INT_IRC8MSTBIC    IRC8M Stabilization Interrupt Clear
: RCU_INT_HXTALSTBIC   %1 19 lshift RCU_INT bis! ;  \ RCU_INT_HXTALSTBIC    HXTAL Stabilization Interrupt Clear
: RCU_INT_PLLSTBIC   %1 20 lshift RCU_INT bis! ;  \ RCU_INT_PLLSTBIC    PLL stabilization Interrupt Clear
: RCU_INT_PLL1STBIC   %1 21 lshift RCU_INT bis! ;  \ RCU_INT_PLL1STBIC    PLL1 stabilization Interrupt Clear
: RCU_INT_PLL2STBIC   %1 22 lshift RCU_INT bis! ;  \ RCU_INT_PLL2STBIC    PLL2 stabilization Interrupt Clear
: RCU_INT_CKMIC   %1 23 lshift RCU_INT bis! ;  \ RCU_INT_CKMIC    HXTAL Clock Stuck Interrupt Clear

\ RCU_APB2RST (read-write)
: RCU_APB2RST_AFRST   %1 0 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_AFRST    Alternate function I/O reset
: RCU_APB2RST_PARST   %1 2 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_PARST    GPIO port A reset
: RCU_APB2RST_PBRST   %1 3 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_PBRST    GPIO port B reset
: RCU_APB2RST_PCRST   %1 4 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_PCRST    GPIO port C reset
: RCU_APB2RST_PDRST   %1 5 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_PDRST    GPIO port D reset
: RCU_APB2RST_PERST   %1 6 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_PERST    GPIO port E reset
: RCU_APB2RST_ADC0RST   %1 9 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_ADC0RST    ADC0 reset
: RCU_APB2RST_ADC1RST   %1 10 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_ADC1RST    ADC1 reset
: RCU_APB2RST_TIMER0RST   %1 11 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_TIMER0RST    Timer 0 reset
: RCU_APB2RST_SPI0RST   %1 12 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_SPI0RST    SPI0 reset
: RCU_APB2RST_USART0RST   %1 14 lshift RCU_APB2RST bis! ;  \ RCU_APB2RST_USART0RST    USART0 Reset

\ RCU_APB1RST (read-write)
: RCU_APB1RST_TIMER1RST   %1 0 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_TIMER1RST    TIMER1 timer reset
: RCU_APB1RST_TIMER2RST   %1 1 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_TIMER2RST    TIMER2 timer reset
: RCU_APB1RST_TIMER3RST   %1 2 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_TIMER3RST    TIMER3 timer reset
: RCU_APB1RST_TIMER4RST   %1 3 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_TIMER4RST    TIMER4 timer reset
: RCU_APB1RST_TIMER5RST   %1 4 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_TIMER5RST    TIMER5 timer reset
: RCU_APB1RST_TIMER6RST   %1 5 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_TIMER6RST    TIMER6 timer reset
: RCU_APB1RST_WWDGTRST   %1 11 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_WWDGTRST    Window watchdog timer reset
: RCU_APB1RST_SPI1RST   %1 14 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_SPI1RST    SPI1 reset
: RCU_APB1RST_SPI2RST   %1 15 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_SPI2RST    SPI2 reset
: RCU_APB1RST_USART1RST   %1 17 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_USART1RST    USART1 reset
: RCU_APB1RST_USART2RST   %1 18 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_USART2RST    USART2 reset
: RCU_APB1RST_UART3RST   %1 19 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_UART3RST    UART3 reset
: RCU_APB1RST_UART4RST   %1 20 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_UART4RST    UART4 reset
: RCU_APB1RST_I2C0RST   %1 21 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_I2C0RST    I2C0 reset
: RCU_APB1RST_I2C1RST   %1 22 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_I2C1RST    I2C1 reset
: RCU_APB1RST_CAN0RST   %1 25 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_CAN0RST    CAN0 reset
: RCU_APB1RST_CAN1RST   %1 26 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_CAN1RST    CAN1 reset
: RCU_APB1RST_BKPIRST   %1 27 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_BKPIRST    Backup interface reset
: RCU_APB1RST_PMURST   %1 28 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_PMURST    Power control reset
: RCU_APB1RST_DACRST   %1 29 lshift RCU_APB1RST bis! ;  \ RCU_APB1RST_DACRST    DAC reset

\ RCU_AHBEN (read-write)
: RCU_AHBEN_DMA0EN   %1 0 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_DMA0EN    DMA0 clock enable
: RCU_AHBEN_DMA1EN   %1 1 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_DMA1EN    DMA1 clock enable
: RCU_AHBEN_SRAMSPEN   %1 2 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_SRAMSPEN    SRAM interface clock enable when sleep mode
: RCU_AHBEN_FMCSPEN   %1 4 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_FMCSPEN    FMC clock enable when sleep mode
: RCU_AHBEN_CRCEN   %1 6 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_CRCEN    CRC clock enable
: RCU_AHBEN_EXMCEN   %1 8 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_EXMCEN    EXMC clock enable
: RCU_AHBEN_USBFSEN   %1 12 lshift RCU_AHBEN bis! ;  \ RCU_AHBEN_USBFSEN    USBFS clock enable

\ RCU_APB2EN (read-write)
: RCU_APB2EN_AFEN   %1 0 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_AFEN    Alternate function IO clock enable 
: RCU_APB2EN_PAEN   %1 2 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_PAEN    GPIO port A clock enable
: RCU_APB2EN_PBEN   %1 3 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_PBEN    GPIO port B clock enable
: RCU_APB2EN_PCEN   %1 4 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_PCEN    GPIO port C clock enable
: RCU_APB2EN_PDEN   %1 5 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_PDEN    GPIO port D clock enable 
: RCU_APB2EN_PEEN   %1 6 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_PEEN    GPIO port E clock enable 
: RCU_APB2EN_ADC0EN   %1 9 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_ADC0EN    ADC0 clock enable
: RCU_APB2EN_ADC1EN   %1 10 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_ADC1EN    ADC1 clock enable
: RCU_APB2EN_TIMER0EN   %1 11 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_TIMER0EN    TIMER0 clock enable 
: RCU_APB2EN_SPI0EN   %1 12 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_SPI0EN    SPI0 clock enable
: RCU_APB2EN_USART0EN   %1 14 lshift RCU_APB2EN bis! ;  \ RCU_APB2EN_USART0EN    USART0 clock enable

\ RCU_APB1EN (read-write)
: RCU_APB1EN_TIMER1EN   %1 0 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_TIMER1EN    TIMER1 timer clock enable
: RCU_APB1EN_TIMER2EN   %1 1 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_TIMER2EN    TIMER2 timer clock enable
: RCU_APB1EN_TIMER3EN   %1 2 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_TIMER3EN    TIMER3 timer clock enable
: RCU_APB1EN_TIMER4EN   %1 3 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_TIMER4EN    TIMER4 timer clock enable
: RCU_APB1EN_TIMER5EN   %1 4 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_TIMER5EN    TIMER5 timer clock enable
: RCU_APB1EN_TIMER6EN   %1 5 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_TIMER6EN    TIMER6 timer clock enable
: RCU_APB1EN_WWDGTEN   %1 11 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_WWDGTEN    Window watchdog timer clock enable
: RCU_APB1EN_SPI1EN   %1 14 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_SPI1EN    SPI1 clock enable
: RCU_APB1EN_SPI2EN   %1 15 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_SPI2EN    SPI2 clock enable
: RCU_APB1EN_USART1EN   %1 17 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_USART1EN    USART1 clock enable
: RCU_APB1EN_USART2EN   %1 18 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_USART2EN    USART2 clock enable
: RCU_APB1EN_UART3EN   %1 19 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_UART3EN    UART3 clock enable
: RCU_APB1EN_UART4EN   %1 20 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_UART4EN    UART4 clock enable
: RCU_APB1EN_I2C0EN   %1 21 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_I2C0EN    I2C0 clock enable
: RCU_APB1EN_I2C1EN   %1 22 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_I2C1EN    I2C1 clock enable
: RCU_APB1EN_CAN0EN   %1 25 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_CAN0EN    CAN0 clock enable
: RCU_APB1EN_CAN1EN   %1 26 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_CAN1EN    CAN1 clock enable
: RCU_APB1EN_BKPIEN   %1 27 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_BKPIEN    Backup interface clock enable 
: RCU_APB1EN_PMUEN   %1 28 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_PMUEN    Power control clock enable 
: RCU_APB1EN_DACEN   %1 29 lshift RCU_APB1EN bis! ;  \ RCU_APB1EN_DACEN    DAC clock enable

\ RCU_BDCTL ()
: RCU_BDCTL_LXTALEN   %1 0 lshift RCU_BDCTL bis! ;  \ RCU_BDCTL_LXTALEN    LXTAL enable
: RCU_BDCTL_LXTALSTB   %1 1 lshift RCU_BDCTL bis! ;  \ RCU_BDCTL_LXTALSTB    External low-speed oscillator stabilization
: RCU_BDCTL_LXTALBPS   %1 2 lshift RCU_BDCTL bis! ;  \ RCU_BDCTL_LXTALBPS    LXTAL bypass mode enable
: RCU_BDCTL_RTCSRC   ( %XX -- ) 8 lshift RCU_BDCTL bis! ;  \ RCU_BDCTL_RTCSRC    RTC clock entry selection
: RCU_BDCTL_RTCEN   %1 15 lshift RCU_BDCTL bis! ;  \ RCU_BDCTL_RTCEN    RTC clock enable
: RCU_BDCTL_BKPRST   %1 16 lshift RCU_BDCTL bis! ;  \ RCU_BDCTL_BKPRST    Backup domain reset

\ RCU_RSTSCK ()
: RCU_RSTSCK_IRC40KEN   %1 0 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_IRC40KEN    IRC40K enable
: RCU_RSTSCK_IRC40KSTB   %1 1 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_IRC40KSTB    IRC40K stabilization
: RCU_RSTSCK_RSTFC   %1 24 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_RSTFC    Reset flag clear
: RCU_RSTSCK_EPRSTF   %1 26 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_EPRSTF    External PIN reset flag
: RCU_RSTSCK_PORRSTF   %1 27 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_PORRSTF    Power reset flag
: RCU_RSTSCK_SWRSTF   %1 28 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_SWRSTF    Software reset flag
: RCU_RSTSCK_FWDGTRSTF   %1 29 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_FWDGTRSTF    Free Watchdog timer reset flag
: RCU_RSTSCK_WWDGTRSTF   %1 30 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_WWDGTRSTF    Window watchdog timer reset flag
: RCU_RSTSCK_LPRSTF   %1 31 lshift RCU_RSTSCK bis! ;  \ RCU_RSTSCK_LPRSTF    Low-power reset flag

\ RCU_AHBRST (read-write)
: RCU_AHBRST_USBFSRST   %1 12 lshift RCU_AHBRST bis! ;  \ RCU_AHBRST_USBFSRST    USBFS reset

\ RCU_CFG1 (read-write)
: RCU_CFG1_PREDV0   ( %XXXX -- ) 0 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_PREDV0    PREDV0 division factor
: RCU_CFG1_PREDV1   ( %XXXX -- ) 4 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_PREDV1    PREDV1 division factor
: RCU_CFG1_PLL1MF   ( %XXXX -- ) 8 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_PLL1MF    The PLL1 clock multiplication factor
: RCU_CFG1_PLL2MF   ( %XXXX -- ) 12 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_PLL2MF    The PLL2 clock multiplication factor
: RCU_CFG1_PREDV0SEL   %1 16 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_PREDV0SEL    PREDV0 input Clock Source Selection
: RCU_CFG1_I2S1SEL   %1 17 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_I2S1SEL    I2S1 Clock Source Selection
: RCU_CFG1_I2S2SEL   %1 18 lshift RCU_CFG1 bis! ;  \ RCU_CFG1_I2S2SEL    I2S2 Clock Source Selection

\ RCU_DSV ()
: RCU_DSV_DSLPVS   ( %XX -- ) 0 lshift RCU_DSV bis! ;  \ RCU_DSV_DSLPVS    Deep-sleep mode voltage select

\ RTC_INTEN (read-write)
: RTC_INTEN_OVIE   %1 2 lshift RTC_INTEN bis! ;  \ RTC_INTEN_OVIE    Overflow interrupt enable
: RTC_INTEN_ALRMIE   %1 1 lshift RTC_INTEN bis! ;  \ RTC_INTEN_ALRMIE    Alarm interrupt enable
: RTC_INTEN_SCIE   %1 0 lshift RTC_INTEN bis! ;  \ RTC_INTEN_SCIE    Second interrupt

\ RTC_CTL (read-write)
: RTC_CTL_LWOFF   %1 5 lshift RTC_CTL bis! ;  \ RTC_CTL_LWOFF    Last write operation finished flag
: RTC_CTL_CMF   %1 4 lshift RTC_CTL bis! ;  \ RTC_CTL_CMF    Configuration mode flag
: RTC_CTL_RSYNF   %1 3 lshift RTC_CTL bis! ;  \ RTC_CTL_RSYNF    Registers synchronized flag
: RTC_CTL_OVIF   %1 2 lshift RTC_CTL bis! ;  \ RTC_CTL_OVIF    Overflow interrupt flag
: RTC_CTL_ALRMIF   %1 1 lshift RTC_CTL bis! ;  \ RTC_CTL_ALRMIF    Alarm interrupt flag
: RTC_CTL_SCIF   %1 0 lshift RTC_CTL bis! ;  \ RTC_CTL_SCIF    Sencond interrupt flag

\ RTC_PSCH ()
: RTC_PSCH_PSC   ( %XXXX -- ) 0 lshift RTC_PSCH bis! ;  \ RTC_PSCH_PSC    RTC prescaler value high

\ RTC_PSCL ()
: RTC_PSCL_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift RTC_PSCL bis! ;  \ RTC_PSCL_PSC    RTC prescaler value low

\ RTC_DIVH (read-only)
: RTC_DIVH_DIV   ( %XXXX -- ) 0 lshift RTC_DIVH bis! ;  \ RTC_DIVH_DIV    RTC divider value high

\ RTC_DIVL (read-only)
: RTC_DIVL_DIV   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift RTC_DIVL bis! ;  \ RTC_DIVL_DIV    RTC divider value low

\ RTC_CNTH (read-write)
: RTC_CNTH_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift RTC_CNTH bis! ;  \ RTC_CNTH_CNT    RTC counter value high

\ RTC_CNTL (read-write)
: RTC_CNTL_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift RTC_CNTL bis! ;  \ RTC_CNTL_CNT    RTC counter value low

\ RTC_ALRMH (write)
: RTC_ALRMH_ALRM   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift RTC_ALRMH bis! ;  \ RTC_ALRMH_ALRM    Alarm value high

\ RTC_ALRML (write)
: RTC_ALRML_ALRM   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift RTC_ALRML bis! ;  \ RTC_ALRML_ALRM    alarm value low

\ SPI0_CTL0 (read-write)
: SPI0_CTL0_BDEN   %1 15 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_BDEN    Bidirectional   enable
: SPI0_CTL0_BDOEN   %1 14 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_BDOEN    Bidirectional Transmit output enable  
: SPI0_CTL0_CRCEN   %1 13 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_CRCEN    CRC Calculation Enable
: SPI0_CTL0_CRCNT   %1 12 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_CRCNT    CRC Next Transfer
: SPI0_CTL0_FF16   %1 11 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_FF16    Data frame format
: SPI0_CTL0_RO   %1 10 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_RO    Receive only
: SPI0_CTL0_SWNSSEN   %1 9 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_SWNSSEN    NSS Software Mode Selection
: SPI0_CTL0_SWNSS   %1 8 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_SWNSS    NSS Pin Selection In NSS Software Mode
: SPI0_CTL0_LF   %1 7 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_LF    LSB First Mode
: SPI0_CTL0_SPIEN   %1 6 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_SPIEN    SPI enable
: SPI0_CTL0_PSC   ( %XXX -- ) 3 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_PSC    Master Clock Prescaler Selection
: SPI0_CTL0_MSTMOD   %1 2 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_MSTMOD    Master Mode Enable
: SPI0_CTL0_CKPL   %1 1 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_CKPL    Clock polarity Selection
: SPI0_CTL0_CKPH   %1 0 lshift SPI0_CTL0 bis! ;  \ SPI0_CTL0_CKPH    Clock Phase Selection

\ SPI0_CTL1 (read-write)
: SPI0_CTL1_TBEIE   %1 7 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_TBEIE    Tx buffer empty interrupt  enable
: SPI0_CTL1_RBNEIE   %1 6 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_RBNEIE    RX buffer not empty interrupt  enable
: SPI0_CTL1_ERRIE   %1 5 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_ERRIE    Error interrupt enable
: SPI0_CTL1_TMOD   %1 4 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_TMOD    SPI TI mode enable
: SPI0_CTL1_NSSP   %1 3 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_NSSP    SPI NSS pulse mode enable
: SPI0_CTL1_NSSDRV   %1 2 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_NSSDRV    Drive NSS Output
: SPI0_CTL1_DMATEN   %1 1 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_DMATEN    Transmit Buffer DMA Enable
: SPI0_CTL1_DMAREN   %1 0 lshift SPI0_CTL1 bis! ;  \ SPI0_CTL1_DMAREN    Rx buffer DMA enable

\ SPI0_STAT ()
: SPI0_STAT_FERR   %1 8 lshift SPI0_STAT bis! ;  \ SPI0_STAT_FERR    Format error
: SPI0_STAT_TRANS   %1 7 lshift SPI0_STAT bis! ;  \ SPI0_STAT_TRANS    Transmitting On-going Bit
: SPI0_STAT_RXORERR   %1 6 lshift SPI0_STAT bis! ;  \ SPI0_STAT_RXORERR    Reception Overrun Error Bit
: SPI0_STAT_CONFERR   %1 5 lshift SPI0_STAT bis! ;  \ SPI0_STAT_CONFERR    SPI Configuration error
: SPI0_STAT_CRCERR   %1 4 lshift SPI0_STAT bis! ;  \ SPI0_STAT_CRCERR    SPI CRC Error Bit
: SPI0_STAT_TXURERR   %1 3 lshift SPI0_STAT bis! ;  \ SPI0_STAT_TXURERR    Transmission underrun error bit
: SPI0_STAT_I2SCH   %1 2 lshift SPI0_STAT bis! ;  \ SPI0_STAT_I2SCH    I2S channel side
: SPI0_STAT_TBE   %1 1 lshift SPI0_STAT bis! ;  \ SPI0_STAT_TBE    Transmit Buffer Empty
: SPI0_STAT_RBNE   %1 0 lshift SPI0_STAT bis! ;  \ SPI0_STAT_RBNE    Receive Buffer Not Empty

\ SPI0_DATA (read-write)
: SPI0_DATA_SPI_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI0_DATA bis! ;  \ SPI0_DATA_SPI_DATA    Data transfer register

\ SPI0_CRCPOLY (read-write)
: SPI0_CRCPOLY_CRCPOLY   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI0_CRCPOLY bis! ;  \ SPI0_CRCPOLY_CRCPOLY    CRC polynomial value

\ SPI0_RCRC (read-only)
: SPI0_RCRC_RCRC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI0_RCRC bis! ;  \ SPI0_RCRC_RCRC    RX CRC value

\ SPI0_TCRC (read-only)
: SPI0_TCRC_TCRC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI0_TCRC bis! ;  \ SPI0_TCRC_TCRC    Tx CRC value

\ SPI0_I2SCTL (read-write)
: SPI0_I2SCTL_I2SSEL   %1 11 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_I2SSEL    I2S mode selection
: SPI0_I2SCTL_I2SEN   %1 10 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_I2SEN    I2S Enable
: SPI0_I2SCTL_I2SOPMOD   ( %XX -- ) 8 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_I2SOPMOD    I2S operation mode
: SPI0_I2SCTL_PCMSMOD   %1 7 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_PCMSMOD    PCM frame synchronization mode
: SPI0_I2SCTL_I2SSTD   ( %XX -- ) 4 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_I2SSTD    I2S standard selection
: SPI0_I2SCTL_CKPL   %1 3 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_CKPL    Idle state clock polarity
: SPI0_I2SCTL_DTLEN   ( %XX -- ) 1 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_DTLEN    Data length
: SPI0_I2SCTL_CHLEN   %1 0 lshift SPI0_I2SCTL bis! ;  \ SPI0_I2SCTL_CHLEN    Channel length number of bits per audio  channel

\ SPI0_I2SPSC (read-write)
: SPI0_I2SPSC_MCKOEN   %1 9 lshift SPI0_I2SPSC bis! ;  \ SPI0_I2SPSC_MCKOEN    I2S_MCK output enable
: SPI0_I2SPSC_OF   %1 8 lshift SPI0_I2SPSC bis! ;  \ SPI0_I2SPSC_OF    Odd factor for the  prescaler
: SPI0_I2SPSC_DIV   ( %XXXXXXXX -- ) 0 lshift SPI0_I2SPSC bis! ;  \ SPI0_I2SPSC_DIV    Dividing factor for the prescaler

\ SPI1_CTL0 (read-write)
: SPI1_CTL0_BDEN   %1 15 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_BDEN    Bidirectional   enable
: SPI1_CTL0_BDOEN   %1 14 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_BDOEN    Bidirectional Transmit output enable  
: SPI1_CTL0_CRCEN   %1 13 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_CRCEN    CRC Calculation Enable
: SPI1_CTL0_CRCNT   %1 12 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_CRCNT    CRC Next Transfer
: SPI1_CTL0_FF16   %1 11 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_FF16    Data frame format
: SPI1_CTL0_RO   %1 10 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_RO    Receive only
: SPI1_CTL0_SWNSSEN   %1 9 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_SWNSSEN    NSS Software Mode Selection
: SPI1_CTL0_SWNSS   %1 8 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_SWNSS    NSS Pin Selection In NSS Software Mode
: SPI1_CTL0_LF   %1 7 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_LF    LSB First Mode
: SPI1_CTL0_SPIEN   %1 6 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_SPIEN    SPI enable
: SPI1_CTL0_PSC   ( %XXX -- ) 3 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_PSC    Master Clock Prescaler Selection
: SPI1_CTL0_MSTMOD   %1 2 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_MSTMOD    Master Mode Enable
: SPI1_CTL0_CKPL   %1 1 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_CKPL    Clock polarity Selection
: SPI1_CTL0_CKPH   %1 0 lshift SPI1_CTL0 bis! ;  \ SPI1_CTL0_CKPH    Clock Phase Selection

\ SPI1_CTL1 (read-write)
: SPI1_CTL1_TBEIE   %1 7 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_TBEIE    Tx buffer empty interrupt  enable
: SPI1_CTL1_RBNEIE   %1 6 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_RBNEIE    RX buffer not empty interrupt  enable
: SPI1_CTL1_ERRIE   %1 5 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_ERRIE    Error interrupt enable
: SPI1_CTL1_TMOD   %1 4 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_TMOD    SPI TI mode enable
: SPI1_CTL1_NSSP   %1 3 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_NSSP    SPI NSS pulse mode enable
: SPI1_CTL1_NSSDRV   %1 2 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_NSSDRV    Drive NSS Output
: SPI1_CTL1_DMATEN   %1 1 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_DMATEN    Transmit Buffer DMA Enable
: SPI1_CTL1_DMAREN   %1 0 lshift SPI1_CTL1 bis! ;  \ SPI1_CTL1_DMAREN    Rx buffer DMA enable

\ SPI1_STAT ()
: SPI1_STAT_FERR   %1 8 lshift SPI1_STAT bis! ;  \ SPI1_STAT_FERR    Format error
: SPI1_STAT_TRANS   %1 7 lshift SPI1_STAT bis! ;  \ SPI1_STAT_TRANS    Transmitting On-going Bit
: SPI1_STAT_RXORERR   %1 6 lshift SPI1_STAT bis! ;  \ SPI1_STAT_RXORERR    Reception Overrun Error Bit
: SPI1_STAT_CONFERR   %1 5 lshift SPI1_STAT bis! ;  \ SPI1_STAT_CONFERR    SPI Configuration error
: SPI1_STAT_CRCERR   %1 4 lshift SPI1_STAT bis! ;  \ SPI1_STAT_CRCERR    SPI CRC Error Bit
: SPI1_STAT_TXURERR   %1 3 lshift SPI1_STAT bis! ;  \ SPI1_STAT_TXURERR    Transmission underrun error bit
: SPI1_STAT_I2SCH   %1 2 lshift SPI1_STAT bis! ;  \ SPI1_STAT_I2SCH    I2S channel side
: SPI1_STAT_TBE   %1 1 lshift SPI1_STAT bis! ;  \ SPI1_STAT_TBE    Transmit Buffer Empty
: SPI1_STAT_RBNE   %1 0 lshift SPI1_STAT bis! ;  \ SPI1_STAT_RBNE    Receive Buffer Not Empty

\ SPI1_DATA (read-write)
: SPI1_DATA_SPI_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI1_DATA bis! ;  \ SPI1_DATA_SPI_DATA    Data transfer register

\ SPI1_CRCPOLY (read-write)
: SPI1_CRCPOLY_CRCPOLY   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI1_CRCPOLY bis! ;  \ SPI1_CRCPOLY_CRCPOLY    CRC polynomial value

\ SPI1_RCRC (read-only)
: SPI1_RCRC_RCRC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI1_RCRC bis! ;  \ SPI1_RCRC_RCRC    RX CRC value

\ SPI1_TCRC (read-only)
: SPI1_TCRC_TCRC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI1_TCRC bis! ;  \ SPI1_TCRC_TCRC    Tx CRC value

\ SPI1_I2SCTL (read-write)
: SPI1_I2SCTL_I2SSEL   %1 11 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_I2SSEL    I2S mode selection
: SPI1_I2SCTL_I2SEN   %1 10 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_I2SEN    I2S Enable
: SPI1_I2SCTL_I2SOPMOD   ( %XX -- ) 8 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_I2SOPMOD    I2S operation mode
: SPI1_I2SCTL_PCMSMOD   %1 7 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_PCMSMOD    PCM frame synchronization mode
: SPI1_I2SCTL_I2SSTD   ( %XX -- ) 4 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_I2SSTD    I2S standard selection
: SPI1_I2SCTL_CKPL   %1 3 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_CKPL    Idle state clock polarity
: SPI1_I2SCTL_DTLEN   ( %XX -- ) 1 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_DTLEN    Data length
: SPI1_I2SCTL_CHLEN   %1 0 lshift SPI1_I2SCTL bis! ;  \ SPI1_I2SCTL_CHLEN    Channel length number of bits per audio  channel

\ SPI1_I2SPSC (read-write)
: SPI1_I2SPSC_MCKOEN   %1 9 lshift SPI1_I2SPSC bis! ;  \ SPI1_I2SPSC_MCKOEN    I2S_MCK output enable
: SPI1_I2SPSC_OF   %1 8 lshift SPI1_I2SPSC bis! ;  \ SPI1_I2SPSC_OF    Odd factor for the  prescaler
: SPI1_I2SPSC_DIV   ( %XXXXXXXX -- ) 0 lshift SPI1_I2SPSC bis! ;  \ SPI1_I2SPSC_DIV    Dividing factor for the prescaler

\ SPI2_CTL0 (read-write)
: SPI2_CTL0_BDEN   %1 15 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_BDEN    Bidirectional   enable
: SPI2_CTL0_BDOEN   %1 14 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_BDOEN    Bidirectional Transmit output enable  
: SPI2_CTL0_CRCEN   %1 13 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_CRCEN    CRC Calculation Enable
: SPI2_CTL0_CRCNT   %1 12 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_CRCNT    CRC Next Transfer
: SPI2_CTL0_FF16   %1 11 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_FF16    Data frame format
: SPI2_CTL0_RO   %1 10 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_RO    Receive only
: SPI2_CTL0_SWNSSEN   %1 9 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_SWNSSEN    NSS Software Mode Selection
: SPI2_CTL0_SWNSS   %1 8 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_SWNSS    NSS Pin Selection In NSS Software Mode
: SPI2_CTL0_LF   %1 7 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_LF    LSB First Mode
: SPI2_CTL0_SPIEN   %1 6 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_SPIEN    SPI enable
: SPI2_CTL0_PSC   ( %XXX -- ) 3 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_PSC    Master Clock Prescaler Selection
: SPI2_CTL0_MSTMOD   %1 2 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_MSTMOD    Master Mode Enable
: SPI2_CTL0_CKPL   %1 1 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_CKPL    Clock polarity Selection
: SPI2_CTL0_CKPH   %1 0 lshift SPI2_CTL0 bis! ;  \ SPI2_CTL0_CKPH    Clock Phase Selection

\ SPI2_CTL1 (read-write)
: SPI2_CTL1_TBEIE   %1 7 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_TBEIE    Tx buffer empty interrupt  enable
: SPI2_CTL1_RBNEIE   %1 6 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_RBNEIE    RX buffer not empty interrupt  enable
: SPI2_CTL1_ERRIE   %1 5 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_ERRIE    Error interrupt enable
: SPI2_CTL1_TMOD   %1 4 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_TMOD    SPI TI mode enable
: SPI2_CTL1_NSSP   %1 3 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_NSSP    SPI NSS pulse mode enable
: SPI2_CTL1_NSSDRV   %1 2 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_NSSDRV    Drive NSS Output
: SPI2_CTL1_DMATEN   %1 1 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_DMATEN    Transmit Buffer DMA Enable
: SPI2_CTL1_DMAREN   %1 0 lshift SPI2_CTL1 bis! ;  \ SPI2_CTL1_DMAREN    Rx buffer DMA enable

\ SPI2_STAT ()
: SPI2_STAT_FERR   %1 8 lshift SPI2_STAT bis! ;  \ SPI2_STAT_FERR    Format error
: SPI2_STAT_TRANS   %1 7 lshift SPI2_STAT bis! ;  \ SPI2_STAT_TRANS    Transmitting On-going Bit
: SPI2_STAT_RXORERR   %1 6 lshift SPI2_STAT bis! ;  \ SPI2_STAT_RXORERR    Reception Overrun Error Bit
: SPI2_STAT_CONFERR   %1 5 lshift SPI2_STAT bis! ;  \ SPI2_STAT_CONFERR    SPI Configuration error
: SPI2_STAT_CRCERR   %1 4 lshift SPI2_STAT bis! ;  \ SPI2_STAT_CRCERR    SPI CRC Error Bit
: SPI2_STAT_TXURERR   %1 3 lshift SPI2_STAT bis! ;  \ SPI2_STAT_TXURERR    Transmission underrun error bit
: SPI2_STAT_I2SCH   %1 2 lshift SPI2_STAT bis! ;  \ SPI2_STAT_I2SCH    I2S channel side
: SPI2_STAT_TBE   %1 1 lshift SPI2_STAT bis! ;  \ SPI2_STAT_TBE    Transmit Buffer Empty
: SPI2_STAT_RBNE   %1 0 lshift SPI2_STAT bis! ;  \ SPI2_STAT_RBNE    Receive Buffer Not Empty

\ SPI2_DATA (read-write)
: SPI2_DATA_SPI_DATA   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI2_DATA bis! ;  \ SPI2_DATA_SPI_DATA    Data transfer register

\ SPI2_CRCPOLY (read-write)
: SPI2_CRCPOLY_CRCPOLY   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI2_CRCPOLY bis! ;  \ SPI2_CRCPOLY_CRCPOLY    CRC polynomial value

\ SPI2_RCRC (read-only)
: SPI2_RCRC_RCRC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI2_RCRC bis! ;  \ SPI2_RCRC_RCRC    RX CRC value

\ SPI2_TCRC (read-only)
: SPI2_TCRC_TCRC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift SPI2_TCRC bis! ;  \ SPI2_TCRC_TCRC    Tx CRC value

\ SPI2_I2SCTL (read-write)
: SPI2_I2SCTL_I2SSEL   %1 11 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_I2SSEL    I2S mode selection
: SPI2_I2SCTL_I2SEN   %1 10 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_I2SEN    I2S Enable
: SPI2_I2SCTL_I2SOPMOD   ( %XX -- ) 8 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_I2SOPMOD    I2S operation mode
: SPI2_I2SCTL_PCMSMOD   %1 7 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_PCMSMOD    PCM frame synchronization mode
: SPI2_I2SCTL_I2SSTD   ( %XX -- ) 4 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_I2SSTD    I2S standard selection
: SPI2_I2SCTL_CKPL   %1 3 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_CKPL    Idle state clock polarity
: SPI2_I2SCTL_DTLEN   ( %XX -- ) 1 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_DTLEN    Data length
: SPI2_I2SCTL_CHLEN   %1 0 lshift SPI2_I2SCTL bis! ;  \ SPI2_I2SCTL_CHLEN    Channel length number of bits per audio  channel

\ SPI2_I2SPSC (read-write)
: SPI2_I2SPSC_MCKOEN   %1 9 lshift SPI2_I2SPSC bis! ;  \ SPI2_I2SPSC_MCKOEN    I2S_MCK output enable
: SPI2_I2SPSC_OF   %1 8 lshift SPI2_I2SPSC bis! ;  \ SPI2_I2SPSC_OF    Odd factor for the  prescaler
: SPI2_I2SPSC_DIV   ( %XXXXXXXX -- ) 0 lshift SPI2_I2SPSC bis! ;  \ SPI2_I2SPSC_DIV    Dividing factor for the prescaler

\ TIMER0_CTL0 (read-write)
: TIMER0_CTL0_CKDIV   ( %XX -- ) 8 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_CKDIV    Clock division
: TIMER0_CTL0_ARSE   %1 7 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_ARSE    Auto-reload shadow enable
: TIMER0_CTL0_CAM   ( %XX -- ) 5 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_CAM    Counter aligns mode  selection
: TIMER0_CTL0_DIR   %1 4 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_DIR    Direction
: TIMER0_CTL0_SPM   %1 3 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_SPM    Single pulse mode
: TIMER0_CTL0_UPS   %1 2 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_UPS    Update source
: TIMER0_CTL0_UPDIS   %1 1 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_UPDIS    Update disable
: TIMER0_CTL0_CEN   %1 0 lshift TIMER0_CTL0 bis! ;  \ TIMER0_CTL0_CEN    Counter enable

\ TIMER0_CTL1 (read-write)
: TIMER0_CTL1_ISO3   %1 14 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO3    Idle state of channel 3 output
: TIMER0_CTL1_ISO2N   %1 13 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO2N    Idle state of channel 2 complementary output
: TIMER0_CTL1_ISO2   %1 12 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO2    Idle state of channel 2 output
: TIMER0_CTL1_ISO1N   %1 11 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO1N    Idle state of channel 1 complementary output
: TIMER0_CTL1_ISO1   %1 10 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO1    Idle state of channel 1 output
: TIMER0_CTL1_ISO0N   %1 9 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO0N    Idle state of channel 0 complementary output
: TIMER0_CTL1_ISO0   %1 8 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_ISO0    Idle state of channel 0 output
: TIMER0_CTL1_TI0S   %1 7 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_TI0S    Channel 0 trigger input selection
: TIMER0_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_MMC    Master mode control
: TIMER0_CTL1_DMAS   %1 3 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_DMAS    DMA request source selection
: TIMER0_CTL1_CCUC   %1 2 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_CCUC    Commutation control shadow register update control
: TIMER0_CTL1_CCSE   %1 0 lshift TIMER0_CTL1 bis! ;  \ TIMER0_CTL1_CCSE    Commutation control shadow enable

\ TIMER0_SMCFG (read-write)
: TIMER0_SMCFG_ETP   %1 15 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_ETP    External trigger polarity
: TIMER0_SMCFG_SMC1   %1 14 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_SMC1    Part of SMC for enable External clock mode1
: TIMER0_SMCFG_ETPSC   ( %XX -- ) 12 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_ETPSC    External trigger prescaler
: TIMER0_SMCFG_ETFC   ( %XXXX -- ) 8 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_ETFC    External trigger filter control
: TIMER0_SMCFG_MSM   %1 7 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_MSM    Master/Slave mode
: TIMER0_SMCFG_TRGS   ( %XXX -- ) 4 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_TRGS    Trigger selection
: TIMER0_SMCFG_SMC   ( %XXX -- ) 0 lshift TIMER0_SMCFG bis! ;  \ TIMER0_SMCFG_SMC    Slave mode selection

\ TIMER0_DMAINTEN (read-write)
: TIMER0_DMAINTEN_TRGDEN   %1 14 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_TRGDEN    Trigger DMA request enable
: TIMER0_DMAINTEN_CMTDEN   %1 13 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CMTDEN    Commutation DMA request enable
: TIMER0_DMAINTEN_CH3DEN   %1 12 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH3DEN    Channel 3 capture/compare DMA request enable
: TIMER0_DMAINTEN_CH2DEN   %1 11 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH2DEN    Channel 2 capture/compare DMA request enable
: TIMER0_DMAINTEN_CH1DEN   %1 10 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH1DEN    Channel 1 capture/compare DMA request enable
: TIMER0_DMAINTEN_CH0DEN   %1 9 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH0DEN    Channel 0 capture/compare DMA request enable
: TIMER0_DMAINTEN_UPDEN   %1 8 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_UPDEN    Update DMA request enable
: TIMER0_DMAINTEN_BRKIE   %1 7 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_BRKIE    Break interrupt enable
: TIMER0_DMAINTEN_TRGIE   %1 6 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_TRGIE    Trigger interrupt enable
: TIMER0_DMAINTEN_CMTIE   %1 5 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CMTIE    commutation interrupt enable
: TIMER0_DMAINTEN_CH3IE   %1 4 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH3IE    Channel 3 capture/compare interrupt enable
: TIMER0_DMAINTEN_CH2IE   %1 3 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH2IE    Channel 2 capture/compare interrupt enable
: TIMER0_DMAINTEN_CH1IE   %1 2 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH1IE    Channel 1 capture/compare interrupt enable
: TIMER0_DMAINTEN_CH0IE   %1 1 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_CH0IE    Channel 0 capture/compare interrupt enable
: TIMER0_DMAINTEN_UPIE   %1 0 lshift TIMER0_DMAINTEN bis! ;  \ TIMER0_DMAINTEN_UPIE    Update interrupt enable

\ TIMER0_INTF (read-write)
: TIMER0_INTF_CH3OF   %1 12 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH3OF    Channel 3 over capture flag
: TIMER0_INTF_CH2OF   %1 11 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH2OF    Channel 2 over capture flag
: TIMER0_INTF_CH1OF   %1 10 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH1OF    Channel 1 over capture flag
: TIMER0_INTF_CH0OF   %1 9 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH0OF    Channel 0 over capture flag
: TIMER0_INTF_BRKIF   %1 7 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_BRKIF    Break interrupt flag
: TIMER0_INTF_TRGIF   %1 6 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_TRGIF    Trigger interrupt flag
: TIMER0_INTF_CMTIF   %1 5 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CMTIF    Channel commutation interrupt flag
: TIMER0_INTF_CH3IF   %1 4 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH3IF    Channel 3 capture/compare interrupt flag
: TIMER0_INTF_CH2IF   %1 3 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH2IF     Channel 2 capture/compare interrupt flag
: TIMER0_INTF_CH1IF   %1 2 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH1IF    Channel 1 capture/compare interrupt flag
: TIMER0_INTF_CH0IF   %1 1 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_CH0IF    Channel 0 capture/compare interrupt flag
: TIMER0_INTF_UPIF   %1 0 lshift TIMER0_INTF bis! ;  \ TIMER0_INTF_UPIF    Update interrupt flag

\ TIMER0_SWEVG (write-only)
: TIMER0_SWEVG_BRKG   %1 7 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_BRKG    Break event generation
: TIMER0_SWEVG_TRGG   %1 6 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_TRGG    Trigger event generation
: TIMER0_SWEVG_CMTG   %1 5 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_CMTG    Channel commutation event generation
: TIMER0_SWEVG_CH3G   %1 4 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_CH3G    Channel 3 capture or compare event generation
: TIMER0_SWEVG_CH2G   %1 3 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_CH2G    Channel 2 capture or compare event generation
: TIMER0_SWEVG_CH1G   %1 2 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_CH1G    Channel 1 capture or compare event generation
: TIMER0_SWEVG_CH0G   %1 1 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_CH0G    Channel 0 capture or compare event generation
: TIMER0_SWEVG_UPG   %1 0 lshift TIMER0_SWEVG bis! ;  \ TIMER0_SWEVG_UPG    Update event generation

\ TIMER0_CHCTL0_Output (read-write)
: TIMER0_CHCTL0_Output_CH1COMCEN   %1 15 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH1COMCEN    Channel 1 output compare clear enable
: TIMER0_CHCTL0_Output_CH1COMCTL   ( %XXX -- ) 12 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH1COMCTL    Channel 1 compare output control
: TIMER0_CHCTL0_Output_CH1COMSEN   %1 11 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH1COMSEN    Channel 1 output compare shadow enable
: TIMER0_CHCTL0_Output_CH1COMFEN   %1 10 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH1COMFEN    Channel 1 output compare fast enable
: TIMER0_CHCTL0_Output_CH1MS   ( %XX -- ) 8 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH1MS    Channel 1 mode selection
: TIMER0_CHCTL0_Output_CH0COMCEN   %1 7 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH0COMCEN    Channel 0 output compare clear enable
: TIMER0_CHCTL0_Output_CH0COMCTL   ( %XXX -- ) 4 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH0COMCTL    Channel 0 compare output control
: TIMER0_CHCTL0_Output_CH0COMSEN   %1 3 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH0COMSEN    Channel 0 compare output shadow enable
: TIMER0_CHCTL0_Output_CH0COMFEN   %1 2 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH0COMFEN    Channel 0 output compare fast enable
: TIMER0_CHCTL0_Output_CH0MS   ( %XX -- ) 0 lshift TIMER0_CHCTL0_Output bis! ;  \ TIMER0_CHCTL0_Output_CH0MS    Channel 0 I/O mode selection

\ TIMER0_CHCTL0_Input (read-write)
: TIMER0_CHCTL0_Input_CH1CAPFLT   ( %XXXX -- ) 12 lshift TIMER0_CHCTL0_Input bis! ;  \ TIMER0_CHCTL0_Input_CH1CAPFLT    Channel 1 input capture filter control
: TIMER0_CHCTL0_Input_CH1CAPPSC   ( %XX -- ) 10 lshift TIMER0_CHCTL0_Input bis! ;  \ TIMER0_CHCTL0_Input_CH1CAPPSC    Channel 1 input capture prescaler
: TIMER0_CHCTL0_Input_CH1MS   ( %XX -- ) 8 lshift TIMER0_CHCTL0_Input bis! ;  \ TIMER0_CHCTL0_Input_CH1MS    Channel 1 mode selection
: TIMER0_CHCTL0_Input_CH0CAPFLT   ( %XXXX -- ) 4 lshift TIMER0_CHCTL0_Input bis! ;  \ TIMER0_CHCTL0_Input_CH0CAPFLT    Channel 0 input capture filter control
: TIMER0_CHCTL0_Input_CH0CAPPSC   ( %XX -- ) 2 lshift TIMER0_CHCTL0_Input bis! ;  \ TIMER0_CHCTL0_Input_CH0CAPPSC    Channel 0 input capture prescaler
: TIMER0_CHCTL0_Input_CH0MS   ( %XX -- ) 0 lshift TIMER0_CHCTL0_Input bis! ;  \ TIMER0_CHCTL0_Input_CH0MS    Channel 0 mode selection

\ TIMER0_CHCTL1_Output (read-write)
: TIMER0_CHCTL1_Output_CH3COMCEN   %1 15 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH3COMCEN    Channel 3 output compare clear enable
: TIMER0_CHCTL1_Output_CH3COMCTL   ( %XXX -- ) 12 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH3COMCTL    Channel 3 compare output control
: TIMER0_CHCTL1_Output_CH3COMSEN   %1 11 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH3COMSEN    Channel 3 output compare shadow enable
: TIMER0_CHCTL1_Output_CH3COMFEN   %1 10 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH3COMFEN    Channel 3 output compare fast enable
: TIMER0_CHCTL1_Output_CH3MS   ( %XX -- ) 8 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH3MS    Channel 3 mode selection
: TIMER0_CHCTL1_Output_CH2COMCEN   %1 7 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH2COMCEN    Channel 2 output compare clear enable
: TIMER0_CHCTL1_Output_CH2COMCTL   ( %XXX -- ) 4 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH2COMCTL    Channel 2 compare output control
: TIMER0_CHCTL1_Output_CH2COMSEN   %1 3 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH2COMSEN    Channel 2 compare output shadow enable
: TIMER0_CHCTL1_Output_CH2COMFEN   %1 2 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH2COMFEN    Channel 2 output compare fast enable
: TIMER0_CHCTL1_Output_CH2MS   ( %XX -- ) 0 lshift TIMER0_CHCTL1_Output bis! ;  \ TIMER0_CHCTL1_Output_CH2MS    Channel 2 I/O mode selection

\ TIMER0_CHCTL1_Input (read-write)
: TIMER0_CHCTL1_Input_CH3CAPFLT   ( %XXXX -- ) 12 lshift TIMER0_CHCTL1_Input bis! ;  \ TIMER0_CHCTL1_Input_CH3CAPFLT    Channel 3 input capture filter control
: TIMER0_CHCTL1_Input_CH3CAPPSC   ( %XX -- ) 10 lshift TIMER0_CHCTL1_Input bis! ;  \ TIMER0_CHCTL1_Input_CH3CAPPSC    Channel 3 input capture prescaler
: TIMER0_CHCTL1_Input_CH3MS   ( %XX -- ) 8 lshift TIMER0_CHCTL1_Input bis! ;  \ TIMER0_CHCTL1_Input_CH3MS    Channel 3 mode selection
: TIMER0_CHCTL1_Input_CH2CAPFLT   ( %XXXX -- ) 4 lshift TIMER0_CHCTL1_Input bis! ;  \ TIMER0_CHCTL1_Input_CH2CAPFLT    Channel 2 input capture filter control
: TIMER0_CHCTL1_Input_CH2CAPPSC   ( %XX -- ) 2 lshift TIMER0_CHCTL1_Input bis! ;  \ TIMER0_CHCTL1_Input_CH2CAPPSC    Channel 2 input capture prescaler
: TIMER0_CHCTL1_Input_CH2MS   ( %XX -- ) 0 lshift TIMER0_CHCTL1_Input bis! ;  \ TIMER0_CHCTL1_Input_CH2MS    Channel 2 mode selection

\ TIMER0_CHCTL2 (read-write)
: TIMER0_CHCTL2_CH3P   %1 13 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH3P    Channel 3 capture/compare function polarity
: TIMER0_CHCTL2_CH3EN   %1 12 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH3EN    Channel 3 capture/compare function enable
: TIMER0_CHCTL2_CH2NP   %1 11 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH2NP    Channel 2 complementary output polarity
: TIMER0_CHCTL2_CH2NEN   %1 10 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH2NEN    Channel 2 complementary output enable
: TIMER0_CHCTL2_CH2P   %1 9 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH2P    Channel 2 capture/compare function polarity
: TIMER0_CHCTL2_CH2EN   %1 8 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH2EN    Channel 2 capture/compare function enable
: TIMER0_CHCTL2_CH1NP   %1 7 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH1NP    Channel 1 complementary output polarity
: TIMER0_CHCTL2_CH1NEN   %1 6 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH1NEN    Channel 1 complementary output enable
: TIMER0_CHCTL2_CH1P   %1 5 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH1P    Channel 1 capture/compare function polarity
: TIMER0_CHCTL2_CH1EN   %1 4 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH1EN    Channel 1 capture/compare function enable
: TIMER0_CHCTL2_CH0NP   %1 3 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH0NP    Channel 0 complementary output polarity
: TIMER0_CHCTL2_CH0NEN   %1 2 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH0NEN    Channel 0 complementary output enable
: TIMER0_CHCTL2_CH0P   %1 1 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH0P    Channel 0 capture/compare function polarity
: TIMER0_CHCTL2_CH0EN   %1 0 lshift TIMER0_CHCTL2 bis! ;  \ TIMER0_CHCTL2_CH0EN    Channel 0 capture/compare function enable

\ TIMER0_CNT (read-write)
: TIMER0_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_CNT bis! ;  \ TIMER0_CNT_CNT    current counter value

\ TIMER0_PSC (read-write)
: TIMER0_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_PSC bis! ;  \ TIMER0_PSC_PSC    Prescaler value of the counter clock

\ TIMER0_CAR (read-write)
: TIMER0_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_CAR bis! ;  \ TIMER0_CAR_CARL    Counter auto reload value

\ TIMER0_CREP (read-write)
: TIMER0_CREP_CREP   ( %XXXXXXXX -- ) 0 lshift TIMER0_CREP bis! ;  \ TIMER0_CREP_CREP    Counter repetition value

\ TIMER0_CH0CV (read-write)
: TIMER0_CH0CV_CH0VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_CH0CV bis! ;  \ TIMER0_CH0CV_CH0VAL    Capture or compare value of channel0

\ TIMER0_CH1CV (read-write)
: TIMER0_CH1CV_CH1VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_CH1CV bis! ;  \ TIMER0_CH1CV_CH1VAL    Capture or compare value of channel1

\ TIMER0_CH2CV (read-write)
: TIMER0_CH2CV_CH2VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_CH2CV bis! ;  \ TIMER0_CH2CV_CH2VAL    Capture or compare value of channel 2

\ TIMER0_CH3CV (read-write)
: TIMER0_CH3CV_CH3VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_CH3CV bis! ;  \ TIMER0_CH3CV_CH3VAL    Capture or compare value of channel 3

\ TIMER0_CCHP (read-write)
: TIMER0_CCHP_POEN   %1 15 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_POEN    Primary output enable
: TIMER0_CCHP_OAEN   %1 14 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_OAEN    Output automatic enable
: TIMER0_CCHP_BRKP   %1 13 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_BRKP    Break polarity
: TIMER0_CCHP_BRKEN   %1 12 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_BRKEN    Break enable
: TIMER0_CCHP_ROS   %1 11 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_ROS    Run mode off-state configure
: TIMER0_CCHP_IOS   %1 10 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_IOS    Idle mode off-state configure
: TIMER0_CCHP_PROT   ( %XX -- ) 8 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_PROT    Complementary register protect control
: TIMER0_CCHP_DTCFG   ( %XXXXXXXX -- ) 0 lshift TIMER0_CCHP bis! ;  \ TIMER0_CCHP_DTCFG    Dead time configure

\ TIMER0_DMACFG (read-write)
: TIMER0_DMACFG_DMATC   ( %XXXXX -- ) 8 lshift TIMER0_DMACFG bis! ;  \ TIMER0_DMACFG_DMATC    DMA transfer count
: TIMER0_DMACFG_DMATA   ( %XXXXX -- ) 0 lshift TIMER0_DMACFG bis! ;  \ TIMER0_DMACFG_DMATA    DMA transfer access start address

\ TIMER0_DMATB (read-write)
: TIMER0_DMATB_DMATB   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER0_DMATB bis! ;  \ TIMER0_DMATB_DMATB    DMA transfer buffer

\ TIMER1_CTL0 (read-write)
: TIMER1_CTL0_CKDIV   ( %XX -- ) 8 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_CKDIV    Clock division
: TIMER1_CTL0_ARSE   %1 7 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_ARSE    Auto-reload shadow enable
: TIMER1_CTL0_CAM   ( %XX -- ) 5 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_CAM    Counter aligns mode selection
: TIMER1_CTL0_DIR   %1 4 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_DIR    Direction
: TIMER1_CTL0_SPM   %1 3 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_SPM    Single pulse mode
: TIMER1_CTL0_UPS   %1 2 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_UPS    Update source
: TIMER1_CTL0_UPDIS   %1 1 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_UPDIS    Update disable
: TIMER1_CTL0_CEN   %1 0 lshift TIMER1_CTL0 bis! ;  \ TIMER1_CTL0_CEN    Counter enable

\ TIMER1_CTL1 (read-write)
: TIMER1_CTL1_TI0S   %1 7 lshift TIMER1_CTL1 bis! ;  \ TIMER1_CTL1_TI0S    Channel 0 trigger input selection
: TIMER1_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER1_CTL1 bis! ;  \ TIMER1_CTL1_MMC    Master mode control
: TIMER1_CTL1_DMAS   %1 3 lshift TIMER1_CTL1 bis! ;  \ TIMER1_CTL1_DMAS    DMA request source selection

\ TIMER1_SMCFG (read-write)
: TIMER1_SMCFG_ETP   %1 15 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_ETP    External trigger polarity
: TIMER1_SMCFG_SMC1   %1 14 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_SMC1    Part of SMC for enable External clock mode1
: TIMER1_SMCFG_ETPSC   ( %XX -- ) 12 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_ETPSC    External trigger prescaler
: TIMER1_SMCFG_ETFC   ( %XXXX -- ) 8 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_ETFC    External trigger filter control
: TIMER1_SMCFG_MSM   %1 7 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_MSM    Master-slave mode
: TIMER1_SMCFG_TRGS   ( %XXX -- ) 4 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_TRGS    Trigger selection
: TIMER1_SMCFG_SMC   ( %XXX -- ) 0 lshift TIMER1_SMCFG bis! ;  \ TIMER1_SMCFG_SMC    Slave mode control

\ TIMER1_DMAINTEN (read-write)
: TIMER1_DMAINTEN_TRGDEN   %1 14 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_TRGDEN    Trigger DMA request enable
: TIMER1_DMAINTEN_CH3DEN   %1 12 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH3DEN    Channel 3 capture/compare DMA request enable
: TIMER1_DMAINTEN_CH2DEN   %1 11 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH2DEN    Channel 2 capture/compare DMA request enable
: TIMER1_DMAINTEN_CH1DEN   %1 10 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH1DEN    Channel 1 capture/compare DMA request enable
: TIMER1_DMAINTEN_CH0DEN   %1 9 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH0DEN    Channel 0 capture/compare DMA request enable
: TIMER1_DMAINTEN_UPDEN   %1 8 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_UPDEN    Update DMA request enable
: TIMER1_DMAINTEN_TRGIE   %1 6 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_TRGIE    Trigger interrupt enable
: TIMER1_DMAINTEN_CH3IE   %1 4 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH3IE    Channel 3 capture/compare interrupt enable
: TIMER1_DMAINTEN_CH2IE   %1 3 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH2IE    Channel 2 capture/compare interrupt enable
: TIMER1_DMAINTEN_CH1IE   %1 2 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH1IE    Channel 1 capture/compare interrupt enable
: TIMER1_DMAINTEN_CH0IE   %1 1 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_CH0IE    Channel 0 capture/compare interrupt enable
: TIMER1_DMAINTEN_UPIE   %1 0 lshift TIMER1_DMAINTEN bis! ;  \ TIMER1_DMAINTEN_UPIE    Update interrupt enable

\ TIMER1_INTF (read-write)
: TIMER1_INTF_CH3OF   %1 12 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH3OF    Channel 3 over capture flag
: TIMER1_INTF_CH2OF   %1 11 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH2OF    Channel 2 over capture flag
: TIMER1_INTF_CH1OF   %1 10 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH1OF    Channel 1 over capture flag
: TIMER1_INTF_CH0OF   %1 9 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH0OF    Channel 0 over capture flag
: TIMER1_INTF_TRGIF   %1 6 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_TRGIF    Trigger interrupt flag
: TIMER1_INTF_CH3IF   %1 4 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH3IF    Channel 3 capture/compare interrupt enable
: TIMER1_INTF_CH2IF   %1 3 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH2IF    Channel 2 capture/compare interrupt enable
: TIMER1_INTF_CH1IF   %1 2 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH1IF    Channel 1 capture/compare interrupt flag
: TIMER1_INTF_CH0IF   %1 1 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_CH0IF    Channel 0 capture/compare interrupt flag
: TIMER1_INTF_UPIF   %1 0 lshift TIMER1_INTF bis! ;  \ TIMER1_INTF_UPIF    Update interrupt flag

\ TIMER1_SWEVG (write-only)
: TIMER1_SWEVG_TRGG   %1 6 lshift TIMER1_SWEVG bis! ;  \ TIMER1_SWEVG_TRGG    Trigger event generation
: TIMER1_SWEVG_CH3G   %1 4 lshift TIMER1_SWEVG bis! ;  \ TIMER1_SWEVG_CH3G    Channel 3 capture or compare event generation
: TIMER1_SWEVG_CH2G   %1 3 lshift TIMER1_SWEVG bis! ;  \ TIMER1_SWEVG_CH2G    Channel 2 capture or compare event generation
: TIMER1_SWEVG_CH1G   %1 2 lshift TIMER1_SWEVG bis! ;  \ TIMER1_SWEVG_CH1G    Channel 1 capture or compare event generation
: TIMER1_SWEVG_CH0G   %1 1 lshift TIMER1_SWEVG bis! ;  \ TIMER1_SWEVG_CH0G    Channel 0 capture or compare event generation
: TIMER1_SWEVG_UPG   %1 0 lshift TIMER1_SWEVG bis! ;  \ TIMER1_SWEVG_UPG    Update generation

\ TIMER1_CHCTL0_Output (read-write)
: TIMER1_CHCTL0_Output_CH1COMCEN   %1 15 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH1COMCEN    Channel 1 output compare clear enable
: TIMER1_CHCTL0_Output_CH1COMCTL   ( %XXX -- ) 12 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH1COMCTL    Channel 1 compare output control
: TIMER1_CHCTL0_Output_CH1COMSEN   %1 11 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH1COMSEN    Channel 1 output compare shadow enable
: TIMER1_CHCTL0_Output_CH1COMFEN   %1 10 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH1COMFEN    Channel 1 output compare fast enable
: TIMER1_CHCTL0_Output_CH1MS   ( %XX -- ) 8 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH1MS    Channel 1 mode selection
: TIMER1_CHCTL0_Output_CH0COMCEN   %1 7 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH0COMCEN    Channel 0 output compare clear enable
: TIMER1_CHCTL0_Output_CH0COMCTL   ( %XXX -- ) 4 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH0COMCTL     Channel 0 compare output control
: TIMER1_CHCTL0_Output_CH0COMSEN   %1 3 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH0COMSEN    Channel 0 compare output shadow enable
: TIMER1_CHCTL0_Output_CH0COMFEN   %1 2 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH0COMFEN    Channel 0 output compare fast enable
: TIMER1_CHCTL0_Output_CH0MS   ( %XX -- ) 0 lshift TIMER1_CHCTL0_Output bis! ;  \ TIMER1_CHCTL0_Output_CH0MS    Channel 0 I/O mode selection

\ TIMER1_CHCTL0_Input (read-write)
: TIMER1_CHCTL0_Input_CH1CAPFLT   ( %XXXX -- ) 12 lshift TIMER1_CHCTL0_Input bis! ;  \ TIMER1_CHCTL0_Input_CH1CAPFLT    Channel 1 input capture filter control
: TIMER1_CHCTL0_Input_CH1CAPPSC   ( %XX -- ) 10 lshift TIMER1_CHCTL0_Input bis! ;  \ TIMER1_CHCTL0_Input_CH1CAPPSC    Channel 1 input capture prescaler
: TIMER1_CHCTL0_Input_CH1MS   ( %XX -- ) 8 lshift TIMER1_CHCTL0_Input bis! ;  \ TIMER1_CHCTL0_Input_CH1MS    Channel 1 mode selection
: TIMER1_CHCTL0_Input_CH0CAPFLT   ( %XXXX -- ) 4 lshift TIMER1_CHCTL0_Input bis! ;  \ TIMER1_CHCTL0_Input_CH0CAPFLT    Channel 0 input capture filter control
: TIMER1_CHCTL0_Input_CH0CAPPSC   ( %XX -- ) 2 lshift TIMER1_CHCTL0_Input bis! ;  \ TIMER1_CHCTL0_Input_CH0CAPPSC    Channel 0 input capture prescaler
: TIMER1_CHCTL0_Input_CH0MS   ( %XX -- ) 0 lshift TIMER1_CHCTL0_Input bis! ;  \ TIMER1_CHCTL0_Input_CH0MS    Channel 0 mode selection

\ TIMER1_CHCTL1_Output (read-write)
: TIMER1_CHCTL1_Output_CH3COMCEN   %1 15 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH3COMCEN    Channel 3 output compare clear enable
: TIMER1_CHCTL1_Output_CH3COMCTL   ( %XXX -- ) 12 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH3COMCTL    Channel 3 compare output control
: TIMER1_CHCTL1_Output_CH3COMSEN   %1 11 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH3COMSEN    Channel 3 output compare shadow enable
: TIMER1_CHCTL1_Output_CH3COMFEN   %1 10 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH3COMFEN    Channel 3 output compare fast enable
: TIMER1_CHCTL1_Output_CH3MS   ( %XX -- ) 8 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH3MS    Channel 3 mode selection
: TIMER1_CHCTL1_Output_CH2COMCEN   %1 7 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH2COMCEN    Channel 2 output compare clear enable
: TIMER1_CHCTL1_Output_CH2COMCTL   ( %XXX -- ) 4 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH2COMCTL    Channel 2 compare output control
: TIMER1_CHCTL1_Output_CH2COMSEN   %1 3 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH2COMSEN    Channel 2 compare output shadow enable
: TIMER1_CHCTL1_Output_CH2COMFEN   %1 2 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH2COMFEN    Channel 2 output compare fast enable
: TIMER1_CHCTL1_Output_CH2MS   ( %XX -- ) 0 lshift TIMER1_CHCTL1_Output bis! ;  \ TIMER1_CHCTL1_Output_CH2MS    Channel 2 I/O mode selection

\ TIMER1_CHCTL1_Input (read-write)
: TIMER1_CHCTL1_Input_CH3CAPFLT   ( %XXXX -- ) 12 lshift TIMER1_CHCTL1_Input bis! ;  \ TIMER1_CHCTL1_Input_CH3CAPFLT    Channel 3 input capture filter control
: TIMER1_CHCTL1_Input_CH3CAPPSC   ( %XX -- ) 10 lshift TIMER1_CHCTL1_Input bis! ;  \ TIMER1_CHCTL1_Input_CH3CAPPSC    Channel 3 input capture prescaler
: TIMER1_CHCTL1_Input_CH3MS   ( %XX -- ) 8 lshift TIMER1_CHCTL1_Input bis! ;  \ TIMER1_CHCTL1_Input_CH3MS    Channel 3 mode selection
: TIMER1_CHCTL1_Input_CH2CAPFLT   ( %XXXX -- ) 4 lshift TIMER1_CHCTL1_Input bis! ;  \ TIMER1_CHCTL1_Input_CH2CAPFLT    Channel 2 input capture filter control
: TIMER1_CHCTL1_Input_CH2CAPPSC   ( %XX -- ) 2 lshift TIMER1_CHCTL1_Input bis! ;  \ TIMER1_CHCTL1_Input_CH2CAPPSC    Channel 2 input capture prescaler
: TIMER1_CHCTL1_Input_CH2MS   ( %XX -- ) 0 lshift TIMER1_CHCTL1_Input bis! ;  \ TIMER1_CHCTL1_Input_CH2MS    Channel 2 mode selection

\ TIMER1_CHCTL2 (read-write)
: TIMER1_CHCTL2_CH3P   %1 13 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH3P    Channel 3 capture/compare function polarity
: TIMER1_CHCTL2_CH3EN   %1 12 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH3EN    Channel 3 capture/compare function enable
: TIMER1_CHCTL2_CH2P   %1 9 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH2P    Channel 2 capture/compare function polarity
: TIMER1_CHCTL2_CH2EN   %1 8 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH2EN    Channel 2 capture/compare function enable
: TIMER1_CHCTL2_CH1P   %1 5 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH1P    Channel 1 capture/compare function polarity
: TIMER1_CHCTL2_CH1EN   %1 4 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH1EN    Channel 1 capture/compare function enable
: TIMER1_CHCTL2_CH0P   %1 1 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH0P    Channel 0 capture/compare function polarity
: TIMER1_CHCTL2_CH0EN   %1 0 lshift TIMER1_CHCTL2 bis! ;  \ TIMER1_CHCTL2_CH0EN    Channel 0 capture/compare function enable

\ TIMER1_CNT (read-write)
: TIMER1_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_CNT bis! ;  \ TIMER1_CNT_CNT    counter value

\ TIMER1_PSC (read-write)
: TIMER1_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_PSC bis! ;  \ TIMER1_PSC_PSC    Prescaler value of the counter clock

\ TIMER1_CAR (read-write)
: TIMER1_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_CAR bis! ;  \ TIMER1_CAR_CARL    Counter auto reload value

\ TIMER1_CH0CV (read-write)
: TIMER1_CH0CV_CH0VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_CH0CV bis! ;  \ TIMER1_CH0CV_CH0VAL    Capture or compare value of channel 0

\ TIMER1_CH1CV (read-write)
: TIMER1_CH1CV_CH1VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_CH1CV bis! ;  \ TIMER1_CH1CV_CH1VAL    Capture or compare value of channel1

\ TIMER1_CH2CV (read-write)
: TIMER1_CH2CV_CH2VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_CH2CV bis! ;  \ TIMER1_CH2CV_CH2VAL    Capture or compare value of channel 2

\ TIMER1_CH3CV (read-write)
: TIMER1_CH3CV_CH3VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_CH3CV bis! ;  \ TIMER1_CH3CV_CH3VAL    Capture or compare value of channel 3

\ TIMER1_DMACFG (read-write)
: TIMER1_DMACFG_DMATC   ( %XXXXX -- ) 8 lshift TIMER1_DMACFG bis! ;  \ TIMER1_DMACFG_DMATC    DMA transfer count
: TIMER1_DMACFG_DMATA   ( %XXXXX -- ) 0 lshift TIMER1_DMACFG bis! ;  \ TIMER1_DMACFG_DMATA    DMA transfer access start address

\ TIMER1_DMATB (read-write)
: TIMER1_DMATB_DMATB   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER1_DMATB bis! ;  \ TIMER1_DMATB_DMATB    DMA transfer buffer

\ TIMER2_CTL0 (read-write)
: TIMER2_CTL0_CKDIV   ( %XX -- ) 8 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_CKDIV    Clock division
: TIMER2_CTL0_ARSE   %1 7 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_ARSE    Auto-reload shadow enable
: TIMER2_CTL0_CAM   ( %XX -- ) 5 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_CAM    Counter aligns mode selection
: TIMER2_CTL0_DIR   %1 4 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_DIR    Direction
: TIMER2_CTL0_SPM   %1 3 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_SPM    Single pulse mode
: TIMER2_CTL0_UPS   %1 2 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_UPS    Update source
: TIMER2_CTL0_UPDIS   %1 1 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_UPDIS    Update disable
: TIMER2_CTL0_CEN   %1 0 lshift TIMER2_CTL0 bis! ;  \ TIMER2_CTL0_CEN    Counter enable

\ TIMER2_CTL1 (read-write)
: TIMER2_CTL1_TI0S   %1 7 lshift TIMER2_CTL1 bis! ;  \ TIMER2_CTL1_TI0S    Channel 0 trigger input selection
: TIMER2_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER2_CTL1 bis! ;  \ TIMER2_CTL1_MMC    Master mode control
: TIMER2_CTL1_DMAS   %1 3 lshift TIMER2_CTL1 bis! ;  \ TIMER2_CTL1_DMAS    DMA request source selection

\ TIMER2_SMCFG (read-write)
: TIMER2_SMCFG_ETP   %1 15 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_ETP    External trigger polarity
: TIMER2_SMCFG_SMC1   %1 14 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_SMC1    Part of SMC for enable External clock mode1
: TIMER2_SMCFG_ETPSC   ( %XX -- ) 12 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_ETPSC    External trigger prescaler
: TIMER2_SMCFG_ETFC   ( %XXXX -- ) 8 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_ETFC    External trigger filter control
: TIMER2_SMCFG_MSM   %1 7 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_MSM    Master-slave mode
: TIMER2_SMCFG_TRGS   ( %XXX -- ) 4 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_TRGS    Trigger selection
: TIMER2_SMCFG_SMC   ( %XXX -- ) 0 lshift TIMER2_SMCFG bis! ;  \ TIMER2_SMCFG_SMC    Slave mode control

\ TIMER2_DMAINTEN (read-write)
: TIMER2_DMAINTEN_TRGDEN   %1 14 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_TRGDEN    Trigger DMA request enable
: TIMER2_DMAINTEN_CH3DEN   %1 12 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH3DEN    Channel 3 capture/compare DMA request enable
: TIMER2_DMAINTEN_CH2DEN   %1 11 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH2DEN    Channel 2 capture/compare DMA request enable
: TIMER2_DMAINTEN_CH1DEN   %1 10 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH1DEN    Channel 1 capture/compare DMA request enable
: TIMER2_DMAINTEN_CH0DEN   %1 9 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH0DEN    Channel 0 capture/compare DMA request enable
: TIMER2_DMAINTEN_UPDEN   %1 8 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_UPDEN    Update DMA request enable
: TIMER2_DMAINTEN_TRGIE   %1 6 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_TRGIE    Trigger interrupt enable
: TIMER2_DMAINTEN_CH3IE   %1 4 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH3IE    Channel 3 capture/compare interrupt enable
: TIMER2_DMAINTEN_CH2IE   %1 3 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH2IE    Channel 2 capture/compare interrupt enable
: TIMER2_DMAINTEN_CH1IE   %1 2 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH1IE    Channel 1 capture/compare interrupt enable
: TIMER2_DMAINTEN_CH0IE   %1 1 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_CH0IE    Channel 0 capture/compare interrupt enable
: TIMER2_DMAINTEN_UPIE   %1 0 lshift TIMER2_DMAINTEN bis! ;  \ TIMER2_DMAINTEN_UPIE    Update interrupt enable

\ TIMER2_INTF (read-write)
: TIMER2_INTF_CH3OF   %1 12 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH3OF    Channel 3 over capture flag
: TIMER2_INTF_CH2OF   %1 11 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH2OF    Channel 2 over capture flag
: TIMER2_INTF_CH1OF   %1 10 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH1OF    Channel 1 over capture flag
: TIMER2_INTF_CH0OF   %1 9 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH0OF    Channel 0 over capture flag
: TIMER2_INTF_TRGIF   %1 6 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_TRGIF    Trigger interrupt flag
: TIMER2_INTF_CH3IF   %1 4 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH3IF    Channel 3 capture/compare interrupt enable
: TIMER2_INTF_CH2IF   %1 3 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH2IF    Channel 2 capture/compare interrupt enable
: TIMER2_INTF_CH1IF   %1 2 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH1IF    Channel 1 capture/compare interrupt flag
: TIMER2_INTF_CH0IF   %1 1 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_CH0IF    Channel 0 capture/compare interrupt flag
: TIMER2_INTF_UPIF   %1 0 lshift TIMER2_INTF bis! ;  \ TIMER2_INTF_UPIF    Update interrupt flag

\ TIMER2_SWEVG (write-only)
: TIMER2_SWEVG_TRGG   %1 6 lshift TIMER2_SWEVG bis! ;  \ TIMER2_SWEVG_TRGG    Trigger event generation
: TIMER2_SWEVG_CH3G   %1 4 lshift TIMER2_SWEVG bis! ;  \ TIMER2_SWEVG_CH3G    Channel 3 capture or compare event generation
: TIMER2_SWEVG_CH2G   %1 3 lshift TIMER2_SWEVG bis! ;  \ TIMER2_SWEVG_CH2G    Channel 2 capture or compare event generation
: TIMER2_SWEVG_CH1G   %1 2 lshift TIMER2_SWEVG bis! ;  \ TIMER2_SWEVG_CH1G    Channel 1 capture or compare event generation
: TIMER2_SWEVG_CH0G   %1 1 lshift TIMER2_SWEVG bis! ;  \ TIMER2_SWEVG_CH0G    Channel 0 capture or compare event generation
: TIMER2_SWEVG_UPG   %1 0 lshift TIMER2_SWEVG bis! ;  \ TIMER2_SWEVG_UPG    Update generation

\ TIMER2_CHCTL0_Output (read-write)
: TIMER2_CHCTL0_Output_CH1COMCEN   %1 15 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH1COMCEN    Channel 1 output compare clear enable
: TIMER2_CHCTL0_Output_CH1COMCTL   ( %XXX -- ) 12 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH1COMCTL    Channel 1 compare output control
: TIMER2_CHCTL0_Output_CH1COMSEN   %1 11 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH1COMSEN    Channel 1 output compare shadow enable
: TIMER2_CHCTL0_Output_CH1COMFEN   %1 10 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH1COMFEN    Channel 1 output compare fast enable
: TIMER2_CHCTL0_Output_CH1MS   ( %XX -- ) 8 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH1MS    Channel 1 mode selection
: TIMER2_CHCTL0_Output_CH0COMCEN   %1 7 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH0COMCEN    Channel 0 output compare clear enable
: TIMER2_CHCTL0_Output_CH0COMCTL   ( %XXX -- ) 4 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH0COMCTL     Channel 0 compare output control
: TIMER2_CHCTL0_Output_CH0COMSEN   %1 3 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH0COMSEN    Channel 0 compare output shadow enable
: TIMER2_CHCTL0_Output_CH0COMFEN   %1 2 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH0COMFEN    Channel 0 output compare fast enable
: TIMER2_CHCTL0_Output_CH0MS   ( %XX -- ) 0 lshift TIMER2_CHCTL0_Output bis! ;  \ TIMER2_CHCTL0_Output_CH0MS    Channel 0 I/O mode selection

\ TIMER2_CHCTL0_Input (read-write)
: TIMER2_CHCTL0_Input_CH1CAPFLT   ( %XXXX -- ) 12 lshift TIMER2_CHCTL0_Input bis! ;  \ TIMER2_CHCTL0_Input_CH1CAPFLT    Channel 1 input capture filter control
: TIMER2_CHCTL0_Input_CH1CAPPSC   ( %XX -- ) 10 lshift TIMER2_CHCTL0_Input bis! ;  \ TIMER2_CHCTL0_Input_CH1CAPPSC    Channel 1 input capture prescaler
: TIMER2_CHCTL0_Input_CH1MS   ( %XX -- ) 8 lshift TIMER2_CHCTL0_Input bis! ;  \ TIMER2_CHCTL0_Input_CH1MS    Channel 1 mode selection
: TIMER2_CHCTL0_Input_CH0CAPFLT   ( %XXXX -- ) 4 lshift TIMER2_CHCTL0_Input bis! ;  \ TIMER2_CHCTL0_Input_CH0CAPFLT    Channel 0 input capture filter control
: TIMER2_CHCTL0_Input_CH0CAPPSC   ( %XX -- ) 2 lshift TIMER2_CHCTL0_Input bis! ;  \ TIMER2_CHCTL0_Input_CH0CAPPSC    Channel 0 input capture prescaler
: TIMER2_CHCTL0_Input_CH0MS   ( %XX -- ) 0 lshift TIMER2_CHCTL0_Input bis! ;  \ TIMER2_CHCTL0_Input_CH0MS    Channel 0 mode selection

\ TIMER2_CHCTL1_Output (read-write)
: TIMER2_CHCTL1_Output_CH3COMCEN   %1 15 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH3COMCEN    Channel 3 output compare clear enable
: TIMER2_CHCTL1_Output_CH3COMCTL   ( %XXX -- ) 12 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH3COMCTL    Channel 3 compare output control
: TIMER2_CHCTL1_Output_CH3COMSEN   %1 11 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH3COMSEN    Channel 3 output compare shadow enable
: TIMER2_CHCTL1_Output_CH3COMFEN   %1 10 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH3COMFEN    Channel 3 output compare fast enable
: TIMER2_CHCTL1_Output_CH3MS   ( %XX -- ) 8 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH3MS    Channel 3 mode selection
: TIMER2_CHCTL1_Output_CH2COMCEN   %1 7 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH2COMCEN    Channel 2 output compare clear enable
: TIMER2_CHCTL1_Output_CH2COMCTL   ( %XXX -- ) 4 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH2COMCTL    Channel 2 compare output control
: TIMER2_CHCTL1_Output_CH2COMSEN   %1 3 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH2COMSEN    Channel 2 compare output shadow enable
: TIMER2_CHCTL1_Output_CH2COMFEN   %1 2 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH2COMFEN    Channel 2 output compare fast enable
: TIMER2_CHCTL1_Output_CH2MS   ( %XX -- ) 0 lshift TIMER2_CHCTL1_Output bis! ;  \ TIMER2_CHCTL1_Output_CH2MS    Channel 2 I/O mode selection

\ TIMER2_CHCTL1_Input (read-write)
: TIMER2_CHCTL1_Input_CH3CAPFLT   ( %XXXX -- ) 12 lshift TIMER2_CHCTL1_Input bis! ;  \ TIMER2_CHCTL1_Input_CH3CAPFLT    Channel 3 input capture filter control
: TIMER2_CHCTL1_Input_CH3CAPPSC   ( %XX -- ) 10 lshift TIMER2_CHCTL1_Input bis! ;  \ TIMER2_CHCTL1_Input_CH3CAPPSC    Channel 3 input capture prescaler
: TIMER2_CHCTL1_Input_CH3MS   ( %XX -- ) 8 lshift TIMER2_CHCTL1_Input bis! ;  \ TIMER2_CHCTL1_Input_CH3MS    Channel 3 mode selection
: TIMER2_CHCTL1_Input_CH2CAPFLT   ( %XXXX -- ) 4 lshift TIMER2_CHCTL1_Input bis! ;  \ TIMER2_CHCTL1_Input_CH2CAPFLT    Channel 2 input capture filter control
: TIMER2_CHCTL1_Input_CH2CAPPSC   ( %XX -- ) 2 lshift TIMER2_CHCTL1_Input bis! ;  \ TIMER2_CHCTL1_Input_CH2CAPPSC    Channel 2 input capture prescaler
: TIMER2_CHCTL1_Input_CH2MS   ( %XX -- ) 0 lshift TIMER2_CHCTL1_Input bis! ;  \ TIMER2_CHCTL1_Input_CH2MS    Channel 2 mode selection

\ TIMER2_CHCTL2 (read-write)
: TIMER2_CHCTL2_CH3P   %1 13 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH3P    Channel 3 capture/compare function polarity
: TIMER2_CHCTL2_CH3EN   %1 12 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH3EN    Channel 3 capture/compare function enable
: TIMER2_CHCTL2_CH2P   %1 9 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH2P    Channel 2 capture/compare function polarity
: TIMER2_CHCTL2_CH2EN   %1 8 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH2EN    Channel 2 capture/compare function enable
: TIMER2_CHCTL2_CH1P   %1 5 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH1P    Channel 1 capture/compare function polarity
: TIMER2_CHCTL2_CH1EN   %1 4 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH1EN    Channel 1 capture/compare function enable
: TIMER2_CHCTL2_CH0P   %1 1 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH0P    Channel 0 capture/compare function polarity
: TIMER2_CHCTL2_CH0EN   %1 0 lshift TIMER2_CHCTL2 bis! ;  \ TIMER2_CHCTL2_CH0EN    Channel 0 capture/compare function enable

\ TIMER2_CNT (read-write)
: TIMER2_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_CNT bis! ;  \ TIMER2_CNT_CNT    counter value

\ TIMER2_PSC (read-write)
: TIMER2_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_PSC bis! ;  \ TIMER2_PSC_PSC    Prescaler value of the counter clock

\ TIMER2_CAR (read-write)
: TIMER2_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_CAR bis! ;  \ TIMER2_CAR_CARL    Counter auto reload value

\ TIMER2_CH0CV (read-write)
: TIMER2_CH0CV_CH0VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_CH0CV bis! ;  \ TIMER2_CH0CV_CH0VAL    Capture or compare value of channel 0

\ TIMER2_CH1CV (read-write)
: TIMER2_CH1CV_CH1VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_CH1CV bis! ;  \ TIMER2_CH1CV_CH1VAL    Capture or compare value of channel1

\ TIMER2_CH2CV (read-write)
: TIMER2_CH2CV_CH2VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_CH2CV bis! ;  \ TIMER2_CH2CV_CH2VAL    Capture or compare value of channel 2

\ TIMER2_CH3CV (read-write)
: TIMER2_CH3CV_CH3VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_CH3CV bis! ;  \ TIMER2_CH3CV_CH3VAL    Capture or compare value of channel 3

\ TIMER2_DMACFG (read-write)
: TIMER2_DMACFG_DMATC   ( %XXXXX -- ) 8 lshift TIMER2_DMACFG bis! ;  \ TIMER2_DMACFG_DMATC    DMA transfer count
: TIMER2_DMACFG_DMATA   ( %XXXXX -- ) 0 lshift TIMER2_DMACFG bis! ;  \ TIMER2_DMACFG_DMATA    DMA transfer access start address

\ TIMER2_DMATB (read-write)
: TIMER2_DMATB_DMATB   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER2_DMATB bis! ;  \ TIMER2_DMATB_DMATB    DMA transfer buffer

\ TIMER3_CTL0 (read-write)
: TIMER3_CTL0_CKDIV   ( %XX -- ) 8 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_CKDIV    Clock division
: TIMER3_CTL0_ARSE   %1 7 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_ARSE    Auto-reload shadow enable
: TIMER3_CTL0_CAM   ( %XX -- ) 5 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_CAM    Counter aligns mode selection
: TIMER3_CTL0_DIR   %1 4 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_DIR    Direction
: TIMER3_CTL0_SPM   %1 3 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_SPM    Single pulse mode
: TIMER3_CTL0_UPS   %1 2 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_UPS    Update source
: TIMER3_CTL0_UPDIS   %1 1 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_UPDIS    Update disable
: TIMER3_CTL0_CEN   %1 0 lshift TIMER3_CTL0 bis! ;  \ TIMER3_CTL0_CEN    Counter enable

\ TIMER3_CTL1 (read-write)
: TIMER3_CTL1_TI0S   %1 7 lshift TIMER3_CTL1 bis! ;  \ TIMER3_CTL1_TI0S    Channel 0 trigger input selection
: TIMER3_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER3_CTL1 bis! ;  \ TIMER3_CTL1_MMC    Master mode control
: TIMER3_CTL1_DMAS   %1 3 lshift TIMER3_CTL1 bis! ;  \ TIMER3_CTL1_DMAS    DMA request source selection

\ TIMER3_SMCFG (read-write)
: TIMER3_SMCFG_ETP   %1 15 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_ETP    External trigger polarity
: TIMER3_SMCFG_SMC1   %1 14 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_SMC1    Part of SMC for enable External clock mode1
: TIMER3_SMCFG_ETPSC   ( %XX -- ) 12 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_ETPSC    External trigger prescaler
: TIMER3_SMCFG_ETFC   ( %XXXX -- ) 8 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_ETFC    External trigger filter control
: TIMER3_SMCFG_MSM   %1 7 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_MSM    Master-slave mode
: TIMER3_SMCFG_TRGS   ( %XXX -- ) 4 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_TRGS    Trigger selection
: TIMER3_SMCFG_SMC   ( %XXX -- ) 0 lshift TIMER3_SMCFG bis! ;  \ TIMER3_SMCFG_SMC    Slave mode control

\ TIMER3_DMAINTEN (read-write)
: TIMER3_DMAINTEN_TRGDEN   %1 14 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_TRGDEN    Trigger DMA request enable
: TIMER3_DMAINTEN_CH3DEN   %1 12 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH3DEN    Channel 3 capture/compare DMA request enable
: TIMER3_DMAINTEN_CH2DEN   %1 11 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH2DEN    Channel 2 capture/compare DMA request enable
: TIMER3_DMAINTEN_CH1DEN   %1 10 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH1DEN    Channel 1 capture/compare DMA request enable
: TIMER3_DMAINTEN_CH0DEN   %1 9 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH0DEN    Channel 0 capture/compare DMA request enable
: TIMER3_DMAINTEN_UPDEN   %1 8 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_UPDEN    Update DMA request enable
: TIMER3_DMAINTEN_TRGIE   %1 6 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_TRGIE    Trigger interrupt enable
: TIMER3_DMAINTEN_CH3IE   %1 4 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH3IE    Channel 3 capture/compare interrupt enable
: TIMER3_DMAINTEN_CH2IE   %1 3 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH2IE    Channel 2 capture/compare interrupt enable
: TIMER3_DMAINTEN_CH1IE   %1 2 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH1IE    Channel 1 capture/compare interrupt enable
: TIMER3_DMAINTEN_CH0IE   %1 1 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_CH0IE    Channel 0 capture/compare interrupt enable
: TIMER3_DMAINTEN_UPIE   %1 0 lshift TIMER3_DMAINTEN bis! ;  \ TIMER3_DMAINTEN_UPIE    Update interrupt enable

\ TIMER3_INTF (read-write)
: TIMER3_INTF_CH3OF   %1 12 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH3OF    Channel 3 over capture flag
: TIMER3_INTF_CH2OF   %1 11 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH2OF    Channel 2 over capture flag
: TIMER3_INTF_CH1OF   %1 10 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH1OF    Channel 1 over capture flag
: TIMER3_INTF_CH0OF   %1 9 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH0OF    Channel 0 over capture flag
: TIMER3_INTF_TRGIF   %1 6 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_TRGIF    Trigger interrupt flag
: TIMER3_INTF_CH3IF   %1 4 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH3IF    Channel 3 capture/compare interrupt enable
: TIMER3_INTF_CH2IF   %1 3 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH2IF    Channel 2 capture/compare interrupt enable
: TIMER3_INTF_CH1IF   %1 2 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH1IF    Channel 1 capture/compare interrupt flag
: TIMER3_INTF_CH0IF   %1 1 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_CH0IF    Channel 0 capture/compare interrupt flag
: TIMER3_INTF_UPIF   %1 0 lshift TIMER3_INTF bis! ;  \ TIMER3_INTF_UPIF    Update interrupt flag

\ TIMER3_SWEVG (write-only)
: TIMER3_SWEVG_TRGG   %1 6 lshift TIMER3_SWEVG bis! ;  \ TIMER3_SWEVG_TRGG    Trigger event generation
: TIMER3_SWEVG_CH3G   %1 4 lshift TIMER3_SWEVG bis! ;  \ TIMER3_SWEVG_CH3G    Channel 3 capture or compare event generation
: TIMER3_SWEVG_CH2G   %1 3 lshift TIMER3_SWEVG bis! ;  \ TIMER3_SWEVG_CH2G    Channel 2 capture or compare event generation
: TIMER3_SWEVG_CH1G   %1 2 lshift TIMER3_SWEVG bis! ;  \ TIMER3_SWEVG_CH1G    Channel 1 capture or compare event generation
: TIMER3_SWEVG_CH0G   %1 1 lshift TIMER3_SWEVG bis! ;  \ TIMER3_SWEVG_CH0G    Channel 0 capture or compare event generation
: TIMER3_SWEVG_UPG   %1 0 lshift TIMER3_SWEVG bis! ;  \ TIMER3_SWEVG_UPG    Update generation

\ TIMER3_CHCTL0_Output (read-write)
: TIMER3_CHCTL0_Output_CH1COMCEN   %1 15 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH1COMCEN    Channel 1 output compare clear enable
: TIMER3_CHCTL0_Output_CH1COMCTL   ( %XXX -- ) 12 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH1COMCTL    Channel 1 compare output control
: TIMER3_CHCTL0_Output_CH1COMSEN   %1 11 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH1COMSEN    Channel 1 output compare shadow enable
: TIMER3_CHCTL0_Output_CH1COMFEN   %1 10 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH1COMFEN    Channel 1 output compare fast enable
: TIMER3_CHCTL0_Output_CH1MS   ( %XX -- ) 8 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH1MS    Channel 1 mode selection
: TIMER3_CHCTL0_Output_CH0COMCEN   %1 7 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH0COMCEN    Channel 0 output compare clear enable
: TIMER3_CHCTL0_Output_CH0COMCTL   ( %XXX -- ) 4 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH0COMCTL     Channel 0 compare output control
: TIMER3_CHCTL0_Output_CH0COMSEN   %1 3 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH0COMSEN    Channel 0 compare output shadow enable
: TIMER3_CHCTL0_Output_CH0COMFEN   %1 2 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH0COMFEN    Channel 0 output compare fast enable
: TIMER3_CHCTL0_Output_CH0MS   ( %XX -- ) 0 lshift TIMER3_CHCTL0_Output bis! ;  \ TIMER3_CHCTL0_Output_CH0MS    Channel 0 I/O mode selection

\ TIMER3_CHCTL0_Input (read-write)
: TIMER3_CHCTL0_Input_CH1CAPFLT   ( %XXXX -- ) 12 lshift TIMER3_CHCTL0_Input bis! ;  \ TIMER3_CHCTL0_Input_CH1CAPFLT    Channel 1 input capture filter control
: TIMER3_CHCTL0_Input_CH1CAPPSC   ( %XX -- ) 10 lshift TIMER3_CHCTL0_Input bis! ;  \ TIMER3_CHCTL0_Input_CH1CAPPSC    Channel 1 input capture prescaler
: TIMER3_CHCTL0_Input_CH1MS   ( %XX -- ) 8 lshift TIMER3_CHCTL0_Input bis! ;  \ TIMER3_CHCTL0_Input_CH1MS    Channel 1 mode selection
: TIMER3_CHCTL0_Input_CH0CAPFLT   ( %XXXX -- ) 4 lshift TIMER3_CHCTL0_Input bis! ;  \ TIMER3_CHCTL0_Input_CH0CAPFLT    Channel 0 input capture filter control
: TIMER3_CHCTL0_Input_CH0CAPPSC   ( %XX -- ) 2 lshift TIMER3_CHCTL0_Input bis! ;  \ TIMER3_CHCTL0_Input_CH0CAPPSC    Channel 0 input capture prescaler
: TIMER3_CHCTL0_Input_CH0MS   ( %XX -- ) 0 lshift TIMER3_CHCTL0_Input bis! ;  \ TIMER3_CHCTL0_Input_CH0MS    Channel 0 mode selection

\ TIMER3_CHCTL1_Output (read-write)
: TIMER3_CHCTL1_Output_CH3COMCEN   %1 15 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH3COMCEN    Channel 3 output compare clear enable
: TIMER3_CHCTL1_Output_CH3COMCTL   ( %XXX -- ) 12 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH3COMCTL    Channel 3 compare output control
: TIMER3_CHCTL1_Output_CH3COMSEN   %1 11 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH3COMSEN    Channel 3 output compare shadow enable
: TIMER3_CHCTL1_Output_CH3COMFEN   %1 10 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH3COMFEN    Channel 3 output compare fast enable
: TIMER3_CHCTL1_Output_CH3MS   ( %XX -- ) 8 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH3MS    Channel 3 mode selection
: TIMER3_CHCTL1_Output_CH2COMCEN   %1 7 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH2COMCEN    Channel 2 output compare clear enable
: TIMER3_CHCTL1_Output_CH2COMCTL   ( %XXX -- ) 4 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH2COMCTL    Channel 2 compare output control
: TIMER3_CHCTL1_Output_CH2COMSEN   %1 3 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH2COMSEN    Channel 2 compare output shadow enable
: TIMER3_CHCTL1_Output_CH2COMFEN   %1 2 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH2COMFEN    Channel 2 output compare fast enable
: TIMER3_CHCTL1_Output_CH2MS   ( %XX -- ) 0 lshift TIMER3_CHCTL1_Output bis! ;  \ TIMER3_CHCTL1_Output_CH2MS    Channel 2 I/O mode selection

\ TIMER3_CHCTL1_Input (read-write)
: TIMER3_CHCTL1_Input_CH3CAPFLT   ( %XXXX -- ) 12 lshift TIMER3_CHCTL1_Input bis! ;  \ TIMER3_CHCTL1_Input_CH3CAPFLT    Channel 3 input capture filter control
: TIMER3_CHCTL1_Input_CH3CAPPSC   ( %XX -- ) 10 lshift TIMER3_CHCTL1_Input bis! ;  \ TIMER3_CHCTL1_Input_CH3CAPPSC    Channel 3 input capture prescaler
: TIMER3_CHCTL1_Input_CH3MS   ( %XX -- ) 8 lshift TIMER3_CHCTL1_Input bis! ;  \ TIMER3_CHCTL1_Input_CH3MS    Channel 3 mode selection
: TIMER3_CHCTL1_Input_CH2CAPFLT   ( %XXXX -- ) 4 lshift TIMER3_CHCTL1_Input bis! ;  \ TIMER3_CHCTL1_Input_CH2CAPFLT    Channel 2 input capture filter control
: TIMER3_CHCTL1_Input_CH2CAPPSC   ( %XX -- ) 2 lshift TIMER3_CHCTL1_Input bis! ;  \ TIMER3_CHCTL1_Input_CH2CAPPSC    Channel 2 input capture prescaler
: TIMER3_CHCTL1_Input_CH2MS   ( %XX -- ) 0 lshift TIMER3_CHCTL1_Input bis! ;  \ TIMER3_CHCTL1_Input_CH2MS    Channel 2 mode selection

\ TIMER3_CHCTL2 (read-write)
: TIMER3_CHCTL2_CH3P   %1 13 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH3P    Channel 3 capture/compare function polarity
: TIMER3_CHCTL2_CH3EN   %1 12 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH3EN    Channel 3 capture/compare function enable
: TIMER3_CHCTL2_CH2P   %1 9 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH2P    Channel 2 capture/compare function polarity
: TIMER3_CHCTL2_CH2EN   %1 8 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH2EN    Channel 2 capture/compare function enable
: TIMER3_CHCTL2_CH1P   %1 5 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH1P    Channel 1 capture/compare function polarity
: TIMER3_CHCTL2_CH1EN   %1 4 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH1EN    Channel 1 capture/compare function enable
: TIMER3_CHCTL2_CH0P   %1 1 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH0P    Channel 0 capture/compare function polarity
: TIMER3_CHCTL2_CH0EN   %1 0 lshift TIMER3_CHCTL2 bis! ;  \ TIMER3_CHCTL2_CH0EN    Channel 0 capture/compare function enable

\ TIMER3_CNT (read-write)
: TIMER3_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_CNT bis! ;  \ TIMER3_CNT_CNT    counter value

\ TIMER3_PSC (read-write)
: TIMER3_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_PSC bis! ;  \ TIMER3_PSC_PSC    Prescaler value of the counter clock

\ TIMER3_CAR (read-write)
: TIMER3_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_CAR bis! ;  \ TIMER3_CAR_CARL    Counter auto reload value

\ TIMER3_CH0CV (read-write)
: TIMER3_CH0CV_CH0VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_CH0CV bis! ;  \ TIMER3_CH0CV_CH0VAL    Capture or compare value of channel 0

\ TIMER3_CH1CV (read-write)
: TIMER3_CH1CV_CH1VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_CH1CV bis! ;  \ TIMER3_CH1CV_CH1VAL    Capture or compare value of channel1

\ TIMER3_CH2CV (read-write)
: TIMER3_CH2CV_CH2VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_CH2CV bis! ;  \ TIMER3_CH2CV_CH2VAL    Capture or compare value of channel 2

\ TIMER3_CH3CV (read-write)
: TIMER3_CH3CV_CH3VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_CH3CV bis! ;  \ TIMER3_CH3CV_CH3VAL    Capture or compare value of channel 3

\ TIMER3_DMACFG (read-write)
: TIMER3_DMACFG_DMATC   ( %XXXXX -- ) 8 lshift TIMER3_DMACFG bis! ;  \ TIMER3_DMACFG_DMATC    DMA transfer count
: TIMER3_DMACFG_DMATA   ( %XXXXX -- ) 0 lshift TIMER3_DMACFG bis! ;  \ TIMER3_DMACFG_DMATA    DMA transfer access start address

\ TIMER3_DMATB (read-write)
: TIMER3_DMATB_DMATB   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER3_DMATB bis! ;  \ TIMER3_DMATB_DMATB    DMA transfer buffer

\ TIMER4_CTL0 (read-write)
: TIMER4_CTL0_CKDIV   ( %XX -- ) 8 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_CKDIV    Clock division
: TIMER4_CTL0_ARSE   %1 7 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_ARSE    Auto-reload shadow enable
: TIMER4_CTL0_CAM   ( %XX -- ) 5 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_CAM    Counter aligns mode selection
: TIMER4_CTL0_DIR   %1 4 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_DIR    Direction
: TIMER4_CTL0_SPM   %1 3 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_SPM    Single pulse mode
: TIMER4_CTL0_UPS   %1 2 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_UPS    Update source
: TIMER4_CTL0_UPDIS   %1 1 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_UPDIS    Update disable
: TIMER4_CTL0_CEN   %1 0 lshift TIMER4_CTL0 bis! ;  \ TIMER4_CTL0_CEN    Counter enable

\ TIMER4_CTL1 (read-write)
: TIMER4_CTL1_TI0S   %1 7 lshift TIMER4_CTL1 bis! ;  \ TIMER4_CTL1_TI0S    Channel 0 trigger input selection
: TIMER4_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER4_CTL1 bis! ;  \ TIMER4_CTL1_MMC    Master mode control
: TIMER4_CTL1_DMAS   %1 3 lshift TIMER4_CTL1 bis! ;  \ TIMER4_CTL1_DMAS    DMA request source selection

\ TIMER4_SMCFG (read-write)
: TIMER4_SMCFG_ETP   %1 15 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_ETP    External trigger polarity
: TIMER4_SMCFG_SMC1   %1 14 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_SMC1    Part of SMC for enable External clock mode1
: TIMER4_SMCFG_ETPSC   ( %XX -- ) 12 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_ETPSC    External trigger prescaler
: TIMER4_SMCFG_ETFC   ( %XXXX -- ) 8 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_ETFC    External trigger filter control
: TIMER4_SMCFG_MSM   %1 7 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_MSM    Master-slave mode
: TIMER4_SMCFG_TRGS   ( %XXX -- ) 4 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_TRGS    Trigger selection
: TIMER4_SMCFG_SMC   ( %XXX -- ) 0 lshift TIMER4_SMCFG bis! ;  \ TIMER4_SMCFG_SMC    Slave mode control

\ TIMER4_DMAINTEN (read-write)
: TIMER4_DMAINTEN_TRGDEN   %1 14 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_TRGDEN    Trigger DMA request enable
: TIMER4_DMAINTEN_CH3DEN   %1 12 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH3DEN    Channel 3 capture/compare DMA request enable
: TIMER4_DMAINTEN_CH2DEN   %1 11 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH2DEN    Channel 2 capture/compare DMA request enable
: TIMER4_DMAINTEN_CH1DEN   %1 10 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH1DEN    Channel 1 capture/compare DMA request enable
: TIMER4_DMAINTEN_CH0DEN   %1 9 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH0DEN    Channel 0 capture/compare DMA request enable
: TIMER4_DMAINTEN_UPDEN   %1 8 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_UPDEN    Update DMA request enable
: TIMER4_DMAINTEN_TRGIE   %1 6 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_TRGIE    Trigger interrupt enable
: TIMER4_DMAINTEN_CH3IE   %1 4 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH3IE    Channel 3 capture/compare interrupt enable
: TIMER4_DMAINTEN_CH2IE   %1 3 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH2IE    Channel 2 capture/compare interrupt enable
: TIMER4_DMAINTEN_CH1IE   %1 2 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH1IE    Channel 1 capture/compare interrupt enable
: TIMER4_DMAINTEN_CH0IE   %1 1 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_CH0IE    Channel 0 capture/compare interrupt enable
: TIMER4_DMAINTEN_UPIE   %1 0 lshift TIMER4_DMAINTEN bis! ;  \ TIMER4_DMAINTEN_UPIE    Update interrupt enable

\ TIMER4_INTF (read-write)
: TIMER4_INTF_CH3OF   %1 12 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH3OF    Channel 3 over capture flag
: TIMER4_INTF_CH2OF   %1 11 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH2OF    Channel 2 over capture flag
: TIMER4_INTF_CH1OF   %1 10 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH1OF    Channel 1 over capture flag
: TIMER4_INTF_CH0OF   %1 9 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH0OF    Channel 0 over capture flag
: TIMER4_INTF_TRGIF   %1 6 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_TRGIF    Trigger interrupt flag
: TIMER4_INTF_CH3IF   %1 4 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH3IF    Channel 3 capture/compare interrupt enable
: TIMER4_INTF_CH2IF   %1 3 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH2IF    Channel 2 capture/compare interrupt enable
: TIMER4_INTF_CH1IF   %1 2 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH1IF    Channel 1 capture/compare interrupt flag
: TIMER4_INTF_CH0IF   %1 1 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_CH0IF    Channel 0 capture/compare interrupt flag
: TIMER4_INTF_UPIF   %1 0 lshift TIMER4_INTF bis! ;  \ TIMER4_INTF_UPIF    Update interrupt flag

\ TIMER4_SWEVG (write-only)
: TIMER4_SWEVG_TRGG   %1 6 lshift TIMER4_SWEVG bis! ;  \ TIMER4_SWEVG_TRGG    Trigger event generation
: TIMER4_SWEVG_CH3G   %1 4 lshift TIMER4_SWEVG bis! ;  \ TIMER4_SWEVG_CH3G    Channel 3 capture or compare event generation
: TIMER4_SWEVG_CH2G   %1 3 lshift TIMER4_SWEVG bis! ;  \ TIMER4_SWEVG_CH2G    Channel 2 capture or compare event generation
: TIMER4_SWEVG_CH1G   %1 2 lshift TIMER4_SWEVG bis! ;  \ TIMER4_SWEVG_CH1G    Channel 1 capture or compare event generation
: TIMER4_SWEVG_CH0G   %1 1 lshift TIMER4_SWEVG bis! ;  \ TIMER4_SWEVG_CH0G    Channel 0 capture or compare event generation
: TIMER4_SWEVG_UPG   %1 0 lshift TIMER4_SWEVG bis! ;  \ TIMER4_SWEVG_UPG    Update generation

\ TIMER4_CHCTL0_Output (read-write)
: TIMER4_CHCTL0_Output_CH1COMCEN   %1 15 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH1COMCEN    Channel 1 output compare clear enable
: TIMER4_CHCTL0_Output_CH1COMCTL   ( %XXX -- ) 12 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH1COMCTL    Channel 1 compare output control
: TIMER4_CHCTL0_Output_CH1COMSEN   %1 11 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH1COMSEN    Channel 1 output compare shadow enable
: TIMER4_CHCTL0_Output_CH1COMFEN   %1 10 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH1COMFEN    Channel 1 output compare fast enable
: TIMER4_CHCTL0_Output_CH1MS   ( %XX -- ) 8 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH1MS    Channel 1 mode selection
: TIMER4_CHCTL0_Output_CH0COMCEN   %1 7 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH0COMCEN    Channel 0 output compare clear enable
: TIMER4_CHCTL0_Output_CH0COMCTL   ( %XXX -- ) 4 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH0COMCTL     Channel 0 compare output control
: TIMER4_CHCTL0_Output_CH0COMSEN   %1 3 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH0COMSEN    Channel 0 compare output shadow enable
: TIMER4_CHCTL0_Output_CH0COMFEN   %1 2 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH0COMFEN    Channel 0 output compare fast enable
: TIMER4_CHCTL0_Output_CH0MS   ( %XX -- ) 0 lshift TIMER4_CHCTL0_Output bis! ;  \ TIMER4_CHCTL0_Output_CH0MS    Channel 0 I/O mode selection

\ TIMER4_CHCTL0_Input (read-write)
: TIMER4_CHCTL0_Input_CH1CAPFLT   ( %XXXX -- ) 12 lshift TIMER4_CHCTL0_Input bis! ;  \ TIMER4_CHCTL0_Input_CH1CAPFLT    Channel 1 input capture filter control
: TIMER4_CHCTL0_Input_CH1CAPPSC   ( %XX -- ) 10 lshift TIMER4_CHCTL0_Input bis! ;  \ TIMER4_CHCTL0_Input_CH1CAPPSC    Channel 1 input capture prescaler
: TIMER4_CHCTL0_Input_CH1MS   ( %XX -- ) 8 lshift TIMER4_CHCTL0_Input bis! ;  \ TIMER4_CHCTL0_Input_CH1MS    Channel 1 mode selection
: TIMER4_CHCTL0_Input_CH0CAPFLT   ( %XXXX -- ) 4 lshift TIMER4_CHCTL0_Input bis! ;  \ TIMER4_CHCTL0_Input_CH0CAPFLT    Channel 0 input capture filter control
: TIMER4_CHCTL0_Input_CH0CAPPSC   ( %XX -- ) 2 lshift TIMER4_CHCTL0_Input bis! ;  \ TIMER4_CHCTL0_Input_CH0CAPPSC    Channel 0 input capture prescaler
: TIMER4_CHCTL0_Input_CH0MS   ( %XX -- ) 0 lshift TIMER4_CHCTL0_Input bis! ;  \ TIMER4_CHCTL0_Input_CH0MS    Channel 0 mode selection

\ TIMER4_CHCTL1_Output (read-write)
: TIMER4_CHCTL1_Output_CH3COMCEN   %1 15 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH3COMCEN    Channel 3 output compare clear enable
: TIMER4_CHCTL1_Output_CH3COMCTL   ( %XXX -- ) 12 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH3COMCTL    Channel 3 compare output control
: TIMER4_CHCTL1_Output_CH3COMSEN   %1 11 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH3COMSEN    Channel 3 output compare shadow enable
: TIMER4_CHCTL1_Output_CH3COMFEN   %1 10 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH3COMFEN    Channel 3 output compare fast enable
: TIMER4_CHCTL1_Output_CH3MS   ( %XX -- ) 8 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH3MS    Channel 3 mode selection
: TIMER4_CHCTL1_Output_CH2COMCEN   %1 7 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH2COMCEN    Channel 2 output compare clear enable
: TIMER4_CHCTL1_Output_CH2COMCTL   ( %XXX -- ) 4 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH2COMCTL    Channel 2 compare output control
: TIMER4_CHCTL1_Output_CH2COMSEN   %1 3 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH2COMSEN    Channel 2 compare output shadow enable
: TIMER4_CHCTL1_Output_CH2COMFEN   %1 2 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH2COMFEN    Channel 2 output compare fast enable
: TIMER4_CHCTL1_Output_CH2MS   ( %XX -- ) 0 lshift TIMER4_CHCTL1_Output bis! ;  \ TIMER4_CHCTL1_Output_CH2MS    Channel 2 I/O mode selection

\ TIMER4_CHCTL1_Input (read-write)
: TIMER4_CHCTL1_Input_CH3CAPFLT   ( %XXXX -- ) 12 lshift TIMER4_CHCTL1_Input bis! ;  \ TIMER4_CHCTL1_Input_CH3CAPFLT    Channel 3 input capture filter control
: TIMER4_CHCTL1_Input_CH3CAPPSC   ( %XX -- ) 10 lshift TIMER4_CHCTL1_Input bis! ;  \ TIMER4_CHCTL1_Input_CH3CAPPSC    Channel 3 input capture prescaler
: TIMER4_CHCTL1_Input_CH3MS   ( %XX -- ) 8 lshift TIMER4_CHCTL1_Input bis! ;  \ TIMER4_CHCTL1_Input_CH3MS    Channel 3 mode selection
: TIMER4_CHCTL1_Input_CH2CAPFLT   ( %XXXX -- ) 4 lshift TIMER4_CHCTL1_Input bis! ;  \ TIMER4_CHCTL1_Input_CH2CAPFLT    Channel 2 input capture filter control
: TIMER4_CHCTL1_Input_CH2CAPPSC   ( %XX -- ) 2 lshift TIMER4_CHCTL1_Input bis! ;  \ TIMER4_CHCTL1_Input_CH2CAPPSC    Channel 2 input capture prescaler
: TIMER4_CHCTL1_Input_CH2MS   ( %XX -- ) 0 lshift TIMER4_CHCTL1_Input bis! ;  \ TIMER4_CHCTL1_Input_CH2MS    Channel 2 mode selection

\ TIMER4_CHCTL2 (read-write)
: TIMER4_CHCTL2_CH3P   %1 13 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH3P    Channel 3 capture/compare function polarity
: TIMER4_CHCTL2_CH3EN   %1 12 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH3EN    Channel 3 capture/compare function enable
: TIMER4_CHCTL2_CH2P   %1 9 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH2P    Channel 2 capture/compare function polarity
: TIMER4_CHCTL2_CH2EN   %1 8 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH2EN    Channel 2 capture/compare function enable
: TIMER4_CHCTL2_CH1P   %1 5 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH1P    Channel 1 capture/compare function polarity
: TIMER4_CHCTL2_CH1EN   %1 4 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH1EN    Channel 1 capture/compare function enable
: TIMER4_CHCTL2_CH0P   %1 1 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH0P    Channel 0 capture/compare function polarity
: TIMER4_CHCTL2_CH0EN   %1 0 lshift TIMER4_CHCTL2 bis! ;  \ TIMER4_CHCTL2_CH0EN    Channel 0 capture/compare function enable

\ TIMER4_CNT (read-write)
: TIMER4_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_CNT bis! ;  \ TIMER4_CNT_CNT    counter value

\ TIMER4_PSC (read-write)
: TIMER4_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_PSC bis! ;  \ TIMER4_PSC_PSC    Prescaler value of the counter clock

\ TIMER4_CAR (read-write)
: TIMER4_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_CAR bis! ;  \ TIMER4_CAR_CARL    Counter auto reload value

\ TIMER4_CH0CV (read-write)
: TIMER4_CH0CV_CH0VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_CH0CV bis! ;  \ TIMER4_CH0CV_CH0VAL    Capture or compare value of channel 0

\ TIMER4_CH1CV (read-write)
: TIMER4_CH1CV_CH1VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_CH1CV bis! ;  \ TIMER4_CH1CV_CH1VAL    Capture or compare value of channel1

\ TIMER4_CH2CV (read-write)
: TIMER4_CH2CV_CH2VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_CH2CV bis! ;  \ TIMER4_CH2CV_CH2VAL    Capture or compare value of channel 2

\ TIMER4_CH3CV (read-write)
: TIMER4_CH3CV_CH3VAL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_CH3CV bis! ;  \ TIMER4_CH3CV_CH3VAL    Capture or compare value of channel 3

\ TIMER4_DMACFG (read-write)
: TIMER4_DMACFG_DMATC   ( %XXXXX -- ) 8 lshift TIMER4_DMACFG bis! ;  \ TIMER4_DMACFG_DMATC    DMA transfer count
: TIMER4_DMACFG_DMATA   ( %XXXXX -- ) 0 lshift TIMER4_DMACFG bis! ;  \ TIMER4_DMACFG_DMATA    DMA transfer access start address

\ TIMER4_DMATB (read-write)
: TIMER4_DMATB_DMATB   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER4_DMATB bis! ;  \ TIMER4_DMATB_DMATB    DMA transfer buffer

\ TIMER5_CTL0 (read-write)
: TIMER5_CTL0_ARSE   %1 7 lshift TIMER5_CTL0 bis! ;  \ TIMER5_CTL0_ARSE    Auto-reload shadow enable
: TIMER5_CTL0_SPM   %1 3 lshift TIMER5_CTL0 bis! ;  \ TIMER5_CTL0_SPM    Single pulse mode
: TIMER5_CTL0_UPS   %1 2 lshift TIMER5_CTL0 bis! ;  \ TIMER5_CTL0_UPS    Update source
: TIMER5_CTL0_UPDIS   %1 1 lshift TIMER5_CTL0 bis! ;  \ TIMER5_CTL0_UPDIS    Update disable
: TIMER5_CTL0_CEN   %1 0 lshift TIMER5_CTL0 bis! ;  \ TIMER5_CTL0_CEN    Counter enable

\ TIMER5_CTL1 (read-write)
: TIMER5_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER5_CTL1 bis! ;  \ TIMER5_CTL1_MMC    Master mode control

\ TIMER5_DMAINTEN (read-write)
: TIMER5_DMAINTEN_UPDEN   %1 8 lshift TIMER5_DMAINTEN bis! ;  \ TIMER5_DMAINTEN_UPDEN    Update DMA request enable
: TIMER5_DMAINTEN_UPIE   %1 0 lshift TIMER5_DMAINTEN bis! ;  \ TIMER5_DMAINTEN_UPIE    Update interrupt enable

\ TIMER5_INTF (read-write)
: TIMER5_INTF_UPIF   %1 0 lshift TIMER5_INTF bis! ;  \ TIMER5_INTF_UPIF    Update interrupt flag

\ TIMER5_SWEVG (write-only)
: TIMER5_SWEVG_UPG   %1 0 lshift TIMER5_SWEVG bis! ;  \ TIMER5_SWEVG_UPG    Update generation

\ TIMER5_CNT (read-write)
: TIMER5_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER5_CNT bis! ;  \ TIMER5_CNT_CNT    Low counter value

\ TIMER5_PSC (read-write)
: TIMER5_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER5_PSC bis! ;  \ TIMER5_PSC_PSC    Prescaler value of the counter clock

\ TIMER5_CAR (read-write)
: TIMER5_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER5_CAR bis! ;  \ TIMER5_CAR_CARL    Counter auto reload value

\ TIMER6_CTL0 (read-write)
: TIMER6_CTL0_ARSE   %1 7 lshift TIMER6_CTL0 bis! ;  \ TIMER6_CTL0_ARSE    Auto-reload shadow enable
: TIMER6_CTL0_SPM   %1 3 lshift TIMER6_CTL0 bis! ;  \ TIMER6_CTL0_SPM    Single pulse mode
: TIMER6_CTL0_UPS   %1 2 lshift TIMER6_CTL0 bis! ;  \ TIMER6_CTL0_UPS    Update source
: TIMER6_CTL0_UPDIS   %1 1 lshift TIMER6_CTL0 bis! ;  \ TIMER6_CTL0_UPDIS    Update disable
: TIMER6_CTL0_CEN   %1 0 lshift TIMER6_CTL0 bis! ;  \ TIMER6_CTL0_CEN    Counter enable

\ TIMER6_CTL1 (read-write)
: TIMER6_CTL1_MMC   ( %XXX -- ) 4 lshift TIMER6_CTL1 bis! ;  \ TIMER6_CTL1_MMC    Master mode control

\ TIMER6_DMAINTEN (read-write)
: TIMER6_DMAINTEN_UPDEN   %1 8 lshift TIMER6_DMAINTEN bis! ;  \ TIMER6_DMAINTEN_UPDEN    Update DMA request enable
: TIMER6_DMAINTEN_UPIE   %1 0 lshift TIMER6_DMAINTEN bis! ;  \ TIMER6_DMAINTEN_UPIE    Update interrupt enable

\ TIMER6_INTF (read-write)
: TIMER6_INTF_UPIF   %1 0 lshift TIMER6_INTF bis! ;  \ TIMER6_INTF_UPIF    Update interrupt flag

\ TIMER6_SWEVG (write-only)
: TIMER6_SWEVG_UPG   %1 0 lshift TIMER6_SWEVG bis! ;  \ TIMER6_SWEVG_UPG    Update generation

\ TIMER6_CNT (read-write)
: TIMER6_CNT_CNT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER6_CNT bis! ;  \ TIMER6_CNT_CNT    Low counter value

\ TIMER6_PSC (read-write)
: TIMER6_PSC_PSC   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER6_PSC bis! ;  \ TIMER6_PSC_PSC    Prescaler value of the counter clock

\ TIMER6_CAR (read-write)
: TIMER6_CAR_CARL   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift TIMER6_CAR bis! ;  \ TIMER6_CAR_CARL    Counter auto reload value

\ USART0_STAT ()
: USART0_STAT_CTSF   %1 9 lshift USART0_STAT bis! ;  \ USART0_STAT_CTSF    CTS change flag
: USART0_STAT_LBDF   %1 8 lshift USART0_STAT bis! ;  \ USART0_STAT_LBDF    LIN break detection flag
: USART0_STAT_TBE   %1 7 lshift USART0_STAT bis! ;  \ USART0_STAT_TBE    Transmit data buffer empty
: USART0_STAT_TC   %1 6 lshift USART0_STAT bis! ;  \ USART0_STAT_TC    Transmission complete
: USART0_STAT_RBNE   %1 5 lshift USART0_STAT bis! ;  \ USART0_STAT_RBNE    Read data buffer not empty
: USART0_STAT_IDLEF   %1 4 lshift USART0_STAT bis! ;  \ USART0_STAT_IDLEF    IDLE frame detected flag
: USART0_STAT_ORERR   %1 3 lshift USART0_STAT bis! ;  \ USART0_STAT_ORERR    Overrun error
: USART0_STAT_NERR   %1 2 lshift USART0_STAT bis! ;  \ USART0_STAT_NERR    Noise error flag
: USART0_STAT_FERR   %1 1 lshift USART0_STAT bis! ;  \ USART0_STAT_FERR    Frame error flag
: USART0_STAT_PERR   %1 0 lshift USART0_STAT bis! ;  \ USART0_STAT_PERR    Parity error flag

\ USART0_DATA (read-write)
: USART0_DATA_DATA   ( %XXXXXXXXX -- ) 0 lshift USART0_DATA bis! ;  \ USART0_DATA_DATA    Transmit or read data value

\ USART0_BAUD (read-write)
: USART0_BAUD_INTDIV   ( %XXXXXXXXXXX -- ) 4 lshift USART0_BAUD bis! ;  \ USART0_BAUD_INTDIV    Integer part of baud-rate divider
: USART0_BAUD_FRADIV   ( %XXXX -- ) 0 lshift USART0_BAUD bis! ;  \ USART0_BAUD_FRADIV    Fraction part of baud-rate divider

\ USART0_CTL0 (read-write)
: USART0_CTL0_UEN   %1 13 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_UEN    USART enable
: USART0_CTL0_WL   %1 12 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_WL    Word length
: USART0_CTL0_WM   %1 11 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_WM    Wakeup method in mute mode
: USART0_CTL0_PCEN   %1 10 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_PCEN    Parity check function enable
: USART0_CTL0_PM   %1 9 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_PM    Parity mode
: USART0_CTL0_PERRIE   %1 8 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_PERRIE    Parity error interrupt enable
: USART0_CTL0_TBEIE   %1 7 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_TBEIE    Transmitter buffer empty interrupt enable
: USART0_CTL0_TCIE   %1 6 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_TCIE    Transmission complete interrupt enable
: USART0_CTL0_RBNEIE   %1 5 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_RBNEIE    Read data buffer not empty interrupt and overrun error interrupt enable
: USART0_CTL0_IDLEIE   %1 4 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_IDLEIE    IDLE line detected interrupt enable
: USART0_CTL0_TEN   %1 3 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_TEN    Transmitter enable
: USART0_CTL0_REN   %1 2 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_REN    Receiver enable
: USART0_CTL0_RWU   %1 1 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_RWU    Receiver wakeup from mute mode
: USART0_CTL0_SBKCMD   %1 0 lshift USART0_CTL0 bis! ;  \ USART0_CTL0_SBKCMD    Send break command

\ USART0_CTL1 (read-write)
: USART0_CTL1_LMEN   %1 14 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_LMEN    LIN mode enable
: USART0_CTL1_STB   ( %XX -- ) 12 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_STB    STOP bits length
: USART0_CTL1_CKEN   %1 11 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_CKEN    CK pin enable
: USART0_CTL1_CPL   %1 10 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_CPL    Clock polarity
: USART0_CTL1_CPH   %1 9 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_CPH    Clock phase
: USART0_CTL1_CLEN   %1 8 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_CLEN    CK Length
: USART0_CTL1_LBDIE   %1 6 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_LBDIE    LIN break detection interrupt  enable
: USART0_CTL1_LBLEN   %1 5 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_LBLEN    LIN break frame length
: USART0_CTL1_ADDR   ( %XXXX -- ) 0 lshift USART0_CTL1 bis! ;  \ USART0_CTL1_ADDR    Address of the USART

\ USART0_CTL2 (read-write)
: USART0_CTL2_CTSIE   %1 10 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_CTSIE    CTS interrupt enable
: USART0_CTL2_CTSEN   %1 9 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_CTSEN    CTS enable
: USART0_CTL2_RTSEN   %1 8 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_RTSEN    RTS enable
: USART0_CTL2_DENT   %1 7 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_DENT    DMA request enable for transmission
: USART0_CTL2_DENR   %1 6 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_DENR    DMA request enable for reception
: USART0_CTL2_SCEN   %1 5 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_SCEN    Smartcard mode enable
: USART0_CTL2_NKEN   %1 4 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_NKEN    Smartcard NACK enable
: USART0_CTL2_HDEN   %1 3 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_HDEN    Half-duplex selection
: USART0_CTL2_IRLP   %1 2 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_IRLP    IrDA low-power
: USART0_CTL2_IREN   %1 1 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_IREN    IrDA mode enable
: USART0_CTL2_ERRIE   %1 0 lshift USART0_CTL2 bis! ;  \ USART0_CTL2_ERRIE    Error interrupt enable

\ USART0_GP (read-write)
: USART0_GP_GUAT   ( %XXXXXXXX -- ) 8 lshift USART0_GP bis! ;  \ USART0_GP_GUAT    Guard time value in Smartcard mode
: USART0_GP_PSC   ( %XXXXXXXX -- ) 0 lshift USART0_GP bis! ;  \ USART0_GP_PSC    Prescaler value

\ USART1_STAT ()
: USART1_STAT_CTSF   %1 9 lshift USART1_STAT bis! ;  \ USART1_STAT_CTSF    CTS change flag
: USART1_STAT_LBDF   %1 8 lshift USART1_STAT bis! ;  \ USART1_STAT_LBDF    LIN break detection flag
: USART1_STAT_TBE   %1 7 lshift USART1_STAT bis! ;  \ USART1_STAT_TBE    Transmit data buffer empty
: USART1_STAT_TC   %1 6 lshift USART1_STAT bis! ;  \ USART1_STAT_TC    Transmission complete
: USART1_STAT_RBNE   %1 5 lshift USART1_STAT bis! ;  \ USART1_STAT_RBNE    Read data buffer not empty
: USART1_STAT_IDLEF   %1 4 lshift USART1_STAT bis! ;  \ USART1_STAT_IDLEF    IDLE frame detected flag
: USART1_STAT_ORERR   %1 3 lshift USART1_STAT bis! ;  \ USART1_STAT_ORERR    Overrun error
: USART1_STAT_NERR   %1 2 lshift USART1_STAT bis! ;  \ USART1_STAT_NERR    Noise error flag
: USART1_STAT_FERR   %1 1 lshift USART1_STAT bis! ;  \ USART1_STAT_FERR    Frame error flag
: USART1_STAT_PERR   %1 0 lshift USART1_STAT bis! ;  \ USART1_STAT_PERR    Parity error flag

\ USART1_DATA (read-write)
: USART1_DATA_DATA   ( %XXXXXXXXX -- ) 0 lshift USART1_DATA bis! ;  \ USART1_DATA_DATA    Transmit or read data value

\ USART1_BAUD (read-write)
: USART1_BAUD_INTDIV   ( %XXXXXXXXXXX -- ) 4 lshift USART1_BAUD bis! ;  \ USART1_BAUD_INTDIV    Integer part of baud-rate divider
: USART1_BAUD_FRADIV   ( %XXXX -- ) 0 lshift USART1_BAUD bis! ;  \ USART1_BAUD_FRADIV    Fraction part of baud-rate divider

\ USART1_CTL0 (read-write)
: USART1_CTL0_UEN   %1 13 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_UEN    USART enable
: USART1_CTL0_WL   %1 12 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_WL    Word length
: USART1_CTL0_WM   %1 11 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_WM    Wakeup method in mute mode
: USART1_CTL0_PCEN   %1 10 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_PCEN    Parity check function enable
: USART1_CTL0_PM   %1 9 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_PM    Parity mode
: USART1_CTL0_PERRIE   %1 8 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_PERRIE    Parity error interrupt enable
: USART1_CTL0_TBEIE   %1 7 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_TBEIE    Transmitter buffer empty interrupt enable
: USART1_CTL0_TCIE   %1 6 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_TCIE    Transmission complete interrupt enable
: USART1_CTL0_RBNEIE   %1 5 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_RBNEIE    Read data buffer not empty interrupt and overrun error interrupt enable
: USART1_CTL0_IDLEIE   %1 4 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_IDLEIE    IDLE line detected interrupt enable
: USART1_CTL0_TEN   %1 3 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_TEN    Transmitter enable
: USART1_CTL0_REN   %1 2 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_REN    Receiver enable
: USART1_CTL0_RWU   %1 1 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_RWU    Receiver wakeup from mute mode
: USART1_CTL0_SBKCMD   %1 0 lshift USART1_CTL0 bis! ;  \ USART1_CTL0_SBKCMD    Send break command

\ USART1_CTL1 (read-write)
: USART1_CTL1_LMEN   %1 14 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_LMEN    LIN mode enable
: USART1_CTL1_STB   ( %XX -- ) 12 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_STB    STOP bits length
: USART1_CTL1_CKEN   %1 11 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_CKEN    CK pin enable
: USART1_CTL1_CPL   %1 10 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_CPL    Clock polarity
: USART1_CTL1_CPH   %1 9 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_CPH    Clock phase
: USART1_CTL1_CLEN   %1 8 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_CLEN    CK Length
: USART1_CTL1_LBDIE   %1 6 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_LBDIE    LIN break detection interrupt  enable
: USART1_CTL1_LBLEN   %1 5 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_LBLEN    LIN break frame length
: USART1_CTL1_ADDR   ( %XXXX -- ) 0 lshift USART1_CTL1 bis! ;  \ USART1_CTL1_ADDR    Address of the USART

\ USART1_CTL2 (read-write)
: USART1_CTL2_CTSIE   %1 10 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_CTSIE    CTS interrupt enable
: USART1_CTL2_CTSEN   %1 9 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_CTSEN    CTS enable
: USART1_CTL2_RTSEN   %1 8 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_RTSEN    RTS enable
: USART1_CTL2_DENT   %1 7 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_DENT    DMA request enable for transmission
: USART1_CTL2_DENR   %1 6 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_DENR    DMA request enable for reception
: USART1_CTL2_SCEN   %1 5 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_SCEN    Smartcard mode enable
: USART1_CTL2_NKEN   %1 4 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_NKEN    Smartcard NACK enable
: USART1_CTL2_HDEN   %1 3 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_HDEN    Half-duplex selection
: USART1_CTL2_IRLP   %1 2 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_IRLP    IrDA low-power
: USART1_CTL2_IREN   %1 1 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_IREN    IrDA mode enable
: USART1_CTL2_ERRIE   %1 0 lshift USART1_CTL2 bis! ;  \ USART1_CTL2_ERRIE    Error interrupt enable

\ USART1_GP (read-write)
: USART1_GP_GUAT   ( %XXXXXXXX -- ) 8 lshift USART1_GP bis! ;  \ USART1_GP_GUAT    Guard time value in Smartcard mode
: USART1_GP_PSC   ( %XXXXXXXX -- ) 0 lshift USART1_GP bis! ;  \ USART1_GP_PSC    Prescaler value

\ USART2_STAT ()
: USART2_STAT_CTSF   %1 9 lshift USART2_STAT bis! ;  \ USART2_STAT_CTSF    CTS change flag
: USART2_STAT_LBDF   %1 8 lshift USART2_STAT bis! ;  \ USART2_STAT_LBDF    LIN break detection flag
: USART2_STAT_TBE   %1 7 lshift USART2_STAT bis! ;  \ USART2_STAT_TBE    Transmit data buffer empty
: USART2_STAT_TC   %1 6 lshift USART2_STAT bis! ;  \ USART2_STAT_TC    Transmission complete
: USART2_STAT_RBNE   %1 5 lshift USART2_STAT bis! ;  \ USART2_STAT_RBNE    Read data buffer not empty
: USART2_STAT_IDLEF   %1 4 lshift USART2_STAT bis! ;  \ USART2_STAT_IDLEF    IDLE frame detected flag
: USART2_STAT_ORERR   %1 3 lshift USART2_STAT bis! ;  \ USART2_STAT_ORERR    Overrun error
: USART2_STAT_NERR   %1 2 lshift USART2_STAT bis! ;  \ USART2_STAT_NERR    Noise error flag
: USART2_STAT_FERR   %1 1 lshift USART2_STAT bis! ;  \ USART2_STAT_FERR    Frame error flag
: USART2_STAT_PERR   %1 0 lshift USART2_STAT bis! ;  \ USART2_STAT_PERR    Parity error flag

\ USART2_DATA (read-write)
: USART2_DATA_DATA   ( %XXXXXXXXX -- ) 0 lshift USART2_DATA bis! ;  \ USART2_DATA_DATA    Transmit or read data value

\ USART2_BAUD (read-write)
: USART2_BAUD_INTDIV   ( %XXXXXXXXXXX -- ) 4 lshift USART2_BAUD bis! ;  \ USART2_BAUD_INTDIV    Integer part of baud-rate divider
: USART2_BAUD_FRADIV   ( %XXXX -- ) 0 lshift USART2_BAUD bis! ;  \ USART2_BAUD_FRADIV    Fraction part of baud-rate divider

\ USART2_CTL0 (read-write)
: USART2_CTL0_UEN   %1 13 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_UEN    USART enable
: USART2_CTL0_WL   %1 12 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_WL    Word length
: USART2_CTL0_WM   %1 11 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_WM    Wakeup method in mute mode
: USART2_CTL0_PCEN   %1 10 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_PCEN    Parity check function enable
: USART2_CTL0_PM   %1 9 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_PM    Parity mode
: USART2_CTL0_PERRIE   %1 8 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_PERRIE    Parity error interrupt enable
: USART2_CTL0_TBEIE   %1 7 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_TBEIE    Transmitter buffer empty interrupt enable
: USART2_CTL0_TCIE   %1 6 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_TCIE    Transmission complete interrupt enable
: USART2_CTL0_RBNEIE   %1 5 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_RBNEIE    Read data buffer not empty interrupt and overrun error interrupt enable
: USART2_CTL0_IDLEIE   %1 4 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_IDLEIE    IDLE line detected interrupt enable
: USART2_CTL0_TEN   %1 3 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_TEN    Transmitter enable
: USART2_CTL0_REN   %1 2 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_REN    Receiver enable
: USART2_CTL0_RWU   %1 1 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_RWU    Receiver wakeup from mute mode
: USART2_CTL0_SBKCMD   %1 0 lshift USART2_CTL0 bis! ;  \ USART2_CTL0_SBKCMD    Send break command

\ USART2_CTL1 (read-write)
: USART2_CTL1_LMEN   %1 14 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_LMEN    LIN mode enable
: USART2_CTL1_STB   ( %XX -- ) 12 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_STB    STOP bits length
: USART2_CTL1_CKEN   %1 11 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_CKEN    CK pin enable
: USART2_CTL1_CPL   %1 10 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_CPL    Clock polarity
: USART2_CTL1_CPH   %1 9 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_CPH    Clock phase
: USART2_CTL1_CLEN   %1 8 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_CLEN    CK Length
: USART2_CTL1_LBDIE   %1 6 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_LBDIE    LIN break detection interrupt  enable
: USART2_CTL1_LBLEN   %1 5 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_LBLEN    LIN break frame length
: USART2_CTL1_ADDR   ( %XXXX -- ) 0 lshift USART2_CTL1 bis! ;  \ USART2_CTL1_ADDR    Address of the USART

\ USART2_CTL2 (read-write)
: USART2_CTL2_CTSIE   %1 10 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_CTSIE    CTS interrupt enable
: USART2_CTL2_CTSEN   %1 9 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_CTSEN    CTS enable
: USART2_CTL2_RTSEN   %1 8 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_RTSEN    RTS enable
: USART2_CTL2_DENT   %1 7 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_DENT    DMA request enable for transmission
: USART2_CTL2_DENR   %1 6 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_DENR    DMA request enable for reception
: USART2_CTL2_SCEN   %1 5 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_SCEN    Smartcard mode enable
: USART2_CTL2_NKEN   %1 4 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_NKEN    Smartcard NACK enable
: USART2_CTL2_HDEN   %1 3 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_HDEN    Half-duplex selection
: USART2_CTL2_IRLP   %1 2 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_IRLP    IrDA low-power
: USART2_CTL2_IREN   %1 1 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_IREN    IrDA mode enable
: USART2_CTL2_ERRIE   %1 0 lshift USART2_CTL2 bis! ;  \ USART2_CTL2_ERRIE    Error interrupt enable

\ USART2_GP (read-write)
: USART2_GP_GUAT   ( %XXXXXXXX -- ) 8 lshift USART2_GP bis! ;  \ USART2_GP_GUAT    Guard time value in Smartcard mode
: USART2_GP_PSC   ( %XXXXXXXX -- ) 0 lshift USART2_GP bis! ;  \ USART2_GP_PSC    Prescaler value

\ UART3_STAT ()
: UART3_STAT_LBDF   %1 8 lshift UART3_STAT bis! ;  \ UART3_STAT_LBDF    LIN break detection flag
: UART3_STAT_TBE   %1 7 lshift UART3_STAT bis! ;  \ UART3_STAT_TBE    Transmit data buffer empty
: UART3_STAT_TC   %1 6 lshift UART3_STAT bis! ;  \ UART3_STAT_TC    Transmission complete
: UART3_STAT_RBNE   %1 5 lshift UART3_STAT bis! ;  \ UART3_STAT_RBNE    Read data buffer not empty
: UART3_STAT_IDLEF   %1 4 lshift UART3_STAT bis! ;  \ UART3_STAT_IDLEF    IDLE frame detected flag
: UART3_STAT_ORERR   %1 3 lshift UART3_STAT bis! ;  \ UART3_STAT_ORERR    Overrun error
: UART3_STAT_NERR   %1 2 lshift UART3_STAT bis! ;  \ UART3_STAT_NERR    Noise error flag
: UART3_STAT_FERR   %1 1 lshift UART3_STAT bis! ;  \ UART3_STAT_FERR    Frame error flag
: UART3_STAT_PERR   %1 0 lshift UART3_STAT bis! ;  \ UART3_STAT_PERR    Parity error flag

\ UART3_DATA (read-write)
: UART3_DATA_DATA   ( %XXXXXXXXX -- ) 0 lshift UART3_DATA bis! ;  \ UART3_DATA_DATA    Transmit or read data value

\ UART3_BAUD (read-write)
: UART3_BAUD_INTDIV   ( %XXXXXXXXXXX -- ) 4 lshift UART3_BAUD bis! ;  \ UART3_BAUD_INTDIV    Integer part of baud-rate divider
: UART3_BAUD_FRADIV   ( %XXXX -- ) 0 lshift UART3_BAUD bis! ;  \ UART3_BAUD_FRADIV    Fraction part of baud-rate divider

\ UART3_CTL0 (read-write)
: UART3_CTL0_UEN   %1 13 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_UEN    USART enable
: UART3_CTL0_WL   %1 12 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_WL    Word length
: UART3_CTL0_WM   %1 11 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_WM    Wakeup method in mute mode
: UART3_CTL0_PCEN   %1 10 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_PCEN    Parity check function enable
: UART3_CTL0_PM   %1 9 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_PM    Parity mode
: UART3_CTL0_PERRIE   %1 8 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_PERRIE    Parity error interrupt enable
: UART3_CTL0_TBEIE   %1 7 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_TBEIE    Transmitter buffer empty interrupt enable
: UART3_CTL0_TCIE   %1 6 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_TCIE    Transmission complete interrupt enable
: UART3_CTL0_RBNEIE   %1 5 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_RBNEIE    Read data buffer not empty interrupt and overrun error interrupt enable
: UART3_CTL0_IDLEIE   %1 4 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_IDLEIE    IDLE line detected interrupt enable
: UART3_CTL0_TEN   %1 3 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_TEN    Transmitter enable
: UART3_CTL0_REN   %1 2 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_REN    Receiver enable
: UART3_CTL0_RWU   %1 1 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_RWU    Receiver wakeup from mute mode
: UART3_CTL0_SBKCMD   %1 0 lshift UART3_CTL0 bis! ;  \ UART3_CTL0_SBKCMD    Send break command

\ UART3_CTL1 (read-write)
: UART3_CTL1_LMEN   %1 14 lshift UART3_CTL1 bis! ;  \ UART3_CTL1_LMEN    LIN mode enable
: UART3_CTL1_STB   ( %XX -- ) 12 lshift UART3_CTL1 bis! ;  \ UART3_CTL1_STB    STOP bits length
: UART3_CTL1_LBDIE   %1 6 lshift UART3_CTL1 bis! ;  \ UART3_CTL1_LBDIE    LIN break detection interrupt  enable
: UART3_CTL1_LBLEN   %1 5 lshift UART3_CTL1 bis! ;  \ UART3_CTL1_LBLEN    LIN break frame length
: UART3_CTL1_ADDR   ( %XXXX -- ) 0 lshift UART3_CTL1 bis! ;  \ UART3_CTL1_ADDR    Address of the USART

\ UART3_CTL2 (read-write)
: UART3_CTL2_DENT   %1 7 lshift UART3_CTL2 bis! ;  \ UART3_CTL2_DENT    DMA request enable for transmission
: UART3_CTL2_DENR   %1 6 lshift UART3_CTL2 bis! ;  \ UART3_CTL2_DENR    DMA request enable for reception
: UART3_CTL2_HDEN   %1 3 lshift UART3_CTL2 bis! ;  \ UART3_CTL2_HDEN    Half-duplex selection
: UART3_CTL2_IRLP   %1 2 lshift UART3_CTL2 bis! ;  \ UART3_CTL2_IRLP    IrDA low-power
: UART3_CTL2_IREN   %1 1 lshift UART3_CTL2 bis! ;  \ UART3_CTL2_IREN    IrDA mode enable
: UART3_CTL2_ERRIE   %1 0 lshift UART3_CTL2 bis! ;  \ UART3_CTL2_ERRIE    Error interrupt enable

\ UART3_GP (read-write)
: UART3_GP_PSC   ( %XXXXXXXX -- ) 0 lshift UART3_GP bis! ;  \ UART3_GP_PSC    Prescaler value

\ UART4_STAT ()
: UART4_STAT_LBDF   %1 8 lshift UART4_STAT bis! ;  \ UART4_STAT_LBDF    LIN break detection flag
: UART4_STAT_TBE   %1 7 lshift UART4_STAT bis! ;  \ UART4_STAT_TBE    Transmit data buffer empty
: UART4_STAT_TC   %1 6 lshift UART4_STAT bis! ;  \ UART4_STAT_TC    Transmission complete
: UART4_STAT_RBNE   %1 5 lshift UART4_STAT bis! ;  \ UART4_STAT_RBNE    Read data buffer not empty
: UART4_STAT_IDLEF   %1 4 lshift UART4_STAT bis! ;  \ UART4_STAT_IDLEF    IDLE frame detected flag
: UART4_STAT_ORERR   %1 3 lshift UART4_STAT bis! ;  \ UART4_STAT_ORERR    Overrun error
: UART4_STAT_NERR   %1 2 lshift UART4_STAT bis! ;  \ UART4_STAT_NERR    Noise error flag
: UART4_STAT_FERR   %1 1 lshift UART4_STAT bis! ;  \ UART4_STAT_FERR    Frame error flag
: UART4_STAT_PERR   %1 0 lshift UART4_STAT bis! ;  \ UART4_STAT_PERR    Parity error flag

\ UART4_DATA (read-write)
: UART4_DATA_DATA   ( %XXXXXXXXX -- ) 0 lshift UART4_DATA bis! ;  \ UART4_DATA_DATA    Transmit or read data value

\ UART4_BAUD (read-write)
: UART4_BAUD_INTDIV   ( %XXXXXXXXXXX -- ) 4 lshift UART4_BAUD bis! ;  \ UART4_BAUD_INTDIV    Integer part of baud-rate divider
: UART4_BAUD_FRADIV   ( %XXXX -- ) 0 lshift UART4_BAUD bis! ;  \ UART4_BAUD_FRADIV    Fraction part of baud-rate divider

\ UART4_CTL0 (read-write)
: UART4_CTL0_UEN   %1 13 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_UEN    USART enable
: UART4_CTL0_WL   %1 12 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_WL    Word length
: UART4_CTL0_WM   %1 11 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_WM    Wakeup method in mute mode
: UART4_CTL0_PCEN   %1 10 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_PCEN    Parity check function enable
: UART4_CTL0_PM   %1 9 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_PM    Parity mode
: UART4_CTL0_PERRIE   %1 8 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_PERRIE    Parity error interrupt enable
: UART4_CTL0_TBEIE   %1 7 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_TBEIE    Transmitter buffer empty interrupt enable
: UART4_CTL0_TCIE   %1 6 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_TCIE    Transmission complete interrupt enable
: UART4_CTL0_RBNEIE   %1 5 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_RBNEIE    Read data buffer not empty interrupt and overrun error interrupt enable
: UART4_CTL0_IDLEIE   %1 4 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_IDLEIE    IDLE line detected interrupt enable
: UART4_CTL0_TEN   %1 3 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_TEN    Transmitter enable
: UART4_CTL0_REN   %1 2 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_REN    Receiver enable
: UART4_CTL0_RWU   %1 1 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_RWU    Receiver wakeup from mute mode
: UART4_CTL0_SBKCMD   %1 0 lshift UART4_CTL0 bis! ;  \ UART4_CTL0_SBKCMD    Send break command

\ UART4_CTL1 (read-write)
: UART4_CTL1_LMEN   %1 14 lshift UART4_CTL1 bis! ;  \ UART4_CTL1_LMEN    LIN mode enable
: UART4_CTL1_STB   ( %XX -- ) 12 lshift UART4_CTL1 bis! ;  \ UART4_CTL1_STB    STOP bits length
: UART4_CTL1_LBDIE   %1 6 lshift UART4_CTL1 bis! ;  \ UART4_CTL1_LBDIE    LIN break detection interrupt  enable
: UART4_CTL1_LBLEN   %1 5 lshift UART4_CTL1 bis! ;  \ UART4_CTL1_LBLEN    LIN break frame length
: UART4_CTL1_ADDR   ( %XXXX -- ) 0 lshift UART4_CTL1 bis! ;  \ UART4_CTL1_ADDR    Address of the USART

\ UART4_CTL2 (read-write)
: UART4_CTL2_DENT   %1 7 lshift UART4_CTL2 bis! ;  \ UART4_CTL2_DENT    DMA request enable for transmission
: UART4_CTL2_DENR   %1 6 lshift UART4_CTL2 bis! ;  \ UART4_CTL2_DENR    DMA request enable for reception
: UART4_CTL2_HDEN   %1 3 lshift UART4_CTL2 bis! ;  \ UART4_CTL2_HDEN    Half-duplex selection
: UART4_CTL2_IRLP   %1 2 lshift UART4_CTL2 bis! ;  \ UART4_CTL2_IRLP    IrDA low-power
: UART4_CTL2_IREN   %1 1 lshift UART4_CTL2 bis! ;  \ UART4_CTL2_IREN    IrDA mode enable
: UART4_CTL2_ERRIE   %1 0 lshift UART4_CTL2 bis! ;  \ UART4_CTL2_ERRIE    Error interrupt enable

\ UART4_GP (read-write)
: UART4_GP_PSC   ( %XXXXXXXX -- ) 0 lshift UART4_GP bis! ;  \ UART4_GP_PSC    Prescaler value

\ USBFS_GLOBAL_GOTGCS ()
: USBFS_GLOBAL_GOTGCS_SRPS   %1 0 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_SRPS    SRP success
: USBFS_GLOBAL_GOTGCS_SRPREQ   %1 1 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_SRPREQ    SRP request
: USBFS_GLOBAL_GOTGCS_HNPS   %1 8 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_HNPS    Host success
: USBFS_GLOBAL_GOTGCS_HNPREQ   %1 9 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_HNPREQ    HNP request
: USBFS_GLOBAL_GOTGCS_HHNPEN   %1 10 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_HHNPEN    Host HNP enable
: USBFS_GLOBAL_GOTGCS_DHNPEN   %1 11 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_DHNPEN    Device HNP enabled
: USBFS_GLOBAL_GOTGCS_IDPS   %1 16 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_IDPS    ID pin status
: USBFS_GLOBAL_GOTGCS_DI   %1 17 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_DI    Debounce interval
: USBFS_GLOBAL_GOTGCS_ASV   %1 18 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_ASV    A-session valid
: USBFS_GLOBAL_GOTGCS_BSV   %1 19 lshift USBFS_GLOBAL_GOTGCS bis! ;  \ USBFS_GLOBAL_GOTGCS_BSV    B-session valid

\ USBFS_GLOBAL_GOTGINTF (read-write)
: USBFS_GLOBAL_GOTGINTF_SESEND   %1 2 lshift USBFS_GLOBAL_GOTGINTF bis! ;  \ USBFS_GLOBAL_GOTGINTF_SESEND    Session end 
: USBFS_GLOBAL_GOTGINTF_SRPEND   %1 8 lshift USBFS_GLOBAL_GOTGINTF bis! ;  \ USBFS_GLOBAL_GOTGINTF_SRPEND    Session request success status  change
: USBFS_GLOBAL_GOTGINTF_HNPEND   %1 9 lshift USBFS_GLOBAL_GOTGINTF bis! ;  \ USBFS_GLOBAL_GOTGINTF_HNPEND    HNP end
: USBFS_GLOBAL_GOTGINTF_HNPDET   %1 17 lshift USBFS_GLOBAL_GOTGINTF bis! ;  \ USBFS_GLOBAL_GOTGINTF_HNPDET    Host negotiation request detected
: USBFS_GLOBAL_GOTGINTF_ADTO   %1 18 lshift USBFS_GLOBAL_GOTGINTF bis! ;  \ USBFS_GLOBAL_GOTGINTF_ADTO    A-device timeout
: USBFS_GLOBAL_GOTGINTF_DF   %1 19 lshift USBFS_GLOBAL_GOTGINTF bis! ;  \ USBFS_GLOBAL_GOTGINTF_DF    Debounce finish

\ USBFS_GLOBAL_GAHBCS (read-write)
: USBFS_GLOBAL_GAHBCS_GINTEN   %1 0 lshift USBFS_GLOBAL_GAHBCS bis! ;  \ USBFS_GLOBAL_GAHBCS_GINTEN    Global interrupt enable
: USBFS_GLOBAL_GAHBCS_TXFTH   %1 7 lshift USBFS_GLOBAL_GAHBCS bis! ;  \ USBFS_GLOBAL_GAHBCS_TXFTH    Tx FIFO threshold
: USBFS_GLOBAL_GAHBCS_PTXFTH   %1 8 lshift USBFS_GLOBAL_GAHBCS bis! ;  \ USBFS_GLOBAL_GAHBCS_PTXFTH    Periodic Tx FIFO threshold

\ USBFS_GLOBAL_GUSBCS ()
: USBFS_GLOBAL_GUSBCS_TOC   ( %XXX -- ) 0 lshift USBFS_GLOBAL_GUSBCS bis! ;  \ USBFS_GLOBAL_GUSBCS_TOC    Timeout calibration
: USBFS_GLOBAL_GUSBCS_SRPCEN   %1 8 lshift USBFS_GLOBAL_GUSBCS bis! ;  \ USBFS_GLOBAL_GUSBCS_SRPCEN    SRP capability enable
: USBFS_GLOBAL_GUSBCS_HNPCEN   %1 9 lshift USBFS_GLOBAL_GUSBCS bis! ;  \ USBFS_GLOBAL_GUSBCS_HNPCEN    HNP capability enable
: USBFS_GLOBAL_GUSBCS_UTT   ( %XXXX -- ) 10 lshift USBFS_GLOBAL_GUSBCS bis! ;  \ USBFS_GLOBAL_GUSBCS_UTT    USB turnaround time
: USBFS_GLOBAL_GUSBCS_FHM   %1 29 lshift USBFS_GLOBAL_GUSBCS bis! ;  \ USBFS_GLOBAL_GUSBCS_FHM    Force host mode
: USBFS_GLOBAL_GUSBCS_FDM   %1 30 lshift USBFS_GLOBAL_GUSBCS bis! ;  \ USBFS_GLOBAL_GUSBCS_FDM    Force device mode

\ USBFS_GLOBAL_GRSTCTL ()
: USBFS_GLOBAL_GRSTCTL_CSRST   %1 0 lshift USBFS_GLOBAL_GRSTCTL bis! ;  \ USBFS_GLOBAL_GRSTCTL_CSRST    Core soft reset
: USBFS_GLOBAL_GRSTCTL_HCSRST   %1 1 lshift USBFS_GLOBAL_GRSTCTL bis! ;  \ USBFS_GLOBAL_GRSTCTL_HCSRST    HCLK soft reset
: USBFS_GLOBAL_GRSTCTL_HFCRST   %1 2 lshift USBFS_GLOBAL_GRSTCTL bis! ;  \ USBFS_GLOBAL_GRSTCTL_HFCRST    Host frame counter reset
: USBFS_GLOBAL_GRSTCTL_RXFF   %1 4 lshift USBFS_GLOBAL_GRSTCTL bis! ;  \ USBFS_GLOBAL_GRSTCTL_RXFF    RxFIFO flush
: USBFS_GLOBAL_GRSTCTL_TXFF   %1 5 lshift USBFS_GLOBAL_GRSTCTL bis! ;  \ USBFS_GLOBAL_GRSTCTL_TXFF    TxFIFO flush
: USBFS_GLOBAL_GRSTCTL_TXFNUM   ( %XXXXX -- ) 6 lshift USBFS_GLOBAL_GRSTCTL bis! ;  \ USBFS_GLOBAL_GRSTCTL_TXFNUM    TxFIFO number

\ USBFS_GLOBAL_GINTF ()
: USBFS_GLOBAL_GINTF_COPM   %1 0 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_COPM    Current operation mode
: USBFS_GLOBAL_GINTF_MFIF   %1 1 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_MFIF    Mode fault interrupt flag
: USBFS_GLOBAL_GINTF_OTGIF   %1 2 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_OTGIF    OTG interrupt flag
: USBFS_GLOBAL_GINTF_SOF   %1 3 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_SOF    Start of frame
: USBFS_GLOBAL_GINTF_RXFNEIF   %1 4 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_RXFNEIF    RxFIFO non-empty interrupt flag
: USBFS_GLOBAL_GINTF_NPTXFEIF   %1 5 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_NPTXFEIF    Non-periodic TxFIFO empty interrupt flag
: USBFS_GLOBAL_GINTF_GNPINAK   %1 6 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_GNPINAK    Global Non-Periodic IN NAK effective
: USBFS_GLOBAL_GINTF_GONAK   %1 7 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_GONAK    Global OUT NAK effective
: USBFS_GLOBAL_GINTF_ESP   %1 10 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_ESP    Early suspend
: USBFS_GLOBAL_GINTF_SP   %1 11 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_SP    USB suspend
: USBFS_GLOBAL_GINTF_RST   %1 12 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_RST    USB reset
: USBFS_GLOBAL_GINTF_ENUMF   %1 13 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_ENUMF    Enumeration finished
: USBFS_GLOBAL_GINTF_ISOOPDIF   %1 14 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_ISOOPDIF    Isochronous OUT packet dropped  interrupt
: USBFS_GLOBAL_GINTF_EOPFIF   %1 15 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_EOPFIF    End of periodic frame  interrupt flag
: USBFS_GLOBAL_GINTF_IEPIF   %1 18 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_IEPIF    IN endpoint interrupt flag
: USBFS_GLOBAL_GINTF_OEPIF   %1 19 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_OEPIF    OUT endpoint interrupt flag
: USBFS_GLOBAL_GINTF_ISOINCIF   %1 20 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_ISOINCIF    Isochronous IN transfer Not Complete Interrupt Flag
: USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF   %1 21 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF    periodic transfer not complete interrupt flagHost  mode/isochronous OUT transfer not complete interrupt flagDevice  mode
: USBFS_GLOBAL_GINTF_HPIF   %1 24 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_HPIF    Host port interrupt flag
: USBFS_GLOBAL_GINTF_HCIF   %1 25 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_HCIF    Host channels interrupt flag
: USBFS_GLOBAL_GINTF_PTXFEIF   %1 26 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_PTXFEIF    Periodic TxFIFO empty interrupt flag
: USBFS_GLOBAL_GINTF_IDPSC   %1 28 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_IDPSC    ID pin status change
: USBFS_GLOBAL_GINTF_DISCIF   %1 29 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_DISCIF    Disconnect interrupt flag
: USBFS_GLOBAL_GINTF_SESIF   %1 30 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_SESIF    Session interrupt flag
: USBFS_GLOBAL_GINTF_WKUPIF   %1 31 lshift USBFS_GLOBAL_GINTF bis! ;  \ USBFS_GLOBAL_GINTF_WKUPIF    Wakeup interrupt flag

\ USBFS_GLOBAL_GINTEN ()
: USBFS_GLOBAL_GINTEN_MFIE   %1 1 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_MFIE    Mode fault interrupt  enable
: USBFS_GLOBAL_GINTEN_OTGIE   %1 2 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_OTGIE    OTG interrupt enable 
: USBFS_GLOBAL_GINTEN_SOFIE   %1 3 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_SOFIE    Start of frame interrupt enable
: USBFS_GLOBAL_GINTEN_RXFNEIE   %1 4 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_RXFNEIE    Receive FIFO non-empty  interrupt enable
: USBFS_GLOBAL_GINTEN_NPTXFEIE   %1 5 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_NPTXFEIE    Non-periodic TxFIFO empty  interrupt enable
: USBFS_GLOBAL_GINTEN_GNPINAKIE   %1 6 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_GNPINAKIE    Global non-periodic IN NAK effective interrupt enable
: USBFS_GLOBAL_GINTEN_GONAKIE   %1 7 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_GONAKIE    Global OUT NAK effective  interrupt enable
: USBFS_GLOBAL_GINTEN_ESPIE   %1 10 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_ESPIE    Early suspend interrupt enable
: USBFS_GLOBAL_GINTEN_SPIE   %1 11 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_SPIE    USB suspend interrupt enable
: USBFS_GLOBAL_GINTEN_RSTIE   %1 12 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_RSTIE    USB reset interrupt enable
: USBFS_GLOBAL_GINTEN_ENUMFIE   %1 13 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_ENUMFIE    Enumeration finish interrupt enable
: USBFS_GLOBAL_GINTEN_ISOOPDIE   %1 14 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_ISOOPDIE    Isochronous OUT packet dropped interrupt enable
: USBFS_GLOBAL_GINTEN_EOPFIE   %1 15 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_EOPFIE    End of periodic frame interrupt enable
: USBFS_GLOBAL_GINTEN_IEPIE   %1 18 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_IEPIE    IN endpoints interrupt enable
: USBFS_GLOBAL_GINTEN_OEPIE   %1 19 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_OEPIE    OUT endpoints interrupt enable
: USBFS_GLOBAL_GINTEN_ISOINCIE   %1 20 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_ISOINCIE    isochronous IN transfer not complete  interrupt enable
: USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE   %1 21 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE    periodic transfer not compelete Interrupt enableHost  mode/isochronous OUT transfer not complete interrupt enableDevice  mode
: USBFS_GLOBAL_GINTEN_HPIE   %1 24 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_HPIE    Host port interrupt enable
: USBFS_GLOBAL_GINTEN_HCIE   %1 25 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_HCIE    Host channels interrupt enable
: USBFS_GLOBAL_GINTEN_PTXFEIE   %1 26 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_PTXFEIE    Periodic TxFIFO empty interrupt enable
: USBFS_GLOBAL_GINTEN_IDPSCIE   %1 28 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_IDPSCIE    ID pin status change interrupt enable
: USBFS_GLOBAL_GINTEN_DISCIE   %1 29 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_DISCIE    Disconnect interrupt enable
: USBFS_GLOBAL_GINTEN_SESIE   %1 30 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_SESIE    Session interrupt enable
: USBFS_GLOBAL_GINTEN_WKUPIE   %1 31 lshift USBFS_GLOBAL_GINTEN bis! ;  \ USBFS_GLOBAL_GINTEN_WKUPIE    Wakeup interrupt enable

\ USBFS_GLOBAL_GRSTATR_Device (read-only)
: USBFS_GLOBAL_GRSTATR_Device_EPNUM   ( %XXXX -- ) 0 lshift USBFS_GLOBAL_GRSTATR_Device bis! ;  \ USBFS_GLOBAL_GRSTATR_Device_EPNUM    Endpoint number
: USBFS_GLOBAL_GRSTATR_Device_BCOUNT  4 lshift USBFS_GLOBAL_GRSTATR_Device bis! ;  \ USBFS_GLOBAL_GRSTATR_Device_BCOUNT    Byte count
: USBFS_GLOBAL_GRSTATR_Device_DPID   ( %XX -- ) 15 lshift USBFS_GLOBAL_GRSTATR_Device bis! ;  \ USBFS_GLOBAL_GRSTATR_Device_DPID    Data PID
: USBFS_GLOBAL_GRSTATR_Device_RPCKST   ( %XXXX -- ) 17 lshift USBFS_GLOBAL_GRSTATR_Device bis! ;  \ USBFS_GLOBAL_GRSTATR_Device_RPCKST    Recieve packet status

\ USBFS_GLOBAL_GRSTATR_Host (read-only)
: USBFS_GLOBAL_GRSTATR_Host_CNUM   ( %XXXX -- ) 0 lshift USBFS_GLOBAL_GRSTATR_Host bis! ;  \ USBFS_GLOBAL_GRSTATR_Host_CNUM    Channel number
: USBFS_GLOBAL_GRSTATR_Host_BCOUNT  4 lshift USBFS_GLOBAL_GRSTATR_Host bis! ;  \ USBFS_GLOBAL_GRSTATR_Host_BCOUNT    Byte count
: USBFS_GLOBAL_GRSTATR_Host_DPID   ( %XX -- ) 15 lshift USBFS_GLOBAL_GRSTATR_Host bis! ;  \ USBFS_GLOBAL_GRSTATR_Host_DPID    Data PID
: USBFS_GLOBAL_GRSTATR_Host_RPCKST   ( %XXXX -- ) 17 lshift USBFS_GLOBAL_GRSTATR_Host bis! ;  \ USBFS_GLOBAL_GRSTATR_Host_RPCKST    Reivece packet status

\ USBFS_GLOBAL_GRSTATP_Device (read-only)
: USBFS_GLOBAL_GRSTATP_Device_EPNUM   ( %XXXX -- ) 0 lshift USBFS_GLOBAL_GRSTATP_Device bis! ;  \ USBFS_GLOBAL_GRSTATP_Device_EPNUM    Endpoint number
: USBFS_GLOBAL_GRSTATP_Device_BCOUNT  4 lshift USBFS_GLOBAL_GRSTATP_Device bis! ;  \ USBFS_GLOBAL_GRSTATP_Device_BCOUNT    Byte count
: USBFS_GLOBAL_GRSTATP_Device_DPID   ( %XX -- ) 15 lshift USBFS_GLOBAL_GRSTATP_Device bis! ;  \ USBFS_GLOBAL_GRSTATP_Device_DPID    Data PID
: USBFS_GLOBAL_GRSTATP_Device_RPCKST   ( %XXXX -- ) 17 lshift USBFS_GLOBAL_GRSTATP_Device bis! ;  \ USBFS_GLOBAL_GRSTATP_Device_RPCKST    Recieve packet status

\ USBFS_GLOBAL_GRSTATP_Host (read-only)
: USBFS_GLOBAL_GRSTATP_Host_CNUM   ( %XXXX -- ) 0 lshift USBFS_GLOBAL_GRSTATP_Host bis! ;  \ USBFS_GLOBAL_GRSTATP_Host_CNUM    Channel number
: USBFS_GLOBAL_GRSTATP_Host_BCOUNT  4 lshift USBFS_GLOBAL_GRSTATP_Host bis! ;  \ USBFS_GLOBAL_GRSTATP_Host_BCOUNT    Byte count
: USBFS_GLOBAL_GRSTATP_Host_DPID   ( %XX -- ) 15 lshift USBFS_GLOBAL_GRSTATP_Host bis! ;  \ USBFS_GLOBAL_GRSTATP_Host_DPID    Data PID
: USBFS_GLOBAL_GRSTATP_Host_RPCKST   ( %XXXX -- ) 17 lshift USBFS_GLOBAL_GRSTATP_Host bis! ;  \ USBFS_GLOBAL_GRSTATP_Host_RPCKST    Reivece packet status

\ USBFS_GLOBAL_GRFLEN (read-write)
: USBFS_GLOBAL_GRFLEN_RXFD   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_GRFLEN bis! ;  \ USBFS_GLOBAL_GRFLEN_RXFD    Rx FIFO depth

\ USBFS_GLOBAL_HNPTFLEN (read-write)
: USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_HNPTFLEN bis! ;  \ USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR    host non-periodic transmit Tx RAM start  address
: USBFS_GLOBAL_HNPTFLEN_HNPTXFD   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_GLOBAL_HNPTFLEN bis! ;  \ USBFS_GLOBAL_HNPTFLEN_HNPTXFD    host non-periodic TxFIFO depth

\ USBFS_GLOBAL_DIEP0TFLEN (read-write)
: USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_GLOBAL_DIEP0TFLEN bis! ;  \ USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD    in endpoint 0 Tx FIFO depth
: USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_DIEP0TFLEN bis! ;  \ USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR    in endpoint 0 Tx RAM start address

\ USBFS_GLOBAL_HNPTFQSTAT (read-only)
: USBFS_GLOBAL_HNPTFQSTAT_NPTXFS   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_HNPTFQSTAT bis! ;  \ USBFS_GLOBAL_HNPTFQSTAT_NPTXFS    Non-periodic TxFIFO space
: USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS   ( %XXXXXXXX -- ) 16 lshift USBFS_GLOBAL_HNPTFQSTAT bis! ;  \ USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS    Non-periodic transmit request queue  space 
: USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP   ( %XXXXXXX -- ) 24 lshift USBFS_GLOBAL_HNPTFQSTAT bis! ;  \ USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP    Top of the non-periodic transmit request  queue

\ USBFS_GLOBAL_GCCFG (read-write)
: USBFS_GLOBAL_GCCFG_PWRON   %1 16 lshift USBFS_GLOBAL_GCCFG bis! ;  \ USBFS_GLOBAL_GCCFG_PWRON    Power on
: USBFS_GLOBAL_GCCFG_VBUSACEN   %1 18 lshift USBFS_GLOBAL_GCCFG bis! ;  \ USBFS_GLOBAL_GCCFG_VBUSACEN    The VBUS A-device Comparer enable
: USBFS_GLOBAL_GCCFG_VBUSBCEN   %1 19 lshift USBFS_GLOBAL_GCCFG bis! ;  \ USBFS_GLOBAL_GCCFG_VBUSBCEN    The VBUS B-device Comparer enable
: USBFS_GLOBAL_GCCFG_SOFOEN   %1 20 lshift USBFS_GLOBAL_GCCFG bis! ;  \ USBFS_GLOBAL_GCCFG_SOFOEN    SOF output enable
: USBFS_GLOBAL_GCCFG_VBUSIG   %1 21 lshift USBFS_GLOBAL_GCCFG bis! ;  \ USBFS_GLOBAL_GCCFG_VBUSIG    VBUS ignored

\ USBFS_GLOBAL_CID (read-write)
: USBFS_GLOBAL_CID_CID   ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_CID bis! ;  \ USBFS_GLOBAL_CID_CID    Core ID

\ USBFS_GLOBAL_HPTFLEN (read-write)
: USBFS_GLOBAL_HPTFLEN_HPTXFSAR   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_HPTFLEN bis! ;  \ USBFS_GLOBAL_HPTFLEN_HPTXFSAR    Host periodic TxFIFO start  address
: USBFS_GLOBAL_HPTFLEN_HPTXFD   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_GLOBAL_HPTFLEN bis! ;  \ USBFS_GLOBAL_HPTFLEN_HPTXFD    Host periodic TxFIFO depth

\ USBFS_GLOBAL_DIEP1TFLEN (read-write)
: USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_DIEP1TFLEN bis! ;  \ USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR    IN endpoint FIFO transmit RAM start  address
: USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_GLOBAL_DIEP1TFLEN bis! ;  \ USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD    IN endpoint TxFIFO depth

\ USBFS_GLOBAL_DIEP2TFLEN (read-write)
: USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_DIEP2TFLEN bis! ;  \ USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR    IN endpoint FIFO transmit RAM start  address
: USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_GLOBAL_DIEP2TFLEN bis! ;  \ USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD    IN endpoint TxFIFO depth

\ USBFS_GLOBAL_DIEP3TFLEN (read-write)
: USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_GLOBAL_DIEP3TFLEN bis! ;  \ USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR    IN endpoint FIFO4 transmit RAM start  address
: USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_GLOBAL_DIEP3TFLEN bis! ;  \ USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD    IN endpoint TxFIFO depth

\ USBFS_HOST_HCTL ()
: USBFS_HOST_HCTL_CLKSEL   ( %XX -- ) 0 lshift USBFS_HOST_HCTL bis! ;  \ USBFS_HOST_HCTL_CLKSEL    clock select for USB clock

\ USBFS_HOST_HFT (read-write)
: USBFS_HOST_HFT_FRI   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_HOST_HFT bis! ;  \ USBFS_HOST_HFT_FRI    Frame interval

\ USBFS_HOST_HFINFR (read-only)
: USBFS_HOST_HFINFR_FRNUM   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_HOST_HFINFR bis! ;  \ USBFS_HOST_HFINFR_FRNUM    Frame number
: USBFS_HOST_HFINFR_FRT   ( %XXXXXXXXXXXXXXXX -- ) 16 lshift USBFS_HOST_HFINFR bis! ;  \ USBFS_HOST_HFINFR_FRT    Frame remaining time

\ USBFS_HOST_HPTFQSTAT ()
: USBFS_HOST_HPTFQSTAT_PTXFS   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_HOST_HPTFQSTAT bis! ;  \ USBFS_HOST_HPTFQSTAT_PTXFS    Periodic transmit data FIFO space  available
: USBFS_HOST_HPTFQSTAT_PTXREQS   ( %XXXXXXXX -- ) 16 lshift USBFS_HOST_HPTFQSTAT bis! ;  \ USBFS_HOST_HPTFQSTAT_PTXREQS    Periodic transmit request queue space  available
: USBFS_HOST_HPTFQSTAT_PTXREQT   ( %XXXXXXXX -- ) 24 lshift USBFS_HOST_HPTFQSTAT bis! ;  \ USBFS_HOST_HPTFQSTAT_PTXREQT    Top of the periodic transmit request  queue

\ USBFS_HOST_HACHINT (read-only)
: USBFS_HOST_HACHINT_HACHINT   ( %XXXXXXXX -- ) 0 lshift USBFS_HOST_HACHINT bis! ;  \ USBFS_HOST_HACHINT_HACHINT    Host all channel interrupts

\ USBFS_HOST_HACHINTEN (read-write)
: USBFS_HOST_HACHINTEN_CINTEN   ( %XXXXXXXX -- ) 0 lshift USBFS_HOST_HACHINTEN bis! ;  \ USBFS_HOST_HACHINTEN_CINTEN    Channel interrupt enable

\ USBFS_HOST_HPCS ()
: USBFS_HOST_HPCS_PCST   %1 0 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PCST    Port connect status
: USBFS_HOST_HPCS_PCD   %1 1 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PCD    Port connect detected
: USBFS_HOST_HPCS_PE   %1 2 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PE    Port enable
: USBFS_HOST_HPCS_PEDC   %1 3 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PEDC    Port enable/disable change
: USBFS_HOST_HPCS_PREM   %1 6 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PREM    Port resume
: USBFS_HOST_HPCS_PSP   %1 7 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PSP    Port suspend
: USBFS_HOST_HPCS_PRST   %1 8 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PRST    Port reset
: USBFS_HOST_HPCS_PLST   ( %XX -- ) 10 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PLST    Port line status
: USBFS_HOST_HPCS_PP   %1 12 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PP    Port power
: USBFS_HOST_HPCS_PS   ( %XX -- ) 17 lshift USBFS_HOST_HPCS bis! ;  \ USBFS_HOST_HPCS_PS    Port speed

\ USBFS_HOST_HCH0CTL (read-write)
: USBFS_HOST_HCH0CTL_MPL  0 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_MPL    Maximum packet size
: USBFS_HOST_HCH0CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH0CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH0CTL_LSD   %1 17 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_LSD    Low-speed device
: USBFS_HOST_HCH0CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH0CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_DAR    Device address
: USBFS_HOST_HCH0CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH0CTL_CDIS   %1 30 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_CDIS    Channel disable
: USBFS_HOST_HCH0CTL_CEN   %1 31 lshift USBFS_HOST_HCH0CTL bis! ;  \ USBFS_HOST_HCH0CTL_CEN    Channel enable

\ USBFS_HOST_HCH1CTL (read-write)
: USBFS_HOST_HCH1CTL_MPL  0 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_MPL    Maximum packet size
: USBFS_HOST_HCH1CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH1CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH1CTL_LSD   %1 17 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_LSD    Low-speed device
: USBFS_HOST_HCH1CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH1CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_DAR    Device address
: USBFS_HOST_HCH1CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH1CTL_CDIS   %1 30 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_CDIS    Channel disable
: USBFS_HOST_HCH1CTL_CEN   %1 31 lshift USBFS_HOST_HCH1CTL bis! ;  \ USBFS_HOST_HCH1CTL_CEN    Channel enable

\ USBFS_HOST_HCH2CTL (read-write)
: USBFS_HOST_HCH2CTL_MPL  0 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_MPL    Maximum packet size
: USBFS_HOST_HCH2CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH2CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH2CTL_LSD   %1 17 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_LSD    Low-speed device
: USBFS_HOST_HCH2CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH2CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_DAR    Device address
: USBFS_HOST_HCH2CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH2CTL_CDIS   %1 30 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_CDIS    Channel disable
: USBFS_HOST_HCH2CTL_CEN   %1 31 lshift USBFS_HOST_HCH2CTL bis! ;  \ USBFS_HOST_HCH2CTL_CEN    Channel enable

\ USBFS_HOST_HCH3CTL (read-write)
: USBFS_HOST_HCH3CTL_MPL  0 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_MPL    Maximum packet size
: USBFS_HOST_HCH3CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH3CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH3CTL_LSD   %1 17 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_LSD    Low-speed device
: USBFS_HOST_HCH3CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH3CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_DAR    Device address
: USBFS_HOST_HCH3CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH3CTL_CDIS   %1 30 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_CDIS    Channel disable
: USBFS_HOST_HCH3CTL_CEN   %1 31 lshift USBFS_HOST_HCH3CTL bis! ;  \ USBFS_HOST_HCH3CTL_CEN    Channel enable

\ USBFS_HOST_HCH4CTL (read-write)
: USBFS_HOST_HCH4CTL_MPL  0 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_MPL    Maximum packet size
: USBFS_HOST_HCH4CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH4CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH4CTL_LSD   %1 17 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_LSD    Low-speed device
: USBFS_HOST_HCH4CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH4CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_DAR    Device address
: USBFS_HOST_HCH4CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH4CTL_CDIS   %1 30 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_CDIS    Channel disable
: USBFS_HOST_HCH4CTL_CEN   %1 31 lshift USBFS_HOST_HCH4CTL bis! ;  \ USBFS_HOST_HCH4CTL_CEN    Channel enable

\ USBFS_HOST_HCH5CTL (read-write)
: USBFS_HOST_HCH5CTL_MPL  0 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_MPL    Maximum packet size
: USBFS_HOST_HCH5CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH5CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH5CTL_LSD   %1 17 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_LSD    Low-speed device
: USBFS_HOST_HCH5CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH5CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_DAR    Device address
: USBFS_HOST_HCH5CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH5CTL_CDIS   %1 30 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_CDIS    Channel disable
: USBFS_HOST_HCH5CTL_CEN   %1 31 lshift USBFS_HOST_HCH5CTL bis! ;  \ USBFS_HOST_HCH5CTL_CEN    Channel enable

\ USBFS_HOST_HCH6CTL (read-write)
: USBFS_HOST_HCH6CTL_MPL  0 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_MPL    Maximum packet size
: USBFS_HOST_HCH6CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH6CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH6CTL_LSD   %1 17 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_LSD    Low-speed device
: USBFS_HOST_HCH6CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH6CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_DAR    Device address
: USBFS_HOST_HCH6CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH6CTL_CDIS   %1 30 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_CDIS    Channel disable
: USBFS_HOST_HCH6CTL_CEN   %1 31 lshift USBFS_HOST_HCH6CTL bis! ;  \ USBFS_HOST_HCH6CTL_CEN    Channel enable

\ USBFS_HOST_HCH7CTL (read-write)
: USBFS_HOST_HCH7CTL_MPL  0 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_MPL    Maximum packet size
: USBFS_HOST_HCH7CTL_EPNUM   ( %XXXX -- ) 11 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_EPNUM    Endpoint number
: USBFS_HOST_HCH7CTL_EPDIR   %1 15 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_EPDIR    Endpoint direction
: USBFS_HOST_HCH7CTL_LSD   %1 17 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_LSD    Low-speed device
: USBFS_HOST_HCH7CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_EPTYPE    Endpoint type
: USBFS_HOST_HCH7CTL_DAR   ( %XXXXXXX -- ) 22 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_DAR    Device address
: USBFS_HOST_HCH7CTL_ODDFRM   %1 29 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_ODDFRM    Odd frame
: USBFS_HOST_HCH7CTL_CDIS   %1 30 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_CDIS    Channel disable
: USBFS_HOST_HCH7CTL_CEN   %1 31 lshift USBFS_HOST_HCH7CTL bis! ;  \ USBFS_HOST_HCH7CTL_CEN    Channel enable

\ USBFS_HOST_HCH0INTF (read-write)
: USBFS_HOST_HCH0INTF_TF   %1 0 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_TF    Transfer finished
: USBFS_HOST_HCH0INTF_CH   %1 1 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_CH    Channel halted
: USBFS_HOST_HCH0INTF_STALL   %1 3 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH0INTF_NAK   %1 4 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH0INTF_ACK   %1 5 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH0INTF_USBER   %1 7 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_USBER    USB bus error
: USBFS_HOST_HCH0INTF_BBER   %1 8 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_BBER    Babble error
: USBFS_HOST_HCH0INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH0INTF_DTER   %1 10 lshift USBFS_HOST_HCH0INTF bis! ;  \ USBFS_HOST_HCH0INTF_DTER    Data toggle error

\ USBFS_HOST_HCH1INTF (read-write)
: USBFS_HOST_HCH1INTF_TF   %1 0 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_TF    Transfer finished
: USBFS_HOST_HCH1INTF_CH   %1 1 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_CH    Channel halted
: USBFS_HOST_HCH1INTF_STALL   %1 3 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH1INTF_NAK   %1 4 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH1INTF_ACK   %1 5 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH1INTF_USBER   %1 7 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_USBER    USB bus error
: USBFS_HOST_HCH1INTF_BBER   %1 8 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_BBER    Babble error
: USBFS_HOST_HCH1INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH1INTF_DTER   %1 10 lshift USBFS_HOST_HCH1INTF bis! ;  \ USBFS_HOST_HCH1INTF_DTER    Data toggle error

\ USBFS_HOST_HCH2INTF (read-write)
: USBFS_HOST_HCH2INTF_TF   %1 0 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_TF    Transfer finished
: USBFS_HOST_HCH2INTF_CH   %1 1 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_CH    Channel halted
: USBFS_HOST_HCH2INTF_STALL   %1 3 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH2INTF_NAK   %1 4 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH2INTF_ACK   %1 5 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH2INTF_USBER   %1 7 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_USBER    USB bus error
: USBFS_HOST_HCH2INTF_BBER   %1 8 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_BBER    Babble error
: USBFS_HOST_HCH2INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH2INTF_DTER   %1 10 lshift USBFS_HOST_HCH2INTF bis! ;  \ USBFS_HOST_HCH2INTF_DTER    Data toggle error

\ USBFS_HOST_HCH3INTF (read-write)
: USBFS_HOST_HCH3INTF_TF   %1 0 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_TF    Transfer finished
: USBFS_HOST_HCH3INTF_CH   %1 1 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_CH    Channel halted
: USBFS_HOST_HCH3INTF_STALL   %1 3 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH3INTF_NAK   %1 4 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH3INTF_ACK   %1 5 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH3INTF_USBER   %1 7 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_USBER    USB bus error
: USBFS_HOST_HCH3INTF_BBER   %1 8 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_BBER    Babble error
: USBFS_HOST_HCH3INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH3INTF_DTER   %1 10 lshift USBFS_HOST_HCH3INTF bis! ;  \ USBFS_HOST_HCH3INTF_DTER    Data toggle error

\ USBFS_HOST_HCH4INTF (read-write)
: USBFS_HOST_HCH4INTF_TF   %1 0 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_TF    Transfer finished
: USBFS_HOST_HCH4INTF_CH   %1 1 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_CH    Channel halted
: USBFS_HOST_HCH4INTF_STALL   %1 3 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH4INTF_NAK   %1 4 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH4INTF_ACK   %1 5 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH4INTF_USBER   %1 7 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_USBER    USB bus error
: USBFS_HOST_HCH4INTF_BBER   %1 8 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_BBER    Babble error
: USBFS_HOST_HCH4INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH4INTF_DTER   %1 10 lshift USBFS_HOST_HCH4INTF bis! ;  \ USBFS_HOST_HCH4INTF_DTER    Data toggle error

\ USBFS_HOST_HCH5INTF (read-write)
: USBFS_HOST_HCH5INTF_TF   %1 0 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_TF    Transfer finished
: USBFS_HOST_HCH5INTF_CH   %1 1 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_CH    Channel halted
: USBFS_HOST_HCH5INTF_STALL   %1 3 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH5INTF_NAK   %1 4 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH5INTF_ACK   %1 5 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH5INTF_USBER   %1 7 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_USBER    USB bus error
: USBFS_HOST_HCH5INTF_BBER   %1 8 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_BBER    Babble error
: USBFS_HOST_HCH5INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH5INTF_DTER   %1 10 lshift USBFS_HOST_HCH5INTF bis! ;  \ USBFS_HOST_HCH5INTF_DTER    Data toggle error

\ USBFS_HOST_HCH6INTF (read-write)
: USBFS_HOST_HCH6INTF_TF   %1 0 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_TF    Transfer finished
: USBFS_HOST_HCH6INTF_CH   %1 1 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_CH    Channel halted
: USBFS_HOST_HCH6INTF_STALL   %1 3 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH6INTF_NAK   %1 4 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH6INTF_ACK   %1 5 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH6INTF_USBER   %1 7 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_USBER    USB bus error
: USBFS_HOST_HCH6INTF_BBER   %1 8 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_BBER    Babble error
: USBFS_HOST_HCH6INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH6INTF_DTER   %1 10 lshift USBFS_HOST_HCH6INTF bis! ;  \ USBFS_HOST_HCH6INTF_DTER    Data toggle error

\ USBFS_HOST_HCH7INTF (read-write)
: USBFS_HOST_HCH7INTF_TF   %1 0 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_TF    Transfer finished
: USBFS_HOST_HCH7INTF_CH   %1 1 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_CH    Channel halted
: USBFS_HOST_HCH7INTF_STALL   %1 3 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_STALL    STALL response received  interrupt
: USBFS_HOST_HCH7INTF_NAK   %1 4 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_NAK    NAK response received  interrupt
: USBFS_HOST_HCH7INTF_ACK   %1 5 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_ACK    ACK response received/transmitted  interrupt
: USBFS_HOST_HCH7INTF_USBER   %1 7 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_USBER    USB bus error
: USBFS_HOST_HCH7INTF_BBER   %1 8 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_BBER    Babble error
: USBFS_HOST_HCH7INTF_REQOVR   %1 9 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_REQOVR    Request queue overrun
: USBFS_HOST_HCH7INTF_DTER   %1 10 lshift USBFS_HOST_HCH7INTF bis! ;  \ USBFS_HOST_HCH7INTF_DTER    Data toggle error

\ USBFS_HOST_HCH0INTEN (read-write)
: USBFS_HOST_HCH0INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH0INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH0INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH0INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH0INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH0INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH0INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH0INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH0INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH0INTEN bis! ;  \ USBFS_HOST_HCH0INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH1INTEN (read-write)
: USBFS_HOST_HCH1INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH1INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH1INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH1INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH1INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH1INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH1INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH1INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH1INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH1INTEN bis! ;  \ USBFS_HOST_HCH1INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH2INTEN (read-write)
: USBFS_HOST_HCH2INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH2INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH2INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH2INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH2INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH2INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH2INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH2INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH2INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH2INTEN bis! ;  \ USBFS_HOST_HCH2INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH3INTEN (read-write)
: USBFS_HOST_HCH3INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH3INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH3INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH3INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH3INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH3INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH3INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH3INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH3INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH3INTEN bis! ;  \ USBFS_HOST_HCH3INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH4INTEN (read-write)
: USBFS_HOST_HCH4INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH4INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH4INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH4INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH4INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH4INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH4INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH4INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH4INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH4INTEN bis! ;  \ USBFS_HOST_HCH4INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH5INTEN (read-write)
: USBFS_HOST_HCH5INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH5INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH5INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH5INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH5INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH5INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH5INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH5INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH5INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH5INTEN bis! ;  \ USBFS_HOST_HCH5INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH6INTEN (read-write)
: USBFS_HOST_HCH6INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH6INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH6INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH6INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH6INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH6INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH6INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH6INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH6INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH6INTEN bis! ;  \ USBFS_HOST_HCH6INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH7INTEN (read-write)
: USBFS_HOST_HCH7INTEN_TFIE   %1 0 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_TFIE    Transfer completed interrupt enable
: USBFS_HOST_HCH7INTEN_CHIE   %1 1 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_CHIE    Channel halted interrupt enable
: USBFS_HOST_HCH7INTEN_STALLIE   %1 3 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_STALLIE    STALL interrupt enable
: USBFS_HOST_HCH7INTEN_NAKIE   %1 4 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_NAKIE    NAK interrupt enable
: USBFS_HOST_HCH7INTEN_ACKIE   %1 5 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_ACKIE    ACK interrupt enable
: USBFS_HOST_HCH7INTEN_USBERIE   %1 7 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_USBERIE    USB bus error interrupt enable
: USBFS_HOST_HCH7INTEN_BBERIE   %1 8 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_BBERIE    Babble error interrupt enable
: USBFS_HOST_HCH7INTEN_REQOVRIE   %1 9 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_REQOVRIE    request queue overrun interrupt enable
: USBFS_HOST_HCH7INTEN_DTERIE   %1 10 lshift USBFS_HOST_HCH7INTEN bis! ;  \ USBFS_HOST_HCH7INTEN_DTERIE    Data toggle error interrupt enable

\ USBFS_HOST_HCH0LEN (read-write)
: USBFS_HOST_HCH0LEN_TLEN  0 lshift USBFS_HOST_HCH0LEN bis! ;  \ USBFS_HOST_HCH0LEN_TLEN    Transfer length
: USBFS_HOST_HCH0LEN_PCNT  19 lshift USBFS_HOST_HCH0LEN bis! ;  \ USBFS_HOST_HCH0LEN_PCNT    Packet count
: USBFS_HOST_HCH0LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH0LEN bis! ;  \ USBFS_HOST_HCH0LEN_DPID    Data PID

\ USBFS_HOST_HCH1LEN (read-write)
: USBFS_HOST_HCH1LEN_TLEN  0 lshift USBFS_HOST_HCH1LEN bis! ;  \ USBFS_HOST_HCH1LEN_TLEN    Transfer length
: USBFS_HOST_HCH1LEN_PCNT  19 lshift USBFS_HOST_HCH1LEN bis! ;  \ USBFS_HOST_HCH1LEN_PCNT    Packet count
: USBFS_HOST_HCH1LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH1LEN bis! ;  \ USBFS_HOST_HCH1LEN_DPID    Data PID

\ USBFS_HOST_HCH2LEN (read-write)
: USBFS_HOST_HCH2LEN_TLEN  0 lshift USBFS_HOST_HCH2LEN bis! ;  \ USBFS_HOST_HCH2LEN_TLEN    Transfer length
: USBFS_HOST_HCH2LEN_PCNT  19 lshift USBFS_HOST_HCH2LEN bis! ;  \ USBFS_HOST_HCH2LEN_PCNT    Packet count
: USBFS_HOST_HCH2LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH2LEN bis! ;  \ USBFS_HOST_HCH2LEN_DPID    Data PID

\ USBFS_HOST_HCH3LEN (read-write)
: USBFS_HOST_HCH3LEN_TLEN  0 lshift USBFS_HOST_HCH3LEN bis! ;  \ USBFS_HOST_HCH3LEN_TLEN    Transfer length
: USBFS_HOST_HCH3LEN_PCNT  19 lshift USBFS_HOST_HCH3LEN bis! ;  \ USBFS_HOST_HCH3LEN_PCNT    Packet count
: USBFS_HOST_HCH3LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH3LEN bis! ;  \ USBFS_HOST_HCH3LEN_DPID    Data PID

\ USBFS_HOST_HCH4LEN (read-write)
: USBFS_HOST_HCH4LEN_TLEN  0 lshift USBFS_HOST_HCH4LEN bis! ;  \ USBFS_HOST_HCH4LEN_TLEN    Transfer length
: USBFS_HOST_HCH4LEN_PCNT  19 lshift USBFS_HOST_HCH4LEN bis! ;  \ USBFS_HOST_HCH4LEN_PCNT    Packet count
: USBFS_HOST_HCH4LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH4LEN bis! ;  \ USBFS_HOST_HCH4LEN_DPID    Data PID

\ USBFS_HOST_HCH5LEN (read-write)
: USBFS_HOST_HCH5LEN_TLEN  0 lshift USBFS_HOST_HCH5LEN bis! ;  \ USBFS_HOST_HCH5LEN_TLEN    Transfer length
: USBFS_HOST_HCH5LEN_PCNT  19 lshift USBFS_HOST_HCH5LEN bis! ;  \ USBFS_HOST_HCH5LEN_PCNT    Packet count
: USBFS_HOST_HCH5LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH5LEN bis! ;  \ USBFS_HOST_HCH5LEN_DPID    Data PID

\ USBFS_HOST_HCH6LEN (read-write)
: USBFS_HOST_HCH6LEN_TLEN  0 lshift USBFS_HOST_HCH6LEN bis! ;  \ USBFS_HOST_HCH6LEN_TLEN    Transfer length
: USBFS_HOST_HCH6LEN_PCNT  19 lshift USBFS_HOST_HCH6LEN bis! ;  \ USBFS_HOST_HCH6LEN_PCNT    Packet count
: USBFS_HOST_HCH6LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH6LEN bis! ;  \ USBFS_HOST_HCH6LEN_DPID    Data PID

\ USBFS_HOST_HCH7LEN (read-write)
: USBFS_HOST_HCH7LEN_TLEN  0 lshift USBFS_HOST_HCH7LEN bis! ;  \ USBFS_HOST_HCH7LEN_TLEN    Transfer length
: USBFS_HOST_HCH7LEN_PCNT  19 lshift USBFS_HOST_HCH7LEN bis! ;  \ USBFS_HOST_HCH7LEN_PCNT    Packet count
: USBFS_HOST_HCH7LEN_DPID   ( %XX -- ) 29 lshift USBFS_HOST_HCH7LEN bis! ;  \ USBFS_HOST_HCH7LEN_DPID    Data PID

\ USBFS_DEVICE_DCFG (read-write)
: USBFS_DEVICE_DCFG_DS   ( %XX -- ) 0 lshift USBFS_DEVICE_DCFG bis! ;  \ USBFS_DEVICE_DCFG_DS    Device speed
: USBFS_DEVICE_DCFG_NZLSOH   %1 2 lshift USBFS_DEVICE_DCFG bis! ;  \ USBFS_DEVICE_DCFG_NZLSOH    Non-zero-length status OUT  handshake
: USBFS_DEVICE_DCFG_DAR   ( %XXXXXXX -- ) 4 lshift USBFS_DEVICE_DCFG bis! ;  \ USBFS_DEVICE_DCFG_DAR    Device address
: USBFS_DEVICE_DCFG_EOPFT   ( %XX -- ) 11 lshift USBFS_DEVICE_DCFG bis! ;  \ USBFS_DEVICE_DCFG_EOPFT    end of periodic frame time

\ USBFS_DEVICE_DCTL ()
: USBFS_DEVICE_DCTL_RWKUP   %1 0 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_RWKUP    Remote wakeup
: USBFS_DEVICE_DCTL_SD   %1 1 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_SD    Soft disconnect
: USBFS_DEVICE_DCTL_GINS   %1 2 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_GINS    Global IN NAK status
: USBFS_DEVICE_DCTL_GONS   %1 3 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_GONS    Global OUT NAK status
: USBFS_DEVICE_DCTL_SGINAK   %1 7 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_SGINAK    Set global IN NAK
: USBFS_DEVICE_DCTL_CGINAK   %1 8 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_CGINAK    Clear global IN NAK
: USBFS_DEVICE_DCTL_SGONAK   %1 9 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_SGONAK    Set global OUT NAK
: USBFS_DEVICE_DCTL_CGONAK   %1 10 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_CGONAK    Clear global OUT NAK
: USBFS_DEVICE_DCTL_POIF   %1 11 lshift USBFS_DEVICE_DCTL bis! ;  \ USBFS_DEVICE_DCTL_POIF    Power-on initialization flag

\ USBFS_DEVICE_DSTAT (read-only)
: USBFS_DEVICE_DSTAT_SPST   %1 0 lshift USBFS_DEVICE_DSTAT bis! ;  \ USBFS_DEVICE_DSTAT_SPST    Suspend status
: USBFS_DEVICE_DSTAT_ES   ( %XX -- ) 1 lshift USBFS_DEVICE_DSTAT bis! ;  \ USBFS_DEVICE_DSTAT_ES    Enumerated speed
: USBFS_DEVICE_DSTAT_FNRSOF   ( %XXXXXXXXXXXXXX -- ) 8 lshift USBFS_DEVICE_DSTAT bis! ;  \ USBFS_DEVICE_DSTAT_FNRSOF    Frame number of the received  SOF

\ USBFS_DEVICE_DIEPINTEN (read-write)
: USBFS_DEVICE_DIEPINTEN_TFEN   %1 0 lshift USBFS_DEVICE_DIEPINTEN bis! ;  \ USBFS_DEVICE_DIEPINTEN_TFEN    Transfer finished interrupt  enable
: USBFS_DEVICE_DIEPINTEN_EPDISEN   %1 1 lshift USBFS_DEVICE_DIEPINTEN bis! ;  \ USBFS_DEVICE_DIEPINTEN_EPDISEN    Endpoint disabled interrupt  enable
: USBFS_DEVICE_DIEPINTEN_CITOEN   %1 3 lshift USBFS_DEVICE_DIEPINTEN bis! ;  \ USBFS_DEVICE_DIEPINTEN_CITOEN    Control IN timeout condition interrupt enable Non-isochronous  endpoints
: USBFS_DEVICE_DIEPINTEN_EPTXFUDEN   %1 4 lshift USBFS_DEVICE_DIEPINTEN bis! ;  \ USBFS_DEVICE_DIEPINTEN_EPTXFUDEN    Endpoint Tx FIFO underrun interrupt enable bit
: USBFS_DEVICE_DIEPINTEN_IEPNEEN   %1 6 lshift USBFS_DEVICE_DIEPINTEN bis! ;  \ USBFS_DEVICE_DIEPINTEN_IEPNEEN    IN endpoint NAK effective  interrupt enable

\ USBFS_DEVICE_DOEPINTEN (read-write)
: USBFS_DEVICE_DOEPINTEN_TFEN   %1 0 lshift USBFS_DEVICE_DOEPINTEN bis! ;  \ USBFS_DEVICE_DOEPINTEN_TFEN    Transfer finished interrupt  enable
: USBFS_DEVICE_DOEPINTEN_EPDISEN   %1 1 lshift USBFS_DEVICE_DOEPINTEN bis! ;  \ USBFS_DEVICE_DOEPINTEN_EPDISEN    Endpoint disabled interrupt  enable
: USBFS_DEVICE_DOEPINTEN_STPFEN   %1 3 lshift USBFS_DEVICE_DOEPINTEN bis! ;  \ USBFS_DEVICE_DOEPINTEN_STPFEN    SETUP phase finished interrupt enable
: USBFS_DEVICE_DOEPINTEN_EPRXFOVREN   %1 4 lshift USBFS_DEVICE_DOEPINTEN bis! ;  \ USBFS_DEVICE_DOEPINTEN_EPRXFOVREN     Endpoint Rx FIFO overrun interrupt enable
: USBFS_DEVICE_DOEPINTEN_BTBSTPEN   %1 6 lshift USBFS_DEVICE_DOEPINTEN bis! ;  \ USBFS_DEVICE_DOEPINTEN_BTBSTPEN     Back-to-back SETUP packets  interrupt enable

\ USBFS_DEVICE_DAEPINT (read-only)
: USBFS_DEVICE_DAEPINT_IEPITB   ( %XXXX -- ) 0 lshift USBFS_DEVICE_DAEPINT bis! ;  \ USBFS_DEVICE_DAEPINT_IEPITB    Device all IN endpoint interrupt bits
: USBFS_DEVICE_DAEPINT_OEPITB   ( %XXXX -- ) 16 lshift USBFS_DEVICE_DAEPINT bis! ;  \ USBFS_DEVICE_DAEPINT_OEPITB    Device all OUT endpoint interrupt bits

\ USBFS_DEVICE_DAEPINTEN (read-write)
: USBFS_DEVICE_DAEPINTEN_IEPIE   ( %XXXX -- ) 0 lshift USBFS_DEVICE_DAEPINTEN bis! ;  \ USBFS_DEVICE_DAEPINTEN_IEPIE    IN EP interrupt interrupt enable bits
: USBFS_DEVICE_DAEPINTEN_OEPIE   ( %XXXX -- ) 16 lshift USBFS_DEVICE_DAEPINTEN bis! ;  \ USBFS_DEVICE_DAEPINTEN_OEPIE    OUT endpoint interrupt enable bits

\ USBFS_DEVICE_DVBUSDT (read-write)
: USBFS_DEVICE_DVBUSDT_DVBUSDT   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_DEVICE_DVBUSDT bis! ;  \ USBFS_DEVICE_DVBUSDT_DVBUSDT    Device VBUS discharge time

\ USBFS_DEVICE_DVBUSPT (read-write)
: USBFS_DEVICE_DVBUSPT_DVBUSPT   ( %XXXXXXXXXXX -- ) 0 lshift USBFS_DEVICE_DVBUSPT bis! ;  \ USBFS_DEVICE_DVBUSPT_DVBUSPT    Device VBUS pulsing time

\ USBFS_DEVICE_DIEPFEINTEN (read-write)
: USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE   ( %XXXX -- ) 0 lshift USBFS_DEVICE_DIEPFEINTEN bis! ;  \ USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE    IN EP Tx FIFO empty interrupt enable  bits

\ USBFS_DEVICE_DIEP0CTL ()
: USBFS_DEVICE_DIEP0CTL_MPL   ( %XX -- ) 0 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_MPL    Maximum packet length
: USBFS_DEVICE_DIEP0CTL_EPACT   %1 15 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_EPACT    endpoint active
: USBFS_DEVICE_DIEP0CTL_NAKS   %1 17 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_NAKS    NAK status
: USBFS_DEVICE_DIEP0CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DIEP0CTL_STALL   %1 21 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_STALL    STALL handshake
: USBFS_DEVICE_DIEP0CTL_TXFNUM   ( %XXXX -- ) 22 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_TXFNUM    TxFIFO number
: USBFS_DEVICE_DIEP0CTL_CNAK   %1 26 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_CNAK    Clear NAK
: USBFS_DEVICE_DIEP0CTL_SNAK   %1 27 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_SNAK    Set NAK
: USBFS_DEVICE_DIEP0CTL_EPD   %1 30 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_EPD    Endpoint disable
: USBFS_DEVICE_DIEP0CTL_EPEN   %1 31 lshift USBFS_DEVICE_DIEP0CTL bis! ;  \ USBFS_DEVICE_DIEP0CTL_EPEN    Endpoint enable

\ USBFS_DEVICE_DIEP1CTL ()
: USBFS_DEVICE_DIEP1CTL_EPEN   %1 31 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DIEP1CTL_EPD   %1 30 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_EPD    Endpoint disable
: USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM   %1 29 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM    Set DATA1 PID/Set odd frame
: USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM   %1 28 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM    SD0PID/SEVNFRM
: USBFS_DEVICE_DIEP1CTL_SNAK   %1 27 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_SNAK    Set NAK
: USBFS_DEVICE_DIEP1CTL_CNAK   %1 26 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_CNAK    Clear NAK
: USBFS_DEVICE_DIEP1CTL_TXFNUM   ( %XXXX -- ) 22 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_TXFNUM    Tx FIFO number
: USBFS_DEVICE_DIEP1CTL_STALL   %1 21 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_STALL    STALL handshake
: USBFS_DEVICE_DIEP1CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DIEP1CTL_NAKS   %1 17 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_NAKS    NAK status
: USBFS_DEVICE_DIEP1CTL_EOFRM_DPID   %1 16 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_EOFRM_DPID    EOFRM/DPID
: USBFS_DEVICE_DIEP1CTL_EPACT   %1 15 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_EPACT    Endpoint active
: USBFS_DEVICE_DIEP1CTL_MPL  0 lshift USBFS_DEVICE_DIEP1CTL bis! ;  \ USBFS_DEVICE_DIEP1CTL_MPL    maximum packet length

\ USBFS_DEVICE_DIEP2CTL ()
: USBFS_DEVICE_DIEP2CTL_EPEN   %1 31 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DIEP2CTL_EPD   %1 30 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_EPD    Endpoint disable
: USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM   %1 29 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM    Set DATA1 PID/Set odd frame
: USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM   %1 28 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM    SD0PID/SEVNFRM
: USBFS_DEVICE_DIEP2CTL_SNAK   %1 27 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_SNAK    Set NAK
: USBFS_DEVICE_DIEP2CTL_CNAK   %1 26 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_CNAK    Clear NAK
: USBFS_DEVICE_DIEP2CTL_TXFNUM   ( %XXXX -- ) 22 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_TXFNUM    Tx FIFO number
: USBFS_DEVICE_DIEP2CTL_STALL   %1 21 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_STALL    STALL handshake
: USBFS_DEVICE_DIEP2CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DIEP2CTL_NAKS   %1 17 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_NAKS    NAK status
: USBFS_DEVICE_DIEP2CTL_EOFRM_DPID   %1 16 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_EOFRM_DPID    EOFRM/DPID
: USBFS_DEVICE_DIEP2CTL_EPACT   %1 15 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_EPACT    Endpoint active
: USBFS_DEVICE_DIEP2CTL_MPL  0 lshift USBFS_DEVICE_DIEP2CTL bis! ;  \ USBFS_DEVICE_DIEP2CTL_MPL    maximum packet length

\ USBFS_DEVICE_DIEP3CTL ()
: USBFS_DEVICE_DIEP3CTL_EPEN   %1 31 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DIEP3CTL_EPD   %1 30 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_EPD    Endpoint disable
: USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM   %1 29 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM    Set DATA1 PID/Set odd frame
: USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM   %1 28 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM    SD0PID/SEVNFRM
: USBFS_DEVICE_DIEP3CTL_SNAK   %1 27 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_SNAK    Set NAK
: USBFS_DEVICE_DIEP3CTL_CNAK   %1 26 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_CNAK    Clear NAK
: USBFS_DEVICE_DIEP3CTL_TXFNUM   ( %XXXX -- ) 22 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_TXFNUM    Tx FIFO number
: USBFS_DEVICE_DIEP3CTL_STALL   %1 21 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_STALL    STALL handshake
: USBFS_DEVICE_DIEP3CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DIEP3CTL_NAKS   %1 17 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_NAKS    NAK status
: USBFS_DEVICE_DIEP3CTL_EOFRM_DPID   %1 16 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_EOFRM_DPID    EOFRM/DPID
: USBFS_DEVICE_DIEP3CTL_EPACT   %1 15 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_EPACT    Endpoint active
: USBFS_DEVICE_DIEP3CTL_MPL  0 lshift USBFS_DEVICE_DIEP3CTL bis! ;  \ USBFS_DEVICE_DIEP3CTL_MPL    maximum packet length

\ USBFS_DEVICE_DOEP0CTL ()
: USBFS_DEVICE_DOEP0CTL_EPEN   %1 31 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DOEP0CTL_EPD   %1 30 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_EPD    Endpoint disable
: USBFS_DEVICE_DOEP0CTL_SNAK   %1 27 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_SNAK    Set NAK
: USBFS_DEVICE_DOEP0CTL_CNAK   %1 26 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_CNAK    Clear NAK
: USBFS_DEVICE_DOEP0CTL_STALL   %1 21 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_STALL    STALL handshake
: USBFS_DEVICE_DOEP0CTL_SNOOP   %1 20 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_SNOOP    Snoop mode
: USBFS_DEVICE_DOEP0CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DOEP0CTL_NAKS   %1 17 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_NAKS    NAK status
: USBFS_DEVICE_DOEP0CTL_EPACT   %1 15 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_EPACT    Endpoint active
: USBFS_DEVICE_DOEP0CTL_MPL   ( %XX -- ) 0 lshift USBFS_DEVICE_DOEP0CTL bis! ;  \ USBFS_DEVICE_DOEP0CTL_MPL    Maximum packet length

\ USBFS_DEVICE_DOEP1CTL ()
: USBFS_DEVICE_DOEP1CTL_EPEN   %1 31 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DOEP1CTL_EPD   %1 30 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_EPD    Endpoint disable
: USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM   %1 29 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM    SD1PID/SODDFRM
: USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM   %1 28 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM    SD0PID/SEVENFRM
: USBFS_DEVICE_DOEP1CTL_SNAK   %1 27 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_SNAK    Set NAK
: USBFS_DEVICE_DOEP1CTL_CNAK   %1 26 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_CNAK    Clear NAK
: USBFS_DEVICE_DOEP1CTL_STALL   %1 21 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_STALL    STALL handshake
: USBFS_DEVICE_DOEP1CTL_SNOOP   %1 20 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_SNOOP    Snoop mode
: USBFS_DEVICE_DOEP1CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DOEP1CTL_NAKS   %1 17 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_NAKS    NAK status
: USBFS_DEVICE_DOEP1CTL_EOFRM_DPID   %1 16 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_EOFRM_DPID    EOFRM/DPID
: USBFS_DEVICE_DOEP1CTL_EPACT   %1 15 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_EPACT    Endpoint active
: USBFS_DEVICE_DOEP1CTL_MPL  0 lshift USBFS_DEVICE_DOEP1CTL bis! ;  \ USBFS_DEVICE_DOEP1CTL_MPL    maximum packet length

\ USBFS_DEVICE_DOEP2CTL ()
: USBFS_DEVICE_DOEP2CTL_EPEN   %1 31 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DOEP2CTL_EPD   %1 30 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_EPD    Endpoint disable
: USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM   %1 29 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM    SD1PID/SODDFRM
: USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM   %1 28 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM    SD0PID/SEVENFRM
: USBFS_DEVICE_DOEP2CTL_SNAK   %1 27 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_SNAK    Set NAK
: USBFS_DEVICE_DOEP2CTL_CNAK   %1 26 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_CNAK    Clear NAK
: USBFS_DEVICE_DOEP2CTL_STALL   %1 21 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_STALL    STALL handshake
: USBFS_DEVICE_DOEP2CTL_SNOOP   %1 20 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_SNOOP    Snoop mode
: USBFS_DEVICE_DOEP2CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DOEP2CTL_NAKS   %1 17 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_NAKS    NAK status
: USBFS_DEVICE_DOEP2CTL_EOFRM_DPID   %1 16 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_EOFRM_DPID    EOFRM/DPID
: USBFS_DEVICE_DOEP2CTL_EPACT   %1 15 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_EPACT    Endpoint active
: USBFS_DEVICE_DOEP2CTL_MPL  0 lshift USBFS_DEVICE_DOEP2CTL bis! ;  \ USBFS_DEVICE_DOEP2CTL_MPL    maximum packet length

\ USBFS_DEVICE_DOEP3CTL ()
: USBFS_DEVICE_DOEP3CTL_EPEN   %1 31 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_EPEN    Endpoint enable
: USBFS_DEVICE_DOEP3CTL_EPD   %1 30 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_EPD    Endpoint disable
: USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM   %1 29 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM    SD1PID/SODDFRM
: USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM   %1 28 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM    SD0PID/SEVENFRM
: USBFS_DEVICE_DOEP3CTL_SNAK   %1 27 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_SNAK    Set NAK
: USBFS_DEVICE_DOEP3CTL_CNAK   %1 26 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_CNAK    Clear NAK
: USBFS_DEVICE_DOEP3CTL_STALL   %1 21 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_STALL    STALL handshake
: USBFS_DEVICE_DOEP3CTL_SNOOP   %1 20 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_SNOOP    Snoop mode
: USBFS_DEVICE_DOEP3CTL_EPTYPE   ( %XX -- ) 18 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_EPTYPE    Endpoint type
: USBFS_DEVICE_DOEP3CTL_NAKS   %1 17 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_NAKS    NAK status
: USBFS_DEVICE_DOEP3CTL_EOFRM_DPID   %1 16 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_EOFRM_DPID    EOFRM/DPID
: USBFS_DEVICE_DOEP3CTL_EPACT   %1 15 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_EPACT    Endpoint active
: USBFS_DEVICE_DOEP3CTL_MPL  0 lshift USBFS_DEVICE_DOEP3CTL bis! ;  \ USBFS_DEVICE_DOEP3CTL_MPL    maximum packet length

\ USBFS_DEVICE_DIEP0INTF ()
: USBFS_DEVICE_DIEP0INTF_TXFE   %1 7 lshift USBFS_DEVICE_DIEP0INTF bis! ;  \ USBFS_DEVICE_DIEP0INTF_TXFE    Transmit FIFO empty
: USBFS_DEVICE_DIEP0INTF_IEPNE   %1 6 lshift USBFS_DEVICE_DIEP0INTF bis! ;  \ USBFS_DEVICE_DIEP0INTF_IEPNE    IN endpoint NAK effective
: USBFS_DEVICE_DIEP0INTF_EPTXFUD   %1 4 lshift USBFS_DEVICE_DIEP0INTF bis! ;  \ USBFS_DEVICE_DIEP0INTF_EPTXFUD    Endpoint Tx FIFO underrun
: USBFS_DEVICE_DIEP0INTF_CITO   %1 3 lshift USBFS_DEVICE_DIEP0INTF bis! ;  \ USBFS_DEVICE_DIEP0INTF_CITO    Control in timeout interrupt
: USBFS_DEVICE_DIEP0INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DIEP0INTF bis! ;  \ USBFS_DEVICE_DIEP0INTF_EPDIS    Endpoint finished
: USBFS_DEVICE_DIEP0INTF_TF   %1 0 lshift USBFS_DEVICE_DIEP0INTF bis! ;  \ USBFS_DEVICE_DIEP0INTF_TF    Transfer finished

\ USBFS_DEVICE_DIEP1INTF ()
: USBFS_DEVICE_DIEP1INTF_TXFE   %1 7 lshift USBFS_DEVICE_DIEP1INTF bis! ;  \ USBFS_DEVICE_DIEP1INTF_TXFE    Transmit FIFO empty
: USBFS_DEVICE_DIEP1INTF_IEPNE   %1 6 lshift USBFS_DEVICE_DIEP1INTF bis! ;  \ USBFS_DEVICE_DIEP1INTF_IEPNE    IN endpoint NAK effective
: USBFS_DEVICE_DIEP1INTF_EPTXFUD   %1 4 lshift USBFS_DEVICE_DIEP1INTF bis! ;  \ USBFS_DEVICE_DIEP1INTF_EPTXFUD    Endpoint Tx FIFO underrun
: USBFS_DEVICE_DIEP1INTF_CITO   %1 3 lshift USBFS_DEVICE_DIEP1INTF bis! ;  \ USBFS_DEVICE_DIEP1INTF_CITO    Control in timeout interrupt
: USBFS_DEVICE_DIEP1INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DIEP1INTF bis! ;  \ USBFS_DEVICE_DIEP1INTF_EPDIS    Endpoint finished
: USBFS_DEVICE_DIEP1INTF_TF   %1 0 lshift USBFS_DEVICE_DIEP1INTF bis! ;  \ USBFS_DEVICE_DIEP1INTF_TF    Transfer finished

\ USBFS_DEVICE_DIEP2INTF ()
: USBFS_DEVICE_DIEP2INTF_TXFE   %1 7 lshift USBFS_DEVICE_DIEP2INTF bis! ;  \ USBFS_DEVICE_DIEP2INTF_TXFE    Transmit FIFO empty
: USBFS_DEVICE_DIEP2INTF_IEPNE   %1 6 lshift USBFS_DEVICE_DIEP2INTF bis! ;  \ USBFS_DEVICE_DIEP2INTF_IEPNE    IN endpoint NAK effective
: USBFS_DEVICE_DIEP2INTF_EPTXFUD   %1 4 lshift USBFS_DEVICE_DIEP2INTF bis! ;  \ USBFS_DEVICE_DIEP2INTF_EPTXFUD    Endpoint Tx FIFO underrun
: USBFS_DEVICE_DIEP2INTF_CITO   %1 3 lshift USBFS_DEVICE_DIEP2INTF bis! ;  \ USBFS_DEVICE_DIEP2INTF_CITO    Control in timeout interrupt
: USBFS_DEVICE_DIEP2INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DIEP2INTF bis! ;  \ USBFS_DEVICE_DIEP2INTF_EPDIS    Endpoint finished
: USBFS_DEVICE_DIEP2INTF_TF   %1 0 lshift USBFS_DEVICE_DIEP2INTF bis! ;  \ USBFS_DEVICE_DIEP2INTF_TF    Transfer finished

\ USBFS_DEVICE_DIEP3INTF ()
: USBFS_DEVICE_DIEP3INTF_TXFE   %1 7 lshift USBFS_DEVICE_DIEP3INTF bis! ;  \ USBFS_DEVICE_DIEP3INTF_TXFE    Transmit FIFO empty
: USBFS_DEVICE_DIEP3INTF_IEPNE   %1 6 lshift USBFS_DEVICE_DIEP3INTF bis! ;  \ USBFS_DEVICE_DIEP3INTF_IEPNE    IN endpoint NAK effective
: USBFS_DEVICE_DIEP3INTF_EPTXFUD   %1 4 lshift USBFS_DEVICE_DIEP3INTF bis! ;  \ USBFS_DEVICE_DIEP3INTF_EPTXFUD    Endpoint Tx FIFO underrun
: USBFS_DEVICE_DIEP3INTF_CITO   %1 3 lshift USBFS_DEVICE_DIEP3INTF bis! ;  \ USBFS_DEVICE_DIEP3INTF_CITO    Control in timeout interrupt
: USBFS_DEVICE_DIEP3INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DIEP3INTF bis! ;  \ USBFS_DEVICE_DIEP3INTF_EPDIS    Endpoint finished
: USBFS_DEVICE_DIEP3INTF_TF   %1 0 lshift USBFS_DEVICE_DIEP3INTF bis! ;  \ USBFS_DEVICE_DIEP3INTF_TF    Transfer finished

\ USBFS_DEVICE_DOEP0INTF (read-write)
: USBFS_DEVICE_DOEP0INTF_BTBSTP   %1 6 lshift USBFS_DEVICE_DOEP0INTF bis! ;  \ USBFS_DEVICE_DOEP0INTF_BTBSTP    Back-to-back SETUP packets
: USBFS_DEVICE_DOEP0INTF_EPRXFOVR   %1 4 lshift USBFS_DEVICE_DOEP0INTF bis! ;  \ USBFS_DEVICE_DOEP0INTF_EPRXFOVR    Endpoint Rx FIFO overrun
: USBFS_DEVICE_DOEP0INTF_STPF   %1 3 lshift USBFS_DEVICE_DOEP0INTF bis! ;  \ USBFS_DEVICE_DOEP0INTF_STPF    Setup phase finished
: USBFS_DEVICE_DOEP0INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DOEP0INTF bis! ;  \ USBFS_DEVICE_DOEP0INTF_EPDIS    Endpoint disabled
: USBFS_DEVICE_DOEP0INTF_TF   %1 0 lshift USBFS_DEVICE_DOEP0INTF bis! ;  \ USBFS_DEVICE_DOEP0INTF_TF    Transfer finished

\ USBFS_DEVICE_DOEP1INTF (read-write)
: USBFS_DEVICE_DOEP1INTF_BTBSTP   %1 6 lshift USBFS_DEVICE_DOEP1INTF bis! ;  \ USBFS_DEVICE_DOEP1INTF_BTBSTP    Back-to-back SETUP packets
: USBFS_DEVICE_DOEP1INTF_EPRXFOVR   %1 4 lshift USBFS_DEVICE_DOEP1INTF bis! ;  \ USBFS_DEVICE_DOEP1INTF_EPRXFOVR    Endpoint Rx FIFO overrun
: USBFS_DEVICE_DOEP1INTF_STPF   %1 3 lshift USBFS_DEVICE_DOEP1INTF bis! ;  \ USBFS_DEVICE_DOEP1INTF_STPF    Setup phase finished
: USBFS_DEVICE_DOEP1INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DOEP1INTF bis! ;  \ USBFS_DEVICE_DOEP1INTF_EPDIS    Endpoint disabled
: USBFS_DEVICE_DOEP1INTF_TF   %1 0 lshift USBFS_DEVICE_DOEP1INTF bis! ;  \ USBFS_DEVICE_DOEP1INTF_TF    Transfer finished

\ USBFS_DEVICE_DOEP2INTF (read-write)
: USBFS_DEVICE_DOEP2INTF_BTBSTP   %1 6 lshift USBFS_DEVICE_DOEP2INTF bis! ;  \ USBFS_DEVICE_DOEP2INTF_BTBSTP    Back-to-back SETUP packets
: USBFS_DEVICE_DOEP2INTF_EPRXFOVR   %1 4 lshift USBFS_DEVICE_DOEP2INTF bis! ;  \ USBFS_DEVICE_DOEP2INTF_EPRXFOVR    Endpoint Rx FIFO overrun
: USBFS_DEVICE_DOEP2INTF_STPF   %1 3 lshift USBFS_DEVICE_DOEP2INTF bis! ;  \ USBFS_DEVICE_DOEP2INTF_STPF    Setup phase finished
: USBFS_DEVICE_DOEP2INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DOEP2INTF bis! ;  \ USBFS_DEVICE_DOEP2INTF_EPDIS    Endpoint disabled
: USBFS_DEVICE_DOEP2INTF_TF   %1 0 lshift USBFS_DEVICE_DOEP2INTF bis! ;  \ USBFS_DEVICE_DOEP2INTF_TF    Transfer finished

\ USBFS_DEVICE_DOEP3INTF (read-write)
: USBFS_DEVICE_DOEP3INTF_BTBSTP   %1 6 lshift USBFS_DEVICE_DOEP3INTF bis! ;  \ USBFS_DEVICE_DOEP3INTF_BTBSTP    Back-to-back SETUP packets
: USBFS_DEVICE_DOEP3INTF_EPRXFOVR   %1 4 lshift USBFS_DEVICE_DOEP3INTF bis! ;  \ USBFS_DEVICE_DOEP3INTF_EPRXFOVR    Endpoint Rx FIFO overrun
: USBFS_DEVICE_DOEP3INTF_STPF   %1 3 lshift USBFS_DEVICE_DOEP3INTF bis! ;  \ USBFS_DEVICE_DOEP3INTF_STPF    Setup phase finished
: USBFS_DEVICE_DOEP3INTF_EPDIS   %1 1 lshift USBFS_DEVICE_DOEP3INTF bis! ;  \ USBFS_DEVICE_DOEP3INTF_EPDIS    Endpoint disabled
: USBFS_DEVICE_DOEP3INTF_TF   %1 0 lshift USBFS_DEVICE_DOEP3INTF bis! ;  \ USBFS_DEVICE_DOEP3INTF_TF    Transfer finished

\ USBFS_DEVICE_DIEP0LEN (read-write)
: USBFS_DEVICE_DIEP0LEN_PCNT   ( %XX -- ) 19 lshift USBFS_DEVICE_DIEP0LEN bis! ;  \ USBFS_DEVICE_DIEP0LEN_PCNT    Packet count
: USBFS_DEVICE_DIEP0LEN_TLEN   ( %XXXXXXX -- ) 0 lshift USBFS_DEVICE_DIEP0LEN bis! ;  \ USBFS_DEVICE_DIEP0LEN_TLEN    Transfer length

\ USBFS_DEVICE_DOEP0LEN (read-write)
: USBFS_DEVICE_DOEP0LEN_STPCNT   ( %XX -- ) 29 lshift USBFS_DEVICE_DOEP0LEN bis! ;  \ USBFS_DEVICE_DOEP0LEN_STPCNT    SETUP packet count
: USBFS_DEVICE_DOEP0LEN_PCNT   %1 19 lshift USBFS_DEVICE_DOEP0LEN bis! ;  \ USBFS_DEVICE_DOEP0LEN_PCNT    Packet count
: USBFS_DEVICE_DOEP0LEN_TLEN   ( %XXXXXXX -- ) 0 lshift USBFS_DEVICE_DOEP0LEN bis! ;  \ USBFS_DEVICE_DOEP0LEN_TLEN    Transfer length

\ USBFS_DEVICE_DIEP1LEN (read-write)
: USBFS_DEVICE_DIEP1LEN_MCPF   ( %XX -- ) 29 lshift USBFS_DEVICE_DIEP1LEN bis! ;  \ USBFS_DEVICE_DIEP1LEN_MCPF    Multi packet count per frame
: USBFS_DEVICE_DIEP1LEN_PCNT  19 lshift USBFS_DEVICE_DIEP1LEN bis! ;  \ USBFS_DEVICE_DIEP1LEN_PCNT    Packet count
: USBFS_DEVICE_DIEP1LEN_TLEN  0 lshift USBFS_DEVICE_DIEP1LEN bis! ;  \ USBFS_DEVICE_DIEP1LEN_TLEN    Transfer length

\ USBFS_DEVICE_DIEP2LEN (read-write)
: USBFS_DEVICE_DIEP2LEN_MCPF   ( %XX -- ) 29 lshift USBFS_DEVICE_DIEP2LEN bis! ;  \ USBFS_DEVICE_DIEP2LEN_MCPF    Multi packet count per frame
: USBFS_DEVICE_DIEP2LEN_PCNT  19 lshift USBFS_DEVICE_DIEP2LEN bis! ;  \ USBFS_DEVICE_DIEP2LEN_PCNT    Packet count
: USBFS_DEVICE_DIEP2LEN_TLEN  0 lshift USBFS_DEVICE_DIEP2LEN bis! ;  \ USBFS_DEVICE_DIEP2LEN_TLEN    Transfer length

\ USBFS_DEVICE_DIEP3LEN (read-write)
: USBFS_DEVICE_DIEP3LEN_MCPF   ( %XX -- ) 29 lshift USBFS_DEVICE_DIEP3LEN bis! ;  \ USBFS_DEVICE_DIEP3LEN_MCPF    Multi packet count per frame
: USBFS_DEVICE_DIEP3LEN_PCNT  19 lshift USBFS_DEVICE_DIEP3LEN bis! ;  \ USBFS_DEVICE_DIEP3LEN_PCNT    Packet count
: USBFS_DEVICE_DIEP3LEN_TLEN  0 lshift USBFS_DEVICE_DIEP3LEN bis! ;  \ USBFS_DEVICE_DIEP3LEN_TLEN    Transfer length

\ USBFS_DEVICE_DOEP1LEN (read-write)
: USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID   ( %XX -- ) 29 lshift USBFS_DEVICE_DOEP1LEN bis! ;  \ USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID    SETUP packet count/Received data PID
: USBFS_DEVICE_DOEP1LEN_PCNT  19 lshift USBFS_DEVICE_DOEP1LEN bis! ;  \ USBFS_DEVICE_DOEP1LEN_PCNT    Packet count
: USBFS_DEVICE_DOEP1LEN_TLEN  0 lshift USBFS_DEVICE_DOEP1LEN bis! ;  \ USBFS_DEVICE_DOEP1LEN_TLEN    Transfer length

\ USBFS_DEVICE_DOEP2LEN (read-write)
: USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID   ( %XX -- ) 29 lshift USBFS_DEVICE_DOEP2LEN bis! ;  \ USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID    SETUP packet count/Received data PID
: USBFS_DEVICE_DOEP2LEN_PCNT  19 lshift USBFS_DEVICE_DOEP2LEN bis! ;  \ USBFS_DEVICE_DOEP2LEN_PCNT    Packet count
: USBFS_DEVICE_DOEP2LEN_TLEN  0 lshift USBFS_DEVICE_DOEP2LEN bis! ;  \ USBFS_DEVICE_DOEP2LEN_TLEN    Transfer length

\ USBFS_DEVICE_DOEP3LEN (read-write)
: USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID   ( %XX -- ) 29 lshift USBFS_DEVICE_DOEP3LEN bis! ;  \ USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID    SETUP packet count/Received data PID
: USBFS_DEVICE_DOEP3LEN_PCNT  19 lshift USBFS_DEVICE_DOEP3LEN bis! ;  \ USBFS_DEVICE_DOEP3LEN_PCNT    Packet count
: USBFS_DEVICE_DOEP3LEN_TLEN  0 lshift USBFS_DEVICE_DOEP3LEN bis! ;  \ USBFS_DEVICE_DOEP3LEN_TLEN    Transfer length

\ USBFS_DEVICE_DIEP0TFSTAT (read-only)
: USBFS_DEVICE_DIEP0TFSTAT_IEPTFS   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_DEVICE_DIEP0TFSTAT bis! ;  \ USBFS_DEVICE_DIEP0TFSTAT_IEPTFS    IN endpoint TxFIFO space  remaining

\ USBFS_DEVICE_DIEP1TFSTAT (read-only)
: USBFS_DEVICE_DIEP1TFSTAT_IEPTFS   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_DEVICE_DIEP1TFSTAT bis! ;  \ USBFS_DEVICE_DIEP1TFSTAT_IEPTFS    IN endpoint TxFIFO space  remaining

\ USBFS_DEVICE_DIEP2TFSTAT (read-only)
: USBFS_DEVICE_DIEP2TFSTAT_IEPTFS   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_DEVICE_DIEP2TFSTAT bis! ;  \ USBFS_DEVICE_DIEP2TFSTAT_IEPTFS    IN endpoint TxFIFO space  remaining

\ USBFS_DEVICE_DIEP3TFSTAT (read-only)
: USBFS_DEVICE_DIEP3TFSTAT_IEPTFS   ( %XXXXXXXXXXXXXXXX -- ) 0 lshift USBFS_DEVICE_DIEP3TFSTAT bis! ;  \ USBFS_DEVICE_DIEP3TFSTAT_IEPTFS    IN endpoint TxFIFO space  remaining

\ USBFS_PWRCLK_PWRCLKCTL (read-write)
: USBFS_PWRCLK_PWRCLKCTL_SUCLK   %1 0 lshift USBFS_PWRCLK_PWRCLKCTL bis! ;  \ USBFS_PWRCLK_PWRCLKCTL_SUCLK    Stop the USB clock
: USBFS_PWRCLK_PWRCLKCTL_SHCLK   %1 1 lshift USBFS_PWRCLK_PWRCLKCTL bis! ;  \ USBFS_PWRCLK_PWRCLKCTL_SHCLK    Stop HCLK

\ WWDGT_CTL (read-write)
: WWDGT_CTL_WDGTEN   %1 7 lshift WWDGT_CTL bis! ;  \ WWDGT_CTL_WDGTEN    Activation bit
: WWDGT_CTL_CNT   ( %XXXXXXX -- ) 0 lshift WWDGT_CTL bis! ;  \ WWDGT_CTL_CNT    7-bit counter

\ WWDGT_CFG (read-write)
: WWDGT_CFG_EWIE   %1 9 lshift WWDGT_CFG bis! ;  \ WWDGT_CFG_EWIE    Early wakeup interrupt
: WWDGT_CFG_PSC   ( %XX -- ) 7 lshift WWDGT_CFG bis! ;  \ WWDGT_CFG_PSC    Prescaler
: WWDGT_CFG_WIN   ( %XXXXXXX -- ) 0 lshift WWDGT_CFG bis! ;  \ WWDGT_CFG_WIN    7-bit window value

\ WWDGT_STAT (read-write)
: WWDGT_STAT_EWIF   %1 0 lshift WWDGT_STAT bis! ;  \ WWDGT_STAT_EWIF    Early wakeup interrupt  flag
