@ arm-none-eabi-as equates file for GD32VF103
@ SVD2GAS Equates Generator, Copyright Terry Porter 2017 "terry@tjporter.com.au" for arm-none-eabi-as 
@ Matthias Koch Complimentary Edition 2017
@ Takes a CMSIS-SVD file plus a hand edited config.xml file as input 
@ Licensed under the GPL, see http://www.gnu.org/licenses/


@=========================== ADC0 ===========================@
.equ ADC0_BASE, 0x40012400 @ (Analog to digital converter) 
    .equ ADC0_STAT, ADC0_BASE + 0x0 @ (status register) 
        .equ ADC0_STRC_Shift, 4   @ bitWidth 1 (Start flag of regular channel group)  
        .equ ADC0_STIC_Shift, 3   @ bitWidth 1 (Start flag of inserted channel group)  
        .equ ADC0_EOIC_Shift, 2   @ bitWidth 1 (End of inserted group conversion flag)  
        .equ ADC0_EOC_Shift, 1   @ bitWidth 1 (End of group conversion flag)  
        .equ ADC0_WDE_Shift, 0   @ bitWidth 1 (Analog watchdog event flag)  
 
    .equ ADC0_CTL0, ADC0_BASE + 0x04 @ (control register 0) 
        .equ ADC0_RWDEN_Shift, 23   @ bitWidth 1 (Regular channel analog watchdog enable)  
        .equ ADC0_IWDEN_Shift, 22   @ bitWidth 1 (Inserted channel analog watchdog  	 enable)  
        .equ ADC0_SYNCM_Shift, 16   @ bitWidth 4 (sync mode selection)  
        .equ ADC0_DISNUM_Shift, 13   @ bitWidth 3 (Number of conversions in  	 discontinuous mode)  
        .equ ADC0_DISIC_Shift, 12   @ bitWidth 1 (Discontinuous mode on  	 inserted channels)  
        .equ ADC0_DISRC_Shift, 11   @ bitWidth 1 (Discontinuous mode on regular  channels)  
        .equ ADC0_ICA_Shift, 10   @ bitWidth 1 (Inserted channel group convert  	 automatically)  
        .equ ADC0_WDSC_Shift, 9   @ bitWidth 1 (When in scan mode, analog watchdog 	 is effective on a single channel)  
        .equ ADC0_SM_Shift, 8   @ bitWidth 1 (Scan mode)  
        .equ ADC0_EOICIE_Shift, 7   @ bitWidth 1 (Interrupt enable for EOIC)  
        .equ ADC0_WDEIE_Shift, 6   @ bitWidth 1 (Interrupt enable for WDE)  
        .equ ADC0_EOCIE_Shift, 5   @ bitWidth 1 (Interrupt enable for EOC)  
        .equ ADC0_WDCHSEL_Shift, 0   @ bitWidth 5 (Analog watchdog channel select)  
 
    .equ ADC0_CTL1, ADC0_BASE + 0x08 @ (control register 1) 
        .equ ADC0_TSVREN_Shift, 23   @ bitWidth 1 (Channel 16 and 17 enable of ADC0)  
        .equ ADC0_SWRCST_Shift, 22   @ bitWidth 1 (Start on regular channel)  
        .equ ADC0_SWICST_Shift, 21   @ bitWidth 1 (Start on inserted channel)  
        .equ ADC0_ETERC_Shift, 20   @ bitWidth 1 (External trigger enable for regular channel)  
        .equ ADC0_ETSRC_Shift, 17   @ bitWidth 3 (External trigger select for regular channel)  
        .equ ADC0_ETEIC_Shift, 15   @ bitWidth 1 (External trigger select for inserted channel)  
        .equ ADC0_ETSIC_Shift, 12   @ bitWidth 3 (External trigger select for inserted channel)  
        .equ ADC0_DAL_Shift, 11   @ bitWidth 1 (Data alignment)  
        .equ ADC0_DMA_Shift, 8   @ bitWidth 1 (DMA request enable)  
        .equ ADC0_RSTCLB_Shift, 3   @ bitWidth 1 (Reset calibration)  
        .equ ADC0_CLB_Shift, 2   @ bitWidth 1 (ADC calibration)  
        .equ ADC0_CTN_Shift, 1   @ bitWidth 1 (Continuous mode)  
        .equ ADC0_ADCON_Shift, 0   @ bitWidth 1 (ADC on)  
 
    .equ ADC0_SAMPT0, ADC0_BASE + 0x0C @ (Sample time register 0) 
        .equ ADC0_SPT10_Shift, 0   @ bitWidth 3 (Channel 10 sample time  selection)  
        .equ ADC0_SPT11_Shift, 3   @ bitWidth 3 (Channel 11 sample time  selection)  
        .equ ADC0_SPT12_Shift, 6   @ bitWidth 3 (Channel 12 sample time  selection)  
        .equ ADC0_SPT13_Shift, 9   @ bitWidth 3 (Channel 13 sample time  selection)  
        .equ ADC0_SPT14_Shift, 12   @ bitWidth 3 (Channel 14 sample time  selection)  
        .equ ADC0_SPT15_Shift, 15   @ bitWidth 3 (Channel 15 sample time  selection)  
        .equ ADC0_SPT16_Shift, 18   @ bitWidth 3 (Channel 16 sample time  selection)  
        .equ ADC0_SPT17_Shift, 21   @ bitWidth 3 (Channel 17 sample time  selection)  
 
    .equ ADC0_SAMPT1, ADC0_BASE + 0x10 @ (Sample time register 1) 
        .equ ADC0_SPT0_Shift, 0   @ bitWidth 3 (Channel 0 sample time  selection)  
        .equ ADC0_SPT1_Shift, 3   @ bitWidth 3 (Channel 1 sample time  selection)  
        .equ ADC0_SPT2_Shift, 6   @ bitWidth 3 (Channel 2 sample time  selection)  
        .equ ADC0_SPT3_Shift, 9   @ bitWidth 3 (Channel 3 sample time  selection)  
        .equ ADC0_SPT4_Shift, 12   @ bitWidth 3 (Channel 4 sample time  selection)  
        .equ ADC0_SPT5_Shift, 15   @ bitWidth 3 (Channel 5 sample time  selection)  
        .equ ADC0_SPT6_Shift, 18   @ bitWidth 3 (Channel 6 sample time  selection)  
        .equ ADC0_SPT7_Shift, 21   @ bitWidth 3 (Channel 7 sample time  selection)  
        .equ ADC0_SPT8_Shift, 24   @ bitWidth 3 (Channel 8 sample time  selection)  
        .equ ADC0_SPT9_Shift, 27   @ bitWidth 3 (Channel 9 sample time  selection)  
 
    .equ ADC0_IOFF0, ADC0_BASE + 0x14 @ (Inserted channel data offset register  0) 
        .equ ADC0_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  0)  
 
    .equ ADC0_IOFF1, ADC0_BASE + 0x18 @ (Inserted channel data offset register  1) 
        .equ ADC0_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  1)  
 
    .equ ADC0_IOFF2, ADC0_BASE + 0x1C @ (Inserted channel data offset register  2) 
        .equ ADC0_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  2)  
 
    .equ ADC0_IOFF3, ADC0_BASE + 0x20 @ (Inserted channel data offset register  3) 
        .equ ADC0_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  3)  
 
    .equ ADC0_WDHT, ADC0_BASE + 0x24 @ (watchdog higher threshold  register) 
        .equ ADC0_WDHT_Shift, 0   @ bitWidth 12 (Analog watchdog higher  threshold)  
 
    .equ ADC0_WDLT, ADC0_BASE + 0x28 @ (watchdog lower threshold  register) 
        .equ ADC0_WDLT_Shift, 0   @ bitWidth 12 (Analog watchdog lower  threshold)  
 
    .equ ADC0_RSQ0, ADC0_BASE + 0x2C @ (regular sequence register 0) 
        .equ ADC0_RL_Shift, 20   @ bitWidth 4 (Regular channel group  length)  
        .equ ADC0_RSQ15_Shift, 15   @ bitWidth 5 (16th conversion in regular  sequence)  
        .equ ADC0_RSQ14_Shift, 10   @ bitWidth 5 (15th conversion in regular  sequence)  
        .equ ADC0_RSQ13_Shift, 5   @ bitWidth 5 (14th conversion in regular  sequence)  
        .equ ADC0_RSQ12_Shift, 0   @ bitWidth 5 (13th conversion in regular  sequence)  
 
    .equ ADC0_RSQ1, ADC0_BASE + 0x30 @ (regular sequence register 1) 
        .equ ADC0_RSQ11_Shift, 25   @ bitWidth 5 (12th conversion in regular  sequence)  
        .equ ADC0_RSQ10_Shift, 20   @ bitWidth 5 (11th conversion in regular  sequence)  
        .equ ADC0_RSQ9_Shift, 15   @ bitWidth 5 (10th conversion in regular  sequence)  
        .equ ADC0_RSQ8_Shift, 10   @ bitWidth 5 (9th conversion in regular  sequence)  
        .equ ADC0_RSQ7_Shift, 5   @ bitWidth 5 (8th conversion in regular  sequence)  
        .equ ADC0_RSQ6_Shift, 0   @ bitWidth 5 (7th conversion in regular  sequence)  
 
    .equ ADC0_RSQ2, ADC0_BASE + 0x34 @ (regular sequence register 2) 
        .equ ADC0_RSQ5_Shift, 25   @ bitWidth 5 (6th conversion in regular  sequence)  
        .equ ADC0_RSQ4_Shift, 20   @ bitWidth 5 (5th conversion in regular  sequence)  
        .equ ADC0_RSQ3_Shift, 15   @ bitWidth 5 (4th conversion in regular  sequence)  
        .equ ADC0_RSQ2_Shift, 10   @ bitWidth 5 (3rd conversion in regular  sequence)  
        .equ ADC0_RSQ1_Shift, 5   @ bitWidth 5 (2nd conversion in regular  sequence)  
        .equ ADC0_RSQ0_Shift, 0   @ bitWidth 5 (1st conversion in regular  sequence)  
 
    .equ ADC0_ISQ, ADC0_BASE + 0x38 @ (Inserted sequence register) 
        .equ ADC0_IL_Shift, 20   @ bitWidth 2 (Inserted channel group length)  
        .equ ADC0_ISQ3_Shift, 15   @ bitWidth 5 (4th conversion in inserted  sequence)  
        .equ ADC0_ISQ2_Shift, 10   @ bitWidth 5 (3rd conversion in inserted  sequence)  
        .equ ADC0_ISQ1_Shift, 5   @ bitWidth 5 (2nd conversion in inserted  sequence)  
        .equ ADC0_ISQ0_Shift, 0   @ bitWidth 5 (1st conversion in inserted  sequence)  
 
    .equ ADC0_IDATA0, ADC0_BASE + 0x3C @ (Inserted data register 0) 
        .equ ADC0_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_IDATA1, ADC0_BASE + 0x40 @ (Inserted data register 1) 
        .equ ADC0_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_IDATA2, ADC0_BASE + 0x44 @ (Inserted data register 2) 
        .equ ADC0_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_IDATA3, ADC0_BASE + 0x48 @ (Inserted data register 3) 
        .equ ADC0_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_RDATA, ADC0_BASE + 0x4C @ (regular data register) 
        .equ ADC0_ADC1RDTR_Shift, 16   @ bitWidth 16 (ADC regular channel data)  
        .equ ADC0_RDATA_Shift, 0   @ bitWidth 16 (Regular channel data)  
 
    .equ ADC0_OVSAMPCTL, ADC0_BASE + 0x80 @ (Oversample control register) 
        .equ ADC0_DRES_Shift, 12   @ bitWidth 2 (ADC resolution)  
        .equ ADC0_TOVS_Shift, 9   @ bitWidth 1 (Triggered Oversampling)  
        .equ ADC0_OVSS_Shift, 5   @ bitWidth 4 (Oversampling shift)  
        .equ ADC0_OVSR_Shift, 2   @ bitWidth 3 (Oversampling ratio)  
        .equ ADC0_OVSEN_Shift, 0   @ bitWidth 1 (Oversampler Enable)  
 

@=========================== ADC1 ===========================@
.equ ADC1_BASE, 0x40012800 @ (Analog to digital converter) 
    .equ ADC1_STAT, ADC1_BASE + 0x0 @ (status register) 
        .equ ADC1_STRC_Shift, 4   @ bitWidth 1 (Start flag of regular channel group)  
        .equ ADC1_STIC_Shift, 3   @ bitWidth 1 (Start flag of inserted channel group)  
        .equ ADC1_EOIC_Shift, 2   @ bitWidth 1 (End of inserted group conversion flag)  
        .equ ADC1_EOC_Shift, 1   @ bitWidth 1 (End of group conversion flag)  
        .equ ADC1_WDE_Shift, 0   @ bitWidth 1 (Analog watchdog event flag)  
 
    .equ ADC1_CTL0, ADC1_BASE + 0x4 @ (control register 0) 
        .equ ADC1_RWDEN_Shift, 23   @ bitWidth 1 (Regular channel analog watchdog  	 enable)  
        .equ ADC1_IWDEN_Shift, 22   @ bitWidth 1 (Inserted channel analog watchdog  	 enable)  
        .equ ADC1_DISNUM_Shift, 13   @ bitWidth 3 (Number of conversions in  	 discontinuous mode)  
        .equ ADC1_DISIC_Shift, 12   @ bitWidth 1 (Discontinuous mode on  	 inserted channels)  
        .equ ADC1_DISRC_Shift, 11   @ bitWidth 1 (Discontinuous mode on regular  channels)  
        .equ ADC1_ICA_Shift, 10   @ bitWidth 1 (Inserted channel group convert  	 automatically)  
        .equ ADC1_WDSC_Shift, 9   @ bitWidth 1 (When in scan mode, analog watchdog 	 is effective on a single channel)  
        .equ ADC1_SM_Shift, 8   @ bitWidth 1 (Scan mode)  
        .equ ADC1_EOICIE_Shift, 7   @ bitWidth 1 (Interrupt enable for EOIC)  
        .equ ADC1_WDEIE_Shift, 6   @ bitWidth 1 (Interrupt enable for WDE)  
        .equ ADC1_EOCIE_Shift, 5   @ bitWidth 1 (Interrupt enable for EOC)  
        .equ ADC1_WDCHSEL_Shift, 0   @ bitWidth 5 (Analog watchdog channel select)  
 
    .equ ADC1_CTL1, ADC1_BASE + 0x08 @ (control register 1) 
        .equ ADC1_SWRCST_Shift, 22   @ bitWidth 1 (Start on regular channel)  
        .equ ADC1_SWICST_Shift, 21   @ bitWidth 1 (Start on inserted channel)  
        .equ ADC1_ETERC_Shift, 20   @ bitWidth 1 (External trigger enable for regular channel)  
        .equ ADC1_ETSRC_Shift, 17   @ bitWidth 3 (External trigger select for regular channel)  
        .equ ADC1_ETEIC_Shift, 15   @ bitWidth 1 (External trigger enable for inserted channel)  
        .equ ADC1_ETSIC_Shift, 12   @ bitWidth 3 (External trigger select for inserted channel)  
        .equ ADC1_DAL_Shift, 11   @ bitWidth 1 (Data alignment)  
        .equ ADC1_DMA_Shift, 8   @ bitWidth 1 (DMA request enable)  
        .equ ADC1_RSTCLB_Shift, 3   @ bitWidth 1 (Reset calibration)  
        .equ ADC1_CLB_Shift, 2   @ bitWidth 1 (ADC calibration)  
        .equ ADC1_CTN_Shift, 1   @ bitWidth 1 (Continuous mode)  
        .equ ADC1_ADCON_Shift, 0   @ bitWidth 1 (ADC on)  
 
    .equ ADC1_SAMPT0, ADC1_BASE + 0x0C @ (Sample time register 0) 
        .equ ADC1_SPT10_Shift, 0   @ bitWidth 3 (Channel 10 sample time  selection)  
        .equ ADC1_SPT11_Shift, 3   @ bitWidth 3 (Channel 11 sample time  selection)  
        .equ ADC1_SPT12_Shift, 6   @ bitWidth 3 (Channel 12 sample time  selection)  
        .equ ADC1_SPT13_Shift, 9   @ bitWidth 3 (Channel 13 sample time  selection)  
        .equ ADC1_SPT14_Shift, 12   @ bitWidth 3 (Channel 14 sample time  selection)  
        .equ ADC1_SPT15_Shift, 15   @ bitWidth 3 (Channel 15 sample time  selection)  
        .equ ADC1_SPT16_Shift, 18   @ bitWidth 3 (Channel 16 sample time  selection)  
        .equ ADC1_SPT17_Shift, 21   @ bitWidth 3 (Channel 17 sample time  selection)  
 
    .equ ADC1_SAMPT1, ADC1_BASE + 0x10 @ (Sample time register 1) 
        .equ ADC1_SPT0_Shift, 0   @ bitWidth 3 (Channel 0 sample time  selection)  
        .equ ADC1_SPT1_Shift, 3   @ bitWidth 3 (Channel 1 sample time  selection)  
        .equ ADC1_SPT2_Shift, 6   @ bitWidth 3 (Channel 2 sample time  selection)  
        .equ ADC1_SPT3_Shift, 9   @ bitWidth 3 (Channel 3 sample time  selection)  
        .equ ADC1_SPT4_Shift, 12   @ bitWidth 3 (Channel 4 sample time  selection)  
        .equ ADC1_SPT5_Shift, 15   @ bitWidth 3 (Channel 5 sample time  selection)  
        .equ ADC1_SPT6_Shift, 18   @ bitWidth 3 (Channel 6 sample time  selection)  
        .equ ADC1_SPT7_Shift, 21   @ bitWidth 3 (Channel 7 sample time  selection)  
        .equ ADC1_SPT8_Shift, 24   @ bitWidth 3 (Channel 8 sample time  selection)  
        .equ ADC1_SPT9_Shift, 27   @ bitWidth 3 (Channel 9 sample time  selection)  
 
    .equ ADC1_IOFF0, ADC1_BASE + 0x14 @ (Inserted channel data offset register  0) 
        .equ ADC1_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  0)  
 
    .equ ADC1_IOFF1, ADC1_BASE + 0x18 @ (Inserted channel data offset register  1) 
        .equ ADC1_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  1)  
 
    .equ ADC1_IOFF2, ADC1_BASE + 0x1C @ (Inserted channel data offset register  2) 
        .equ ADC1_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  2)  
 
    .equ ADC1_IOFF3, ADC1_BASE + 0x20 @ (Inserted channel data offset register  3) 
        .equ ADC1_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  3)  
 
    .equ ADC1_WDHT, ADC1_BASE + 0x24 @ (watchdog higher threshold  register) 
        .equ ADC1_WDHT_Shift, 0   @ bitWidth 12 (Analog watchdog higher  threshold)  
 
    .equ ADC1_WDLT, ADC1_BASE + 0x28 @ (watchdog lower threshold  register) 
        .equ ADC1_WDLT_Shift, 0   @ bitWidth 12 (Analog watchdog lower  threshold)  
 
    .equ ADC1_RSQ0, ADC1_BASE + 0x2C @ (regular sequence register 0) 
        .equ ADC1_RL_Shift, 20   @ bitWidth 4 (Regular channel group  length)  
        .equ ADC1_RSQ15_Shift, 15   @ bitWidth 5 (16th conversion in regular  sequence)  
        .equ ADC1_RSQ14_Shift, 10   @ bitWidth 5 (15th conversion in regular  sequence)  
        .equ ADC1_RSQ13_Shift, 5   @ bitWidth 5 (14th conversion in regular  sequence)  
        .equ ADC1_RSQ12_Shift, 0   @ bitWidth 5 (13th conversion in regular  sequence)  
 
    .equ ADC1_RSQ1, ADC1_BASE + 0x30 @ (regular sequence register 1) 
        .equ ADC1_RSQ11_Shift, 25   @ bitWidth 5 (12th conversion in regular  sequence)  
        .equ ADC1_RSQ10_Shift, 20   @ bitWidth 5 (11th conversion in regular  sequence)  
        .equ ADC1_RSQ9_Shift, 15   @ bitWidth 5 (10th conversion in regular  sequence)  
        .equ ADC1_RSQ8_Shift, 10   @ bitWidth 5 (9th conversion in regular  sequence)  
        .equ ADC1_RSQ7_Shift, 5   @ bitWidth 5 (8th conversion in regular  sequence)  
        .equ ADC1_RSQ6_Shift, 0   @ bitWidth 5 (7th conversion in regular  sequence)  
 
    .equ ADC1_RSQ2, ADC1_BASE + 0x34 @ (regular sequence register 2) 
        .equ ADC1_RSQ5_Shift, 25   @ bitWidth 5 (6th conversion in regular  sequence)  
        .equ ADC1_RSQ4_Shift, 20   @ bitWidth 5 (5th conversion in regular  sequence)  
        .equ ADC1_RSQ3_Shift, 15   @ bitWidth 5 (4th conversion in regular  sequence)  
        .equ ADC1_RSQ2_Shift, 10   @ bitWidth 5 (3rd conversion in regular  sequence)  
        .equ ADC1_RSQ1_Shift, 5   @ bitWidth 5 (2nd conversion in regular  sequence)  
        .equ ADC1_RSQ0_Shift, 0   @ bitWidth 5 (1st conversion in regular  sequence)  
 
    .equ ADC1_ISQ, ADC1_BASE + 0x38 @ (Inserted sequence register) 
        .equ ADC1_IL_Shift, 20   @ bitWidth 2 (Inserted channel group length)  
        .equ ADC1_ISQ3_Shift, 15   @ bitWidth 5 (4th conversion in inserted  sequence)  
        .equ ADC1_ISQ2_Shift, 10   @ bitWidth 5 (3rd conversion in inserted  sequence)  
        .equ ADC1_ISQ1_Shift, 5   @ bitWidth 5 (2nd conversion in inserted  sequence)  
        .equ ADC1_ISQ0_Shift, 0   @ bitWidth 5 (1st conversion in inserted  sequence)  
 
    .equ ADC1_IDATA0, ADC1_BASE + 0x3C @ (Inserted data register 0) 
        .equ ADC1_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_IDATA1, ADC1_BASE + 0x40 @ (Inserted data register 1) 
        .equ ADC1_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_IDATA2, ADC1_BASE + 0x44 @ (Inserted data register 2) 
        .equ ADC1_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_IDATA3, ADC1_BASE + 0x48 @ (Inserted data register 3) 
        .equ ADC1_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_RDATA, ADC1_BASE + 0x4C @ (regular data register) 
        .equ ADC1_RDATA_Shift, 0   @ bitWidth 16 (Regular channel data)  
 

@=========================== AFIO ===========================@
.equ AFIO_BASE, 0x40010000 @ (Alternate-function I/Os) 
    .equ AFIO_EC, AFIO_BASE + 0x0 @ (Event control register) 
        .equ AFIO_EOE_Shift, 7   @ bitWidth 1 (Event output enable)  
        .equ AFIO_PORT_Shift, 4   @ bitWidth 3 (Event output port selection)  
        .equ AFIO_PIN_Shift, 0   @ bitWidth 4 (Event output pin selection)  
 
    .equ AFIO_PCF0, AFIO_BASE + 0x04 @ (AFIO port configuration register 0) 
        .equ AFIO_TIMER1ITI1_REMAP_Shift, 29   @ bitWidth 1 (TIMER1 internal trigger 1 remapping)  
        .equ AFIO_SPI2_REMAP_Shift, 28   @ bitWidth 1 ( SPI2/I2S2 remapping)  
        .equ AFIO_SWJ_CFG_Shift, 24   @ bitWidth 3 (Serial wire JTAG configuration)  
        .equ AFIO_CAN1_REMAP_Shift, 22   @ bitWidth 1 (CAN1 I/O remapping)  
        .equ AFIO_TIMER4CH3_IREMAP_Shift, 16   @ bitWidth 1 (TIMER4 channel3 internal remapping)  
        .equ AFIO_PD01_REMAP_Shift, 15   @ bitWidth 1 (Port D0/Port D1 mapping on OSC_IN/OSC_OUT)  
        .equ AFIO_CAN0_REMAP_Shift, 13   @ bitWidth 2 (CAN0 alternate interface remapping)  
        .equ AFIO_TIMER3_REMAP_Shift, 12   @ bitWidth 1 (TIMER3 remapping)  
        .equ AFIO_TIMER2_REMAP_Shift, 10   @ bitWidth 2 (TIMER2 remapping)  
        .equ AFIO_TIMER1_REMAP_Shift, 8   @ bitWidth 2 (TIMER1 remapping)  
        .equ AFIO_TIMER0_REMAP_Shift, 6   @ bitWidth 2 (TIMER0 remapping)  
        .equ AFIO_USART2_REMAP_Shift, 4   @ bitWidth 2 (USART2 remapping)  
        .equ AFIO_USART1_REMAP_Shift, 3   @ bitWidth 1 (USART1 remapping)  
        .equ AFIO_USART0_REMAP_Shift, 2   @ bitWidth 1 (USART0 remapping)  
        .equ AFIO_I2C0_REMAP_Shift, 1   @ bitWidth 1 (I2C0 remapping)  
        .equ AFIO_SPI0_REMAP_Shift, 0   @ bitWidth 1 (SPI0 remapping)  
 
    .equ AFIO_EXTISS0, AFIO_BASE + 0x08 @ (EXTI sources selection register 0) 
        .equ AFIO_EXTI3_SS_Shift, 12   @ bitWidth 4 (EXTI 3 sources selection)  
        .equ AFIO_EXTI2_SS_Shift, 8   @ bitWidth 4 (EXTI 2 sources selection)  
        .equ AFIO_EXTI1_SS_Shift, 4   @ bitWidth 4 (EXTI 1 sources selection)  
        .equ AFIO_EXTI0_SS_Shift, 0   @ bitWidth 4 (EXTI 0 sources selection)  
 
    .equ AFIO_EXTISS1, AFIO_BASE + 0x0C @ (EXTI sources selection register 1) 
        .equ AFIO_EXTI7_SS_Shift, 12   @ bitWidth 4 (EXTI 7 sources selection)  
        .equ AFIO_EXTI6_SS_Shift, 8   @ bitWidth 4 (EXTI 6 sources selection)  
        .equ AFIO_EXTI5_SS_Shift, 4   @ bitWidth 4 (EXTI 5 sources selection)  
        .equ AFIO_EXTI4_SS_Shift, 0   @ bitWidth 4 (EXTI 4 sources selection)  
 
    .equ AFIO_EXTISS2, AFIO_BASE + 0x10 @ (EXTI sources selection register 2) 
        .equ AFIO_EXTI11_SS_Shift, 12   @ bitWidth 4 (EXTI 11 sources selection)  
        .equ AFIO_EXTI10_SS_Shift, 8   @ bitWidth 4 (EXTI 10 sources selection)  
        .equ AFIO_EXTI9_SS_Shift, 4   @ bitWidth 4 (EXTI 9 sources selection)  
        .equ AFIO_EXTI8_SS_Shift, 0   @ bitWidth 4 (EXTI 8 sources selection)  
 
    .equ AFIO_EXTISS3, AFIO_BASE + 0x14 @ (EXTI sources selection register 3) 
        .equ AFIO_EXTI15_SS_Shift, 12   @ bitWidth 4 (EXTI 15 sources selection)  
        .equ AFIO_EXTI14_SS_Shift, 8   @ bitWidth 4 (EXTI 14 sources selection)  
        .equ AFIO_EXTI13_SS_Shift, 4   @ bitWidth 4 (EXTI 13 sources selection)  
        .equ AFIO_EXTI12_SS_Shift, 0   @ bitWidth 4 (EXTI 12 sources selection)  
 
    .equ AFIO_PCF1, AFIO_BASE + 0x1C @ (AFIO port configuration register 1) 
        .equ AFIO_EXMC_NADV_Shift, 10   @ bitWidth 1 (EXMC_NADV connect/disconnect)  
 

@=========================== BKP ===========================@
.equ BKP_BASE, 0x40006C00 @ (Backup registers) 
    .equ BKP_DATA0, BKP_BASE + 0x4 @ (Backup data register 0) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA1, BKP_BASE + 0x8 @ (Backup data register 1) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA2, BKP_BASE + 0xC @ (Backup data register 2) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA3, BKP_BASE + 0x10 @ (Backup data register 3) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA4, BKP_BASE + 0x14 @ (Backup data register 4) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA5, BKP_BASE + 0x18 @ (Backup data register 5) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA6, BKP_BASE + 0x1C @ (Backup data register 6) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA7, BKP_BASE + 0x20 @ (Backup data register 7) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA8, BKP_BASE + 0x24 @ (Backup data register 8) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA9, BKP_BASE + 0x28 @ (Backup data register 9) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA10, BKP_BASE + 0x40 @ (Backup data register 10) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA11, BKP_BASE + 0x44 @ (Backup data register 11) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA12, BKP_BASE + 0x48 @ (Backup data register 12) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA13, BKP_BASE + 0x4C @ (Backup data register 13) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA14, BKP_BASE + 0x50 @ (Backup data register 14) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA15, BKP_BASE + 0x54 @ (Backup data register 15) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA16, BKP_BASE + 0x58 @ (Backup data register 16) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA17, BKP_BASE + 0x5C @ (Backup data register 17) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA18, BKP_BASE + 0x60 @ (Backup data register 18) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA19, BKP_BASE + 0x64 @ (Backup data register 19) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA20, BKP_BASE + 0x68 @ (Backup data register 20) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA21, BKP_BASE + 0x6C @ (Backup data register 21) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA22, BKP_BASE + 0x70 @ (Backup data register 22) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA23, BKP_BASE + 0x74 @ (Backup data register 23) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA24, BKP_BASE + 0x78 @ (Backup data register 24) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA25, BKP_BASE + 0x7C @ (Backup data register 25) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA26, BKP_BASE + 0x80 @ (Backup data register 26) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA27, BKP_BASE + 0x84 @ (Backup data register 27) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA28, BKP_BASE + 0x88 @ (Backup data register 28) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA29, BKP_BASE + 0x8C @ (Backup data register 29) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA30, BKP_BASE + 0x90 @ (Backup data register 30) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA31, BKP_BASE + 0x94 @ (Backup data register 31) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA32, BKP_BASE + 0x98 @ (Backup data register 32) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA33, BKP_BASE + 0x9C @ (Backup data register 33) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA34, BKP_BASE + 0xA0 @ (Backup data register 34) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA35, BKP_BASE + 0xA4 @ (Backup data register 35) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA36, BKP_BASE + 0xA8 @ (Backup data register 36) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA37, BKP_BASE + 0xAC @ (Backup data register 37) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA38, BKP_BASE + 0xB0 @ (Backup data register 38) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA39, BKP_BASE + 0xB4 @ (Backup data register 39) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA40, BKP_BASE + 0xB8 @ (Backup data register 40) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA41, BKP_BASE + 0xBC @ (Backup data register 41) 
        .equ BKP_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_OCTL, BKP_BASE + 0x2C @ (RTC signal output control register) 
        .equ BKP_ROSEL_Shift, 9   @ bitWidth 1 (RTC output selection)  
        .equ BKP_ASOEN_Shift, 8   @ bitWidth 1 (RTC alarm or second signal output enable)  
        .equ BKP_COEN_Shift, 7   @ bitWidth 1 (RTC clock calibration output enable)  
        .equ BKP_RCCV_Shift, 0   @ bitWidth 7 (RTC clock calibration value)  
 
    .equ BKP_TPCTL, BKP_BASE + 0x30 @ (Tamper pin control register) 
        .equ BKP_TPAL_Shift, 1   @ bitWidth 1 (TAMPER pin active level)  
        .equ BKP_TPEN_Shift, 0   @ bitWidth 1 (TAMPER detection enable)  
 
    .equ BKP_TPCS, BKP_BASE + 0x34 @ (Tamper control and status register) 
        .equ BKP_TIF_Shift, 9   @ bitWidth 1 (Tamper interrupt flag)  
        .equ BKP_TEF_Shift, 8   @ bitWidth 1 (Tamper event flag)  
        .equ BKP_TPIE_Shift, 2   @ bitWidth 1 (Tamper interrupt enable)  
        .equ BKP_TIR_Shift, 1   @ bitWidth 1 (Tamper interrupt reset)  
        .equ BKP_TER_Shift, 0   @ bitWidth 1 (Tamper event reset)  
 

@=========================== CAN0 ===========================@
.equ CAN0_BASE, 0x40006400 @ (Controller area network) 
    .equ CAN0_CTL, CAN0_BASE + 0x0 @ (Control register) 
        .equ CAN0_DFZ_Shift, 16   @ bitWidth 1 (Debug freeze)  
        .equ CAN0_SWRST_Shift, 15   @ bitWidth 1 (Software reset)  
        .equ CAN0_TTC_Shift, 7   @ bitWidth 1 (Time-triggered communication)  
        .equ CAN0_ABOR_Shift, 6   @ bitWidth 1 (Automatic bus-off recovery)  
        .equ CAN0_AWU_Shift, 5   @ bitWidth 1 (Automatic wakeup)  
        .equ CAN0_ARD_Shift, 4   @ bitWidth 1 (Automatic retransmission disable)  
        .equ CAN0_RFOD_Shift, 3   @ bitWidth 1 (Receive FIFO overwrite disable)  
        .equ CAN0_TFO_Shift, 2   @ bitWidth 1 (Transmit FIFO order)  
        .equ CAN0_SLPWMOD_Shift, 1   @ bitWidth 1 (Sleep working mode)  
        .equ CAN0_IWMOD_Shift, 0   @ bitWidth 1 (Initial working mode)  
 
    .equ CAN0_STAT, CAN0_BASE + 0x04 @ (Status register) 
        .equ CAN0_RXL_Shift, 11   @ bitWidth 1 (RX level)  
        .equ CAN0_LASTRX_Shift, 10   @ bitWidth 1 (Last sample value of RX pin)  
        .equ CAN0_RS_Shift, 9   @ bitWidth 1 (Receiving state)  
        .equ CAN0_TS_Shift, 8   @ bitWidth 1 (Transmitting state)  
        .equ CAN0_SLPIF_Shift, 4   @ bitWidth 1 (Status change interrupt flag of sleep  	 working mode entering)  
        .equ CAN0_WUIF_Shift, 3   @ bitWidth 1 (Status change interrupt flag of wakeup  	 from sleep working mode)  
        .equ CAN0_ERRIF_Shift, 2   @ bitWidth 1 (Error interrupt flag)  
        .equ CAN0_SLPWS_Shift, 1   @ bitWidth 1 (Sleep working state)  
        .equ CAN0_IWS_Shift, 0   @ bitWidth 1 (Initial working state)  
 
    .equ CAN0_TSTAT, CAN0_BASE + 0x8 @ (Transmit status register) 
        .equ CAN0_TMLS2_Shift, 31   @ bitWidth 1 (Transmit mailbox 2 last sending  	 in transmit FIFO)  
        .equ CAN0_TMLS1_Shift, 30   @ bitWidth 1 (Transmit mailbox 1 last sending  	 in transmit FIFO)  
        .equ CAN0_TMLS0_Shift, 29   @ bitWidth 1 (Transmit mailbox 0 last sending  	 in transmit FIFO)  
        .equ CAN0_TME2_Shift, 28   @ bitWidth 1 (Transmit mailbox 2 empty)  
        .equ CAN0_TME1_Shift, 27   @ bitWidth 1 (Transmit mailbox 1 empty)  
        .equ CAN0_TME0_Shift, 26   @ bitWidth 1 (Transmit mailbox 0 empty)  
        .equ CAN0_NUM_Shift, 24   @ bitWidth 2 (number of the transmit FIFO mailbox in  	 which the frame will be transmitted if at least one mailbox is empty)  
        .equ CAN0_MST2_Shift, 23   @ bitWidth 1 (Mailbox 2 stop transmitting)  
        .equ CAN0_MTE2_Shift, 19   @ bitWidth 1 (Mailbox 2 transmit error)  
        .equ CAN0_MAL2_Shift, 18   @ bitWidth 1 (Mailbox 2 arbitration lost)  
        .equ CAN0_MTFNERR2_Shift, 17   @ bitWidth 1 (Mailbox 2 transmit finished and no error)  
        .equ CAN0_MTF2_Shift, 16   @ bitWidth 1 (Mailbox 2 transmit finished)  
        .equ CAN0_MST1_Shift, 15   @ bitWidth 1 (Mailbox 1 stop transmitting)  
        .equ CAN0_MTE1_Shift, 11   @ bitWidth 1 (Mailbox 1 transmit error)  
        .equ CAN0_MAL1_Shift, 10   @ bitWidth 1 (Mailbox 1 arbitration lost)  
        .equ CAN0_MTFNERR1_Shift, 9   @ bitWidth 1 (Mailbox 1 transmit finished and no error)  
        .equ CAN0_MTF1_Shift, 8   @ bitWidth 1 (Mailbox 1 transmit finished)  
        .equ CAN0_MST0_Shift, 7   @ bitWidth 1 (Mailbox 0 stop transmitting)  
        .equ CAN0_MTE0_Shift, 3   @ bitWidth 1 (Mailbox 0 transmit error)  
        .equ CAN0_MAL0_Shift, 2   @ bitWidth 1 (Mailbox 0 arbitration lost)  
        .equ CAN0_MTFNERR0_Shift, 1   @ bitWidth 1 (Mailbox 0 transmit finished and no error)  
        .equ CAN0_MTF0_Shift, 0   @ bitWidth 1 (Mailbox 0 transmit finished)  
 
    .equ CAN0_RFIFO0, CAN0_BASE + 0x0C @ (Receive message FIFO0 register) 
        .equ CAN0_RFD0_Shift, 5   @ bitWidth 1 (Receive FIFO0 dequeue)  
        .equ CAN0_RFO0_Shift, 4   @ bitWidth 1 (Receive FIFO0 overfull)  
        .equ CAN0_RFF0_Shift, 3   @ bitWidth 1 (Receive FIFO0 full)  
        .equ CAN0_RFL0_Shift, 0   @ bitWidth 2 (Receive FIFO0 length)  
 
    .equ CAN0_RFIFO1, CAN0_BASE + 0x10 @ (Receive message FIFO1 register) 
        .equ CAN0_RFD1_Shift, 5   @ bitWidth 1 (Receive FIFO1 dequeue)  
        .equ CAN0_RFO1_Shift, 4   @ bitWidth 1 (Receive FIFO1 overfull)  
        .equ CAN0_RFF1_Shift, 3   @ bitWidth 1 (Receive FIFO1 full)  
        .equ CAN0_RFL1_Shift, 0   @ bitWidth 2 (Receive FIFO1 length)  
 
    .equ CAN0_INTEN, CAN0_BASE + 0x14 @ (Interrupt enable register) 
        .equ CAN0_SLPWIE_Shift, 17   @ bitWidth 1 (Sleep working interrupt enable)  
        .equ CAN0_WIE_Shift, 16   @ bitWidth 1 (Wakeup interrupt enable)  
        .equ CAN0_ERRIE_Shift, 15   @ bitWidth 1 (Error interrupt enable)  
        .equ CAN0_ERRNIE_Shift, 11   @ bitWidth 1 (Error number interrupt enable)  
        .equ CAN0_BOIE_Shift, 10   @ bitWidth 1 (Bus-off interrupt enable)  
        .equ CAN0_PERRIE_Shift, 9   @ bitWidth 1 (Passive error interrupt enable)  
        .equ CAN0_WERRIE_Shift, 8   @ bitWidth 1 (Warning error interrupt enable)  
        .equ CAN0_RFOIE1_Shift, 6   @ bitWidth 1 (Receive FIFO1 overfull interrupt enable)  
        .equ CAN0_RFFIE1_Shift, 5   @ bitWidth 1 (Receive FIFO1 full interrupt enable)  
        .equ CAN0_RFNEIE1_Shift, 4   @ bitWidth 1 (Receive FIFO1 not empty interrupt enable)  
        .equ CAN0_RFOIE0_Shift, 3   @ bitWidth 1 (Receive FIFO0 overfull interrupt enable)  
        .equ CAN0_RFFIE0_Shift, 2   @ bitWidth 1 (Receive FIFO0 full interrupt enable)  
        .equ CAN0_RFNEIE0_Shift, 1   @ bitWidth 1 (Receive FIFO0 not empty interrupt enable)  
        .equ CAN0_TMEIE_Shift, 0   @ bitWidth 1 (Transmit mailbox empty interrupt enable)  
 
    .equ CAN0_ERR, CAN0_BASE + 0x18 @ (Error register) 
        .equ CAN0_RECNT_Shift, 24   @ bitWidth 8 (Receive Error Count defined  	 by the CAN standard)  
        .equ CAN0_TECNT_Shift, 16   @ bitWidth 8 (Transmit Error Count defined  	 by the CAN standard)  
        .equ CAN0_ERRN_Shift, 4   @ bitWidth 3 (Error number)  
        .equ CAN0_BOERR_Shift, 2   @ bitWidth 1 (Bus-off error)  
        .equ CAN0_PERR_Shift, 1   @ bitWidth 1 (Passive error)  
        .equ CAN0_WERR_Shift, 0   @ bitWidth 1 (Warning error)  
 
    .equ CAN0_BT, CAN0_BASE + 0x1C @ (Bit timing register) 
        .equ CAN0_SCMOD_Shift, 31   @ bitWidth 1 (Silent communication mode)  
        .equ CAN0_LCMOD_Shift, 30   @ bitWidth 1 (Loopback communication mode)  
        .equ CAN0_SJW_Shift, 24   @ bitWidth 2 (Resynchronization jump width)  
        .equ CAN0_BS2_Shift, 20   @ bitWidth 3 (Bit segment 2)  
        .equ CAN0_BS1_Shift, 16   @ bitWidth 4 (Bit segment 1)  
        .equ CAN0_BAUDPSC_Shift, 0   @ bitWidth 10 (Baud rate prescaler)  
 
    .equ CAN0_TMI0, CAN0_BASE + 0x180 @ (Transmit mailbox identifier register 0) 
        .equ CAN0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_FT_Shift, 1   @ bitWidth 1 (Frame type)  
        .equ CAN0_TEN_Shift, 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN0_TMP0, CAN0_BASE + 0x184 @ (Transmit mailbox property register 0) 
        .equ CAN0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_TSEN_Shift, 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_TMDATA00, CAN0_BASE + 0x188 @ (Transmit mailbox data0 register) 
        .equ CAN0_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_TMDATA10, CAN0_BASE + 0x18C @ (Transmit mailbox data1 register) 
        .equ CAN0_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_TMI1, CAN0_BASE + 0x190 @ (Transmit mailbox identifier register 1) 
        .equ CAN0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_FT_Shift, 1   @ bitWidth 1 (Frame type)  
        .equ CAN0_TEN_Shift, 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN0_TMP1, CAN0_BASE + 0x194 @ (Transmit mailbox property register 1) 
        .equ CAN0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_TSEN_Shift, 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_TMDATA01, CAN0_BASE + 0x198 @ (Transmit mailbox data0 register) 
        .equ CAN0_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_TMDATA11, CAN0_BASE + 0x19C @ (Transmit mailbox data1 register) 
        .equ CAN0_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_TMI2, CAN0_BASE + 0x1A0 @ (Transmit mailbox identifier register 2) 
        .equ CAN0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_FT_Shift, 1   @ bitWidth 1 (Frame type)  
        .equ CAN0_TEN_Shift, 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN0_TMP2, CAN0_BASE + 0x1A4 @ (Transmit mailbox property register 2) 
        .equ CAN0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_TSEN_Shift, 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_TMDATA02, CAN0_BASE + 0x1A8 @ (Transmit mailbox data0 register) 
        .equ CAN0_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_TMDATA12, CAN0_BASE + 0x1AC @ (Transmit mailbox data1 register) 
        .equ CAN0_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_RFIFOMI0, CAN0_BASE + 0x1B0 @ (Receive FIFO mailbox identifier register) 
        .equ CAN0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_FT_Shift, 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN0_RFIFOMP0, CAN0_BASE + 0x1B4 @ (Receive FIFO0 mailbox property register) 
        .equ CAN0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_RFIFOMDATA00, CAN0_BASE + 0x1B8 @ (Receive FIFO0 mailbox data0 register) 
        .equ CAN0_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_RFIFOMDATA10, CAN0_BASE + 0x1BC @ (Receive FIFO0 mailbox data1 register) 
        .equ CAN0_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_RFIFOMI1, CAN0_BASE + 0x1C0 @ (Receive FIFO1 mailbox identifier register) 
        .equ CAN0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_FT_Shift, 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN0_RFIFOMP1, CAN0_BASE + 0x1C4 @ (Receive FIFO1 mailbox property register) 
        .equ CAN0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_RFIFOMDATA01, CAN0_BASE + 0x1C8 @ (Receive FIFO1 mailbox data0 register) 
        .equ CAN0_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_RFIFOMDATA11, CAN0_BASE + 0x1CC @ (Receive FIFO1 mailbox data1 register) 
        .equ CAN0_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_FCTL, CAN0_BASE + 0x200 @ (Filter control register) 
        .equ CAN0_HBC1F_Shift, 8   @ bitWidth 6 (Header bank of CAN1 filter)  
        .equ CAN0_FLD_Shift, 0   @ bitWidth 1 (Filter lock disable)  
 
    .equ CAN0_FMCFG, CAN0_BASE + 0x204 @ (Filter mode configuration register) 
        .equ CAN0_FMOD27_Shift, 27   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD26_Shift, 26   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD25_Shift, 25   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD24_Shift, 24   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD23_Shift, 23   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD22_Shift, 22   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD21_Shift, 21   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD20_Shift, 20   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD19_Shift, 19   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD18_Shift, 18   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD17_Shift, 17   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD16_Shift, 16   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD15_Shift, 15   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD14_Shift, 14   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD13_Shift, 13   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD12_Shift, 12   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD11_Shift, 11   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD10_Shift, 10   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD9_Shift, 9   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD8_Shift, 8   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD7_Shift, 7   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD6_Shift, 6   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD5_Shift, 5   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD4_Shift, 4   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD3_Shift, 3   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD2_Shift, 2   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD1_Shift, 1   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMOD0_Shift, 0   @ bitWidth 1 (Filter mode)  
 
    .equ CAN0_FSCFG, CAN0_BASE + 0x20C @ (Filter scale configuration register) 
        .equ CAN0_FS0_Shift, 0   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS1_Shift, 1   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS2_Shift, 2   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS3_Shift, 3   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS4_Shift, 4   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS5_Shift, 5   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS6_Shift, 6   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS7_Shift, 7   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS8_Shift, 8   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS9_Shift, 9   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS10_Shift, 10   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS11_Shift, 11   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS12_Shift, 12   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS13_Shift, 13   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS14_Shift, 14   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS15_Shift, 15   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS16_Shift, 16   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS17_Shift, 17   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS18_Shift, 18   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS19_Shift, 19   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS20_Shift, 20   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS21_Shift, 21   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS22_Shift, 22   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS23_Shift, 23   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS24_Shift, 24   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS25_Shift, 25   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS26_Shift, 26   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FS27_Shift, 27   @ bitWidth 1 (Filter scale configuration)  
 
    .equ CAN0_FAFIFO, CAN0_BASE + 0x214 @ (Filter associated FIFO register) 
        .equ CAN0_FAF0_Shift, 0   @ bitWidth 1 (Filter 0 associated with FIFO)  
        .equ CAN0_FAF1_Shift, 1   @ bitWidth 1 (Filter 1 associated with FIFO)  
        .equ CAN0_FAF2_Shift, 2   @ bitWidth 1 (Filter 2 associated with FIFO)  
        .equ CAN0_FAF3_Shift, 3   @ bitWidth 1 (Filter 3 associated with FIFO)  
        .equ CAN0_FAF4_Shift, 4   @ bitWidth 1 (Filter 4 associated with FIFO)  
        .equ CAN0_FAF5_Shift, 5   @ bitWidth 1 (Filter 5 associated with FIFO)  
        .equ CAN0_FAF6_Shift, 6   @ bitWidth 1 (Filter 6 associated with FIFO)  
        .equ CAN0_FAF7_Shift, 7   @ bitWidth 1 (Filter 7 associated with FIFO)  
        .equ CAN0_FAF8_Shift, 8   @ bitWidth 1 (Filter 8 associated with FIFO)  
        .equ CAN0_FAF9_Shift, 9   @ bitWidth 1 (Filter 9 associated with FIFO)  
        .equ CAN0_FAF10_Shift, 10   @ bitWidth 1 (Filter 10 associated with FIFO)  
        .equ CAN0_FAF11_Shift, 11   @ bitWidth 1 (Filter 11 associated with FIFO)  
        .equ CAN0_FAF12_Shift, 12   @ bitWidth 1 (Filter 12 associated with FIFO)  
        .equ CAN0_FAF13_Shift, 13   @ bitWidth 1 (Filter 13 associated with FIFO)  
        .equ CAN0_FAF14_Shift, 14   @ bitWidth 1 (Filter 14 associated with FIFO)  
        .equ CAN0_FAF15_Shift, 15   @ bitWidth 1 (Filter 15 associated with FIFO)  
        .equ CAN0_FAF16_Shift, 16   @ bitWidth 1 (Filter 16 associated with FIFO)  
        .equ CAN0_FAF17_Shift, 17   @ bitWidth 1 (Filter 17 associated with FIFO)  
        .equ CAN0_FAF18_Shift, 18   @ bitWidth 1 (Filter 18 associated with FIFO)  
        .equ CAN0_FAF19_Shift, 19   @ bitWidth 1 (Filter 19 associated with FIFO)  
        .equ CAN0_FAF20_Shift, 20   @ bitWidth 1 (Filter 20 associated with FIFO)  
        .equ CAN0_FAF21_Shift, 21   @ bitWidth 1 (Filter 21 associated with FIFO)  
        .equ CAN0_FAF22_Shift, 22   @ bitWidth 1 (Filter 22 associated with FIFO)  
        .equ CAN0_FAF23_Shift, 23   @ bitWidth 1 (Filter 23 associated with FIFO)  
        .equ CAN0_FAF24_Shift, 24   @ bitWidth 1 (Filter 24 associated with FIFO)  
        .equ CAN0_FAF25_Shift, 25   @ bitWidth 1 (Filter 25 associated with FIFO)  
        .equ CAN0_FAF26_Shift, 26   @ bitWidth 1 (Filter 26 associated with FIFO)  
        .equ CAN0_FAF27_Shift, 27   @ bitWidth 1 (Filter 27 associated with FIFO)  
 
    .equ CAN0_FW, CAN0_BASE + 0x21C @ (Filter working register) 
        .equ CAN0_FW0_Shift, 0   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW1_Shift, 1   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW2_Shift, 2   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW3_Shift, 3   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW4_Shift, 4   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW5_Shift, 5   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW6_Shift, 6   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW7_Shift, 7   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW8_Shift, 8   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW9_Shift, 9   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW10_Shift, 10   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW11_Shift, 11   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW12_Shift, 12   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW13_Shift, 13   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW14_Shift, 14   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW15_Shift, 15   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW16_Shift, 16   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW17_Shift, 17   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW18_Shift, 18   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW19_Shift, 19   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW20_Shift, 20   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW21_Shift, 21   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW22_Shift, 22   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW23_Shift, 23   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW24_Shift, 24   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW25_Shift, 25   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW26_Shift, 26   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW27_Shift, 27   @ bitWidth 1 (Filter working)  
 
    .equ CAN0_F0DATA0, CAN0_BASE + 0x240 @ (Filter 0 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F0DATA1, CAN0_BASE + 0x244 @ (Filter 0 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F1DATA0, CAN0_BASE + 0x248 @ (Filter 1 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F1DATA1, CAN0_BASE + 0x24C @ (Filter 1 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F2DATA0, CAN0_BASE + 0x250 @ (Filter 2 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F2DATA1, CAN0_BASE + 0x254 @ (Filter 2 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F3DATA0, CAN0_BASE + 0x258 @ (Filter 3 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F3DATA1, CAN0_BASE + 0x25C @ (Filter 3 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F4DATA0, CAN0_BASE + 0x260 @ (Filter 4 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F4DATA1, CAN0_BASE + 0x264 @ (Filter 4 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F5DATA0, CAN0_BASE + 0x268 @ (Filter 5 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F5DATA1, CAN0_BASE + 0x26C @ (Filter 5 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F6DATA0, CAN0_BASE + 0x270 @ (Filter 6 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F6DATA1, CAN0_BASE + 0x274 @ (Filter 6 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F7DATA0, CAN0_BASE + 0x278 @ (Filter 7 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F7DATA1, CAN0_BASE + 0x27C @ (Filter 7 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F8DATA0, CAN0_BASE + 0x280 @ (Filter 8 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F8DATA1, CAN0_BASE + 0x284 @ (Filter 8 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F9DATA0, CAN0_BASE + 0x288 @ (Filter 9 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F9DATA1, CAN0_BASE + 0x28C @ (Filter 9 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F10DATA0, CAN0_BASE + 0x290 @ (Filter 10 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F10DATA1, CAN0_BASE + 0x294 @ (Filter 10 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F11DATA0, CAN0_BASE + 0x298 @ (Filter 11 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F11DATA1, CAN0_BASE + 0x29C @ (Filter 11 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F12DATA0, CAN0_BASE + 0x2A0 @ (Filter 12 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F12DATA1, CAN0_BASE + 0x2A4 @ (Filter 12 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F13DATA0, CAN0_BASE + 0x2A8 @ (Filter 13 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F13DATA1, CAN0_BASE + 0x2AC @ (Filter 13 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F14DATA0, CAN0_BASE + 0x2B0 @ (Filter 14 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F14DATA1, CAN0_BASE + 0x2B4 @ (Filter 14 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F15DATA0, CAN0_BASE + 0x2B8 @ (Filter 15 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F15DATA1, CAN0_BASE + 0x2BC @ (Filter 15 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F16DATA0, CAN0_BASE + 0x2C0 @ (Filter 16 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F16DATA1, CAN0_BASE + 0x2C4 @ (Filter 16 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F17DATA0, CAN0_BASE + 0x2C8 @ (Filter 17 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F17DATA1, CAN0_BASE + 0x2CC @ (Filter 17 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F18DATA0, CAN0_BASE + 0x2D0 @ (Filter 18 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F18DATA1, CAN0_BASE + 0x2D4 @ (Filter 18 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F19DATA0, CAN0_BASE + 0x2D8 @ (Filter 19 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F19DATA1, CAN0_BASE + 0x2DC @ (Filter 19 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F20DATA0, CAN0_BASE + 0x2E0 @ (Filter 20 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F20DATA1, CAN0_BASE + 0x2E4 @ (Filter 20 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F21DATA0, CAN0_BASE + 0x2E8 @ (Filter 21 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F21DATA1, CAN0_BASE + 0x2EC @ (Filter 21 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F22DATA0, CAN0_BASE + 0x2F0 @ (Filter 22 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F22DATA1, CAN0_BASE + 0x2F4 @ (Filter 22 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F23DATA0, CAN0_BASE + 0x2F8 @ (Filter 23 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F23DATA1, CAN0_BASE + 0x2FC @ (Filter 23 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F24DATA0, CAN0_BASE + 0x300 @ (Filter 24 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F24DATA1, CAN0_BASE + 0x304 @ (Filter 24 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F25DATA0, CAN0_BASE + 0x308 @ (Filter 25 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F25DATA1, CAN0_BASE + 0x30C @ (Filter 25 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F26DATA0, CAN0_BASE + 0x310 @ (Filter 26 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F26DATA1, CAN0_BASE + 0x314 @ (Filter 26 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F27DATA0, CAN0_BASE + 0x318 @ (Filter 27 data 0 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F27DATA1, CAN0_BASE + 0x31C @ (Filter 27 data 1 register) 
        .equ CAN0_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 

@=========================== CAN1 ===========================@
.equ CAN1_BASE, 0x40006800 @ (Controller area network) 
    .equ CAN1_CTL, CAN1_BASE + 0x0 @ (Control register) 
        .equ CAN1_DFZ_Shift, 16   @ bitWidth 1 (Debug freeze)  
        .equ CAN1_SWRST_Shift, 15   @ bitWidth 1 (Software reset)  
        .equ CAN1_TTC_Shift, 7   @ bitWidth 1 (Time-triggered communication)  
        .equ CAN1_ABOR_Shift, 6   @ bitWidth 1 (Automatic bus-off recovery)  
        .equ CAN1_AWU_Shift, 5   @ bitWidth 1 (Automatic wakeup)  
        .equ CAN1_ARD_Shift, 4   @ bitWidth 1 (Automatic retransmission disable)  
        .equ CAN1_RFOD_Shift, 3   @ bitWidth 1 (Receive FIFO overwrite disable)  
        .equ CAN1_TFO_Shift, 2   @ bitWidth 1 (Transmit FIFO order)  
        .equ CAN1_SLPWMOD_Shift, 1   @ bitWidth 1 (Sleep working mode)  
        .equ CAN1_IWMOD_Shift, 0   @ bitWidth 1 (Initial working mode)  
 
    .equ CAN1_STAT, CAN1_BASE + 0x04 @ (Status register) 
        .equ CAN1_RXL_Shift, 11   @ bitWidth 1 (RX level)  
        .equ CAN1_LASTRX_Shift, 10   @ bitWidth 1 (Last sample value of RX pin)  
        .equ CAN1_RS_Shift, 9   @ bitWidth 1 (Receiving state)  
        .equ CAN1_TS_Shift, 8   @ bitWidth 1 (Transmitting state)  
        .equ CAN1_SLPIF_Shift, 4   @ bitWidth 1 (Status change interrupt flag of sleep  	 working mode entering)  
        .equ CAN1_WUIF_Shift, 3   @ bitWidth 1 (Status change interrupt flag of wakeup  	 from sleep working mode)  
        .equ CAN1_ERRIF_Shift, 2   @ bitWidth 1 (Error interrupt flag)  
        .equ CAN1_SLPWS_Shift, 1   @ bitWidth 1 (Sleep working state)  
        .equ CAN1_IWS_Shift, 0   @ bitWidth 1 (Initial working state)  
 
    .equ CAN1_TSTAT, CAN1_BASE + 0x8 @ (Transmit status register) 
        .equ CAN1_TMLS2_Shift, 31   @ bitWidth 1 (Transmit mailbox 2 last sending  	 in transmit FIFO)  
        .equ CAN1_TMLS1_Shift, 30   @ bitWidth 1 (Transmit mailbox 1 last sending  	 in transmit FIFO)  
        .equ CAN1_TMLS0_Shift, 29   @ bitWidth 1 (Transmit mailbox 0 last sending  	 in transmit FIFO)  
        .equ CAN1_TME2_Shift, 28   @ bitWidth 1 (Transmit mailbox 2 empty)  
        .equ CAN1_TME1_Shift, 27   @ bitWidth 1 (Transmit mailbox 1 empty)  
        .equ CAN1_TME0_Shift, 26   @ bitWidth 1 (Transmit mailbox 0 empty)  
        .equ CAN1_NUM_Shift, 24   @ bitWidth 2 (number of the transmit FIFO mailbox in  	 which the frame will be transmitted if at least one mailbox is empty)  
        .equ CAN1_MST2_Shift, 23   @ bitWidth 1 (Mailbox 2 stop transmitting)  
        .equ CAN1_MTE2_Shift, 19   @ bitWidth 1 (Mailbox 2 transmit error)  
        .equ CAN1_MAL2_Shift, 18   @ bitWidth 1 (Mailbox 2 arbitration lost)  
        .equ CAN1_MTFNERR2_Shift, 17   @ bitWidth 1 (Mailbox 2 transmit finished and no error)  
        .equ CAN1_MTF2_Shift, 16   @ bitWidth 1 (Mailbox 2 transmit finished)  
        .equ CAN1_MST1_Shift, 15   @ bitWidth 1 (Mailbox 1 stop transmitting)  
        .equ CAN1_MTE1_Shift, 11   @ bitWidth 1 (Mailbox 1 transmit error)  
        .equ CAN1_MAL1_Shift, 10   @ bitWidth 1 (Mailbox 1 arbitration lost)  
        .equ CAN1_MTFNERR1_Shift, 9   @ bitWidth 1 (Mailbox 1 transmit finished and no error)  
        .equ CAN1_MTF1_Shift, 8   @ bitWidth 1 (Mailbox 1 transmit finished)  
        .equ CAN1_MST0_Shift, 7   @ bitWidth 1 (Mailbox 0 stop transmitting)  
        .equ CAN1_MTE0_Shift, 3   @ bitWidth 1 (Mailbox 0 transmit error)  
        .equ CAN1_MAL0_Shift, 2   @ bitWidth 1 (Mailbox 0 arbitration lost)  
        .equ CAN1_MTFNERR0_Shift, 1   @ bitWidth 1 (Mailbox 0 transmit finished and no error)  
        .equ CAN1_MTF0_Shift, 0   @ bitWidth 1 (Mailbox 0 transmit finished)  
 
    .equ CAN1_RFIFO0, CAN1_BASE + 0x0C @ (Receive message FIFO0 register) 
        .equ CAN1_RFD0_Shift, 5   @ bitWidth 1 (Receive FIFO0 dequeue)  
        .equ CAN1_RFO0_Shift, 4   @ bitWidth 1 (Receive FIFO0 overfull)  
        .equ CAN1_RFF0_Shift, 3   @ bitWidth 1 (Receive FIFO0 full)  
        .equ CAN1_RFL0_Shift, 0   @ bitWidth 2 (Receive FIFO0 length)  
 
    .equ CAN1_RFIFO1, CAN1_BASE + 0x10 @ (Receive message FIFO1 register) 
        .equ CAN1_RFD1_Shift, 5   @ bitWidth 1 (Receive FIFO1 dequeue)  
        .equ CAN1_RFO1_Shift, 4   @ bitWidth 1 (Receive FIFO1 overfull)  
        .equ CAN1_RFF1_Shift, 3   @ bitWidth 1 (Receive FIFO1 full)  
        .equ CAN1_RFL1_Shift, 0   @ bitWidth 2 (Receive FIFO1 length)  
 
    .equ CAN1_INTEN, CAN1_BASE + 0x14 @ (Interrupt enable register) 
        .equ CAN1_SLPWIE_Shift, 17   @ bitWidth 1 (Sleep working interrupt enable)  
        .equ CAN1_WIE_Shift, 16   @ bitWidth 1 (Wakeup interrupt enable)  
        .equ CAN1_ERRIE_Shift, 15   @ bitWidth 1 (Error interrupt enable)  
        .equ CAN1_ERRNIE_Shift, 11   @ bitWidth 1 (Error number interrupt enable)  
        .equ CAN1_BOIE_Shift, 10   @ bitWidth 1 (Bus-off interrupt enable)  
        .equ CAN1_PERRIE_Shift, 9   @ bitWidth 1 (Passive error interrupt enable)  
        .equ CAN1_WERRIE_Shift, 8   @ bitWidth 1 (Warning error interrupt enable)  
        .equ CAN1_RFOIE1_Shift, 6   @ bitWidth 1 (Receive FIFO1 overfull interrupt enable)  
        .equ CAN1_RFFIE1_Shift, 5   @ bitWidth 1 (Receive FIFO1 full interrupt enable)  
        .equ CAN1_RFNEIE1_Shift, 4   @ bitWidth 1 (Receive FIFO1 not empty interrupt enable)  
        .equ CAN1_RFOIE0_Shift, 3   @ bitWidth 1 (Receive FIFO0 overfull interrupt enable)  
        .equ CAN1_RFFIE0_Shift, 2   @ bitWidth 1 (Receive FIFO0 full interrupt enable)  
        .equ CAN1_RFNEIE0_Shift, 1   @ bitWidth 1 (Receive FIFO0 not empty interrupt enable)  
        .equ CAN1_TMEIE_Shift, 0   @ bitWidth 1 (Transmit mailbox empty interrupt enable)  
 
    .equ CAN1_ERR, CAN1_BASE + 0x18 @ (Error register) 
        .equ CAN1_RECNT_Shift, 24   @ bitWidth 8 (Receive Error Count defined  	 by the CAN standard)  
        .equ CAN1_TECNT_Shift, 16   @ bitWidth 8 (Transmit Error Count defined  	 by the CAN standard)  
        .equ CAN1_ERRN_Shift, 4   @ bitWidth 3 (Error number)  
        .equ CAN1_BOERR_Shift, 2   @ bitWidth 1 (Bus-off error)  
        .equ CAN1_PERR_Shift, 1   @ bitWidth 1 (Passive error)  
        .equ CAN1_WERR_Shift, 0   @ bitWidth 1 (Warning error)  
 
    .equ CAN1_BT, CAN1_BASE + 0x1C @ (Bit timing register) 
        .equ CAN1_SCMOD_Shift, 31   @ bitWidth 1 (Silent communication mode)  
        .equ CAN1_LCMOD_Shift, 30   @ bitWidth 1 (Loopback communication mode)  
        .equ CAN1_SJW_Shift, 24   @ bitWidth 2 (Resynchronization jump width)  
        .equ CAN1_BS2_Shift, 20   @ bitWidth 3 (Bit segment 2)  
        .equ CAN1_BS1_Shift, 16   @ bitWidth 4 (Bit segment 1)  
        .equ CAN1_BAUDPSC_Shift, 0   @ bitWidth 10 (Baud rate prescaler)  
 
    .equ CAN1_TMI0, CAN1_BASE + 0x180 @ (Transmit mailbox identifier register 0) 
        .equ CAN1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_FT_Shift, 1   @ bitWidth 1 (Frame type)  
        .equ CAN1_TEN_Shift, 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN1_TMP0, CAN1_BASE + 0x184 @ (Transmit mailbox property register 0) 
        .equ CAN1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_TSEN_Shift, 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_TMDATA00, CAN1_BASE + 0x188 @ (Transmit mailbox data0 register) 
        .equ CAN1_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_TMDATA10, CAN1_BASE + 0x18C @ (Transmit mailbox data1 register) 
        .equ CAN1_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_TMI1, CAN1_BASE + 0x190 @ (Transmit mailbox identifier register 1) 
        .equ CAN1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_FT_Shift, 1   @ bitWidth 1 (Frame type)  
        .equ CAN1_TEN_Shift, 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN1_TMP1, CAN1_BASE + 0x194 @ (Transmit mailbox property register 1) 
        .equ CAN1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_TSEN_Shift, 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_TMDATA01, CAN1_BASE + 0x198 @ (Transmit mailbox data0 register) 
        .equ CAN1_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_TMDATA11, CAN1_BASE + 0x19C @ (Transmit mailbox data1 register) 
        .equ CAN1_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_TMI2, CAN1_BASE + 0x1A0 @ (Transmit mailbox identifier register 2) 
        .equ CAN1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_FT_Shift, 1   @ bitWidth 1 (Frame type)  
        .equ CAN1_TEN_Shift, 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN1_TMP2, CAN1_BASE + 0x1A4 @ (Transmit mailbox property register 2) 
        .equ CAN1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_TSEN_Shift, 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_TMDATA02, CAN1_BASE + 0x1A8 @ (Transmit mailbox data0 register) 
        .equ CAN1_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_TMDATA12, CAN1_BASE + 0x1AC @ (Transmit mailbox data1 register) 
        .equ CAN1_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_RFIFOMI0, CAN1_BASE + 0x1B0 @ (Receive FIFO mailbox identifier register) 
        .equ CAN1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_FT_Shift, 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN1_RFIFOMP0, CAN1_BASE + 0x1B4 @ (Receive FIFO0 mailbox property register) 
        .equ CAN1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_RFIFOMDATA00, CAN1_BASE + 0x1B8 @ (Receive FIFO0 mailbox data0 register) 
        .equ CAN1_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_RFIFOMDATA10, CAN1_BASE + 0x1BC @ (Receive FIFO0 mailbox data1 register) 
        .equ CAN1_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_RFIFOMI1, CAN1_BASE + 0x1C0 @ (Receive FIFO1 mailbox identifier register) 
        .equ CAN1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_FF_Shift, 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_FT_Shift, 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN1_RFIFOMP1, CAN1_BASE + 0x1C4 @ (Receive FIFO1 mailbox property register) 
        .equ CAN1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_RFIFOMDATA01, CAN1_BASE + 0x1C8 @ (Receive FIFO1 mailbox data0 register) 
        .equ CAN1_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_RFIFOMDATA11, CAN1_BASE + 0x1CC @ (Receive FIFO1 mailbox data1 register) 
        .equ CAN1_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_FCTL, CAN1_BASE + 0x200 @ (Filter control register) 
        .equ CAN1_HBC1F_Shift, 8   @ bitWidth 6 (Header bank of CAN1 filter)  
        .equ CAN1_FLD_Shift, 0   @ bitWidth 1 (Filter lock disable)  
 
    .equ CAN1_FMCFG, CAN1_BASE + 0x204 @ (Filter mode configuration register) 
        .equ CAN1_FMOD27_Shift, 27   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD26_Shift, 26   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD25_Shift, 25   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD24_Shift, 24   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD23_Shift, 23   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD22_Shift, 22   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD21_Shift, 21   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD20_Shift, 20   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD19_Shift, 19   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD18_Shift, 18   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD17_Shift, 17   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD16_Shift, 16   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD15_Shift, 15   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD14_Shift, 14   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD13_Shift, 13   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD12_Shift, 12   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD11_Shift, 11   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD10_Shift, 10   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD9_Shift, 9   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD8_Shift, 8   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD7_Shift, 7   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD6_Shift, 6   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD5_Shift, 5   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD4_Shift, 4   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD3_Shift, 3   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD2_Shift, 2   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD1_Shift, 1   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMOD0_Shift, 0   @ bitWidth 1 (Filter mode)  
 
    .equ CAN1_FSCFG, CAN1_BASE + 0x20C @ (Filter scale configuration register) 
        .equ CAN1_FS0_Shift, 0   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS1_Shift, 1   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS2_Shift, 2   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS3_Shift, 3   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS4_Shift, 4   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS5_Shift, 5   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS6_Shift, 6   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS7_Shift, 7   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS8_Shift, 8   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS9_Shift, 9   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS10_Shift, 10   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS11_Shift, 11   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS12_Shift, 12   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS13_Shift, 13   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS14_Shift, 14   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS15_Shift, 15   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS16_Shift, 16   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS17_Shift, 17   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS18_Shift, 18   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS19_Shift, 19   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS20_Shift, 20   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS21_Shift, 21   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS22_Shift, 22   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS23_Shift, 23   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS24_Shift, 24   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS25_Shift, 25   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS26_Shift, 26   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FS27_Shift, 27   @ bitWidth 1 (Filter scale configuration)  
 
    .equ CAN1_FAFIFO, CAN1_BASE + 0x214 @ (Filter associated FIFO register) 
        .equ CAN1_FAF0_Shift, 0   @ bitWidth 1 (Filter 0 associated with FIFO)  
        .equ CAN1_FAF1_Shift, 1   @ bitWidth 1 (Filter 1 associated with FIFO)  
        .equ CAN1_FAF2_Shift, 2   @ bitWidth 1 (Filter 2 associated with FIFO)  
        .equ CAN1_FAF3_Shift, 3   @ bitWidth 1 (Filter 3 associated with FIFO)  
        .equ CAN1_FAF4_Shift, 4   @ bitWidth 1 (Filter 4 associated with FIFO)  
        .equ CAN1_FAF5_Shift, 5   @ bitWidth 1 (Filter 5 associated with FIFO)  
        .equ CAN1_FAF6_Shift, 6   @ bitWidth 1 (Filter 6 associated with FIFO)  
        .equ CAN1_FAF7_Shift, 7   @ bitWidth 1 (Filter 7 associated with FIFO)  
        .equ CAN1_FAF8_Shift, 8   @ bitWidth 1 (Filter 8 associated with FIFO)  
        .equ CAN1_FAF9_Shift, 9   @ bitWidth 1 (Filter 9 associated with FIFO)  
        .equ CAN1_FAF10_Shift, 10   @ bitWidth 1 (Filter 10 associated with FIFO)  
        .equ CAN1_FAF11_Shift, 11   @ bitWidth 1 (Filter 11 associated with FIFO)  
        .equ CAN1_FAF12_Shift, 12   @ bitWidth 1 (Filter 12 associated with FIFO)  
        .equ CAN1_FAF13_Shift, 13   @ bitWidth 1 (Filter 13 associated with FIFO)  
        .equ CAN1_FAF14_Shift, 14   @ bitWidth 1 (Filter 14 associated with FIFO)  
        .equ CAN1_FAF15_Shift, 15   @ bitWidth 1 (Filter 15 associated with FIFO)  
        .equ CAN1_FAF16_Shift, 16   @ bitWidth 1 (Filter 16 associated with FIFO)  
        .equ CAN1_FAF17_Shift, 17   @ bitWidth 1 (Filter 17 associated with FIFO)  
        .equ CAN1_FAF18_Shift, 18   @ bitWidth 1 (Filter 18 associated with FIFO)  
        .equ CAN1_FAF19_Shift, 19   @ bitWidth 1 (Filter 19 associated with FIFO)  
        .equ CAN1_FAF20_Shift, 20   @ bitWidth 1 (Filter 20 associated with FIFO)  
        .equ CAN1_FAF21_Shift, 21   @ bitWidth 1 (Filter 21 associated with FIFO)  
        .equ CAN1_FAF22_Shift, 22   @ bitWidth 1 (Filter 22 associated with FIFO)  
        .equ CAN1_FAF23_Shift, 23   @ bitWidth 1 (Filter 23 associated with FIFO)  
        .equ CAN1_FAF24_Shift, 24   @ bitWidth 1 (Filter 24 associated with FIFO)  
        .equ CAN1_FAF25_Shift, 25   @ bitWidth 1 (Filter 25 associated with FIFO)  
        .equ CAN1_FAF26_Shift, 26   @ bitWidth 1 (Filter 26 associated with FIFO)  
        .equ CAN1_FAF27_Shift, 27   @ bitWidth 1 (Filter 27 associated with FIFO)  
 
    .equ CAN1_FW, CAN1_BASE + 0x21C @ (Filter working register) 
        .equ CAN1_FW0_Shift, 0   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW1_Shift, 1   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW2_Shift, 2   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW3_Shift, 3   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW4_Shift, 4   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW5_Shift, 5   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW6_Shift, 6   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW7_Shift, 7   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW8_Shift, 8   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW9_Shift, 9   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW10_Shift, 10   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW11_Shift, 11   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW12_Shift, 12   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW13_Shift, 13   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW14_Shift, 14   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW15_Shift, 15   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW16_Shift, 16   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW17_Shift, 17   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW18_Shift, 18   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW19_Shift, 19   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW20_Shift, 20   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW21_Shift, 21   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW22_Shift, 22   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW23_Shift, 23   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW24_Shift, 24   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW25_Shift, 25   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW26_Shift, 26   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW27_Shift, 27   @ bitWidth 1 (Filter working)  
 
    .equ CAN1_F0DATA0, CAN1_BASE + 0x240 @ (Filter 0 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F0DATA1, CAN1_BASE + 0x244 @ (Filter 0 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F1DATA0, CAN1_BASE + 0x248 @ (Filter 1 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F1DATA1, CAN1_BASE + 0x24C @ (Filter 1 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F2DATA0, CAN1_BASE + 0x250 @ (Filter 2 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F2DATA1, CAN1_BASE + 0x254 @ (Filter 2 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F3DATA0, CAN1_BASE + 0x258 @ (Filter 3 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F3DATA1, CAN1_BASE + 0x25C @ (Filter 3 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F4DATA0, CAN1_BASE + 0x260 @ (Filter 4 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F4DATA1, CAN1_BASE + 0x264 @ (Filter 4 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F5DATA0, CAN1_BASE + 0x268 @ (Filter 5 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F5DATA1, CAN1_BASE + 0x26C @ (Filter 5 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F6DATA0, CAN1_BASE + 0x270 @ (Filter 6 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F6DATA1, CAN1_BASE + 0x274 @ (Filter 6 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F7DATA0, CAN1_BASE + 0x278 @ (Filter 7 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F7DATA1, CAN1_BASE + 0x27C @ (Filter 7 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F8DATA0, CAN1_BASE + 0x280 @ (Filter 8 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F8DATA1, CAN1_BASE + 0x284 @ (Filter 8 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F9DATA0, CAN1_BASE + 0x288 @ (Filter 9 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F9DATA1, CAN1_BASE + 0x28C @ (Filter 9 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F10DATA0, CAN1_BASE + 0x290 @ (Filter 10 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F10DATA1, CAN1_BASE + 0x294 @ (Filter 10 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F11DATA0, CAN1_BASE + 0x298 @ (Filter 11 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F11DATA1, CAN1_BASE + 0x29C @ (Filter 11 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F12DATA0, CAN1_BASE + 0x2A0 @ (Filter 12 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F12DATA1, CAN1_BASE + 0x2A4 @ (Filter 12 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F13DATA0, CAN1_BASE + 0x2A8 @ (Filter 13 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F13DATA1, CAN1_BASE + 0x2AC @ (Filter 13 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F14DATA0, CAN1_BASE + 0x2B0 @ (Filter 14 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F14DATA1, CAN1_BASE + 0x2B4 @ (Filter 14 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F15DATA0, CAN1_BASE + 0x2B8 @ (Filter 15 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F15DATA1, CAN1_BASE + 0x2BC @ (Filter 15 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F16DATA0, CAN1_BASE + 0x2C0 @ (Filter 16 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F16DATA1, CAN1_BASE + 0x2C4 @ (Filter 16 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F17DATA0, CAN1_BASE + 0x2C8 @ (Filter 17 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F17DATA1, CAN1_BASE + 0x2CC @ (Filter 17 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F18DATA0, CAN1_BASE + 0x2D0 @ (Filter 18 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F18DATA1, CAN1_BASE + 0x2D4 @ (Filter 18 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F19DATA0, CAN1_BASE + 0x2D8 @ (Filter 19 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F19DATA1, CAN1_BASE + 0x2DC @ (Filter 19 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F20DATA0, CAN1_BASE + 0x2E0 @ (Filter 20 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F20DATA1, CAN1_BASE + 0x2E4 @ (Filter 20 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F21DATA0, CAN1_BASE + 0x2E8 @ (Filter 21 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F21DATA1, CAN1_BASE + 0x2EC @ (Filter 21 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F22DATA0, CAN1_BASE + 0x2F0 @ (Filter 22 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F22DATA1, CAN1_BASE + 0x2F4 @ (Filter 22 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F23DATA0, CAN1_BASE + 0x2F8 @ (Filter 23 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F23DATA1, CAN1_BASE + 0x2FC @ (Filter 23 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F24DATA0, CAN1_BASE + 0x300 @ (Filter 24 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F24DATA1, CAN1_BASE + 0x304 @ (Filter 24 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F25DATA0, CAN1_BASE + 0x308 @ (Filter 25 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F25DATA1, CAN1_BASE + 0x30C @ (Filter 25 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F26DATA0, CAN1_BASE + 0x310 @ (Filter 26 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F26DATA1, CAN1_BASE + 0x314 @ (Filter 26 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F27DATA0, CAN1_BASE + 0x318 @ (Filter 27 data 0 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F27DATA1, CAN1_BASE + 0x31C @ (Filter 27 data 1 register) 
        .equ CAN1_FD0_Shift, 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD1_Shift, 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD2_Shift, 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD3_Shift, 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD4_Shift, 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD5_Shift, 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD6_Shift, 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD7_Shift, 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD8_Shift, 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD9_Shift, 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD10_Shift, 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD11_Shift, 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD12_Shift, 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD13_Shift, 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD14_Shift, 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD15_Shift, 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD16_Shift, 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD17_Shift, 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD18_Shift, 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD19_Shift, 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD20_Shift, 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD21_Shift, 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD22_Shift, 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD23_Shift, 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD24_Shift, 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD25_Shift, 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD26_Shift, 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD27_Shift, 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD28_Shift, 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD29_Shift, 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD30_Shift, 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_FD31_Shift, 31   @ bitWidth 1 (Filter bits)  
 

@=========================== CRC ===========================@
.equ CRC_BASE, 0x40023000 @ (cyclic redundancy check calculation unit) 
    .equ CRC_DATA, CRC_BASE + 0x0 @ (Data register) 
        .equ CRC_DATA_Shift, 0   @ bitWidth 32 (CRC calculation result bits)  
 
    .equ CRC_FDATA, CRC_BASE + 0x04 @ (Free data register) 
        .equ CRC_FDATA_Shift, 0   @ bitWidth 8 (Free Data Register bits)  
 
    .equ CRC_CTL, CRC_BASE + 0x08 @ (Control register) 
        .equ CRC_RST_Shift, 0   @ bitWidth 1 (reset bit)  
 

@=========================== DAC ===========================@
.equ DAC_BASE, 0x40007400 @ (Digital-to-analog converter) 
    .equ DAC_CTL, DAC_BASE + 0x0 @ (control register) 
        .equ DAC_DEN0_Shift, 0   @ bitWidth 1 (DAC0 enable)  
        .equ DAC_DBOFF0_Shift, 1   @ bitWidth 1 (DAC0 output buffer turn off)  
        .equ DAC_DTEN0_Shift, 2   @ bitWidth 1 (DAC0 trigger enable)  
        .equ DAC_DTSEL0_Shift, 3   @ bitWidth 3 (DAC0 trigger selection)  
        .equ DAC_DWM0_Shift, 6   @ bitWidth 2 (DAC0 noise wave mode)  
        .equ DAC_DWBW0_Shift, 8   @ bitWidth 4 (DAC0 noise wave bit width)  
        .equ DAC_DDMAEN0_Shift, 12   @ bitWidth 1 (DAC0 DMA enable)  
        .equ DAC_DEN1_Shift, 16   @ bitWidth 1 (DAC1 enable)  
        .equ DAC_DBOFF1_Shift, 17   @ bitWidth 1 (DAC1 output buffer turn off)  
        .equ DAC_DTEN1_Shift, 18   @ bitWidth 1 (DAC1 trigger enable)  
        .equ DAC_DTSEL1_Shift, 19   @ bitWidth 3 (DAC1 trigger selection)  
        .equ DAC_DWM1_Shift, 22   @ bitWidth 2 (DAC1 noise wave mode)  
        .equ DAC_DWBW1_Shift, 24   @ bitWidth 4 (DAC1 noise wave bit width)  
        .equ DAC_DDMAEN1_Shift, 28   @ bitWidth 1 (DAC1 DMA enable)  
 
    .equ DAC_SWT, DAC_BASE + 0x04 @ (software trigger register) 
        .equ DAC_SWTR0_Shift, 0   @ bitWidth 1 (DAC0 software trigger)  
        .equ DAC_SWTR1_Shift, 1   @ bitWidth 1 (DAC1 software trigger)  
 
    .equ DAC_DAC0_R12DH, DAC_BASE + 0x08 @ (DAC0 12-bit right-aligned data holding register) 
        .equ DAC_DAC0_DH_Shift, 0   @ bitWidth 12 (DAC0 12-bit right-aligned  data)  
 
    .equ DAC_DAC0_L12DH, DAC_BASE + 0x0C @ (DAC0 12-bit left-aligned data holding register) 
        .equ DAC_DAC0_DH_Shift, 4   @ bitWidth 12 (DAC0 12-bit left-aligned  data)  
 
    .equ DAC_DAC0_R8DH, DAC_BASE + 0x10 @ (DAC0 8-bit right aligned data holding  register) 
        .equ DAC_DAC0_DH_Shift, 0   @ bitWidth 8 (DAC0 8-bit right-aligned  data)  
 
    .equ DAC_DAC1_R12DH, DAC_BASE + 0x14 @ (DAC1 12-bit right-aligned data holding  register) 
        .equ DAC_DAC1_DH_Shift, 0   @ bitWidth 12 (DAC1 12-bit right-aligned  data)  
 
    .equ DAC_DAC1_L12DH, DAC_BASE + 0x18 @ (DAC1 12-bit left aligned data holding  register) 
        .equ DAC_DAC1_DH_Shift, 4   @ bitWidth 12 (DAC1 12-bit left-aligned  data)  
 
    .equ DAC_DAC1_R8DH, DAC_BASE + 0x1C @ (DAC1 8-bit right aligned data holding  register) 
        .equ DAC_DAC1_DH_Shift, 0   @ bitWidth 8 (DAC1 8-bit right-aligned  data)  
 
    .equ DAC_DACC_R12DH, DAC_BASE + 0x20 @ (DAC concurrent mode 12-bit right-aligned data holding  register) 
        .equ DAC_DAC0_DH_Shift, 0   @ bitWidth 12 (DAC0 12-bit right-aligned  data)  
        .equ DAC_DAC1_DH_Shift, 16   @ bitWidth 12 (DAC1 12-bit right-aligned  data)  
 
    .equ DAC_DACC_L12DH, DAC_BASE + 0x24 @ (DAC concurrent mode 12-bit left aligned data holding  register) 
        .equ DAC_DAC0_DH_Shift, 4   @ bitWidth 12 (DAC0 12-bit left-aligned  data)  
        .equ DAC_DAC1_DH_Shift, 20   @ bitWidth 12 (DAC1 12-bit left-aligned  data)  
 
    .equ DAC_DACC_R8DH, DAC_BASE + 0x28 @ (DAC concurrent mode 8-bit right aligned data holding  register) 
        .equ DAC_DAC0_DH_Shift, 0   @ bitWidth 8 (DAC0 8-bit right-aligned  data)  
        .equ DAC_DAC1_DH_Shift, 8   @ bitWidth 8 (DAC1 8-bit right-aligned  data)  
 
    .equ DAC_DAC0_DO, DAC_BASE + 0x2C @ (DAC0 data output register) 
        .equ DAC_DAC0_DO_Shift, 0   @ bitWidth 12 (DAC0 data output)  
 
    .equ DAC_DAC1_DO, DAC_BASE + 0x30 @ (DAC1 data output register) 
        .equ DAC_DAC1_DO_Shift, 0   @ bitWidth 12 (DAC1 data output)  
 

@=========================== DBG ===========================@
.equ DBG_BASE, 0xE0042000 @ (Debug support) 
    .equ DBG_ID, DBG_BASE + 0x0 @ (ID code register) 
        .equ DBG_ID_CODE_Shift, 0   @ bitWidth 32 (DBG ID code register)  
 
    .equ DBG_CTL, DBG_BASE + 0x4 @ (Control register 0) 
        .equ DBG_SLP_HOLD_Shift, 0   @ bitWidth 1 (Sleep mode hold register)  
        .equ DBG_DSLP_HOLD_Shift, 1   @ bitWidth 1 (Deep-sleep mode hold register)  
        .equ DBG_STB_HOLD_Shift, 2   @ bitWidth 1 (Standby mode hold register)  
        .equ DBG_FWDGT_HOLD_Shift, 8   @ bitWidth 1 (FWDGT hold bit)  
        .equ DBG_WWDGT_HOLD_Shift, 9   @ bitWidth 1 (WWDGT hold bit)  
        .equ DBG_TIMER0_HOLD_Shift, 10   @ bitWidth 1 (TIMER 0 hold bit)  
        .equ DBG_TIMER1_HOLD_Shift, 11   @ bitWidth 1 (TIMER 1 hold bit)  
        .equ DBG_TIMER2_HOLD_Shift, 12   @ bitWidth 1 (TIMER 2 hold bit)  
        .equ DBG_TIMER3_HOLD_Shift, 13   @ bitWidth 1 (TIMER 23 hold bit)  
        .equ DBG_CAN0_HOLD_Shift, 14   @ bitWidth 1 (CAN0 hold bit)  
        .equ DBG_I2C0_HOLD_Shift, 15   @ bitWidth 1 (I2C0 hold bit)  
        .equ DBG_I2C1_HOLD_Shift, 16   @ bitWidth 1 (I2C1 hold bit)  
        .equ DBG_TIMER4_HOLD_Shift, 18   @ bitWidth 1 (TIMER4_HOLD)  
        .equ DBG_TIMER5_HOLD_Shift, 19   @ bitWidth 1 (TIMER 5 hold bit)  
        .equ DBG_TIMER6_HOLD_Shift, 20   @ bitWidth 1 (TIMER 6 hold bit)  
        .equ DBG_CAN1_HOLD_Shift, 21   @ bitWidth 1 (CAN1 hold bit)  
 

@=========================== DMA0 ===========================@
.equ DMA0_BASE, 0x40020000 @ (DMA controller) 
    .equ DMA0_INTF, DMA0_BASE + 0x0 @ (Interrupt flag register ) 
        .equ DMA0_GIF0_Shift, 0   @ bitWidth 1 (Global interrupt flag of channel 0)  
        .equ DMA0_FTFIF0_Shift, 1   @ bitWidth 1 (Full Transfer finish flag of channe 0)  
        .equ DMA0_HTFIF0_Shift, 2   @ bitWidth 1 (Half transfer finish flag of channel 0)  
        .equ DMA0_ERRIF0_Shift, 3   @ bitWidth 1 (Error flag of channel 0)  
        .equ DMA0_GIF1_Shift, 4   @ bitWidth 1 (Global interrupt flag of channel 1)  
        .equ DMA0_FTFIF1_Shift, 5   @ bitWidth 1 (Full Transfer finish flag of channe 1)  
        .equ DMA0_HTFIF1_Shift, 6   @ bitWidth 1 (Half transfer finish flag of channel 1)  
        .equ DMA0_ERRIF1_Shift, 7   @ bitWidth 1 (Error flag of channel 1)  
        .equ DMA0_GIF2_Shift, 8   @ bitWidth 1 (Global interrupt flag of channel 2)  
        .equ DMA0_FTFIF2_Shift, 9   @ bitWidth 1 (Full Transfer finish flag of channe 2)  
        .equ DMA0_HTFIF2_Shift, 10   @ bitWidth 1 (Half transfer finish flag of channel 2)  
        .equ DMA0_ERRIF2_Shift, 11   @ bitWidth 1 (Error flag of channel 2)  
        .equ DMA0_GIF3_Shift, 12   @ bitWidth 1 (Global interrupt flag of channel 3)  
        .equ DMA0_FTFIF3_Shift, 13   @ bitWidth 1 (Full Transfer finish flag of channe 3)  
        .equ DMA0_HTFIF3_Shift, 14   @ bitWidth 1 (Half transfer finish flag of channel 3)  
        .equ DMA0_ERRIF3_Shift, 15   @ bitWidth 1 (Error flag of channel 3)  
        .equ DMA0_GIF4_Shift, 16   @ bitWidth 1 (Global interrupt flag of channel 4)  
        .equ DMA0_FTFIF4_Shift, 17   @ bitWidth 1 (Full Transfer finish flag of channe 4)  
        .equ DMA0_HTFIF4_Shift, 18   @ bitWidth 1 (Half transfer finish flag of channel 4)  
        .equ DMA0_ERRIF4_Shift, 19   @ bitWidth 1 (Error flag of channel 4)  
        .equ DMA0_GIF5_Shift, 20   @ bitWidth 1 (Global interrupt flag of channel 5)  
        .equ DMA0_FTFIF5_Shift, 21   @ bitWidth 1 (Full Transfer finish flag of channe 5)  
        .equ DMA0_HTFIF5_Shift, 22   @ bitWidth 1 (Half transfer finish flag of channel 5)  
        .equ DMA0_ERRIF5_Shift, 23   @ bitWidth 1 (Error flag of channel 5)  
        .equ DMA0_GIF6_Shift, 24   @ bitWidth 1 (Global interrupt flag of channel 6)  
        .equ DMA0_FTFIF6_Shift, 25   @ bitWidth 1 (Full Transfer finish flag of channe 6)  
        .equ DMA0_HTFIF6_Shift, 26   @ bitWidth 1 (Half transfer finish flag of channel 6)  
        .equ DMA0_ERRIF6_Shift, 27   @ bitWidth 1 (Error flag of channel 6)  
 
    .equ DMA0_INTC, DMA0_BASE + 0x04 @ (Interrupt flag clear register ) 
        .equ DMA0_GIFC0_Shift, 0   @ bitWidth 1 (Clear global interrupt flag of channel 0)  
        .equ DMA0_FTFIFC0_Shift, 1   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 0)  
        .equ DMA0_HTFIFC0_Shift, 2   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 0)  
        .equ DMA0_ERRIFC0_Shift, 3   @ bitWidth 1 (Clear bit for error flag of channel 0)  
        .equ DMA0_GIFC1_Shift, 4   @ bitWidth 1 (Clear global interrupt flag of channel 1)  
        .equ DMA0_FTFIFC1_Shift, 5   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 1)  
        .equ DMA0_HTFIFC1_Shift, 6   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 1)  
        .equ DMA0_ERRIFC1_Shift, 7   @ bitWidth 1 (Clear bit for error flag of channel 1)  
        .equ DMA0_GIFC2_Shift, 8   @ bitWidth 1 (Clear global interrupt flag of channel 2)  
        .equ DMA0_FTFIFC2_Shift, 9   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 2)  
        .equ DMA0_HTFIFC2_Shift, 10   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 2)  
        .equ DMA0_ERRIFC2_Shift, 11   @ bitWidth 1 (Clear bit for error flag of channel 2)  
        .equ DMA0_GIFC3_Shift, 12   @ bitWidth 1 (Clear global interrupt flag of channel 3)  
        .equ DMA0_FTFIFC3_Shift, 13   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 3)  
        .equ DMA0_HTFIFC3_Shift, 14   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 3)  
        .equ DMA0_ERRIFC3_Shift, 15   @ bitWidth 1 (Clear bit for error flag of channel 3)  
        .equ DMA0_GIFC4_Shift, 16   @ bitWidth 1 (Clear global interrupt flag of channel 4)  
        .equ DMA0_FTFIFC4_Shift, 17   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 4)  
        .equ DMA0_HTFIFC4_Shift, 18   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 4)  
        .equ DMA0_ERRIFC4_Shift, 19   @ bitWidth 1 (Clear bit for error flag of channel 4)  
        .equ DMA0_GIFC5_Shift, 20   @ bitWidth 1 (Clear global interrupt flag of channel 5)  
        .equ DMA0_FTFIFC5_Shift, 21   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 5)  
        .equ DMA0_HTFIFC5_Shift, 22   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 5)  
        .equ DMA0_ERRIFC5_Shift, 23   @ bitWidth 1 (Clear bit for error flag of channel 5)  
        .equ DMA0_GIFC6_Shift, 24   @ bitWidth 1 (Clear global interrupt flag of channel 6)  
        .equ DMA0_FTFIFC6_Shift, 25   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 6)  
        .equ DMA0_HTFIFC6_Shift, 26   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 6)  
        .equ DMA0_ERRIFC6_Shift, 27   @ bitWidth 1 (Clear bit for error flag of channel 6)  
 
    .equ DMA0_CH0CTL, DMA0_BASE + 0x08 @ (Channel 0 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH0CNT, DMA0_BASE + 0x0C @ (Channel 0 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH0PADDR, DMA0_BASE + 0x10 @ (Channel 0 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH0MADDR, DMA0_BASE + 0x14 @ (Channel 0 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH1CTL, DMA0_BASE + 0x1C @ (Channel 1 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH1CNT, DMA0_BASE + 0x20 @ (Channel 1 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH1PADDR, DMA0_BASE + 0x24 @ (Channel 1 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH1MADDR, DMA0_BASE + 0x28 @ (Channel 1 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH2CTL, DMA0_BASE + 0x30 @ (Channel 2 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH2CNT, DMA0_BASE + 0x34 @ (Channel 2 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH2PADDR, DMA0_BASE + 0x38 @ (Channel 2 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH2MADDR, DMA0_BASE + 0x3C @ (Channel 2 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH3CTL, DMA0_BASE + 0x44 @ (Channel 3 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH3CNT, DMA0_BASE + 0x48 @ (Channel 3 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH3PADDR, DMA0_BASE + 0x4C @ (Channel 3 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH3MADDR, DMA0_BASE + 0x50 @ (Channel 3 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH4CTL, DMA0_BASE + 0x58 @ (Channel 4 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH4CNT, DMA0_BASE + 0x5C @ (Channel 4 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH4PADDR, DMA0_BASE + 0x60 @ (Channel 4 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH4MADDR, DMA0_BASE + 0x64 @ (Channel 4 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH5CTL, DMA0_BASE + 0x6C @ (Channel 5 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH5CNT, DMA0_BASE + 0x70 @ (Channel 5 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH5PADDR, DMA0_BASE + 0x74 @ (Channel 5 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH5MADDR, DMA0_BASE + 0x78 @ (Channel 5 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH6CTL, DMA0_BASE + 0x80 @ (Channel 6 control register) 
        .equ DMA0_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH6CNT, DMA0_BASE + 0x84 @ (Channel 6 counter register) 
        .equ DMA0_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH6PADDR, DMA0_BASE + 0x88 @ (Channel 6 peripheral base address register) 
        .equ DMA0_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH6MADDR, DMA0_BASE + 0x8C @ (Channel 6 memory base address register) 
        .equ DMA0_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 

@=========================== DMA1 ===========================@
.equ DMA1_BASE, 0x40020000 @ (Direct memory access controller) 
    .equ DMA1_INTF, DMA1_BASE + 0x0 @ (Interrupt flag register ) 
        .equ DMA1_GIF0_Shift, 0   @ bitWidth 1 (Global interrupt flag of channel 0)  
        .equ DMA1_FTFIF0_Shift, 1   @ bitWidth 1 (Full Transfer finish flag of channe 0)  
        .equ DMA1_HTFIF0_Shift, 2   @ bitWidth 1 (Half transfer finish flag of channel 0)  
        .equ DMA1_ERRIF0_Shift, 3   @ bitWidth 1 (Error flag of channel 0)  
        .equ DMA1_GIF1_Shift, 4   @ bitWidth 1 (Global interrupt flag of channel 1)  
        .equ DMA1_FTFIF1_Shift, 5   @ bitWidth 1 (Full Transfer finish flag of channe 1)  
        .equ DMA1_HTFIF1_Shift, 6   @ bitWidth 1 (Half transfer finish flag of channel 1)  
        .equ DMA1_ERRIF1_Shift, 7   @ bitWidth 1 (Error flag of channel 1)  
        .equ DMA1_GIF2_Shift, 8   @ bitWidth 1 (Global interrupt flag of channel 2)  
        .equ DMA1_FTFIF2_Shift, 9   @ bitWidth 1 (Full Transfer finish flag of channe 2)  
        .equ DMA1_HTFIF2_Shift, 10   @ bitWidth 1 (Half transfer finish flag of channel 2)  
        .equ DMA1_ERRIF2_Shift, 11   @ bitWidth 1 (Error flag of channel 2)  
        .equ DMA1_GIF3_Shift, 12   @ bitWidth 1 (Global interrupt flag of channel 3)  
        .equ DMA1_FTFIF3_Shift, 13   @ bitWidth 1 (Full Transfer finish flag of channe 3)  
        .equ DMA1_HTFIF3_Shift, 14   @ bitWidth 1 (Half transfer finish flag of channel 3)  
        .equ DMA1_ERRIF3_Shift, 15   @ bitWidth 1 (Error flag of channel 3)  
        .equ DMA1_GIF4_Shift, 16   @ bitWidth 1 (Global interrupt flag of channel 4)  
        .equ DMA1_FTFIF4_Shift, 17   @ bitWidth 1 (Full Transfer finish flag of channe 4)  
        .equ DMA1_HTFIF4_Shift, 18   @ bitWidth 1 (Half transfer finish flag of channel 4)  
        .equ DMA1_ERRIF4_Shift, 19   @ bitWidth 1 (Error flag of channel 4)  
 
    .equ DMA1_INTC, DMA1_BASE + 0x04 @ (Interrupt flag clear register ) 
        .equ DMA1_GIFC0_Shift, 0   @ bitWidth 1 (Clear global interrupt flag of channel 0)  
        .equ DMA1_FTFIFC0_Shift, 1   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 0)  
        .equ DMA1_HTFIFC0_Shift, 2   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 0)  
        .equ DMA1_ERRIFC0_Shift, 3   @ bitWidth 1 (Clear bit for error flag of channel 0)  
        .equ DMA1_GIFC1_Shift, 4   @ bitWidth 1 (Clear global interrupt flag of channel 1)  
        .equ DMA1_FTFIFC1_Shift, 5   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 1)  
        .equ DMA1_HTFIFC1_Shift, 6   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 1)  
        .equ DMA1_ERRIFC1_Shift, 7   @ bitWidth 1 (Clear bit for error flag of channel 1)  
        .equ DMA1_GIFC2_Shift, 8   @ bitWidth 1 (Clear global interrupt flag of channel 2)  
        .equ DMA1_FTFIFC2_Shift, 9   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 2)  
        .equ DMA1_HTFIFC2_Shift, 10   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 2)  
        .equ DMA1_ERRIFC2_Shift, 11   @ bitWidth 1 (Clear bit for error flag of channel 2)  
        .equ DMA1_GIFC3_Shift, 12   @ bitWidth 1 (Clear global interrupt flag of channel 3)  
        .equ DMA1_FTFIFC3_Shift, 13   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 3)  
        .equ DMA1_HTFIFC3_Shift, 14   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 3)  
        .equ DMA1_ERRIFC3_Shift, 15   @ bitWidth 1 (Clear bit for error flag of channel 3)  
        .equ DMA1_GIFC4_Shift, 16   @ bitWidth 1 (Clear global interrupt flag of channel 4)  
        .equ DMA1_FTFIFC4_Shift, 17   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 4)  
        .equ DMA1_HTFIFC4_Shift, 18   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 4)  
        .equ DMA1_ERRIFC4_Shift, 19   @ bitWidth 1 (Clear bit for error flag of channel 4)  
 
    .equ DMA1_CH0CTL, DMA1_BASE + 0x08 @ (Channel 0 control register) 
        .equ DMA1_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH0CNT, DMA1_BASE + 0x0C @ (Channel 0 counter register) 
        .equ DMA1_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH0PADDR, DMA1_BASE + 0x10 @ (Channel 0 peripheral base address register) 
        .equ DMA1_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH0MADDR, DMA1_BASE + 0x14 @ (Channel 0 memory base address register) 
        .equ DMA1_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH1CTL, DMA1_BASE + 0x1C @ (Channel 1 control register) 
        .equ DMA1_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH1CNT, DMA1_BASE + 0x20 @ (Channel 1 counter register) 
        .equ DMA1_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH1PADDR, DMA1_BASE + 0x24 @ (Channel 1 peripheral base address register) 
        .equ DMA1_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH1MADDR, DMA1_BASE + 0x28 @ (Channel 1 memory base address register) 
        .equ DMA1_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH2CTL, DMA1_BASE + 0x30 @ (Channel 2 control register) 
        .equ DMA1_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH2CNT, DMA1_BASE + 0x34 @ (Channel 2 counter register) 
        .equ DMA1_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH2PADDR, DMA1_BASE + 0x38 @ (Channel 2 peripheral base address register) 
        .equ DMA1_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH2MADDR, DMA1_BASE + 0x3C @ (Channel 2 memory base address register) 
        .equ DMA1_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH3CTL, DMA1_BASE + 0x44 @ (Channel 3 control register) 
        .equ DMA1_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH3CNT, DMA1_BASE + 0x48 @ (Channel 3 counter register) 
        .equ DMA1_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH3PADDR, DMA1_BASE + 0x4C @ (Channel 3 peripheral base address register) 
        .equ DMA1_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH3MADDR, DMA1_BASE + 0x50 @ (Channel 3 memory base address register) 
        .equ DMA1_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH4CTL, DMA1_BASE + 0x58 @ (Channel 4 control register) 
        .equ DMA1_CHEN_Shift, 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_FTFIE_Shift, 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_HTFIE_Shift, 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_ERRIE_Shift, 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CMEN_Shift, 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_PNAGA_Shift, 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_MNAGA_Shift, 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_M2M_Shift, 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH4CNT, DMA1_BASE + 0x5C @ (Channel 4 counter register) 
        .equ DMA1_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH4PADDR, DMA1_BASE + 0x60 @ (Channel 4 peripheral base address register) 
        .equ DMA1_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH4MADDR, DMA1_BASE + 0x64 @ (Channel 4 memory base address register) 
        .equ DMA1_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 

@=========================== EXMC ===========================@
.equ EXMC_BASE, 0xA0000000 @ (External memory controller) 
    .equ EXMC_SNCTL0, EXMC_BASE + 0x0 @ (SRAM/NOR flash control register 0) 
        .equ EXMC_ASYNCWAIT_Shift, 15   @ bitWidth 1 (Asynchronous wait)  
        .equ EXMC_NRWTEN_Shift, 13   @ bitWidth 1 (NWAIT signal enable)  
        .equ EXMC_WREN_Shift, 12   @ bitWidth 1 (Write enable)  
        .equ EXMC_NRWTPOL_Shift, 9   @ bitWidth 1 (NWAIT signal polarity)  
        .equ EXMC_NREN_Shift, 6   @ bitWidth 1 (NOR Flash access enable)  
        .equ EXMC_NRW_Shift, 4   @ bitWidth 2 (NOR bank memory data bus width)  
        .equ EXMC_NRTP_Shift, 2   @ bitWidth 2 (NOR bank memory type)  
        .equ EXMC_NRMUX_Shift, 1   @ bitWidth 1 (NOR bank memory address/data multiplexing)  
        .equ EXMC_NRBKEN_Shift, 0   @ bitWidth 1 (NOR bank enable)  
 
    .equ EXMC_SNTCFG0, EXMC_BASE + 0x4 @ (SRAM/NOR flash timing configuration register 0) 
        .equ EXMC_BUSLAT_Shift, 16   @ bitWidth 4 (Bus latency)  
        .equ EXMC_DSET_Shift, 8   @ bitWidth 8 (Data setup time)  
        .equ EXMC_AHLD_Shift, 4   @ bitWidth 4 (Address hold time)  
        .equ EXMC_ASET_Shift, 0   @ bitWidth 4 (Address setup time)  
 
    .equ EXMC_SNCTL1, EXMC_BASE + 0x8 @ (SRAM/NOR flash control register 1) 
        .equ EXMC_ASYNCWAIT_Shift, 15   @ bitWidth 1 (Asynchronous wait)  
        .equ EXMC_NRWTEN_Shift, 13   @ bitWidth 1 (NWAIT signal enable)  
        .equ EXMC_WREN_Shift, 12   @ bitWidth 1 (Write enable)  
        .equ EXMC_NRWTPOL_Shift, 9   @ bitWidth 1 (NWAIT signal polarity)  
        .equ EXMC_NREN_Shift, 6   @ bitWidth 1 (NOR Flash access enable)  
        .equ EXMC_NRW_Shift, 4   @ bitWidth 2 (NOR bank memory data bus width)  
        .equ EXMC_NRTP_Shift, 2   @ bitWidth 2 (NOR bank memory type)  
        .equ EXMC_NRMUX_Shift, 1   @ bitWidth 1 (NOR bank memory address/data multiplexing)  
        .equ EXMC_NRBKEN_Shift, 0   @ bitWidth 1 (NOR bank enable)  
 

@=========================== EXTI ===========================@
.equ EXTI_BASE, 0x40010400 @ (External interrupt/event  controller) 
    .equ EXTI_INTEN, EXTI_BASE + 0x0 @ (Interrupt enable register  EXTI_INTEN) 
        .equ EXTI_INTEN0_Shift, 0   @ bitWidth 1 (Enable Interrupt on line 0)  
        .equ EXTI_INTEN1_Shift, 1   @ bitWidth 1 (Enable Interrupt on line 1)  
        .equ EXTI_INTEN2_Shift, 2   @ bitWidth 1 (Enable Interrupt on line 2)  
        .equ EXTI_INTEN3_Shift, 3   @ bitWidth 1 (Enable Interrupt on line 3)  
        .equ EXTI_INTEN4_Shift, 4   @ bitWidth 1 (Enable Interrupt on line 4)  
        .equ EXTI_INTEN5_Shift, 5   @ bitWidth 1 (Enable Interrupt on line 5)  
        .equ EXTI_INTEN6_Shift, 6   @ bitWidth 1 (Enable Interrupt on line 6)  
        .equ EXTI_INTEN7_Shift, 7   @ bitWidth 1 (Enable Interrupt on line 7)  
        .equ EXTI_INTEN8_Shift, 8   @ bitWidth 1 (Enable Interrupt on line 8)  
        .equ EXTI_INTEN9_Shift, 9   @ bitWidth 1 (Enable Interrupt on line 9)  
        .equ EXTI_INTEN10_Shift, 10   @ bitWidth 1 (Enable Interrupt on line 10)  
        .equ EXTI_INTEN11_Shift, 11   @ bitWidth 1 (Enable Interrupt on line 11)  
        .equ EXTI_INTEN12_Shift, 12   @ bitWidth 1 (Enable Interrupt on line 12)  
        .equ EXTI_INTEN13_Shift, 13   @ bitWidth 1 (Enable Interrupt on line 13)  
        .equ EXTI_INTEN14_Shift, 14   @ bitWidth 1 (Enable Interrupt on line 14)  
        .equ EXTI_INTEN15_Shift, 15   @ bitWidth 1 (Enable Interrupt on line 15)  
        .equ EXTI_INTEN16_Shift, 16   @ bitWidth 1 (Enable Interrupt on line 16)  
        .equ EXTI_INTEN17_Shift, 17   @ bitWidth 1 (Enable Interrupt on line 17)  
        .equ EXTI_INTEN18_Shift, 18   @ bitWidth 1 (Enable Interrupt on line 18)  
 
    .equ EXTI_EVEN, EXTI_BASE + 0x04 @ (Event enable register EXTI_EVEN) 
        .equ EXTI_EVEN0_Shift, 0   @ bitWidth 1 (Enable Event on line 0)  
        .equ EXTI_EVEN1_Shift, 1   @ bitWidth 1 (Enable Event on line 1)  
        .equ EXTI_EVEN2_Shift, 2   @ bitWidth 1 (Enable Event on line 2)  
        .equ EXTI_EVEN3_Shift, 3   @ bitWidth 1 (Enable Event on line 3)  
        .equ EXTI_EVEN4_Shift, 4   @ bitWidth 1 (Enable Event on line 4)  
        .equ EXTI_EVEN5_Shift, 5   @ bitWidth 1 (Enable Event on line 5)  
        .equ EXTI_EVEN6_Shift, 6   @ bitWidth 1 (Enable Event on line 6)  
        .equ EXTI_EVEN7_Shift, 7   @ bitWidth 1 (Enable Event on line 7)  
        .equ EXTI_EVEN8_Shift, 8   @ bitWidth 1 (Enable Event on line 8)  
        .equ EXTI_EVEN9_Shift, 9   @ bitWidth 1 (Enable Event on line 9)  
        .equ EXTI_EVEN10_Shift, 10   @ bitWidth 1 (Enable Event on line 10)  
        .equ EXTI_EVEN11_Shift, 11   @ bitWidth 1 (Enable Event on line 11)  
        .equ EXTI_EVEN12_Shift, 12   @ bitWidth 1 (Enable Event on line 12)  
        .equ EXTI_EVEN13_Shift, 13   @ bitWidth 1 (Enable Event on line 13)  
        .equ EXTI_EVEN14_Shift, 14   @ bitWidth 1 (Enable Event on line 14)  
        .equ EXTI_EVEN15_Shift, 15   @ bitWidth 1 (Enable Event on line 15)  
        .equ EXTI_EVEN16_Shift, 16   @ bitWidth 1 (Enable Event on line 16)  
        .equ EXTI_EVEN17_Shift, 17   @ bitWidth 1 (Enable Event on line 17)  
        .equ EXTI_EVEN18_Shift, 18   @ bitWidth 1 (Enable Event on line 18)  
 
    .equ EXTI_RTEN, EXTI_BASE + 0x08 @ (Rising Edge Trigger Enable register  EXTI_RTEN) 
        .equ EXTI_RTEN0_Shift, 0   @ bitWidth 1 (Rising edge trigger enable of  line 0)  
        .equ EXTI_RTEN1_Shift, 1   @ bitWidth 1 (Rising edge trigger enable of  line 1)  
        .equ EXTI_RTEN2_Shift, 2   @ bitWidth 1 (Rising edge trigger enable of  line 2)  
        .equ EXTI_RTEN3_Shift, 3   @ bitWidth 1 (Rising edge trigger enable of  line 3)  
        .equ EXTI_RTEN4_Shift, 4   @ bitWidth 1 (Rising edge trigger enable of  line 4)  
        .equ EXTI_RTEN5_Shift, 5   @ bitWidth 1 (Rising edge trigger enable of  line 5)  
        .equ EXTI_RTEN6_Shift, 6   @ bitWidth 1 (Rising edge trigger enable of  line 6)  
        .equ EXTI_RTEN7_Shift, 7   @ bitWidth 1 (Rising edge trigger enable of  line 7)  
        .equ EXTI_RTEN8_Shift, 8   @ bitWidth 1 (Rising edge trigger enable of  line 8)  
        .equ EXTI_RTEN9_Shift, 9   @ bitWidth 1 (Rising edge trigger enable of  line 9)  
        .equ EXTI_RTEN10_Shift, 10   @ bitWidth 1 (Rising edge trigger enable of  line 10)  
        .equ EXTI_RTEN11_Shift, 11   @ bitWidth 1 (Rising edge trigger enable of  line 11)  
        .equ EXTI_RTEN12_Shift, 12   @ bitWidth 1 (Rising edge trigger enable of  line 12)  
        .equ EXTI_RTEN13_Shift, 13   @ bitWidth 1 (Rising edge trigger enable of  line 13)  
        .equ EXTI_RTEN14_Shift, 14   @ bitWidth 1 (Rising edge trigger enable of  line 14)  
        .equ EXTI_RTEN15_Shift, 15   @ bitWidth 1 (Rising edge trigger enable of  line 15)  
        .equ EXTI_RTEN16_Shift, 16   @ bitWidth 1 (Rising edge trigger enable of  line 16)  
        .equ EXTI_RTEN17_Shift, 17   @ bitWidth 1 (Rising edge trigger enable of  line 17)  
        .equ EXTI_RTEN18_Shift, 18   @ bitWidth 1 (Rising edge trigger enable of  line 18)  
 
    .equ EXTI_FTEN, EXTI_BASE + 0x0C @ (Falling Egde Trigger Enable register  EXTI_FTEN) 
        .equ EXTI_FTEN0_Shift, 0   @ bitWidth 1 (Falling edge trigger enable of  line 0)  
        .equ EXTI_FTEN1_Shift, 1   @ bitWidth 1 (Falling edge trigger enable of  line 1)  
        .equ EXTI_FTEN2_Shift, 2   @ bitWidth 1 (Falling edge trigger enable of  line 2)  
        .equ EXTI_FTEN3_Shift, 3   @ bitWidth 1 (Falling edge trigger enable of  line 3)  
        .equ EXTI_FTEN4_Shift, 4   @ bitWidth 1 (Falling edge trigger enable of  line 4)  
        .equ EXTI_FTEN5_Shift, 5   @ bitWidth 1 (Falling edge trigger enable of  line 5)  
        .equ EXTI_FTEN6_Shift, 6   @ bitWidth 1 (Falling edge trigger enable of  line 6)  
        .equ EXTI_FTEN7_Shift, 7   @ bitWidth 1 (Falling edge trigger enable of  line 7)  
        .equ EXTI_FTEN8_Shift, 8   @ bitWidth 1 (Falling edge trigger enable of  line 8)  
        .equ EXTI_FTEN9_Shift, 9   @ bitWidth 1 (Falling edge trigger enable of  line 9)  
        .equ EXTI_FTEN10_Shift, 10   @ bitWidth 1 (Falling edge trigger enable of  line 10)  
        .equ EXTI_FTEN11_Shift, 11   @ bitWidth 1 (Falling edge trigger enable of  line 11)  
        .equ EXTI_FTEN12_Shift, 12   @ bitWidth 1 (Falling edge trigger enable of  line 12)  
        .equ EXTI_FTEN13_Shift, 13   @ bitWidth 1 (Falling edge trigger enable of  line 13)  
        .equ EXTI_FTEN14_Shift, 14   @ bitWidth 1 (Falling edge trigger enable of  line 14)  
        .equ EXTI_FTEN15_Shift, 15   @ bitWidth 1 (Falling edge trigger enable of  line 15)  
        .equ EXTI_FTEN16_Shift, 16   @ bitWidth 1 (Falling edge trigger enable of  line 16)  
        .equ EXTI_FTEN17_Shift, 17   @ bitWidth 1 (Falling edge trigger enable of  line 17)  
        .equ EXTI_FTEN18_Shift, 18   @ bitWidth 1 (Falling edge trigger enable of  line 18)  
 
    .equ EXTI_SWIEV, EXTI_BASE + 0x10 @ (Software interrupt event register  EXTI_SWIEV) 
        .equ EXTI_SWIEV0_Shift, 0   @ bitWidth 1 (Interrupt/Event software trigger on line  0)  
        .equ EXTI_SWIEV1_Shift, 1   @ bitWidth 1 (Interrupt/Event software trigger on line  1)  
        .equ EXTI_SWIEV2_Shift, 2   @ bitWidth 1 (Interrupt/Event software trigger on line  2)  
        .equ EXTI_SWIEV3_Shift, 3   @ bitWidth 1 (Interrupt/Event software trigger on line  3)  
        .equ EXTI_SWIEV4_Shift, 4   @ bitWidth 1 (Interrupt/Event software trigger on line  4)  
        .equ EXTI_SWIEV5_Shift, 5   @ bitWidth 1 (Interrupt/Event software trigger on line  5)  
        .equ EXTI_SWIEV6_Shift, 6   @ bitWidth 1 (Interrupt/Event software trigger on line  6)  
        .equ EXTI_SWIEV7_Shift, 7   @ bitWidth 1 (Interrupt/Event software trigger on line  7)  
        .equ EXTI_SWIEV8_Shift, 8   @ bitWidth 1 (Interrupt/Event software trigger on line  8)  
        .equ EXTI_SWIEV9_Shift, 9   @ bitWidth 1 (Interrupt/Event software trigger on line  9)  
        .equ EXTI_SWIEV10_Shift, 10   @ bitWidth 1 (Interrupt/Event software trigger on line  10)  
        .equ EXTI_SWIEV11_Shift, 11   @ bitWidth 1 (Interrupt/Event software trigger on line  11)  
        .equ EXTI_SWIEV12_Shift, 12   @ bitWidth 1 (Interrupt/Event software trigger on line  12)  
        .equ EXTI_SWIEV13_Shift, 13   @ bitWidth 1 (Interrupt/Event software trigger on line  13)  
        .equ EXTI_SWIEV14_Shift, 14   @ bitWidth 1 (Interrupt/Event software trigger on line  14)  
        .equ EXTI_SWIEV15_Shift, 15   @ bitWidth 1 (Interrupt/Event software trigger on line  15)  
        .equ EXTI_SWIEV16_Shift, 16   @ bitWidth 1 (Interrupt/Event software trigger on line  16)  
        .equ EXTI_SWIEV17_Shift, 17   @ bitWidth 1 (Interrupt/Event software trigger on line  17)  
        .equ EXTI_SWIEV18_Shift, 18   @ bitWidth 1 (Interrupt/Event software trigger on line  18)  
 
    .equ EXTI_PD, EXTI_BASE + 0x14 @ (Pending register EXTI_PD) 
        .equ EXTI_PD0_Shift, 0   @ bitWidth 1 (Interrupt pending status of line 0)  
        .equ EXTI_PD1_Shift, 1   @ bitWidth 1 (Interrupt pending status of line 1)  
        .equ EXTI_PD2_Shift, 2   @ bitWidth 1 (Interrupt pending status of line 2)  
        .equ EXTI_PD3_Shift, 3   @ bitWidth 1 (Interrupt pending status of line 3)  
        .equ EXTI_PD4_Shift, 4   @ bitWidth 1 (Interrupt pending status of line 4)  
        .equ EXTI_PD5_Shift, 5   @ bitWidth 1 (Interrupt pending status of line 5)  
        .equ EXTI_PD6_Shift, 6   @ bitWidth 1 (Interrupt pending status of line 6)  
        .equ EXTI_PD7_Shift, 7   @ bitWidth 1 (Interrupt pending status of line 7)  
        .equ EXTI_PD8_Shift, 8   @ bitWidth 1 (Interrupt pending status of line 8)  
        .equ EXTI_PD9_Shift, 9   @ bitWidth 1 (Interrupt pending status of line 9)  
        .equ EXTI_PD10_Shift, 10   @ bitWidth 1 (Interrupt pending status of line 10)  
        .equ EXTI_PD11_Shift, 11   @ bitWidth 1 (Interrupt pending status of line 11)  
        .equ EXTI_PD12_Shift, 12   @ bitWidth 1 (Interrupt pending status of line 12)  
        .equ EXTI_PD13_Shift, 13   @ bitWidth 1 (Interrupt pending status of line 13)  
        .equ EXTI_PD14_Shift, 14   @ bitWidth 1 (Interrupt pending status of line 14)  
        .equ EXTI_PD15_Shift, 15   @ bitWidth 1 (Interrupt pending status of line 15)  
        .equ EXTI_PD16_Shift, 16   @ bitWidth 1 (Interrupt pending status of line 16)  
        .equ EXTI_PD17_Shift, 17   @ bitWidth 1 (Interrupt pending status of line 17)  
        .equ EXTI_PD18_Shift, 18   @ bitWidth 1 (Interrupt pending status of line 18)  
 

@=========================== FMC ===========================@
.equ FMC_BASE, 0x40022000 @ (FMC) 
    .equ FMC_WS, FMC_BASE + 0x0 @ (wait state counter register) 
        .equ FMC_WSCNT_Shift, 0   @ bitWidth 3 (wait state counter register)  
 
    .equ FMC_KEY0, FMC_BASE + 0x04 @ (Unlock key register 0) 
        .equ FMC_KEY_Shift, 0   @ bitWidth 32 (FMC_CTL0 unlock key)  
 
    .equ FMC_OBKEY, FMC_BASE + 0x08 @ (Option byte unlock key register) 
        .equ FMC_OBKEY_Shift, 0   @ bitWidth 32 (FMC_ CTL0 option byte operation unlock register)  
 
    .equ FMC_STAT0, FMC_BASE + 0x0C @ (Status register 0) 
        .equ FMC_ENDF_Shift, 5   @ bitWidth 1 (End of operation flag bit)  
        .equ FMC_WPERR_Shift, 4   @ bitWidth 1 (Erase/Program protection error flag bit)  
        .equ FMC_PGERR_Shift, 2   @ bitWidth 1 (Program error flag bit)  
        .equ FMC_BUSY_Shift, 0   @ bitWidth 1 (The flash is busy bit)  
 
    .equ FMC_CTL0, FMC_BASE + 0x10 @ (Control register 0) 
        .equ FMC_ENDIE_Shift, 12   @ bitWidth 1 (End of operation interrupt enable bit)  
        .equ FMC_ERRIE_Shift, 10   @ bitWidth 1 (Error interrupt enable bit)  
        .equ FMC_OBWEN_Shift, 9   @ bitWidth 1 (Option byte erase/program enable bit)  
        .equ FMC_LK_Shift, 7   @ bitWidth 1 (FMC_CTL0 lock bit)  
        .equ FMC_START_Shift, 6   @ bitWidth 1 (Send erase command to FMC bit)  
        .equ FMC_OBER_Shift, 5   @ bitWidth 1 (Option bytes erase command bit)  
        .equ FMC_OBPG_Shift, 4   @ bitWidth 1 (Option bytes program command bit)  
        .equ FMC_MER_Shift, 2   @ bitWidth 1 (Main flash mass erase for bank0 command bit)  
        .equ FMC_PER_Shift, 1   @ bitWidth 1 (Main flash page erase for bank0 command bit)  
        .equ FMC_PG_Shift, 0   @ bitWidth 1 (Main flash program for bank0 command bit)  
 
    .equ FMC_ADDR0, FMC_BASE + 0x14 @ (Address register 0) 
        .equ FMC_ADDR_Shift, 0   @ bitWidth 32 (Flash erase/program command address bits)  
 
    .equ FMC_OBSTAT, FMC_BASE + 0x1C @ (Option byte status register) 
        .equ FMC_OBERR_Shift, 0   @ bitWidth 1 (Option bytes read error bit)  
        .equ FMC_SPC_Shift, 1   @ bitWidth 1 (Option bytes security protection code)  
        .equ FMC_USER_Shift, 2   @ bitWidth 8 (Store USER of option bytes block after system reset)  
        .equ FMC_DATA_Shift, 10   @ bitWidth 16 (Store DATA[15:0] of option bytes block after system reset)  
 
    .equ FMC_WP, FMC_BASE + 0x20 @ (Erase/Program Protection register) 
        .equ FMC_WP_Shift, 0   @ bitWidth 32 (Store WP[31:0] of option bytes block after system reset)  
 
    .equ FMC_PID, FMC_BASE + 0x100 @ (Product ID register) 
        .equ FMC_PID_Shift, 0   @ bitWidth 32 (Product reserved ID code register)  
 

@=========================== FWDGT ===========================@
.equ FWDGT_BASE, 0x40003000 @ (free watchdog timer) 
    .equ FWDGT_CTL, FWDGT_BASE + 0x00 @ (Control register) 
        .equ FWDGT_CMD_Shift, 0   @ bitWidth 16 (Key value)  
 
    .equ FWDGT_PSC, FWDGT_BASE + 0x04 @ (Prescaler register) 
        .equ FWDGT_PSC_Shift, 0   @ bitWidth 3 (Free watchdog timer prescaler selection)  
 
    .equ FWDGT_RLD, FWDGT_BASE + 0x08 @ (Reload register) 
        .equ FWDGT_RLD_Shift, 0   @ bitWidth 12 (Free watchdog timer counter reload value)  
 
    .equ FWDGT_STAT, FWDGT_BASE + 0x0C @ (Status register) 
        .equ FWDGT_PUD_Shift, 0   @ bitWidth 1 (Free watchdog timer prescaler value update)  
        .equ FWDGT_RUD_Shift, 1   @ bitWidth 1 (Free watchdog timer counter reload value update)  
 

@=========================== GPIOA ===========================@
.equ GPIOA_BASE, 0x40010800 @ (General-purpose I/Os) 
    .equ GPIOA_CTL0, GPIOA_BASE + 0x0 @ (port control register 0) 
        .equ GPIOA_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOA_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOA_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOA_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOA_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOA_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOA_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOA_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOA_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOA_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOA_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOA_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOA_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOA_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOA_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOA_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOA_CTL1, GPIOA_BASE + 0x04 @ (port control register 1) 
        .equ GPIOA_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOA_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOA_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOA_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOA_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOA_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOA_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOA_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOA_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOA_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOA_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOA_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOA_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOA_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOA_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOA_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOA_ISTAT, GPIOA_BASE + 0x08 @ (Port input status register) 
        .equ GPIOA_ISTAT15_Shift, 15   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT14_Shift, 14   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT13_Shift, 13   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT12_Shift, 12   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT11_Shift, 11   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT10_Shift, 10   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT9_Shift, 9   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT8_Shift, 8   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT7_Shift, 7   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT6_Shift, 6   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT5_Shift, 5   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT4_Shift, 4   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT3_Shift, 3   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT2_Shift, 2   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT1_Shift, 1   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT0_Shift, 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOA_OCTL, GPIOA_BASE + 0x0C @ (Port output control register) 
        .equ GPIOA_OCTL15_Shift, 15   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL14_Shift, 14   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL13_Shift, 13   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL12_Shift, 12   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL11_Shift, 11   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL10_Shift, 10   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL9_Shift, 9   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL8_Shift, 8   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL7_Shift, 7   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL6_Shift, 6   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL5_Shift, 5   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL4_Shift, 4   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL3_Shift, 3   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL2_Shift, 2   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL1_Shift, 1   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL0_Shift, 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOA_BOP, GPIOA_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOA_CR15_Shift, 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOA_CR14_Shift, 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOA_CR13_Shift, 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOA_CR12_Shift, 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOA_CR11_Shift, 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOA_CR10_Shift, 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOA_CR9_Shift, 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOA_CR8_Shift, 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOA_CR7_Shift, 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOA_CR6_Shift, 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOA_CR5_Shift, 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOA_CR4_Shift, 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOA_CR3_Shift, 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOA_CR2_Shift, 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOA_CR1_Shift, 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOA_CR0_Shift, 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOA_BOP15_Shift, 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOA_BOP14_Shift, 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOA_BOP13_Shift, 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOA_BOP12_Shift, 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOA_BOP11_Shift, 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOA_BOP10_Shift, 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOA_BOP9_Shift, 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOA_BOP8_Shift, 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOA_BOP7_Shift, 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOA_BOP6_Shift, 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOA_BOP5_Shift, 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOA_BOP4_Shift, 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOA_BOP3_Shift, 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOA_BOP2_Shift, 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOA_BOP1_Shift, 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOA_BOP0_Shift, 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOA_BC, GPIOA_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOA_CR15_Shift, 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOA_CR14_Shift, 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOA_CR13_Shift, 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOA_CR12_Shift, 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOA_CR11_Shift, 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOA_CR10_Shift, 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOA_CR9_Shift, 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOA_CR8_Shift, 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOA_CR7_Shift, 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOA_CR6_Shift, 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOA_CR5_Shift, 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOA_CR4_Shift, 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOA_CR3_Shift, 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOA_CR2_Shift, 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOA_CR1_Shift, 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOA_CR0_Shift, 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOA_LOCK, GPIOA_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOA_LKK_Shift, 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOA_LK15_Shift, 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOA_LK14_Shift, 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOA_LK13_Shift, 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOA_LK12_Shift, 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOA_LK11_Shift, 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOA_LK10_Shift, 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOA_LK9_Shift, 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOA_LK8_Shift, 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOA_LK7_Shift, 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOA_LK6_Shift, 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOA_LK5_Shift, 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOA_LK4_Shift, 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOA_LK3_Shift, 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOA_LK2_Shift, 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOA_LK1_Shift, 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOA_LK0_Shift, 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOB ===========================@
.equ GPIOB_BASE, 0x40010C00 @ (General-purpose I/Os) 
    .equ GPIOB_CTL0, GPIOB_BASE + 0x0 @ (port control register 0) 
        .equ GPIOB_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOB_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOB_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOB_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOB_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOB_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOB_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOB_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOB_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOB_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOB_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOB_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOB_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOB_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOB_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOB_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOB_CTL1, GPIOB_BASE + 0x04 @ (port control register 1) 
        .equ GPIOB_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOB_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOB_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOB_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOB_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOB_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOB_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOB_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOB_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOB_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOB_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOB_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOB_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOB_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOB_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOB_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOB_ISTAT, GPIOB_BASE + 0x08 @ (Port input status register) 
        .equ GPIOB_ISTAT15_Shift, 15   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT14_Shift, 14   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT13_Shift, 13   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT12_Shift, 12   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT11_Shift, 11   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT10_Shift, 10   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT9_Shift, 9   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT8_Shift, 8   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT7_Shift, 7   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT6_Shift, 6   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT5_Shift, 5   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT4_Shift, 4   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT3_Shift, 3   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT2_Shift, 2   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT1_Shift, 1   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT0_Shift, 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOB_OCTL, GPIOB_BASE + 0x0C @ (Port output control register) 
        .equ GPIOB_OCTL15_Shift, 15   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL14_Shift, 14   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL13_Shift, 13   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL12_Shift, 12   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL11_Shift, 11   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL10_Shift, 10   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL9_Shift, 9   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL8_Shift, 8   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL7_Shift, 7   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL6_Shift, 6   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL5_Shift, 5   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL4_Shift, 4   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL3_Shift, 3   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL2_Shift, 2   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL1_Shift, 1   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL0_Shift, 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOB_BOP, GPIOB_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOB_CR15_Shift, 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOB_CR14_Shift, 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOB_CR13_Shift, 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOB_CR12_Shift, 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOB_CR11_Shift, 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOB_CR10_Shift, 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOB_CR9_Shift, 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOB_CR8_Shift, 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOB_CR7_Shift, 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOB_CR6_Shift, 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOB_CR5_Shift, 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOB_CR4_Shift, 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOB_CR3_Shift, 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOB_CR2_Shift, 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOB_CR1_Shift, 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOB_CR0_Shift, 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOB_BOP15_Shift, 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOB_BOP14_Shift, 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOB_BOP13_Shift, 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOB_BOP12_Shift, 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOB_BOP11_Shift, 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOB_BOP10_Shift, 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOB_BOP9_Shift, 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOB_BOP8_Shift, 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOB_BOP7_Shift, 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOB_BOP6_Shift, 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOB_BOP5_Shift, 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOB_BOP4_Shift, 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOB_BOP3_Shift, 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOB_BOP2_Shift, 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOB_BOP1_Shift, 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOB_BOP0_Shift, 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOB_BC, GPIOB_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOB_CR15_Shift, 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOB_CR14_Shift, 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOB_CR13_Shift, 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOB_CR12_Shift, 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOB_CR11_Shift, 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOB_CR10_Shift, 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOB_CR9_Shift, 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOB_CR8_Shift, 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOB_CR7_Shift, 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOB_CR6_Shift, 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOB_CR5_Shift, 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOB_CR4_Shift, 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOB_CR3_Shift, 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOB_CR2_Shift, 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOB_CR1_Shift, 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOB_CR0_Shift, 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOB_LOCK, GPIOB_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOB_LKK_Shift, 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOB_LK15_Shift, 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOB_LK14_Shift, 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOB_LK13_Shift, 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOB_LK12_Shift, 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOB_LK11_Shift, 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOB_LK10_Shift, 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOB_LK9_Shift, 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOB_LK8_Shift, 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOB_LK7_Shift, 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOB_LK6_Shift, 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOB_LK5_Shift, 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOB_LK4_Shift, 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOB_LK3_Shift, 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOB_LK2_Shift, 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOB_LK1_Shift, 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOB_LK0_Shift, 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOC ===========================@
.equ GPIOC_BASE, 0x40011000 @ (General-purpose I/Os) 
    .equ GPIOC_CTL0, GPIOC_BASE + 0x0 @ (port control register 0) 
        .equ GPIOC_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOC_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOC_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOC_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOC_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOC_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOC_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOC_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOC_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOC_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOC_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOC_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOC_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOC_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOC_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOC_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOC_CTL1, GPIOC_BASE + 0x04 @ (port control register 1) 
        .equ GPIOC_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOC_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOC_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOC_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOC_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOC_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOC_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOC_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOC_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOC_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOC_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOC_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOC_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOC_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOC_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOC_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOC_ISTAT, GPIOC_BASE + 0x08 @ (Port input status register) 
        .equ GPIOC_ISTAT15_Shift, 15   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT14_Shift, 14   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT13_Shift, 13   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT12_Shift, 12   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT11_Shift, 11   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT10_Shift, 10   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT9_Shift, 9   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT8_Shift, 8   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT7_Shift, 7   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT6_Shift, 6   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT5_Shift, 5   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT4_Shift, 4   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT3_Shift, 3   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT2_Shift, 2   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT1_Shift, 1   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT0_Shift, 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOC_OCTL, GPIOC_BASE + 0x0C @ (Port output control register) 
        .equ GPIOC_OCTL15_Shift, 15   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL14_Shift, 14   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL13_Shift, 13   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL12_Shift, 12   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL11_Shift, 11   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL10_Shift, 10   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL9_Shift, 9   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL8_Shift, 8   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL7_Shift, 7   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL6_Shift, 6   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL5_Shift, 5   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL4_Shift, 4   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL3_Shift, 3   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL2_Shift, 2   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL1_Shift, 1   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL0_Shift, 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOC_BOP, GPIOC_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOC_CR15_Shift, 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOC_CR14_Shift, 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOC_CR13_Shift, 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOC_CR12_Shift, 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOC_CR11_Shift, 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOC_CR10_Shift, 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOC_CR9_Shift, 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOC_CR8_Shift, 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOC_CR7_Shift, 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOC_CR6_Shift, 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOC_CR5_Shift, 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOC_CR4_Shift, 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOC_CR3_Shift, 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOC_CR2_Shift, 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOC_CR1_Shift, 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOC_CR0_Shift, 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOC_BOP15_Shift, 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOC_BOP14_Shift, 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOC_BOP13_Shift, 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOC_BOP12_Shift, 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOC_BOP11_Shift, 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOC_BOP10_Shift, 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOC_BOP9_Shift, 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOC_BOP8_Shift, 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOC_BOP7_Shift, 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOC_BOP6_Shift, 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOC_BOP5_Shift, 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOC_BOP4_Shift, 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOC_BOP3_Shift, 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOC_BOP2_Shift, 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOC_BOP1_Shift, 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOC_BOP0_Shift, 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOC_BC, GPIOC_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOC_CR15_Shift, 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOC_CR14_Shift, 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOC_CR13_Shift, 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOC_CR12_Shift, 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOC_CR11_Shift, 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOC_CR10_Shift, 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOC_CR9_Shift, 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOC_CR8_Shift, 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOC_CR7_Shift, 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOC_CR6_Shift, 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOC_CR5_Shift, 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOC_CR4_Shift, 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOC_CR3_Shift, 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOC_CR2_Shift, 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOC_CR1_Shift, 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOC_CR0_Shift, 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOC_LOCK, GPIOC_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOC_LKK_Shift, 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOC_LK15_Shift, 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOC_LK14_Shift, 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOC_LK13_Shift, 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOC_LK12_Shift, 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOC_LK11_Shift, 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOC_LK10_Shift, 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOC_LK9_Shift, 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOC_LK8_Shift, 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOC_LK7_Shift, 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOC_LK6_Shift, 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOC_LK5_Shift, 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOC_LK4_Shift, 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOC_LK3_Shift, 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOC_LK2_Shift, 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOC_LK1_Shift, 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOC_LK0_Shift, 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOD ===========================@
.equ GPIOD_BASE, 0x40011400 @ (General-purpose I/Os) 
    .equ GPIOD_CTL0, GPIOD_BASE + 0x0 @ (port control register 0) 
        .equ GPIOD_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOD_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOD_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOD_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOD_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOD_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOD_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOD_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOD_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOD_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOD_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOD_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOD_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOD_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOD_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOD_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOD_CTL1, GPIOD_BASE + 0x04 @ (port control register 1) 
        .equ GPIOD_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOD_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOD_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOD_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOD_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOD_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOD_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOD_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOD_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOD_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOD_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOD_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOD_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOD_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOD_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOD_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOD_ISTAT, GPIOD_BASE + 0x08 @ (Port input status register) 
        .equ GPIOD_ISTAT15_Shift, 15   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT14_Shift, 14   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT13_Shift, 13   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT12_Shift, 12   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT11_Shift, 11   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT10_Shift, 10   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT9_Shift, 9   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT8_Shift, 8   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT7_Shift, 7   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT6_Shift, 6   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT5_Shift, 5   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT4_Shift, 4   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT3_Shift, 3   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT2_Shift, 2   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT1_Shift, 1   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT0_Shift, 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOD_OCTL, GPIOD_BASE + 0x0C @ (Port output control register) 
        .equ GPIOD_OCTL15_Shift, 15   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL14_Shift, 14   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL13_Shift, 13   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL12_Shift, 12   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL11_Shift, 11   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL10_Shift, 10   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL9_Shift, 9   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL8_Shift, 8   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL7_Shift, 7   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL6_Shift, 6   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL5_Shift, 5   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL4_Shift, 4   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL3_Shift, 3   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL2_Shift, 2   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL1_Shift, 1   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL0_Shift, 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOD_BOP, GPIOD_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOD_CR15_Shift, 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOD_CR14_Shift, 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOD_CR13_Shift, 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOD_CR12_Shift, 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOD_CR11_Shift, 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOD_CR10_Shift, 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOD_CR9_Shift, 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOD_CR8_Shift, 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOD_CR7_Shift, 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOD_CR6_Shift, 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOD_CR5_Shift, 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOD_CR4_Shift, 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOD_CR3_Shift, 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOD_CR2_Shift, 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOD_CR1_Shift, 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOD_CR0_Shift, 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOD_BOP15_Shift, 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOD_BOP14_Shift, 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOD_BOP13_Shift, 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOD_BOP12_Shift, 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOD_BOP11_Shift, 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOD_BOP10_Shift, 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOD_BOP9_Shift, 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOD_BOP8_Shift, 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOD_BOP7_Shift, 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOD_BOP6_Shift, 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOD_BOP5_Shift, 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOD_BOP4_Shift, 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOD_BOP3_Shift, 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOD_BOP2_Shift, 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOD_BOP1_Shift, 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOD_BOP0_Shift, 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOD_BC, GPIOD_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOD_CR15_Shift, 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOD_CR14_Shift, 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOD_CR13_Shift, 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOD_CR12_Shift, 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOD_CR11_Shift, 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOD_CR10_Shift, 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOD_CR9_Shift, 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOD_CR8_Shift, 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOD_CR7_Shift, 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOD_CR6_Shift, 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOD_CR5_Shift, 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOD_CR4_Shift, 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOD_CR3_Shift, 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOD_CR2_Shift, 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOD_CR1_Shift, 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOD_CR0_Shift, 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOD_LOCK, GPIOD_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOD_LKK_Shift, 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOD_LK15_Shift, 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOD_LK14_Shift, 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOD_LK13_Shift, 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOD_LK12_Shift, 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOD_LK11_Shift, 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOD_LK10_Shift, 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOD_LK9_Shift, 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOD_LK8_Shift, 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOD_LK7_Shift, 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOD_LK6_Shift, 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOD_LK5_Shift, 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOD_LK4_Shift, 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOD_LK3_Shift, 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOD_LK2_Shift, 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOD_LK1_Shift, 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOD_LK0_Shift, 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOE ===========================@
.equ GPIOE_BASE, 0x40011800 @ (General-purpose I/Os) 
    .equ GPIOE_CTL0, GPIOE_BASE + 0x0 @ (port control register 0) 
        .equ GPIOE_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOE_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOE_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOE_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOE_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOE_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOE_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOE_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOE_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOE_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOE_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOE_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOE_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOE_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOE_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOE_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOE_CTL1, GPIOE_BASE + 0x04 @ (port control register 1) 
        .equ GPIOE_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOE_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOE_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOE_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOE_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOE_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOE_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOE_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOE_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOE_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOE_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOE_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOE_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOE_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOE_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOE_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOE_ISTAT, GPIOE_BASE + 0x08 @ (Port input status register) 
        .equ GPIOE_ISTAT15_Shift, 15   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT14_Shift, 14   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT13_Shift, 13   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT12_Shift, 12   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT11_Shift, 11   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT10_Shift, 10   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT9_Shift, 9   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT8_Shift, 8   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT7_Shift, 7   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT6_Shift, 6   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT5_Shift, 5   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT4_Shift, 4   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT3_Shift, 3   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT2_Shift, 2   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT1_Shift, 1   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT0_Shift, 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOE_OCTL, GPIOE_BASE + 0x0C @ (Port output control register) 
        .equ GPIOE_OCTL15_Shift, 15   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL14_Shift, 14   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL13_Shift, 13   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL12_Shift, 12   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL11_Shift, 11   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL10_Shift, 10   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL9_Shift, 9   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL8_Shift, 8   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL7_Shift, 7   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL6_Shift, 6   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL5_Shift, 5   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL4_Shift, 4   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL3_Shift, 3   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL2_Shift, 2   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL1_Shift, 1   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL0_Shift, 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOE_BOP, GPIOE_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOE_CR15_Shift, 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOE_CR14_Shift, 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOE_CR13_Shift, 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOE_CR12_Shift, 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOE_CR11_Shift, 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOE_CR10_Shift, 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOE_CR9_Shift, 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOE_CR8_Shift, 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOE_CR7_Shift, 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOE_CR6_Shift, 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOE_CR5_Shift, 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOE_CR4_Shift, 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOE_CR3_Shift, 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOE_CR2_Shift, 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOE_CR1_Shift, 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOE_CR0_Shift, 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOE_BOP15_Shift, 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOE_BOP14_Shift, 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOE_BOP13_Shift, 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOE_BOP12_Shift, 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOE_BOP11_Shift, 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOE_BOP10_Shift, 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOE_BOP9_Shift, 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOE_BOP8_Shift, 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOE_BOP7_Shift, 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOE_BOP6_Shift, 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOE_BOP5_Shift, 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOE_BOP4_Shift, 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOE_BOP3_Shift, 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOE_BOP2_Shift, 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOE_BOP1_Shift, 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOE_BOP0_Shift, 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOE_BC, GPIOE_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOE_CR15_Shift, 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOE_CR14_Shift, 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOE_CR13_Shift, 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOE_CR12_Shift, 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOE_CR11_Shift, 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOE_CR10_Shift, 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOE_CR9_Shift, 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOE_CR8_Shift, 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOE_CR7_Shift, 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOE_CR6_Shift, 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOE_CR5_Shift, 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOE_CR4_Shift, 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOE_CR3_Shift, 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOE_CR2_Shift, 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOE_CR1_Shift, 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOE_CR0_Shift, 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOE_LOCK, GPIOE_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOE_LKK_Shift, 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOE_LK15_Shift, 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOE_LK14_Shift, 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOE_LK13_Shift, 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOE_LK12_Shift, 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOE_LK11_Shift, 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOE_LK10_Shift, 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOE_LK9_Shift, 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOE_LK8_Shift, 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOE_LK7_Shift, 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOE_LK6_Shift, 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOE_LK5_Shift, 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOE_LK4_Shift, 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOE_LK3_Shift, 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOE_LK2_Shift, 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOE_LK1_Shift, 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOE_LK0_Shift, 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== I2C0 ===========================@
.equ I2C0_BASE, 0x40005400 @ (Inter integrated circuit) 
    .equ I2C0_CTL0, I2C0_BASE + 0x0 @ (Control register 0) 
        .equ I2C0_SRESET_Shift, 15   @ bitWidth 1 (Software reset)  
        .equ I2C0_SALT_Shift, 13   @ bitWidth 1 (SMBus alert)  
        .equ I2C0_PECTRANS_Shift, 12   @ bitWidth 1 (PEC Transfer)  
        .equ I2C0_POAP_Shift, 11   @ bitWidth 1 (Position of ACK and PEC when receiving)  
        .equ I2C0_ACKEN_Shift, 10   @ bitWidth 1 (Whether or not to send an ACK)  
        .equ I2C0_STOP_Shift, 9   @ bitWidth 1 (Generate a STOP condition on I2C bus)  
        .equ I2C0_START_Shift, 8   @ bitWidth 1 (Generate a START condition on I2C bus)  
        .equ I2C0_SS_Shift, 7   @ bitWidth 1 (Whether to stretch SCL low when data is not ready in slave mode)  
        .equ I2C0_GCEN_Shift, 6   @ bitWidth 1 (Whether or not to response to a General Call 0x00)  
        .equ I2C0_PECEN_Shift, 5   @ bitWidth 1 (PEC Calculation Switch)  
        .equ I2C0_ARPEN_Shift, 4   @ bitWidth 1 (ARP protocol in SMBus switch)  
        .equ I2C0_SMBSEL_Shift, 3   @ bitWidth 1 (SMBusType Selection)  
        .equ I2C0_SMBEN_Shift, 1   @ bitWidth 1 (SMBus/I2C mode switch)  
        .equ I2C0_I2CEN_Shift, 0   @ bitWidth 1 (I2C peripheral enable)  
 
    .equ I2C0_CTL1, I2C0_BASE + 0x04 @ (Control register 1) 
        .equ I2C0_DMALST_Shift, 12   @ bitWidth 1 (Flag indicating DMA last transfer)  
        .equ I2C0_DMAON_Shift, 11   @ bitWidth 1 (DMA mode switch)  
        .equ I2C0_BUFIE_Shift, 10   @ bitWidth 1 (Buffer interrupt enable)  
        .equ I2C0_EVIE_Shift, 9   @ bitWidth 1 (Event interrupt enable)  
        .equ I2C0_ERRIE_Shift, 8   @ bitWidth 1 (Error interrupt enable)  
        .equ I2C0_I2CCLK_Shift, 0   @ bitWidth 6 (I2C Peripheral clock frequency)  
 
    .equ I2C0_SADDR0, I2C0_BASE + 0x08 @ (Slave address register 0) 
        .equ I2C0_ADDFORMAT_Shift, 15   @ bitWidth 1 (Address mode for the I2C slave)  
        .equ I2C0_ADDRESS9_8_Shift, 8   @ bitWidth 2 (Highest two bits of a 10-bit address)  
        .equ I2C0_ADDRESS7_1_Shift, 1   @ bitWidth 7 (7-bit address or bits 7:1 of a 10-bit address)  
        .equ I2C0_ADDRESS0_Shift, 0   @ bitWidth 1 (Bit 0 of a 10-bit address)  
 
    .equ I2C0_SADDR1, I2C0_BASE + 0x0C @ (Slave address register 1) 
        .equ I2C0_ADDRESS2_Shift, 1   @ bitWidth 7 (Second I2C address for the slave in Dual-Address mode)  
        .equ I2C0_DUADEN_Shift, 0   @ bitWidth 1 (Dual-Address mode switch)  
 
    .equ I2C0_DATA, I2C0_BASE + 0x10 @ (Transfer buffer register) 
        .equ I2C0_TRB_Shift, 0   @ bitWidth 8 (Transmission or reception data buffer register)  
 
    .equ I2C0_STAT0, I2C0_BASE + 0x14 @ (Transfer status register 0) 
        .equ I2C0_SMBALT_Shift, 15   @ bitWidth 1 (SMBus Alert status)  
        .equ I2C0_SMBTO_Shift, 14   @ bitWidth 1 (Timeout signal in SMBus mode)  
        .equ I2C0_PECERR_Shift, 12   @ bitWidth 1 (PEC error when receiving data)  
        .equ I2C0_OUERR_Shift, 11   @ bitWidth 1 (Over-run or under-run situation occurs in slave mode)  
        .equ I2C0_AERR_Shift, 10   @ bitWidth 1 (Acknowledge error)  
        .equ I2C0_LOSTARB_Shift, 9   @ bitWidth 1 (Arbitration Lost in master mode)  
        .equ I2C0_BERR_Shift, 8   @ bitWidth 1 (A bus error occurs indication a unexpected START or STOP condition on I2C bus)  
        .equ I2C0_TBE_Shift, 7   @ bitWidth 1 (I2C_DATA is Empty during transmitting)  
        .equ I2C0_RBNE_Shift, 6   @ bitWidth 1 (I2C_DATA is not Empty during receiving)  
        .equ I2C0_STPDET_Shift, 4   @ bitWidth 1 (STOP condition detected in slave mode)  
        .equ I2C0_ADD10SEND_Shift, 3   @ bitWidth 1 (Header of 10-bit address is sent in master mode)  
        .equ I2C0_BTC_Shift, 2   @ bitWidth 1 (Byte transmission completed)  
        .equ I2C0_ADDSEND_Shift, 1   @ bitWidth 1 (Address is sent in master mode or received and matches in slave mode)  
        .equ I2C0_SBSEND_Shift, 0   @ bitWidth 1 (START condition sent out in master mode)  
 
    .equ I2C0_STAT1, I2C0_BASE + 0x18 @ (Transfer status register 1) 
        .equ I2C0_PECV_Shift, 8   @ bitWidth 8 (Packet Error Checking Value that calculated by hardware when PEC is enabled)  
        .equ I2C0_DUMODF_Shift, 7   @ bitWidth 1 (Dual Flag in slave mode)  
        .equ I2C0_HSTSMB_Shift, 6   @ bitWidth 1 (SMBus Host Header detected in slave mode)  
        .equ I2C0_DEFSMB_Shift, 5   @ bitWidth 1 (Default address of SMBusDevice)  
        .equ I2C0_RXGC_Shift, 4   @ bitWidth 1 (General call address 00h received)  
        .equ I2C0_TR_Shift, 2   @ bitWidth 1 (Whether the I2C is a transmitter or a receiver)  
        .equ I2C0_I2CBSY_Shift, 1   @ bitWidth 1 (Busy flag)  
        .equ I2C0_MASTER_Shift, 0   @ bitWidth 1 (A flag indicating whether I2C block is in master or slave mode)  
 
    .equ I2C0_CKCFG, I2C0_BASE + 0x1C @ (Clock configure register) 
        .equ I2C0_FAST_Shift, 15   @ bitWidth 1 (I2C speed selection in master mode)  
        .equ I2C0_DTCY_Shift, 14   @ bitWidth 1 (Duty cycle in fast mode)  
        .equ I2C0_CLKC_Shift, 0   @ bitWidth 12 (I2C Clock control in master mode)  
 
    .equ I2C0_RT, I2C0_BASE + 0x20 @ (Rise time register) 
        .equ I2C0_RISETIME_Shift, 0   @ bitWidth 6 (Maximum rise time in master mode)  
 

@=========================== I2C1 ===========================@
.equ I2C1_BASE, 0x40005800 @ (Inter integrated circuit) 
    .equ I2C1_CTL0, I2C1_BASE + 0x0 @ (Control register 0) 
        .equ I2C1_SRESET_Shift, 15   @ bitWidth 1 (Software reset)  
        .equ I2C1_SALT_Shift, 13   @ bitWidth 1 (SMBus alert)  
        .equ I2C1_PECTRANS_Shift, 12   @ bitWidth 1 (PEC Transfer)  
        .equ I2C1_POAP_Shift, 11   @ bitWidth 1 (Position of ACK and PEC when receiving)  
        .equ I2C1_ACKEN_Shift, 10   @ bitWidth 1 (Whether or not to send an ACK)  
        .equ I2C1_STOP_Shift, 9   @ bitWidth 1 (Generate a STOP condition on I2C bus)  
        .equ I2C1_START_Shift, 8   @ bitWidth 1 (Generate a START condition on I2C bus)  
        .equ I2C1_SS_Shift, 7   @ bitWidth 1 (Whether to stretch SCL low when data is not ready in slave mode)  
        .equ I2C1_GCEN_Shift, 6   @ bitWidth 1 (Whether or not to response to a General Call 0x00)  
        .equ I2C1_PECEN_Shift, 5   @ bitWidth 1 (PEC Calculation Switch)  
        .equ I2C1_ARPEN_Shift, 4   @ bitWidth 1 (ARP protocol in SMBus switch)  
        .equ I2C1_SMBSEL_Shift, 3   @ bitWidth 1 (SMBusType Selection)  
        .equ I2C1_SMBEN_Shift, 1   @ bitWidth 1 (SMBus/I2C mode switch)  
        .equ I2C1_I2CEN_Shift, 0   @ bitWidth 1 (I2C peripheral enable)  
 
    .equ I2C1_CTL1, I2C1_BASE + 0x04 @ (Control register 1) 
        .equ I2C1_DMALST_Shift, 12   @ bitWidth 1 (Flag indicating DMA last transfer)  
        .equ I2C1_DMAON_Shift, 11   @ bitWidth 1 (DMA mode switch)  
        .equ I2C1_BUFIE_Shift, 10   @ bitWidth 1 (Buffer interrupt enable)  
        .equ I2C1_EVIE_Shift, 9   @ bitWidth 1 (Event interrupt enable)  
        .equ I2C1_ERRIE_Shift, 8   @ bitWidth 1 (Error interrupt enable)  
        .equ I2C1_I2CCLK_Shift, 0   @ bitWidth 6 (I2C Peripheral clock frequency)  
 
    .equ I2C1_SADDR0, I2C1_BASE + 0x08 @ (Slave address register 0) 
        .equ I2C1_ADDFORMAT_Shift, 15   @ bitWidth 1 (Address mode for the I2C slave)  
        .equ I2C1_ADDRESS9_8_Shift, 8   @ bitWidth 2 (Highest two bits of a 10-bit address)  
        .equ I2C1_ADDRESS7_1_Shift, 1   @ bitWidth 7 (7-bit address or bits 7:1 of a 10-bit address)  
        .equ I2C1_ADDRESS0_Shift, 0   @ bitWidth 1 (Bit 0 of a 10-bit address)  
 
    .equ I2C1_SADDR1, I2C1_BASE + 0x0C @ (Slave address register 1) 
        .equ I2C1_ADDRESS2_Shift, 1   @ bitWidth 7 (Second I2C address for the slave in Dual-Address mode)  
        .equ I2C1_DUADEN_Shift, 0   @ bitWidth 1 (Dual-Address mode switch)  
 
    .equ I2C1_DATA, I2C1_BASE + 0x10 @ (Transfer buffer register) 
        .equ I2C1_TRB_Shift, 0   @ bitWidth 8 (Transmission or reception data buffer register)  
 
    .equ I2C1_STAT0, I2C1_BASE + 0x14 @ (Transfer status register 0) 
        .equ I2C1_SMBALT_Shift, 15   @ bitWidth 1 (SMBus Alert status)  
        .equ I2C1_SMBTO_Shift, 14   @ bitWidth 1 (Timeout signal in SMBus mode)  
        .equ I2C1_PECERR_Shift, 12   @ bitWidth 1 (PEC error when receiving data)  
        .equ I2C1_OUERR_Shift, 11   @ bitWidth 1 (Over-run or under-run situation occurs in slave mode)  
        .equ I2C1_AERR_Shift, 10   @ bitWidth 1 (Acknowledge error)  
        .equ I2C1_LOSTARB_Shift, 9   @ bitWidth 1 (Arbitration Lost in master mode)  
        .equ I2C1_BERR_Shift, 8   @ bitWidth 1 (A bus error occurs indication a unexpected START or STOP condition on I2C bus)  
        .equ I2C1_TBE_Shift, 7   @ bitWidth 1 (I2C_DATA is Empty during transmitting)  
        .equ I2C1_RBNE_Shift, 6   @ bitWidth 1 (I2C_DATA is not Empty during receiving)  
        .equ I2C1_STPDET_Shift, 4   @ bitWidth 1 (STOP condition detected in slave mode)  
        .equ I2C1_ADD10SEND_Shift, 3   @ bitWidth 1 (Header of 10-bit address is sent in master mode)  
        .equ I2C1_BTC_Shift, 2   @ bitWidth 1 (Byte transmission completed)  
        .equ I2C1_ADDSEND_Shift, 1   @ bitWidth 1 (Address is sent in master mode or received and matches in slave mode)  
        .equ I2C1_SBSEND_Shift, 0   @ bitWidth 1 (START condition sent out in master mode)  
 
    .equ I2C1_STAT1, I2C1_BASE + 0x18 @ (Transfer status register 1) 
        .equ I2C1_PECV_Shift, 8   @ bitWidth 8 (Packet Error Checking Value that calculated by hardware when PEC is enabled)  
        .equ I2C1_DUMODF_Shift, 7   @ bitWidth 1 (Dual Flag in slave mode)  
        .equ I2C1_HSTSMB_Shift, 6   @ bitWidth 1 (SMBus Host Header detected in slave mode)  
        .equ I2C1_DEFSMB_Shift, 5   @ bitWidth 1 (Default address of SMBusDevice)  
        .equ I2C1_RXGC_Shift, 4   @ bitWidth 1 (General call address 00h received)  
        .equ I2C1_TR_Shift, 2   @ bitWidth 1 (Whether the I2C is a transmitter or a receiver)  
        .equ I2C1_I2CBSY_Shift, 1   @ bitWidth 1 (Busy flag)  
        .equ I2C1_MASTER_Shift, 0   @ bitWidth 1 (A flag indicating whether I2C block is in master or slave mode)  
 
    .equ I2C1_CKCFG, I2C1_BASE + 0x1C @ (Clock configure register) 
        .equ I2C1_FAST_Shift, 15   @ bitWidth 1 (I2C speed selection in master mode)  
        .equ I2C1_DTCY_Shift, 14   @ bitWidth 1 (Duty cycle in fast mode)  
        .equ I2C1_CLKC_Shift, 0   @ bitWidth 12 (I2C Clock control in master mode)  
 
    .equ I2C1_RT, I2C1_BASE + 0x20 @ (Rise time register) 
        .equ I2C1_RISETIME_Shift, 0   @ bitWidth 6 (Maximum rise time in master mode)  
 

@=========================== ECLIC ===========================@
.equ ECLIC_BASE, 0xD2000000 @ (Enhanced Core Local Interrupt Controller) 
    .equ ECLIC_CLICCFG, ECLIC_BASE + 0x0 @ (cliccfg Register) 
        .equ ECLIC_NLBITS_Shift, 1   @ bitWidth 4 (NLBITS)  
 
    .equ ECLIC_CLICINFO, ECLIC_BASE + 0x04 @ (clicinfo Register) 
        .equ ECLIC_NUM_INTERRUPT_Shift, 0   @ bitWidth 13 (NUM_INTERRUPT)  
        .equ ECLIC_VERSION_Shift, 13   @ bitWidth 8 (VERSION)  
        .equ ECLIC_CLICINTCTLBITS_Shift, 21   @ bitWidth 4 (CLICINTCTLBITS)  
 
    .equ ECLIC_MTH, ECLIC_BASE + 0x0b @ (MTH Register) 
        .equ ECLIC_MTH_Shift, 0   @ bitWidth 8 (MTH)  
 
    .equ ECLIC_CLICINTIP_0, ECLIC_BASE + 0x1000 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_1, ECLIC_BASE + 0x1004 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_2, ECLIC_BASE + 0x1008 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_3, ECLIC_BASE + 0x100C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_4, ECLIC_BASE + 0x1010 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_5, ECLIC_BASE + 0x1014 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_6, ECLIC_BASE + 0x1018 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_7, ECLIC_BASE + 0x101C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_8, ECLIC_BASE + 0x1020 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_9, ECLIC_BASE + 0x1024 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_10, ECLIC_BASE + 0x1028 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_11, ECLIC_BASE + 0x102C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_12, ECLIC_BASE + 0x1030 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_13, ECLIC_BASE + 0x1034 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_14, ECLIC_BASE + 0x1038 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_15, ECLIC_BASE + 0x103C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_16, ECLIC_BASE + 0x1040 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_17, ECLIC_BASE + 0x1044 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_18, ECLIC_BASE + 0x1048 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_19, ECLIC_BASE + 0x104C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_20, ECLIC_BASE + 0x1050 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_21, ECLIC_BASE + 0x1054 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_22, ECLIC_BASE + 0x1058 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_23, ECLIC_BASE + 0x105C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_24, ECLIC_BASE + 0x1060 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_25, ECLIC_BASE + 0x1064 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_26, ECLIC_BASE + 0x1068 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_27, ECLIC_BASE + 0x106C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_28, ECLIC_BASE + 0x1070 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_29, ECLIC_BASE + 0x1074 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_30, ECLIC_BASE + 0x1078 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_31, ECLIC_BASE + 0x107C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_32, ECLIC_BASE + 0x1080 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_33, ECLIC_BASE + 0x1084 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_34, ECLIC_BASE + 0x1088 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_35, ECLIC_BASE + 0x108C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_36, ECLIC_BASE + 0x1090 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_37, ECLIC_BASE + 0x1094 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_38, ECLIC_BASE + 0x1098 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_39, ECLIC_BASE + 0x109C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_40, ECLIC_BASE + 0x10A0 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_41, ECLIC_BASE + 0x10A4 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_42, ECLIC_BASE + 0x10A8 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_43, ECLIC_BASE + 0x10AC @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_44, ECLIC_BASE + 0x10B0 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_45, ECLIC_BASE + 0x10B4 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_46, ECLIC_BASE + 0x10B8 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_47, ECLIC_BASE + 0x10BC @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_48, ECLIC_BASE + 0x10C0 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_49, ECLIC_BASE + 0x10C4 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_50, ECLIC_BASE + 0x10C8 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_51, ECLIC_BASE + 0x10CC @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_52, ECLIC_BASE + 0x10D0 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_53, ECLIC_BASE + 0x10D4 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_54, ECLIC_BASE + 0x10D8 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_55, ECLIC_BASE + 0x10DC @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_56, ECLIC_BASE + 0x10E0 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_57, ECLIC_BASE + 0x10E4 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_58, ECLIC_BASE + 0x10E8 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_59, ECLIC_BASE + 0x10EC @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_60, ECLIC_BASE + 0x10F0 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_61, ECLIC_BASE + 0x10F4 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_62, ECLIC_BASE + 0x10F8 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_63, ECLIC_BASE + 0x10FC @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_64, ECLIC_BASE + 0x1100 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_65, ECLIC_BASE + 0x1104 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_66, ECLIC_BASE + 0x1108 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_67, ECLIC_BASE + 0x110C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_68, ECLIC_BASE + 0x1110 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_69, ECLIC_BASE + 0x1114 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_70, ECLIC_BASE + 0x1118 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_71, ECLIC_BASE + 0x111C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_72, ECLIC_BASE + 0x1120 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_73, ECLIC_BASE + 0x1124 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_74, ECLIC_BASE + 0x1128 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_75, ECLIC_BASE + 0x112C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_76, ECLIC_BASE + 0x1130 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_77, ECLIC_BASE + 0x1134 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_78, ECLIC_BASE + 0x1138 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_79, ECLIC_BASE + 0x113C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_80, ECLIC_BASE + 0x1140 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_81, ECLIC_BASE + 0x1144 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_82, ECLIC_BASE + 0x1148 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_83, ECLIC_BASE + 0x114C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_84, ECLIC_BASE + 0x1150 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_85, ECLIC_BASE + 0x1158 @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_86, ECLIC_BASE + 0x115C @ (clicintip Register) 
        .equ ECLIC_IP_Shift, 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIE_0, ECLIC_BASE + 0x1001 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_1, ECLIC_BASE + 0x1005 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_2, ECLIC_BASE + 0x1009 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_3, ECLIC_BASE + 0x100D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_4, ECLIC_BASE + 0x1011 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_5, ECLIC_BASE + 0x1015 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_6, ECLIC_BASE + 0x1019 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_7, ECLIC_BASE + 0x101D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_8, ECLIC_BASE + 0x1021 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_9, ECLIC_BASE + 0x1025 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_10, ECLIC_BASE + 0x1029 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_11, ECLIC_BASE + 0x102D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_12, ECLIC_BASE + 0x1031 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_13, ECLIC_BASE + 0x1035 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_14, ECLIC_BASE + 0x1039 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_15, ECLIC_BASE + 0x103D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_16, ECLIC_BASE + 0x1041 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_17, ECLIC_BASE + 0x1045 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_18, ECLIC_BASE + 0x1049 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_19, ECLIC_BASE + 0x104D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_20, ECLIC_BASE + 0x1051 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_21, ECLIC_BASE + 0x1055 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_22, ECLIC_BASE + 0x1059 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_23, ECLIC_BASE + 0x105D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_24, ECLIC_BASE + 0x1061 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_25, ECLIC_BASE + 0x1065 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_26, ECLIC_BASE + 0x1069 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_27, ECLIC_BASE + 0x106D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_28, ECLIC_BASE + 0x1071 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_29, ECLIC_BASE + 0x1075 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_30, ECLIC_BASE + 0x1079 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_31, ECLIC_BASE + 0x107D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_32, ECLIC_BASE + 0x1081 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_33, ECLIC_BASE + 0x1085 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_34, ECLIC_BASE + 0x1089 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_35, ECLIC_BASE + 0x108D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_36, ECLIC_BASE + 0x1091 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_37, ECLIC_BASE + 0x1095 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_38, ECLIC_BASE + 0x1099 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_39, ECLIC_BASE + 0x109D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_40, ECLIC_BASE + 0x10A1 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_41, ECLIC_BASE + 0x10A5 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_42, ECLIC_BASE + 0x10A9 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_43, ECLIC_BASE + 0x10AD @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_44, ECLIC_BASE + 0x10B1 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_45, ECLIC_BASE + 0x10B5 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_46, ECLIC_BASE + 0x10B9 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_47, ECLIC_BASE + 0x10BD @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_48, ECLIC_BASE + 0x10C1 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_49, ECLIC_BASE + 0x10C5 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_50, ECLIC_BASE + 0x10C9 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_51, ECLIC_BASE + 0x10CD @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_52, ECLIC_BASE + 0x10D1 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_53, ECLIC_BASE + 0x10D5 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_54, ECLIC_BASE + 0x10D9 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_55, ECLIC_BASE + 0x10DD @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_56, ECLIC_BASE + 0x10E1 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_57, ECLIC_BASE + 0x10E5 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_58, ECLIC_BASE + 0x10E9 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_59, ECLIC_BASE + 0x10ED @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_60, ECLIC_BASE + 0x10F1 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_61, ECLIC_BASE + 0x10F5 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_62, ECLIC_BASE + 0x10F9 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_63, ECLIC_BASE + 0x10FD @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_64, ECLIC_BASE + 0x1101 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_65, ECLIC_BASE + 0x1105 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_66, ECLIC_BASE + 0x1109 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_67, ECLIC_BASE + 0x110D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_68, ECLIC_BASE + 0x1111 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_69, ECLIC_BASE + 0x1115 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_70, ECLIC_BASE + 0x1119 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_71, ECLIC_BASE + 0x111D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_72, ECLIC_BASE + 0x1121 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_73, ECLIC_BASE + 0x1125 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_74, ECLIC_BASE + 0x1129 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_75, ECLIC_BASE + 0x112D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_76, ECLIC_BASE + 0x1131 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_77, ECLIC_BASE + 0x1135 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_78, ECLIC_BASE + 0x1139 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_79, ECLIC_BASE + 0x113D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_80, ECLIC_BASE + 0x1141 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_81, ECLIC_BASE + 0x1145 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_82, ECLIC_BASE + 0x1149 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_83, ECLIC_BASE + 0x114D @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_84, ECLIC_BASE + 0x1151 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_85, ECLIC_BASE + 0x1155 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_86, ECLIC_BASE + 0x1159 @ (clicintie Register) 
        .equ ECLIC_IE_Shift, 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTATTR_0, ECLIC_BASE + 0x1002 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_1, ECLIC_BASE + 0x1006 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_2, ECLIC_BASE + 0x100A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_3, ECLIC_BASE + 0x100E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_4, ECLIC_BASE + 0x1012 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_5, ECLIC_BASE + 0x1016 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_6, ECLIC_BASE + 0x101A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_7, ECLIC_BASE + 0x101E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_8, ECLIC_BASE + 0x1022 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_9, ECLIC_BASE + 0x1026 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_10, ECLIC_BASE + 0x102A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_11, ECLIC_BASE + 0x102E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_12, ECLIC_BASE + 0x1032 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_13, ECLIC_BASE + 0x1036 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_14, ECLIC_BASE + 0x103A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_15, ECLIC_BASE + 0x103E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_16, ECLIC_BASE + 0x1042 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_17, ECLIC_BASE + 0x1046 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_18, ECLIC_BASE + 0x104A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_19, ECLIC_BASE + 0x104E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_20, ECLIC_BASE + 0x1052 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_21, ECLIC_BASE + 0x1056 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_22, ECLIC_BASE + 0x105A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_23, ECLIC_BASE + 0x105E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_24, ECLIC_BASE + 0x1062 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_25, ECLIC_BASE + 0x1066 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_26, ECLIC_BASE + 0x106A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_27, ECLIC_BASE + 0x106E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_28, ECLIC_BASE + 0x1072 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_29, ECLIC_BASE + 0x1076 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_30, ECLIC_BASE + 0x107A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_31, ECLIC_BASE + 0x107E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_32, ECLIC_BASE + 0x1082 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_33, ECLIC_BASE + 0x1086 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_34, ECLIC_BASE + 0x108A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_35, ECLIC_BASE + 0x108E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_36, ECLIC_BASE + 0x1092 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_37, ECLIC_BASE + 0x1096 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_38, ECLIC_BASE + 0x109A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_39, ECLIC_BASE + 0x109E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_40, ECLIC_BASE + 0x10A2 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_41, ECLIC_BASE + 0x10A6 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_42, ECLIC_BASE + 0x10AA @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_43, ECLIC_BASE + 0x10AE @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_44, ECLIC_BASE + 0x10B2 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_45, ECLIC_BASE + 0x10B6 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_46, ECLIC_BASE + 0x10BA @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_47, ECLIC_BASE + 0x10BE @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_48, ECLIC_BASE + 0x10C2 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_49, ECLIC_BASE + 0x10C6 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_50, ECLIC_BASE + 0x10CA @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_51, ECLIC_BASE + 0x10CE @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_52, ECLIC_BASE + 0x10D2 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_53, ECLIC_BASE + 0x10D6 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_54, ECLIC_BASE + 0x10DA @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_55, ECLIC_BASE + 0x10DE @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_56, ECLIC_BASE + 0x10E2 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_57, ECLIC_BASE + 0x10E6 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_58, ECLIC_BASE + 0x10EA @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_59, ECLIC_BASE + 0x10EE @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_60, ECLIC_BASE + 0x10F2 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_61, ECLIC_BASE + 0x10F6 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_62, ECLIC_BASE + 0x10FA @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_63, ECLIC_BASE + 0x10FE @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_64, ECLIC_BASE + 0x1102 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_65, ECLIC_BASE + 0x1106 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_66, ECLIC_BASE + 0x110A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_67, ECLIC_BASE + 0x110E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_68, ECLIC_BASE + 0x1112 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_69, ECLIC_BASE + 0x1116 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_70, ECLIC_BASE + 0x111A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_71, ECLIC_BASE + 0x111E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_72, ECLIC_BASE + 0x1122 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_73, ECLIC_BASE + 0x1126 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_74, ECLIC_BASE + 0x112A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_75, ECLIC_BASE + 0x112E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_76, ECLIC_BASE + 0x1132 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_77, ECLIC_BASE + 0x1136 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_78, ECLIC_BASE + 0x113A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_79, ECLIC_BASE + 0x113E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_80, ECLIC_BASE + 0x1142 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_81, ECLIC_BASE + 0x1146 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_82, ECLIC_BASE + 0x114A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_83, ECLIC_BASE + 0x114E @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_84, ECLIC_BASE + 0x1152 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_85, ECLIC_BASE + 0x1156 @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_86, ECLIC_BASE + 0x115A @ (clicintattr Register) 
        .equ ECLIC_SHV_Shift, 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTCTL_0, ECLIC_BASE + 0x1003 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_1, ECLIC_BASE + 0x1007 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_2, ECLIC_BASE + 0x100B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_3, ECLIC_BASE + 0x100F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_4, ECLIC_BASE + 0x1013 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_5, ECLIC_BASE + 0x1017 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_6, ECLIC_BASE + 0x101B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_7, ECLIC_BASE + 0x101F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_8, ECLIC_BASE + 0x1023 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_9, ECLIC_BASE + 0x1027 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_10, ECLIC_BASE + 0x102B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_11, ECLIC_BASE + 0x102F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_12, ECLIC_BASE + 0x1033 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_13, ECLIC_BASE + 0x1037 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_14, ECLIC_BASE + 0x103B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_15, ECLIC_BASE + 0x103F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_16, ECLIC_BASE + 0x1043 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_17, ECLIC_BASE + 0x1047 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_18, ECLIC_BASE + 0x104B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_19, ECLIC_BASE + 0x104F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_20, ECLIC_BASE + 0x1053 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_21, ECLIC_BASE + 0x1057 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_22, ECLIC_BASE + 0x105B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_23, ECLIC_BASE + 0x105F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_24, ECLIC_BASE + 0x1063 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_25, ECLIC_BASE + 0x1067 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_26, ECLIC_BASE + 0x106B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_27, ECLIC_BASE + 0x106F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_28, ECLIC_BASE + 0x1073 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_29, ECLIC_BASE + 0x1077 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_30, ECLIC_BASE + 0x107B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_31, ECLIC_BASE + 0x107F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_32, ECLIC_BASE + 0x1083 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_33, ECLIC_BASE + 0x1087 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_34, ECLIC_BASE + 0x108B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_35, ECLIC_BASE + 0x108F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_36, ECLIC_BASE + 0x1093 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_37, ECLIC_BASE + 0x1097 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_38, ECLIC_BASE + 0x109B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_39, ECLIC_BASE + 0x109F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_40, ECLIC_BASE + 0x10A3 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_41, ECLIC_BASE + 0x10A7 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_42, ECLIC_BASE + 0x10AB @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_43, ECLIC_BASE + 0x10AF @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_44, ECLIC_BASE + 0x10B3 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_45, ECLIC_BASE + 0x10B7 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_46, ECLIC_BASE + 0x10BB @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_47, ECLIC_BASE + 0x10BF @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_48, ECLIC_BASE + 0x10C3 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_49, ECLIC_BASE + 0x10C7 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_50, ECLIC_BASE + 0x10CB @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_51, ECLIC_BASE + 0x10CF @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_52, ECLIC_BASE + 0x10D3 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_53, ECLIC_BASE + 0x10D7 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_54, ECLIC_BASE + 0x10DB @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_55, ECLIC_BASE + 0x10DF @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_56, ECLIC_BASE + 0x10E3 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_57, ECLIC_BASE + 0x10E7 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_58, ECLIC_BASE + 0x10EB @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_59, ECLIC_BASE + 0x10EF @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_60, ECLIC_BASE + 0x10F3 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_61, ECLIC_BASE + 0x10F7 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_62, ECLIC_BASE + 0x10FB @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_63, ECLIC_BASE + 0x10FF @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_64, ECLIC_BASE + 0x1103 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_65, ECLIC_BASE + 0x1107 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_66, ECLIC_BASE + 0x110B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_67, ECLIC_BASE + 0x110F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_68, ECLIC_BASE + 0x1113 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_69, ECLIC_BASE + 0x1117 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_70, ECLIC_BASE + 0x111B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_71, ECLIC_BASE + 0x111F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_72, ECLIC_BASE + 0x1123 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_73, ECLIC_BASE + 0x1127 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_74, ECLIC_BASE + 0x112B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_75, ECLIC_BASE + 0x112F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_76, ECLIC_BASE + 0x1133 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_77, ECLIC_BASE + 0x1137 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_78, ECLIC_BASE + 0x113B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_79, ECLIC_BASE + 0x113F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_80, ECLIC_BASE + 0x1143 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_81, ECLIC_BASE + 0x1147 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_82, ECLIC_BASE + 0x114B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_83, ECLIC_BASE + 0x114F @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_84, ECLIC_BASE + 0x1153 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_85, ECLIC_BASE + 0x1157 @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_86, ECLIC_BASE + 0x115B @ (clicintctl Register) 
        .equ ECLIC_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 

@=========================== PMU ===========================@
.equ PMU_BASE, 0x40007000 @ (Power management unit) 
    .equ PMU_CTL, PMU_BASE + 0x00 @ (power control register) 
        .equ PMU_BKPWEN_Shift, 8   @ bitWidth 1 (Backup Domain Write Enable)  
        .equ PMU_LVDT_Shift, 5   @ bitWidth 3 (Low Voltage Detector Threshold)  
        .equ PMU_LVDEN_Shift, 4   @ bitWidth 1 (Low Voltage Detector Enable)  
        .equ PMU_STBRST_Shift, 3   @ bitWidth 1 (Standby Flag Reset)  
        .equ PMU_WURST_Shift, 2   @ bitWidth 1 (Wakeup Flag Reset)  
        .equ PMU_STBMOD_Shift, 1   @ bitWidth 1 (Standby Mode)  
        .equ PMU_LDOLP_Shift, 0   @ bitWidth 1 (LDO Low Power Mode)  
 
    .equ PMU_CS, PMU_BASE + 0x04 @ (power control/status register) 
        .equ PMU_WUPEN_Shift, 8   @ bitWidth 1 (Enable WKUP pin)  
        .equ PMU_LVDF_Shift, 2   @ bitWidth 1 (Low Voltage Detector Status Flag)  
        .equ PMU_STBF_Shift, 1   @ bitWidth 1 (Standby flag)  
        .equ PMU_WUF_Shift, 0   @ bitWidth 1 (Wakeup flag)  
 

@=========================== RCU ===========================@
.equ RCU_BASE, 0x40021000 @ (Reset and clock unit) 
    .equ RCU_CTL, RCU_BASE + 0x0 @ (Control register) 
        .equ RCU_IRC8MEN_Shift, 0   @ bitWidth 1 (Internal 8MHz RC oscillator Enable)  
        .equ RCU_IRC8MSTB_Shift, 1   @ bitWidth 1 (IRC8M Internal 8MHz RC Oscillator stabilization Flag)  
        .equ RCU_IRC8MADJ_Shift, 3   @ bitWidth 5 (Internal 8MHz RC Oscillator clock trim adjust value)  
        .equ RCU_IRC8MCALIB_Shift, 8   @ bitWidth 8 (Internal 8MHz RC Oscillator calibration value register)  
        .equ RCU_HXTALEN_Shift, 16   @ bitWidth 1 (External High Speed oscillator Enable)  
        .equ RCU_HXTALSTB_Shift, 17   @ bitWidth 1 (External crystal oscillator HXTAL clock stabilization flag)  
        .equ RCU_HXTALBPS_Shift, 18   @ bitWidth 1 (External crystal oscillator HXTAL clock bypass mode enable)  
        .equ RCU_CKMEN_Shift, 19   @ bitWidth 1 (HXTAL Clock Monitor Enable)  
        .equ RCU_PLLEN_Shift, 24   @ bitWidth 1 (PLL enable)  
        .equ RCU_PLLSTB_Shift, 25   @ bitWidth 1 (PLL Clock Stabilization Flag)  
        .equ RCU_PLL1EN_Shift, 26   @ bitWidth 1 (PLL1 enable)  
        .equ RCU_PLL1STB_Shift, 27   @ bitWidth 1 (PLL1 Clock Stabilization Flag)  
        .equ RCU_PLL2EN_Shift, 28   @ bitWidth 1 (PLL2 enable)  
        .equ RCU_PLL2STB_Shift, 29   @ bitWidth 1 (PLL2 Clock Stabilization Flag)  
 
    .equ RCU_CFG0, RCU_BASE + 0x04 @ (Clock configuration register 0  RCU_CFG0) 
        .equ RCU_SCS_Shift, 0   @ bitWidth 2 (System clock switch)  
        .equ RCU_SCSS_Shift, 2   @ bitWidth 2 (System clock switch status)  
        .equ RCU_AHBPSC_Shift, 4   @ bitWidth 4 (AHB prescaler selection)  
        .equ RCU_APB1PSC_Shift, 8   @ bitWidth 3 (APB1 prescaler selection)  
        .equ RCU_APB2PSC_Shift, 11   @ bitWidth 3 (APB2 prescaler selection)  
        .equ RCU_ADCPSC_1_0_Shift, 14   @ bitWidth 2 (ADC clock prescaler selection)  
        .equ RCU_PLLSEL_Shift, 16   @ bitWidth 1 (PLL Clock Source Selection)  
        .equ RCU_PREDV0_LSB_Shift, 17   @ bitWidth 1 (The LSB of PREDV0 division factor)  
        .equ RCU_PLLMF_3_0_Shift, 18   @ bitWidth 4 (The PLL clock multiplication factor)  
        .equ RCU_USBFSPSC_Shift, 22   @ bitWidth 2 (USBFS clock prescaler selection)  
        .equ RCU_CKOUT0SEL_Shift, 24   @ bitWidth 4 (CKOUT0 Clock Source Selection)  
        .equ RCU_ADCPSC_2_Shift, 28   @ bitWidth 1 (Bit 2 of ADCPSC)  
        .equ RCU_PLLMF_4_Shift, 29   @ bitWidth 1 (Bit 4 of PLLMF)  
 
    .equ RCU_INT, RCU_BASE + 0x08 @ (Clock interrupt register  RCU_INT) 
        .equ RCU_IRC40KSTBIF_Shift, 0   @ bitWidth 1 (IRC40K stabilization interrupt flag)  
        .equ RCU_LXTALSTBIF_Shift, 1   @ bitWidth 1 (LXTAL stabilization interrupt flag)  
        .equ RCU_IRC8MSTBIF_Shift, 2   @ bitWidth 1 (IRC8M stabilization interrupt flag)  
        .equ RCU_HXTALSTBIF_Shift, 3   @ bitWidth 1 (HXTAL stabilization interrupt flag)  
        .equ RCU_PLLSTBIF_Shift, 4   @ bitWidth 1 (PLL stabilization interrupt flag)  
        .equ RCU_PLL1STBIF_Shift, 5   @ bitWidth 1 (PLL1 stabilization interrupt flag)  
        .equ RCU_PLL2STBIF_Shift, 6   @ bitWidth 1 (PLL2 stabilization interrupt flag)  
        .equ RCU_CKMIF_Shift, 7   @ bitWidth 1 (HXTAL Clock Stuck Interrupt Flag)  
        .equ RCU_IRC40KSTBIE_Shift, 8   @ bitWidth 1 (IRC40K Stabilization interrupt enable)  
        .equ RCU_LXTALSTBIE_Shift, 9   @ bitWidth 1 (LXTAL Stabilization Interrupt Enable)  
        .equ RCU_IRC8MSTBIE_Shift, 10   @ bitWidth 1 (IRC8M Stabilization Interrupt Enable)  
        .equ RCU_HXTALSTBIE_Shift, 11   @ bitWidth 1 (HXTAL Stabilization Interrupt Enable)  
        .equ RCU_PLLSTBIE_Shift, 12   @ bitWidth 1 (PLL Stabilization Interrupt Enable)  
        .equ RCU_PLL1STBIE_Shift, 13   @ bitWidth 1 (PLL1 Stabilization Interrupt Enable)  
        .equ RCU_PLL2STBIE_Shift, 14   @ bitWidth 1 (PLL2 Stabilization Interrupt Enable)  
        .equ RCU_IRC40KSTBIC_Shift, 16   @ bitWidth 1 (IRC40K Stabilization Interrupt Clear)  
        .equ RCU_LXTALSTBIC_Shift, 17   @ bitWidth 1 (LXTAL Stabilization Interrupt Clear)  
        .equ RCU_IRC8MSTBIC_Shift, 18   @ bitWidth 1 (IRC8M Stabilization Interrupt Clear)  
        .equ RCU_HXTALSTBIC_Shift, 19   @ bitWidth 1 (HXTAL Stabilization Interrupt Clear)  
        .equ RCU_PLLSTBIC_Shift, 20   @ bitWidth 1 (PLL stabilization Interrupt Clear)  
        .equ RCU_PLL1STBIC_Shift, 21   @ bitWidth 1 (PLL1 stabilization Interrupt Clear)  
        .equ RCU_PLL2STBIC_Shift, 22   @ bitWidth 1 (PLL2 stabilization Interrupt Clear)  
        .equ RCU_CKMIC_Shift, 23   @ bitWidth 1 (HXTAL Clock Stuck Interrupt Clear)  
 
    .equ RCU_APB2RST, RCU_BASE + 0x0C @ (APB2 reset register  RCU_APB2RST) 
        .equ RCU_AFRST_Shift, 0   @ bitWidth 1 (Alternate function I/O reset)  
        .equ RCU_PARST_Shift, 2   @ bitWidth 1 (GPIO port A reset)  
        .equ RCU_PBRST_Shift, 3   @ bitWidth 1 (GPIO port B reset)  
        .equ RCU_PCRST_Shift, 4   @ bitWidth 1 (GPIO port C reset)  
        .equ RCU_PDRST_Shift, 5   @ bitWidth 1 (GPIO port D reset)  
        .equ RCU_PERST_Shift, 6   @ bitWidth 1 (GPIO port E reset)  
        .equ RCU_ADC0RST_Shift, 9   @ bitWidth 1 (ADC0 reset)  
        .equ RCU_ADC1RST_Shift, 10   @ bitWidth 1 (ADC1 reset)  
        .equ RCU_TIMER0RST_Shift, 11   @ bitWidth 1 (Timer 0 reset)  
        .equ RCU_SPI0RST_Shift, 12   @ bitWidth 1 (SPI0 reset)  
        .equ RCU_USART0RST_Shift, 14   @ bitWidth 1 (USART0 Reset)  
 
    .equ RCU_APB1RST, RCU_BASE + 0x10 @ (APB1 reset register  RCU_APB1RST) 
        .equ RCU_TIMER1RST_Shift, 0   @ bitWidth 1 (TIMER1 timer reset)  
        .equ RCU_TIMER2RST_Shift, 1   @ bitWidth 1 (TIMER2 timer reset)  
        .equ RCU_TIMER3RST_Shift, 2   @ bitWidth 1 (TIMER3 timer reset)  
        .equ RCU_TIMER4RST_Shift, 3   @ bitWidth 1 (TIMER4 timer reset)  
        .equ RCU_TIMER5RST_Shift, 4   @ bitWidth 1 (TIMER5 timer reset)  
        .equ RCU_TIMER6RST_Shift, 5   @ bitWidth 1 (TIMER6 timer reset)  
        .equ RCU_WWDGTRST_Shift, 11   @ bitWidth 1 (Window watchdog timer reset)  
        .equ RCU_SPI1RST_Shift, 14   @ bitWidth 1 (SPI1 reset)  
        .equ RCU_SPI2RST_Shift, 15   @ bitWidth 1 (SPI2 reset)  
        .equ RCU_USART1RST_Shift, 17   @ bitWidth 1 (USART1 reset)  
        .equ RCU_USART2RST_Shift, 18   @ bitWidth 1 (USART2 reset)  
        .equ RCU_UART3RST_Shift, 19   @ bitWidth 1 (UART3 reset)  
        .equ RCU_UART4RST_Shift, 20   @ bitWidth 1 (UART4 reset)  
        .equ RCU_I2C0RST_Shift, 21   @ bitWidth 1 (I2C0 reset)  
        .equ RCU_I2C1RST_Shift, 22   @ bitWidth 1 (I2C1 reset)  
        .equ RCU_CAN0RST_Shift, 25   @ bitWidth 1 (CAN0 reset)  
        .equ RCU_CAN1RST_Shift, 26   @ bitWidth 1 (CAN1 reset)  
        .equ RCU_BKPIRST_Shift, 27   @ bitWidth 1 (Backup interface reset)  
        .equ RCU_PMURST_Shift, 28   @ bitWidth 1 (Power control reset)  
        .equ RCU_DACRST_Shift, 29   @ bitWidth 1 (DAC reset)  
 
    .equ RCU_AHBEN, RCU_BASE + 0x14 @ (AHB enable register) 
        .equ RCU_DMA0EN_Shift, 0   @ bitWidth 1 (DMA0 clock enable)  
        .equ RCU_DMA1EN_Shift, 1   @ bitWidth 1 (DMA1 clock enable)  
        .equ RCU_SRAMSPEN_Shift, 2   @ bitWidth 1 (SRAM interface clock enable when sleep mode)  
        .equ RCU_FMCSPEN_Shift, 4   @ bitWidth 1 (FMC clock enable when sleep mode)  
        .equ RCU_CRCEN_Shift, 6   @ bitWidth 1 (CRC clock enable)  
        .equ RCU_EXMCEN_Shift, 8   @ bitWidth 1 (EXMC clock enable)  
        .equ RCU_USBFSEN_Shift, 12   @ bitWidth 1 (USBFS clock enable)  
 
    .equ RCU_APB2EN, RCU_BASE + 0x18 @ (APB2 clock enable register  RCU_APB2EN) 
        .equ RCU_AFEN_Shift, 0   @ bitWidth 1 (Alternate function IO clock enable )  
        .equ RCU_PAEN_Shift, 2   @ bitWidth 1 (GPIO port A clock enable)  
        .equ RCU_PBEN_Shift, 3   @ bitWidth 1 (GPIO port B clock enable)  
        .equ RCU_PCEN_Shift, 4   @ bitWidth 1 (GPIO port C clock enable)  
        .equ RCU_PDEN_Shift, 5   @ bitWidth 1 (GPIO port D clock enable )  
        .equ RCU_PEEN_Shift, 6   @ bitWidth 1 (GPIO port E clock enable )  
        .equ RCU_ADC0EN_Shift, 9   @ bitWidth 1 (ADC0 clock enable)  
        .equ RCU_ADC1EN_Shift, 10   @ bitWidth 1 (ADC1 clock enable)  
        .equ RCU_TIMER0EN_Shift, 11   @ bitWidth 1 (TIMER0 clock enable )  
        .equ RCU_SPI0EN_Shift, 12   @ bitWidth 1 (SPI0 clock enable)  
        .equ RCU_USART0EN_Shift, 14   @ bitWidth 1 (USART0 clock enable)  
 
    .equ RCU_APB1EN, RCU_BASE + 0x1C @ (APB1 clock enable register  RCU_APB1EN) 
        .equ RCU_TIMER1EN_Shift, 0   @ bitWidth 1 (TIMER1 timer clock enable)  
        .equ RCU_TIMER2EN_Shift, 1   @ bitWidth 1 (TIMER2 timer clock enable)  
        .equ RCU_TIMER3EN_Shift, 2   @ bitWidth 1 (TIMER3 timer clock enable)  
        .equ RCU_TIMER4EN_Shift, 3   @ bitWidth 1 (TIMER4 timer clock enable)  
        .equ RCU_TIMER5EN_Shift, 4   @ bitWidth 1 (TIMER5 timer clock enable)  
        .equ RCU_TIMER6EN_Shift, 5   @ bitWidth 1 (TIMER6 timer clock enable)  
        .equ RCU_WWDGTEN_Shift, 11   @ bitWidth 1 (Window watchdog timer clock enable)  
        .equ RCU_SPI1EN_Shift, 14   @ bitWidth 1 (SPI1 clock enable)  
        .equ RCU_SPI2EN_Shift, 15   @ bitWidth 1 (SPI2 clock enable)  
        .equ RCU_USART1EN_Shift, 17   @ bitWidth 1 (USART1 clock enable)  
        .equ RCU_USART2EN_Shift, 18   @ bitWidth 1 (USART2 clock enable)  
        .equ RCU_UART3EN_Shift, 19   @ bitWidth 1 (UART3 clock enable)  
        .equ RCU_UART4EN_Shift, 20   @ bitWidth 1 (UART4 clock enable)  
        .equ RCU_I2C0EN_Shift, 21   @ bitWidth 1 (I2C0 clock enable)  
        .equ RCU_I2C1EN_Shift, 22   @ bitWidth 1 (I2C1 clock enable)  
        .equ RCU_CAN0EN_Shift, 25   @ bitWidth 1 (CAN0 clock enable)  
        .equ RCU_CAN1EN_Shift, 26   @ bitWidth 1 (CAN1 clock enable)  
        .equ RCU_BKPIEN_Shift, 27   @ bitWidth 1 (Backup interface clock enable )  
        .equ RCU_PMUEN_Shift, 28   @ bitWidth 1 (Power control clock enable )  
        .equ RCU_DACEN_Shift, 29   @ bitWidth 1 (DAC clock enable)  
 
    .equ RCU_BDCTL, RCU_BASE + 0x20 @ (Backup domain control register  RCU_BDCTL) 
        .equ RCU_LXTALEN_Shift, 0   @ bitWidth 1 (LXTAL enable)  
        .equ RCU_LXTALSTB_Shift, 1   @ bitWidth 1 (External low-speed oscillator stabilization)  
        .equ RCU_LXTALBPS_Shift, 2   @ bitWidth 1 (LXTAL bypass mode enable)  
        .equ RCU_RTCSRC_Shift, 8   @ bitWidth 2 (RTC clock entry selection)  
        .equ RCU_RTCEN_Shift, 15   @ bitWidth 1 (RTC clock enable)  
        .equ RCU_BKPRST_Shift, 16   @ bitWidth 1 (Backup domain reset)  
 
    .equ RCU_RSTSCK, RCU_BASE + 0x24 @ (Reset source /clock register  RCU_RSTSCK) 
        .equ RCU_IRC40KEN_Shift, 0   @ bitWidth 1 (IRC40K enable)  
        .equ RCU_IRC40KSTB_Shift, 1   @ bitWidth 1 (IRC40K stabilization)  
        .equ RCU_RSTFC_Shift, 24   @ bitWidth 1 (Reset flag clear)  
        .equ RCU_EPRSTF_Shift, 26   @ bitWidth 1 (External PIN reset flag)  
        .equ RCU_PORRSTF_Shift, 27   @ bitWidth 1 (Power reset flag)  
        .equ RCU_SWRSTF_Shift, 28   @ bitWidth 1 (Software reset flag)  
        .equ RCU_FWDGTRSTF_Shift, 29   @ bitWidth 1 (Free Watchdog timer reset flag)  
        .equ RCU_WWDGTRSTF_Shift, 30   @ bitWidth 1 (Window watchdog timer reset flag)  
        .equ RCU_LPRSTF_Shift, 31   @ bitWidth 1 (Low-power reset flag)  
 
    .equ RCU_AHBRST, RCU_BASE + 0x28 @ (AHB reset register) 
        .equ RCU_USBFSRST_Shift, 12   @ bitWidth 1 (USBFS reset)  
 
    .equ RCU_CFG1, RCU_BASE + 0x2C @ (Clock Configuration register 1) 
        .equ RCU_PREDV0_Shift, 0   @ bitWidth 4 (PREDV0 division factor)  
        .equ RCU_PREDV1_Shift, 4   @ bitWidth 4 (PREDV1 division factor)  
        .equ RCU_PLL1MF_Shift, 8   @ bitWidth 4 (The PLL1 clock multiplication factor)  
        .equ RCU_PLL2MF_Shift, 12   @ bitWidth 4 (The PLL2 clock multiplication factor)  
        .equ RCU_PREDV0SEL_Shift, 16   @ bitWidth 1 (PREDV0 input Clock Source Selection)  
        .equ RCU_I2S1SEL_Shift, 17   @ bitWidth 1 (I2S1 Clock Source Selection)  
        .equ RCU_I2S2SEL_Shift, 18   @ bitWidth 1 (I2S2 Clock Source Selection)  
 
    .equ RCU_DSV, RCU_BASE + 0x34 @ (Deep sleep mode Voltage register) 
        .equ RCU_DSLPVS_Shift, 0   @ bitWidth 2 (Deep-sleep mode voltage select)  
 

@=========================== RTC ===========================@
.equ RTC_BASE, 0x40002800 @ (Real-time clock) 
    .equ RTC_INTEN, RTC_BASE + 0x0 @ (RTC interrupt enable register) 
        .equ RTC_OVIE_Shift, 2   @ bitWidth 1 (Overflow interrupt enable)  
        .equ RTC_ALRMIE_Shift, 1   @ bitWidth 1 (Alarm interrupt enable)  
        .equ RTC_SCIE_Shift, 0   @ bitWidth 1 (Second interrupt)  
 
    .equ RTC_CTL, RTC_BASE + 0x04 @ (control register) 
        .equ RTC_LWOFF_Shift, 5   @ bitWidth 1 (Last write operation finished flag)  
        .equ RTC_CMF_Shift, 4   @ bitWidth 1 (Configuration mode flag)  
        .equ RTC_RSYNF_Shift, 3   @ bitWidth 1 (Registers synchronized flag)  
        .equ RTC_OVIF_Shift, 2   @ bitWidth 1 (Overflow interrupt flag)  
        .equ RTC_ALRMIF_Shift, 1   @ bitWidth 1 (Alarm interrupt flag)  
        .equ RTC_SCIF_Shift, 0   @ bitWidth 1 (Sencond interrupt flag)  
 
    .equ RTC_PSCH, RTC_BASE + 0x08 @ (RTC prescaler high register) 
        .equ RTC_PSC_Shift, 0   @ bitWidth 4 (RTC prescaler value high)  
 
    .equ RTC_PSCL, RTC_BASE + 0x0C @ ( RTC prescaler low  register) 
        .equ RTC_PSC_Shift, 0   @ bitWidth 16 (RTC prescaler value low)  
 
    .equ RTC_DIVH, RTC_BASE + 0x10 @ (RTC divider high register) 
        .equ RTC_DIV_Shift, 0   @ bitWidth 4 (RTC divider value high)  
 
    .equ RTC_DIVL, RTC_BASE + 0x14 @ (RTC divider low register) 
        .equ RTC_DIV_Shift, 0   @ bitWidth 16 (RTC divider value low)  
 
    .equ RTC_CNTH, RTC_BASE + 0x18 @ (RTC counter high register) 
        .equ RTC_CNT_Shift, 0   @ bitWidth 16 (RTC counter value high)  
 
    .equ RTC_CNTL, RTC_BASE + 0x1C @ (RTC counter low register) 
        .equ RTC_CNT_Shift, 0   @ bitWidth 16 (RTC counter value low)  
 
    .equ RTC_ALRMH, RTC_BASE + 0x20 @ (Alarm high register) 
        .equ RTC_ALRM_Shift, 0   @ bitWidth 16 (Alarm value high)  
 
    .equ RTC_ALRML, RTC_BASE + 0x24 @ (RTC alarm low register) 
        .equ RTC_ALRM_Shift, 0   @ bitWidth 16 (alarm value low)  
 

@=========================== SPI0 ===========================@
.equ SPI0_BASE, 0x40013000 @ (Serial peripheral interface) 
    .equ SPI0_CTL0, SPI0_BASE + 0x0 @ (control register 0) 
        .equ SPI0_BDEN_Shift, 15   @ bitWidth 1 (Bidirectional   enable)  
        .equ SPI0_BDOEN_Shift, 14   @ bitWidth 1 (Bidirectional Transmit output enable  )  
        .equ SPI0_CRCEN_Shift, 13   @ bitWidth 1 (CRC Calculation Enable)  
        .equ SPI0_CRCNT_Shift, 12   @ bitWidth 1 (CRC Next Transfer)  
        .equ SPI0_FF16_Shift, 11   @ bitWidth 1 (Data frame format)  
        .equ SPI0_RO_Shift, 10   @ bitWidth 1 (Receive only)  
        .equ SPI0_SWNSSEN_Shift, 9   @ bitWidth 1 (NSS Software Mode Selection)  
        .equ SPI0_SWNSS_Shift, 8   @ bitWidth 1 (NSS Pin Selection In NSS Software Mode)  
        .equ SPI0_LF_Shift, 7   @ bitWidth 1 (LSB First Mode)  
        .equ SPI0_SPIEN_Shift, 6   @ bitWidth 1 (SPI enable)  
        .equ SPI0_PSC_Shift, 3   @ bitWidth 3 (Master Clock Prescaler Selection)  
        .equ SPI0_MSTMOD_Shift, 2   @ bitWidth 1 (Master Mode Enable)  
        .equ SPI0_CKPL_Shift, 1   @ bitWidth 1 (Clock polarity Selection)  
        .equ SPI0_CKPH_Shift, 0   @ bitWidth 1 (Clock Phase Selection)  
 
    .equ SPI0_CTL1, SPI0_BASE + 0x04 @ (control register 1) 
        .equ SPI0_TBEIE_Shift, 7   @ bitWidth 1 (Tx buffer empty interrupt  enable)  
        .equ SPI0_RBNEIE_Shift, 6   @ bitWidth 1 (RX buffer not empty interrupt  enable)  
        .equ SPI0_ERRIE_Shift, 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI0_TMOD_Shift, 4   @ bitWidth 1 (SPI TI mode enable)  
        .equ SPI0_NSSP_Shift, 3   @ bitWidth 1 (SPI NSS pulse mode enable)  
        .equ SPI0_NSSDRV_Shift, 2   @ bitWidth 1 (Drive NSS Output)  
        .equ SPI0_DMATEN_Shift, 1   @ bitWidth 1 (Transmit Buffer DMA Enable)  
        .equ SPI0_DMAREN_Shift, 0   @ bitWidth 1 (Rx buffer DMA enable)  
 
    .equ SPI0_STAT, SPI0_BASE + 0x08 @ (status register) 
        .equ SPI0_FERR_Shift, 8   @ bitWidth 1 (Format error)  
        .equ SPI0_TRANS_Shift, 7   @ bitWidth 1 (Transmitting On-going Bit)  
        .equ SPI0_RXORERR_Shift, 6   @ bitWidth 1 (Reception Overrun Error Bit)  
        .equ SPI0_CONFERR_Shift, 5   @ bitWidth 1 (SPI Configuration error)  
        .equ SPI0_CRCERR_Shift, 4   @ bitWidth 1 (SPI CRC Error Bit)  
        .equ SPI0_TXURERR_Shift, 3   @ bitWidth 1 (Transmission underrun error bit)  
        .equ SPI0_I2SCH_Shift, 2   @ bitWidth 1 (I2S channel side)  
        .equ SPI0_TBE_Shift, 1   @ bitWidth 1 (Transmit Buffer Empty)  
        .equ SPI0_RBNE_Shift, 0   @ bitWidth 1 (Receive Buffer Not Empty)  
 
    .equ SPI0_DATA, SPI0_BASE + 0x0C @ (data register) 
        .equ SPI0_SPI_DATA_Shift, 0   @ bitWidth 16 (Data transfer register)  
 
    .equ SPI0_CRCPOLY, SPI0_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI0_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial value)  
 
    .equ SPI0_RCRC, SPI0_BASE + 0x14 @ (RX CRC register) 
        .equ SPI0_RCRC_Shift, 0   @ bitWidth 16 (RX CRC value)  
 
    .equ SPI0_TCRC, SPI0_BASE + 0x18 @ (TX CRC register) 
        .equ SPI0_TCRC_Shift, 0   @ bitWidth 16 (Tx CRC value)  
 
    .equ SPI0_I2SCTL, SPI0_BASE + 0x1C @ (I2S control register) 
        .equ SPI0_I2SSEL_Shift, 11   @ bitWidth 1 (I2S mode selection)  
        .equ SPI0_I2SEN_Shift, 10   @ bitWidth 1 (I2S Enable)  
        .equ SPI0_I2SOPMOD_Shift, 8   @ bitWidth 2 (I2S operation mode)  
        .equ SPI0_PCMSMOD_Shift, 7   @ bitWidth 1 (PCM frame synchronization mode)  
        .equ SPI0_I2SSTD_Shift, 4   @ bitWidth 2 (I2S standard selection)  
        .equ SPI0_CKPL_Shift, 3   @ bitWidth 1 (Idle state clock polarity)  
        .equ SPI0_DTLEN_Shift, 1   @ bitWidth 2 (Data length)  
        .equ SPI0_CHLEN_Shift, 0   @ bitWidth 1 (Channel length number of bits per audio  channel)  
 
    .equ SPI0_I2SPSC, SPI0_BASE + 0x20 @ (I2S prescaler register) 
        .equ SPI0_MCKOEN_Shift, 9   @ bitWidth 1 (I2S_MCK output enable)  
        .equ SPI0_OF_Shift, 8   @ bitWidth 1 (Odd factor for the  prescaler)  
        .equ SPI0_DIV_Shift, 0   @ bitWidth 8 (Dividing factor for the prescaler)  
 

@=========================== SPI1 ===========================@
.equ SPI1_BASE, 0x40003800 @ (Serial peripheral interface) 
    .equ SPI1_CTL0, SPI1_BASE + 0x0 @ (control register 0) 
        .equ SPI1_BDEN_Shift, 15   @ bitWidth 1 (Bidirectional   enable)  
        .equ SPI1_BDOEN_Shift, 14   @ bitWidth 1 (Bidirectional Transmit output enable  )  
        .equ SPI1_CRCEN_Shift, 13   @ bitWidth 1 (CRC Calculation Enable)  
        .equ SPI1_CRCNT_Shift, 12   @ bitWidth 1 (CRC Next Transfer)  
        .equ SPI1_FF16_Shift, 11   @ bitWidth 1 (Data frame format)  
        .equ SPI1_RO_Shift, 10   @ bitWidth 1 (Receive only)  
        .equ SPI1_SWNSSEN_Shift, 9   @ bitWidth 1 (NSS Software Mode Selection)  
        .equ SPI1_SWNSS_Shift, 8   @ bitWidth 1 (NSS Pin Selection In NSS Software Mode)  
        .equ SPI1_LF_Shift, 7   @ bitWidth 1 (LSB First Mode)  
        .equ SPI1_SPIEN_Shift, 6   @ bitWidth 1 (SPI enable)  
        .equ SPI1_PSC_Shift, 3   @ bitWidth 3 (Master Clock Prescaler Selection)  
        .equ SPI1_MSTMOD_Shift, 2   @ bitWidth 1 (Master Mode Enable)  
        .equ SPI1_CKPL_Shift, 1   @ bitWidth 1 (Clock polarity Selection)  
        .equ SPI1_CKPH_Shift, 0   @ bitWidth 1 (Clock Phase Selection)  
 
    .equ SPI1_CTL1, SPI1_BASE + 0x04 @ (control register 1) 
        .equ SPI1_TBEIE_Shift, 7   @ bitWidth 1 (Tx buffer empty interrupt  enable)  
        .equ SPI1_RBNEIE_Shift, 6   @ bitWidth 1 (RX buffer not empty interrupt  enable)  
        .equ SPI1_ERRIE_Shift, 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI1_TMOD_Shift, 4   @ bitWidth 1 (SPI TI mode enable)  
        .equ SPI1_NSSP_Shift, 3   @ bitWidth 1 (SPI NSS pulse mode enable)  
        .equ SPI1_NSSDRV_Shift, 2   @ bitWidth 1 (Drive NSS Output)  
        .equ SPI1_DMATEN_Shift, 1   @ bitWidth 1 (Transmit Buffer DMA Enable)  
        .equ SPI1_DMAREN_Shift, 0   @ bitWidth 1 (Rx buffer DMA enable)  
 
    .equ SPI1_STAT, SPI1_BASE + 0x08 @ (status register) 
        .equ SPI1_FERR_Shift, 8   @ bitWidth 1 (Format error)  
        .equ SPI1_TRANS_Shift, 7   @ bitWidth 1 (Transmitting On-going Bit)  
        .equ SPI1_RXORERR_Shift, 6   @ bitWidth 1 (Reception Overrun Error Bit)  
        .equ SPI1_CONFERR_Shift, 5   @ bitWidth 1 (SPI Configuration error)  
        .equ SPI1_CRCERR_Shift, 4   @ bitWidth 1 (SPI CRC Error Bit)  
        .equ SPI1_TXURERR_Shift, 3   @ bitWidth 1 (Transmission underrun error bit)  
        .equ SPI1_I2SCH_Shift, 2   @ bitWidth 1 (I2S channel side)  
        .equ SPI1_TBE_Shift, 1   @ bitWidth 1 (Transmit Buffer Empty)  
        .equ SPI1_RBNE_Shift, 0   @ bitWidth 1 (Receive Buffer Not Empty)  
 
    .equ SPI1_DATA, SPI1_BASE + 0x0C @ (data register) 
        .equ SPI1_SPI_DATA_Shift, 0   @ bitWidth 16 (Data transfer register)  
 
    .equ SPI1_CRCPOLY, SPI1_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI1_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial value)  
 
    .equ SPI1_RCRC, SPI1_BASE + 0x14 @ (RX CRC register) 
        .equ SPI1_RCRC_Shift, 0   @ bitWidth 16 (RX CRC value)  
 
    .equ SPI1_TCRC, SPI1_BASE + 0x18 @ (TX CRC register) 
        .equ SPI1_TCRC_Shift, 0   @ bitWidth 16 (Tx CRC value)  
 
    .equ SPI1_I2SCTL, SPI1_BASE + 0x1C @ (I2S control register) 
        .equ SPI1_I2SSEL_Shift, 11   @ bitWidth 1 (I2S mode selection)  
        .equ SPI1_I2SEN_Shift, 10   @ bitWidth 1 (I2S Enable)  
        .equ SPI1_I2SOPMOD_Shift, 8   @ bitWidth 2 (I2S operation mode)  
        .equ SPI1_PCMSMOD_Shift, 7   @ bitWidth 1 (PCM frame synchronization mode)  
        .equ SPI1_I2SSTD_Shift, 4   @ bitWidth 2 (I2S standard selection)  
        .equ SPI1_CKPL_Shift, 3   @ bitWidth 1 (Idle state clock polarity)  
        .equ SPI1_DTLEN_Shift, 1   @ bitWidth 2 (Data length)  
        .equ SPI1_CHLEN_Shift, 0   @ bitWidth 1 (Channel length number of bits per audio  channel)  
 
    .equ SPI1_I2SPSC, SPI1_BASE + 0x20 @ (I2S prescaler register) 
        .equ SPI1_MCKOEN_Shift, 9   @ bitWidth 1 (I2S_MCK output enable)  
        .equ SPI1_OF_Shift, 8   @ bitWidth 1 (Odd factor for the  prescaler)  
        .equ SPI1_DIV_Shift, 0   @ bitWidth 8 (Dividing factor for the prescaler)  
 

@=========================== SPI2 ===========================@
.equ SPI2_BASE, 0x40003C00 @ (Serial peripheral interface) 
    .equ SPI2_CTL0, SPI2_BASE + 0x0 @ (control register 0) 
        .equ SPI2_BDEN_Shift, 15   @ bitWidth 1 (Bidirectional   enable)  
        .equ SPI2_BDOEN_Shift, 14   @ bitWidth 1 (Bidirectional Transmit output enable  )  
        .equ SPI2_CRCEN_Shift, 13   @ bitWidth 1 (CRC Calculation Enable)  
        .equ SPI2_CRCNT_Shift, 12   @ bitWidth 1 (CRC Next Transfer)  
        .equ SPI2_FF16_Shift, 11   @ bitWidth 1 (Data frame format)  
        .equ SPI2_RO_Shift, 10   @ bitWidth 1 (Receive only)  
        .equ SPI2_SWNSSEN_Shift, 9   @ bitWidth 1 (NSS Software Mode Selection)  
        .equ SPI2_SWNSS_Shift, 8   @ bitWidth 1 (NSS Pin Selection In NSS Software Mode)  
        .equ SPI2_LF_Shift, 7   @ bitWidth 1 (LSB First Mode)  
        .equ SPI2_SPIEN_Shift, 6   @ bitWidth 1 (SPI enable)  
        .equ SPI2_PSC_Shift, 3   @ bitWidth 3 (Master Clock Prescaler Selection)  
        .equ SPI2_MSTMOD_Shift, 2   @ bitWidth 1 (Master Mode Enable)  
        .equ SPI2_CKPL_Shift, 1   @ bitWidth 1 (Clock polarity Selection)  
        .equ SPI2_CKPH_Shift, 0   @ bitWidth 1 (Clock Phase Selection)  
 
    .equ SPI2_CTL1, SPI2_BASE + 0x04 @ (control register 1) 
        .equ SPI2_TBEIE_Shift, 7   @ bitWidth 1 (Tx buffer empty interrupt  enable)  
        .equ SPI2_RBNEIE_Shift, 6   @ bitWidth 1 (RX buffer not empty interrupt  enable)  
        .equ SPI2_ERRIE_Shift, 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI2_TMOD_Shift, 4   @ bitWidth 1 (SPI TI mode enable)  
        .equ SPI2_NSSP_Shift, 3   @ bitWidth 1 (SPI NSS pulse mode enable)  
        .equ SPI2_NSSDRV_Shift, 2   @ bitWidth 1 (Drive NSS Output)  
        .equ SPI2_DMATEN_Shift, 1   @ bitWidth 1 (Transmit Buffer DMA Enable)  
        .equ SPI2_DMAREN_Shift, 0   @ bitWidth 1 (Rx buffer DMA enable)  
 
    .equ SPI2_STAT, SPI2_BASE + 0x08 @ (status register) 
        .equ SPI2_FERR_Shift, 8   @ bitWidth 1 (Format error)  
        .equ SPI2_TRANS_Shift, 7   @ bitWidth 1 (Transmitting On-going Bit)  
        .equ SPI2_RXORERR_Shift, 6   @ bitWidth 1 (Reception Overrun Error Bit)  
        .equ SPI2_CONFERR_Shift, 5   @ bitWidth 1 (SPI Configuration error)  
        .equ SPI2_CRCERR_Shift, 4   @ bitWidth 1 (SPI CRC Error Bit)  
        .equ SPI2_TXURERR_Shift, 3   @ bitWidth 1 (Transmission underrun error bit)  
        .equ SPI2_I2SCH_Shift, 2   @ bitWidth 1 (I2S channel side)  
        .equ SPI2_TBE_Shift, 1   @ bitWidth 1 (Transmit Buffer Empty)  
        .equ SPI2_RBNE_Shift, 0   @ bitWidth 1 (Receive Buffer Not Empty)  
 
    .equ SPI2_DATA, SPI2_BASE + 0x0C @ (data register) 
        .equ SPI2_SPI_DATA_Shift, 0   @ bitWidth 16 (Data transfer register)  
 
    .equ SPI2_CRCPOLY, SPI2_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI2_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial value)  
 
    .equ SPI2_RCRC, SPI2_BASE + 0x14 @ (RX CRC register) 
        .equ SPI2_RCRC_Shift, 0   @ bitWidth 16 (RX CRC value)  
 
    .equ SPI2_TCRC, SPI2_BASE + 0x18 @ (TX CRC register) 
        .equ SPI2_TCRC_Shift, 0   @ bitWidth 16 (Tx CRC value)  
 
    .equ SPI2_I2SCTL, SPI2_BASE + 0x1C @ (I2S control register) 
        .equ SPI2_I2SSEL_Shift, 11   @ bitWidth 1 (I2S mode selection)  
        .equ SPI2_I2SEN_Shift, 10   @ bitWidth 1 (I2S Enable)  
        .equ SPI2_I2SOPMOD_Shift, 8   @ bitWidth 2 (I2S operation mode)  
        .equ SPI2_PCMSMOD_Shift, 7   @ bitWidth 1 (PCM frame synchronization mode)  
        .equ SPI2_I2SSTD_Shift, 4   @ bitWidth 2 (I2S standard selection)  
        .equ SPI2_CKPL_Shift, 3   @ bitWidth 1 (Idle state clock polarity)  
        .equ SPI2_DTLEN_Shift, 1   @ bitWidth 2 (Data length)  
        .equ SPI2_CHLEN_Shift, 0   @ bitWidth 1 (Channel length number of bits per audio  channel)  
 
    .equ SPI2_I2SPSC, SPI2_BASE + 0x20 @ (I2S prescaler register) 
        .equ SPI2_MCKOEN_Shift, 9   @ bitWidth 1 (I2S_MCK output enable)  
        .equ SPI2_OF_Shift, 8   @ bitWidth 1 (Odd factor for the  prescaler)  
        .equ SPI2_DIV_Shift, 0   @ bitWidth 8 (Dividing factor for the prescaler)  
 

@=========================== TIMER0 ===========================@
.equ TIMER0_BASE, 0x40012c00 @ (Advanced-timers) 
    .equ TIMER0_CTL0, TIMER0_BASE + 0x0 @ (control register 0) 
        .equ TIMER0_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER0_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER0_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode  selection)  
        .equ TIMER0_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIMER0_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER0_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER0_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER0_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER0_CTL1, TIMER0_BASE + 0x04 @ (control register 1) 
        .equ TIMER0_ISO3_Shift, 14   @ bitWidth 1 (Idle state of channel 3 output)  
        .equ TIMER0_ISO2N_Shift, 13   @ bitWidth 1 (Idle state of channel 2 complementary output)  
        .equ TIMER0_ISO2_Shift, 12   @ bitWidth 1 (Idle state of channel 2 output)  
        .equ TIMER0_ISO1N_Shift, 11   @ bitWidth 1 (Idle state of channel 1 complementary output)  
        .equ TIMER0_ISO1_Shift, 10   @ bitWidth 1 (Idle state of channel 1 output)  
        .equ TIMER0_ISO0N_Shift, 9   @ bitWidth 1 (Idle state of channel 0 complementary output)  
        .equ TIMER0_ISO0_Shift, 8   @ bitWidth 1 (Idle state of channel 0 output)  
        .equ TIMER0_TI0S_Shift, 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER0_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER0_DMAS_Shift, 3   @ bitWidth 1 (DMA request source selection)  
        .equ TIMER0_CCUC_Shift, 2   @ bitWidth 1 (Commutation control shadow register update control)  
        .equ TIMER0_CCSE_Shift, 0   @ bitWidth 1 (Commutation control shadow enable)  
 
    .equ TIMER0_SMCFG, TIMER0_BASE + 0x08 @ (slave mode configuration register) 
        .equ TIMER0_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER0_SMC1_Shift, 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER0_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER0_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER0_MSM_Shift, 7   @ bitWidth 1 (Master/Slave mode)  
        .equ TIMER0_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER0_SMC_Shift, 0   @ bitWidth 3 (Slave mode selection)  
 
    .equ TIMER0_DMAINTEN, TIMER0_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER0_TRGDEN_Shift, 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER0_CMTDEN_Shift, 13   @ bitWidth 1 (Commutation DMA request enable)  
        .equ TIMER0_CH3DEN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER0_CH2DEN_Shift, 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER0_CH1DEN_Shift, 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER0_CH0DEN_Shift, 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER0_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER0_BRKIE_Shift, 7   @ bitWidth 1 (Break interrupt enable)  
        .equ TIMER0_TRGIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER0_CMTIE_Shift, 5   @ bitWidth 1 (commutation interrupt enable)  
        .equ TIMER0_CH3IE_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER0_CH2IE_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER0_CH1IE_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER0_CH0IE_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER0_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER0_INTF, TIMER0_BASE + 0x10 @ (Interrupt flag register) 
        .equ TIMER0_CH3OF_Shift, 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER0_CH2OF_Shift, 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER0_CH1OF_Shift, 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER0_CH0OF_Shift, 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER0_BRKIF_Shift, 7   @ bitWidth 1 (Break interrupt flag)  
        .equ TIMER0_TRGIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER0_CMTIF_Shift, 5   @ bitWidth 1 (Channel commutation interrupt flag)  
        .equ TIMER0_CH3IF_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt flag)  
        .equ TIMER0_CH2IF_Shift, 3   @ bitWidth 1 ( Channel 2 capture/compare interrupt flag)  
        .equ TIMER0_CH1IF_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER0_CH0IF_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER0_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER0_SWEVG, TIMER0_BASE + 0x14 @ (Software event generation register) 
        .equ TIMER0_BRKG_Shift, 7   @ bitWidth 1 (Break event generation)  
        .equ TIMER0_TRGG_Shift, 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER0_CMTG_Shift, 5   @ bitWidth 1 (Channel commutation event generation)  
        .equ TIMER0_CH3G_Shift, 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER0_CH2G_Shift, 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER0_CH1G_Shift, 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER0_CH0G_Shift, 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER0_UPG_Shift, 0   @ bitWidth 1 (Update event generation)  
 
    .equ TIMER0_CHCTL0_Output, TIMER0_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER0_CH1COMCEN_Shift, 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER0_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER0_CH1COMSEN_Shift, 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER0_CH1COMFEN_Shift, 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER0_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER0_CH0COMCEN_Shift, 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER0_CH0COMCTL_Shift, 4   @ bitWidth 3 (Channel 0 compare output control)  
        .equ TIMER0_CH0COMSEN_Shift, 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER0_CH0COMFEN_Shift, 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER0_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER0_CHCTL0_Input, TIMER0_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER0_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER0_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER0_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER0_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER0_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER0_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER0_CHCTL1_Output, TIMER0_BASE + 0x1C @ (Channel control register 1 output  mode) 
        .equ TIMER0_CH3COMCEN_Shift, 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER0_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER0_CH3COMSEN_Shift, 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER0_CH3COMFEN_Shift, 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER0_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER0_CH2COMCEN_Shift, 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER0_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER0_CH2COMSEN_Shift, 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER0_CH2COMFEN_Shift, 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER0_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER0_CHCTL1_Input, TIMER0_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER0_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER0_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER0_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER0_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER0_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER0_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER0_CHCTL2, TIMER0_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER0_CH3P_Shift, 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER0_CH3EN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER0_CH2NP_Shift, 11   @ bitWidth 1 (Channel 2 complementary output polarity)  
        .equ TIMER0_CH2NEN_Shift, 10   @ bitWidth 1 (Channel 2 complementary output enable)  
        .equ TIMER0_CH2P_Shift, 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER0_CH2EN_Shift, 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER0_CH1NP_Shift, 7   @ bitWidth 1 (Channel 1 complementary output polarity)  
        .equ TIMER0_CH1NEN_Shift, 6   @ bitWidth 1 (Channel 1 complementary output enable)  
        .equ TIMER0_CH1P_Shift, 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER0_CH1EN_Shift, 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER0_CH0NP_Shift, 3   @ bitWidth 1 (Channel 0 complementary output polarity)  
        .equ TIMER0_CH0NEN_Shift, 2   @ bitWidth 1 (Channel 0 complementary output enable)  
        .equ TIMER0_CH0P_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER0_CH0EN_Shift, 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER0_CNT, TIMER0_BASE + 0x24 @ (counter) 
        .equ TIMER0_CNT_Shift, 0   @ bitWidth 16 (current counter value)  
 
    .equ TIMER0_PSC, TIMER0_BASE + 0x28 @ (prescaler) 
        .equ TIMER0_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER0_CAR, TIMER0_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER0_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER0_CREP, TIMER0_BASE + 0x30 @ (Counter repetition register) 
        .equ TIMER0_CREP_Shift, 0   @ bitWidth 8 (Counter repetition value)  
 
    .equ TIMER0_CH0CV, TIMER0_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER0_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel0)  
 
    .equ TIMER0_CH1CV, TIMER0_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER0_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER0_CH2CV, TIMER0_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER0_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER0_CH3CV, TIMER0_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER0_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER0_CCHP, TIMER0_BASE + 0x44 @ (channel complementary protection register) 
        .equ TIMER0_POEN_Shift, 15   @ bitWidth 1 (Primary output enable)  
        .equ TIMER0_OAEN_Shift, 14   @ bitWidth 1 (Output automatic enable)  
        .equ TIMER0_BRKP_Shift, 13   @ bitWidth 1 (Break polarity)  
        .equ TIMER0_BRKEN_Shift, 12   @ bitWidth 1 (Break enable)  
        .equ TIMER0_ROS_Shift, 11   @ bitWidth 1 (Run mode off-state configure)  
        .equ TIMER0_IOS_Shift, 10   @ bitWidth 1 (Idle mode off-state configure)  
        .equ TIMER0_PROT_Shift, 8   @ bitWidth 2 (Complementary register protect control)  
        .equ TIMER0_DTCFG_Shift, 0   @ bitWidth 8 (Dead time configure)  
 
    .equ TIMER0_DMACFG, TIMER0_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER0_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER0_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER0_DMATB, TIMER0_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER0_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER1 ===========================@
.equ TIMER1_BASE, 0x40000000 @ (General-purpose-timers) 
    .equ TIMER1_CTL0, TIMER1_BASE + 0x0 @ (control register 0) 
        .equ TIMER1_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER1_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER1_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER1_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIMER1_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER1_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER1_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER1_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER1_CTL1, TIMER1_BASE + 0x04 @ (control register 1) 
        .equ TIMER1_TI0S_Shift, 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER1_DMAS_Shift, 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER1_SMCFG, TIMER1_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER1_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER1_SMC1_Shift, 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER1_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER1_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER1_MSM_Shift, 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER1_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER1_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER1_DMAINTEN, TIMER1_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER1_TRGDEN_Shift, 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER1_CH3DEN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER1_CH2DEN_Shift, 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER1_CH1DEN_Shift, 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER1_CH0DEN_Shift, 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER1_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER1_TRGIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER1_CH3IE_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER1_CH2IE_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER1_CH1IE_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER1_CH0IE_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER1_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER1_INTF, TIMER1_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER1_CH3OF_Shift, 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER1_CH2OF_Shift, 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER1_CH1OF_Shift, 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER1_CH0OF_Shift, 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER1_TRGIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER1_CH3IF_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER1_CH2IF_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER1_CH1IF_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER1_CH0IF_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER1_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER1_SWEVG, TIMER1_BASE + 0x14 @ (event generation register) 
        .equ TIMER1_TRGG_Shift, 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER1_CH3G_Shift, 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER1_CH2G_Shift, 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER1_CH1G_Shift, 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER1_CH0G_Shift, 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER1_UPG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER1_CHCTL0_Output, TIMER1_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER1_CH1COMCEN_Shift, 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER1_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER1_CH1COMSEN_Shift, 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER1_CH1COMFEN_Shift, 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER1_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER1_CH0COMCEN_Shift, 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER1_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER1_CH0COMSEN_Shift, 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER1_CH0COMFEN_Shift, 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER1_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER1_CHCTL0_Input, TIMER1_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER1_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER1_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER1_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER1_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER1_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER1_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER1_CHCTL1_Output, TIMER1_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER1_CH3COMCEN_Shift, 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER1_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER1_CH3COMSEN_Shift, 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER1_CH3COMFEN_Shift, 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER1_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER1_CH2COMCEN_Shift, 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER1_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER1_CH2COMSEN_Shift, 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER1_CH2COMFEN_Shift, 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER1_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER1_CHCTL1_Input, TIMER1_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER1_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER1_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER1_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER1_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER1_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER1_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER1_CHCTL2, TIMER1_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER1_CH3P_Shift, 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER1_CH3EN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER1_CH2P_Shift, 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER1_CH2EN_Shift, 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER1_CH1P_Shift, 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER1_CH1EN_Shift, 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER1_CH0P_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER1_CH0EN_Shift, 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER1_CNT, TIMER1_BASE + 0x24 @ (Counter register) 
        .equ TIMER1_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER1_PSC, TIMER1_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER1_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER1_CAR, TIMER1_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER1_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER1_CH0CV, TIMER1_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER1_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER1_CH1CV, TIMER1_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER1_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER1_CH2CV, TIMER1_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER1_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER1_CH3CV, TIMER1_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER1_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER1_DMACFG, TIMER1_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER1_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER1_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER1_DMATB, TIMER1_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER1_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER2 ===========================@
.equ TIMER2_BASE, 0x40000400 @ (General-purpose-timers) 
    .equ TIMER2_CTL0, TIMER2_BASE + 0x0 @ (control register 0) 
        .equ TIMER2_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER2_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER2_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER2_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIMER2_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER2_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER2_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER2_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER2_CTL1, TIMER2_BASE + 0x04 @ (control register 1) 
        .equ TIMER2_TI0S_Shift, 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER2_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER2_DMAS_Shift, 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER2_SMCFG, TIMER2_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER2_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER2_SMC1_Shift, 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER2_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER2_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER2_MSM_Shift, 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER2_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER2_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER2_DMAINTEN, TIMER2_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER2_TRGDEN_Shift, 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER2_CH3DEN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER2_CH2DEN_Shift, 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER2_CH1DEN_Shift, 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER2_CH0DEN_Shift, 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER2_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER2_TRGIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER2_CH3IE_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER2_CH2IE_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER2_CH1IE_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER2_CH0IE_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER2_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER2_INTF, TIMER2_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER2_CH3OF_Shift, 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER2_CH2OF_Shift, 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER2_CH1OF_Shift, 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER2_CH0OF_Shift, 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER2_TRGIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER2_CH3IF_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER2_CH2IF_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER2_CH1IF_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER2_CH0IF_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER2_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER2_SWEVG, TIMER2_BASE + 0x14 @ (event generation register) 
        .equ TIMER2_TRGG_Shift, 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER2_CH3G_Shift, 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER2_CH2G_Shift, 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER2_CH1G_Shift, 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER2_CH0G_Shift, 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER2_UPG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER2_CHCTL0_Output, TIMER2_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER2_CH1COMCEN_Shift, 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER2_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER2_CH1COMSEN_Shift, 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER2_CH1COMFEN_Shift, 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER2_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER2_CH0COMCEN_Shift, 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER2_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER2_CH0COMSEN_Shift, 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER2_CH0COMFEN_Shift, 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER2_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER2_CHCTL0_Input, TIMER2_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER2_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER2_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER2_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER2_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER2_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER2_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER2_CHCTL1_Output, TIMER2_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER2_CH3COMCEN_Shift, 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER2_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER2_CH3COMSEN_Shift, 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER2_CH3COMFEN_Shift, 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER2_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER2_CH2COMCEN_Shift, 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER2_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER2_CH2COMSEN_Shift, 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER2_CH2COMFEN_Shift, 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER2_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER2_CHCTL1_Input, TIMER2_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER2_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER2_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER2_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER2_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER2_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER2_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER2_CHCTL2, TIMER2_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER2_CH3P_Shift, 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER2_CH3EN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER2_CH2P_Shift, 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER2_CH2EN_Shift, 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER2_CH1P_Shift, 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER2_CH1EN_Shift, 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER2_CH0P_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER2_CH0EN_Shift, 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER2_CNT, TIMER2_BASE + 0x24 @ (Counter register) 
        .equ TIMER2_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER2_PSC, TIMER2_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER2_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER2_CAR, TIMER2_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER2_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER2_CH0CV, TIMER2_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER2_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER2_CH1CV, TIMER2_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER2_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER2_CH2CV, TIMER2_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER2_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER2_CH3CV, TIMER2_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER2_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER2_DMACFG, TIMER2_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER2_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER2_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER2_DMATB, TIMER2_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER2_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER3 ===========================@
.equ TIMER3_BASE, 0x40000800 @ (General-purpose-timers) 
    .equ TIMER3_CTL0, TIMER3_BASE + 0x0 @ (control register 0) 
        .equ TIMER3_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER3_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER3_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER3_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIMER3_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER3_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER3_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER3_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER3_CTL1, TIMER3_BASE + 0x04 @ (control register 1) 
        .equ TIMER3_TI0S_Shift, 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER3_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER3_DMAS_Shift, 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER3_SMCFG, TIMER3_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER3_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER3_SMC1_Shift, 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER3_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER3_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER3_MSM_Shift, 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER3_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER3_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER3_DMAINTEN, TIMER3_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER3_TRGDEN_Shift, 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER3_CH3DEN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER3_CH2DEN_Shift, 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER3_CH1DEN_Shift, 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER3_CH0DEN_Shift, 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER3_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER3_TRGIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER3_CH3IE_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER3_CH2IE_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER3_CH1IE_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER3_CH0IE_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER3_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER3_INTF, TIMER3_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER3_CH3OF_Shift, 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER3_CH2OF_Shift, 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER3_CH1OF_Shift, 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER3_CH0OF_Shift, 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER3_TRGIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER3_CH3IF_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER3_CH2IF_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER3_CH1IF_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER3_CH0IF_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER3_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER3_SWEVG, TIMER3_BASE + 0x14 @ (event generation register) 
        .equ TIMER3_TRGG_Shift, 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER3_CH3G_Shift, 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER3_CH2G_Shift, 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER3_CH1G_Shift, 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER3_CH0G_Shift, 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER3_UPG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER3_CHCTL0_Output, TIMER3_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER3_CH1COMCEN_Shift, 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER3_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER3_CH1COMSEN_Shift, 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER3_CH1COMFEN_Shift, 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER3_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER3_CH0COMCEN_Shift, 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER3_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER3_CH0COMSEN_Shift, 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER3_CH0COMFEN_Shift, 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER3_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER3_CHCTL0_Input, TIMER3_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER3_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER3_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER3_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER3_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER3_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER3_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER3_CHCTL1_Output, TIMER3_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER3_CH3COMCEN_Shift, 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER3_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER3_CH3COMSEN_Shift, 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER3_CH3COMFEN_Shift, 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER3_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER3_CH2COMCEN_Shift, 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER3_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER3_CH2COMSEN_Shift, 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER3_CH2COMFEN_Shift, 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER3_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER3_CHCTL1_Input, TIMER3_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER3_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER3_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER3_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER3_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER3_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER3_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER3_CHCTL2, TIMER3_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER3_CH3P_Shift, 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER3_CH3EN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER3_CH2P_Shift, 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER3_CH2EN_Shift, 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER3_CH1P_Shift, 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER3_CH1EN_Shift, 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER3_CH0P_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER3_CH0EN_Shift, 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER3_CNT, TIMER3_BASE + 0x24 @ (Counter register) 
        .equ TIMER3_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER3_PSC, TIMER3_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER3_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER3_CAR, TIMER3_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER3_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER3_CH0CV, TIMER3_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER3_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER3_CH1CV, TIMER3_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER3_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER3_CH2CV, TIMER3_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER3_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER3_CH3CV, TIMER3_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER3_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER3_DMACFG, TIMER3_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER3_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER3_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER3_DMATB, TIMER3_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER3_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER4 ===========================@
.equ TIMER4_BASE, 0x40000C00 @ (General-purpose-timers) 
    .equ TIMER4_CTL0, TIMER4_BASE + 0x0 @ (control register 0) 
        .equ TIMER4_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER4_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER4_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER4_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIMER4_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER4_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER4_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER4_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER4_CTL1, TIMER4_BASE + 0x04 @ (control register 1) 
        .equ TIMER4_TI0S_Shift, 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER4_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER4_DMAS_Shift, 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER4_SMCFG, TIMER4_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER4_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER4_SMC1_Shift, 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER4_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER4_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER4_MSM_Shift, 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER4_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER4_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER4_DMAINTEN, TIMER4_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER4_TRGDEN_Shift, 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER4_CH3DEN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER4_CH2DEN_Shift, 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER4_CH1DEN_Shift, 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER4_CH0DEN_Shift, 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER4_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER4_TRGIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER4_CH3IE_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER4_CH2IE_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER4_CH1IE_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER4_CH0IE_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER4_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER4_INTF, TIMER4_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER4_CH3OF_Shift, 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER4_CH2OF_Shift, 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER4_CH1OF_Shift, 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER4_CH0OF_Shift, 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER4_TRGIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER4_CH3IF_Shift, 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER4_CH2IF_Shift, 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER4_CH1IF_Shift, 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER4_CH0IF_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER4_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER4_SWEVG, TIMER4_BASE + 0x14 @ (event generation register) 
        .equ TIMER4_TRGG_Shift, 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER4_CH3G_Shift, 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER4_CH2G_Shift, 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER4_CH1G_Shift, 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER4_CH0G_Shift, 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER4_UPG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER4_CHCTL0_Output, TIMER4_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER4_CH1COMCEN_Shift, 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER4_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER4_CH1COMSEN_Shift, 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER4_CH1COMFEN_Shift, 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER4_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER4_CH0COMCEN_Shift, 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER4_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER4_CH0COMSEN_Shift, 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER4_CH0COMFEN_Shift, 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER4_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER4_CHCTL0_Input, TIMER4_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER4_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER4_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER4_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER4_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER4_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER4_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER4_CHCTL1_Output, TIMER4_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER4_CH3COMCEN_Shift, 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER4_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER4_CH3COMSEN_Shift, 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER4_CH3COMFEN_Shift, 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER4_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER4_CH2COMCEN_Shift, 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER4_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER4_CH2COMSEN_Shift, 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER4_CH2COMFEN_Shift, 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER4_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER4_CHCTL1_Input, TIMER4_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER4_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER4_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER4_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER4_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER4_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER4_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER4_CHCTL2, TIMER4_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER4_CH3P_Shift, 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER4_CH3EN_Shift, 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER4_CH2P_Shift, 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER4_CH2EN_Shift, 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER4_CH1P_Shift, 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER4_CH1EN_Shift, 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER4_CH0P_Shift, 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER4_CH0EN_Shift, 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER4_CNT, TIMER4_BASE + 0x24 @ (Counter register) 
        .equ TIMER4_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER4_PSC, TIMER4_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER4_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER4_CAR, TIMER4_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER4_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER4_CH0CV, TIMER4_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER4_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER4_CH1CV, TIMER4_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER4_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER4_CH2CV, TIMER4_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER4_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER4_CH3CV, TIMER4_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER4_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER4_DMACFG, TIMER4_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER4_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER4_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER4_DMATB, TIMER4_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER4_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER5 ===========================@
.equ TIMER5_BASE, 0x40001000 @ (Basic-timers) 
    .equ TIMER5_CTL0, TIMER5_BASE + 0x0 @ (control register 0) 
        .equ TIMER5_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER5_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER5_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER5_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER5_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER5_CTL1, TIMER5_BASE + 0x04 @ (control register 1) 
        .equ TIMER5_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
 
    .equ TIMER5_DMAINTEN, TIMER5_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER5_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER5_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER5_INTF, TIMER5_BASE + 0x10 @ (Interrupt flag register) 
        .equ TIMER5_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER5_SWEVG, TIMER5_BASE + 0x14 @ (event generation register) 
        .equ TIMER5_UPG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER5_CNT, TIMER5_BASE + 0x24 @ (Counter register) 
        .equ TIMER5_CNT_Shift, 0   @ bitWidth 16 (Low counter value)  
 
    .equ TIMER5_PSC, TIMER5_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER5_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER5_CAR, TIMER5_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER5_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 

@=========================== TIMER6 ===========================@
.equ TIMER6_BASE, 0x40001400 @ (Basic-timers) 
    .equ TIMER6_CTL0, TIMER6_BASE + 0x0 @ (control register 0) 
        .equ TIMER6_ARSE_Shift, 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER6_SPM_Shift, 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER6_UPS_Shift, 2   @ bitWidth 1 (Update source)  
        .equ TIMER6_UPDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIMER6_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER6_CTL1, TIMER6_BASE + 0x04 @ (control register 1) 
        .equ TIMER6_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
 
    .equ TIMER6_DMAINTEN, TIMER6_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER6_UPDEN_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER6_UPIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER6_INTF, TIMER6_BASE + 0x10 @ (Interrupt flag register) 
        .equ TIMER6_UPIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER6_SWEVG, TIMER6_BASE + 0x14 @ (event generation register) 
        .equ TIMER6_UPG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER6_CNT, TIMER6_BASE + 0x24 @ (Counter register) 
        .equ TIMER6_CNT_Shift, 0   @ bitWidth 16 (Low counter value)  
 
    .equ TIMER6_PSC, TIMER6_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER6_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER6_CAR, TIMER6_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER6_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 

@=========================== USART0 ===========================@
.equ USART0_BASE, 0x40013800 @ (Universal synchronous asynchronous receiver  transmitter) 
    .equ USART0_STAT, USART0_BASE + 0x00 @ (Status register ) 
        .equ USART0_CTSF_Shift, 9   @ bitWidth 1 (CTS change flag)  
        .equ USART0_LBDF_Shift, 8   @ bitWidth 1 (LIN break detection flag)  
        .equ USART0_TBE_Shift, 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ USART0_TC_Shift, 6   @ bitWidth 1 (Transmission complete)  
        .equ USART0_RBNE_Shift, 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ USART0_IDLEF_Shift, 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ USART0_ORERR_Shift, 3   @ bitWidth 1 (Overrun error)  
        .equ USART0_NERR_Shift, 2   @ bitWidth 1 (Noise error flag)  
        .equ USART0_FERR_Shift, 1   @ bitWidth 1 (Frame error flag)  
        .equ USART0_PERR_Shift, 0   @ bitWidth 1 (Parity error flag)  
 
    .equ USART0_DATA, USART0_BASE + 0x04 @ (Data register) 
        .equ USART0_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ USART0_BAUD, USART0_BASE + 0x08 @ (Baud rate register) 
        .equ USART0_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ USART0_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ USART0_CTL0, USART0_BASE + 0x0C @ (Control register 0) 
        .equ USART0_UEN_Shift, 13   @ bitWidth 1 (USART enable)  
        .equ USART0_WL_Shift, 12   @ bitWidth 1 (Word length)  
        .equ USART0_WM_Shift, 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ USART0_PCEN_Shift, 10   @ bitWidth 1 (Parity check function enable)  
        .equ USART0_PM_Shift, 9   @ bitWidth 1 (Parity mode)  
        .equ USART0_PERRIE_Shift, 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ USART0_TBEIE_Shift, 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ USART0_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART0_RBNEIE_Shift, 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ USART0_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ USART0_TEN_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART0_REN_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ USART0_RWU_Shift, 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ USART0_SBKCMD_Shift, 0   @ bitWidth 1 (Send break command)  
 
    .equ USART0_CTL1, USART0_BASE + 0x10 @ (Control register 1) 
        .equ USART0_LMEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART0_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ USART0_CKEN_Shift, 11   @ bitWidth 1 (CK pin enable)  
        .equ USART0_CPL_Shift, 10   @ bitWidth 1 (Clock polarity)  
        .equ USART0_CPH_Shift, 9   @ bitWidth 1 (Clock phase)  
        .equ USART0_CLEN_Shift, 8   @ bitWidth 1 (CK Length)  
        .equ USART0_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ USART0_LBLEN_Shift, 5   @ bitWidth 1 (LIN break frame length)  
        .equ USART0_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ USART0_CTL2, USART0_BASE + 0x14 @ (Control register 2) 
        .equ USART0_CTSIE_Shift, 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART0_CTSEN_Shift, 9   @ bitWidth 1 (CTS enable)  
        .equ USART0_RTSEN_Shift, 8   @ bitWidth 1 (RTS enable)  
        .equ USART0_DENT_Shift, 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ USART0_DENR_Shift, 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ USART0_SCEN_Shift, 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART0_NKEN_Shift, 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART0_HDEN_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART0_IRLP_Shift, 2   @ bitWidth 1 (IrDA low-power)  
        .equ USART0_IREN_Shift, 1   @ bitWidth 1 (IrDA mode enable)  
        .equ USART0_ERRIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART0_GP, USART0_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ USART0_GUAT_Shift, 8   @ bitWidth 8 (Guard time value in Smartcard mode)  
        .equ USART0_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== USART1 ===========================@
.equ USART1_BASE, 0x40004400 @ (Universal synchronous asynchronous receiver  transmitter) 
    .equ USART1_STAT, USART1_BASE + 0x00 @ (Status register ) 
        .equ USART1_CTSF_Shift, 9   @ bitWidth 1 (CTS change flag)  
        .equ USART1_LBDF_Shift, 8   @ bitWidth 1 (LIN break detection flag)  
        .equ USART1_TBE_Shift, 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ USART1_TC_Shift, 6   @ bitWidth 1 (Transmission complete)  
        .equ USART1_RBNE_Shift, 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ USART1_IDLEF_Shift, 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ USART1_ORERR_Shift, 3   @ bitWidth 1 (Overrun error)  
        .equ USART1_NERR_Shift, 2   @ bitWidth 1 (Noise error flag)  
        .equ USART1_FERR_Shift, 1   @ bitWidth 1 (Frame error flag)  
        .equ USART1_PERR_Shift, 0   @ bitWidth 1 (Parity error flag)  
 
    .equ USART1_DATA, USART1_BASE + 0x04 @ (Data register) 
        .equ USART1_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ USART1_BAUD, USART1_BASE + 0x08 @ (Baud rate register) 
        .equ USART1_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ USART1_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ USART1_CTL0, USART1_BASE + 0x0C @ (Control register 0) 
        .equ USART1_UEN_Shift, 13   @ bitWidth 1 (USART enable)  
        .equ USART1_WL_Shift, 12   @ bitWidth 1 (Word length)  
        .equ USART1_WM_Shift, 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ USART1_PCEN_Shift, 10   @ bitWidth 1 (Parity check function enable)  
        .equ USART1_PM_Shift, 9   @ bitWidth 1 (Parity mode)  
        .equ USART1_PERRIE_Shift, 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ USART1_TBEIE_Shift, 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ USART1_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART1_RBNEIE_Shift, 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ USART1_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ USART1_TEN_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART1_REN_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ USART1_RWU_Shift, 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ USART1_SBKCMD_Shift, 0   @ bitWidth 1 (Send break command)  
 
    .equ USART1_CTL1, USART1_BASE + 0x10 @ (Control register 1) 
        .equ USART1_LMEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART1_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ USART1_CKEN_Shift, 11   @ bitWidth 1 (CK pin enable)  
        .equ USART1_CPL_Shift, 10   @ bitWidth 1 (Clock polarity)  
        .equ USART1_CPH_Shift, 9   @ bitWidth 1 (Clock phase)  
        .equ USART1_CLEN_Shift, 8   @ bitWidth 1 (CK Length)  
        .equ USART1_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ USART1_LBLEN_Shift, 5   @ bitWidth 1 (LIN break frame length)  
        .equ USART1_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ USART1_CTL2, USART1_BASE + 0x14 @ (Control register 2) 
        .equ USART1_CTSIE_Shift, 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART1_CTSEN_Shift, 9   @ bitWidth 1 (CTS enable)  
        .equ USART1_RTSEN_Shift, 8   @ bitWidth 1 (RTS enable)  
        .equ USART1_DENT_Shift, 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ USART1_DENR_Shift, 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ USART1_SCEN_Shift, 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART1_NKEN_Shift, 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART1_HDEN_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART1_IRLP_Shift, 2   @ bitWidth 1 (IrDA low-power)  
        .equ USART1_IREN_Shift, 1   @ bitWidth 1 (IrDA mode enable)  
        .equ USART1_ERRIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART1_GP, USART1_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ USART1_GUAT_Shift, 8   @ bitWidth 8 (Guard time value in Smartcard mode)  
        .equ USART1_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== USART2 ===========================@
.equ USART2_BASE, 0x40004800 @ (Universal synchronous asynchronous receiver  transmitter) 
    .equ USART2_STAT, USART2_BASE + 0x00 @ (Status register ) 
        .equ USART2_CTSF_Shift, 9   @ bitWidth 1 (CTS change flag)  
        .equ USART2_LBDF_Shift, 8   @ bitWidth 1 (LIN break detection flag)  
        .equ USART2_TBE_Shift, 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ USART2_TC_Shift, 6   @ bitWidth 1 (Transmission complete)  
        .equ USART2_RBNE_Shift, 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ USART2_IDLEF_Shift, 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ USART2_ORERR_Shift, 3   @ bitWidth 1 (Overrun error)  
        .equ USART2_NERR_Shift, 2   @ bitWidth 1 (Noise error flag)  
        .equ USART2_FERR_Shift, 1   @ bitWidth 1 (Frame error flag)  
        .equ USART2_PERR_Shift, 0   @ bitWidth 1 (Parity error flag)  
 
    .equ USART2_DATA, USART2_BASE + 0x04 @ (Data register) 
        .equ USART2_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ USART2_BAUD, USART2_BASE + 0x08 @ (Baud rate register) 
        .equ USART2_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ USART2_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ USART2_CTL0, USART2_BASE + 0x0C @ (Control register 0) 
        .equ USART2_UEN_Shift, 13   @ bitWidth 1 (USART enable)  
        .equ USART2_WL_Shift, 12   @ bitWidth 1 (Word length)  
        .equ USART2_WM_Shift, 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ USART2_PCEN_Shift, 10   @ bitWidth 1 (Parity check function enable)  
        .equ USART2_PM_Shift, 9   @ bitWidth 1 (Parity mode)  
        .equ USART2_PERRIE_Shift, 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ USART2_TBEIE_Shift, 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ USART2_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART2_RBNEIE_Shift, 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ USART2_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ USART2_TEN_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART2_REN_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ USART2_RWU_Shift, 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ USART2_SBKCMD_Shift, 0   @ bitWidth 1 (Send break command)  
 
    .equ USART2_CTL1, USART2_BASE + 0x10 @ (Control register 1) 
        .equ USART2_LMEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART2_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ USART2_CKEN_Shift, 11   @ bitWidth 1 (CK pin enable)  
        .equ USART2_CPL_Shift, 10   @ bitWidth 1 (Clock polarity)  
        .equ USART2_CPH_Shift, 9   @ bitWidth 1 (Clock phase)  
        .equ USART2_CLEN_Shift, 8   @ bitWidth 1 (CK Length)  
        .equ USART2_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ USART2_LBLEN_Shift, 5   @ bitWidth 1 (LIN break frame length)  
        .equ USART2_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ USART2_CTL2, USART2_BASE + 0x14 @ (Control register 2) 
        .equ USART2_CTSIE_Shift, 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART2_CTSEN_Shift, 9   @ bitWidth 1 (CTS enable)  
        .equ USART2_RTSEN_Shift, 8   @ bitWidth 1 (RTS enable)  
        .equ USART2_DENT_Shift, 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ USART2_DENR_Shift, 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ USART2_SCEN_Shift, 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART2_NKEN_Shift, 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART2_HDEN_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART2_IRLP_Shift, 2   @ bitWidth 1 (IrDA low-power)  
        .equ USART2_IREN_Shift, 1   @ bitWidth 1 (IrDA mode enable)  
        .equ USART2_ERRIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART2_GP, USART2_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ USART2_GUAT_Shift, 8   @ bitWidth 8 (Guard time value in Smartcard mode)  
        .equ USART2_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== UART3 ===========================@
.equ UART3_BASE, 0x40004C00 @ (Universal asynchronous receiver  transmitter) 
    .equ UART3_STAT, UART3_BASE + 0x00 @ (Status register ) 
        .equ UART3_LBDF_Shift, 8   @ bitWidth 1 (LIN break detection flag)  
        .equ UART3_TBE_Shift, 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ UART3_TC_Shift, 6   @ bitWidth 1 (Transmission complete)  
        .equ UART3_RBNE_Shift, 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ UART3_IDLEF_Shift, 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ UART3_ORERR_Shift, 3   @ bitWidth 1 (Overrun error)  
        .equ UART3_NERR_Shift, 2   @ bitWidth 1 (Noise error flag)  
        .equ UART3_FERR_Shift, 1   @ bitWidth 1 (Frame error flag)  
        .equ UART3_PERR_Shift, 0   @ bitWidth 1 (Parity error flag)  
 
    .equ UART3_DATA, UART3_BASE + 0x04 @ (Data register) 
        .equ UART3_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ UART3_BAUD, UART3_BASE + 0x08 @ (Baud rate register) 
        .equ UART3_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ UART3_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ UART3_CTL0, UART3_BASE + 0x0C @ (Control register 0) 
        .equ UART3_UEN_Shift, 13   @ bitWidth 1 (USART enable)  
        .equ UART3_WL_Shift, 12   @ bitWidth 1 (Word length)  
        .equ UART3_WM_Shift, 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ UART3_PCEN_Shift, 10   @ bitWidth 1 (Parity check function enable)  
        .equ UART3_PM_Shift, 9   @ bitWidth 1 (Parity mode)  
        .equ UART3_PERRIE_Shift, 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ UART3_TBEIE_Shift, 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ UART3_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ UART3_RBNEIE_Shift, 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ UART3_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ UART3_TEN_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ UART3_REN_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ UART3_RWU_Shift, 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ UART3_SBKCMD_Shift, 0   @ bitWidth 1 (Send break command)  
 
    .equ UART3_CTL1, UART3_BASE + 0x10 @ (Control register 1) 
        .equ UART3_LMEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ UART3_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ UART3_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ UART3_LBLEN_Shift, 5   @ bitWidth 1 (LIN break frame length)  
        .equ UART3_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ UART3_CTL2, UART3_BASE + 0x14 @ (Control register 2) 
        .equ UART3_DENT_Shift, 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ UART3_DENR_Shift, 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ UART3_HDEN_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ UART3_IRLP_Shift, 2   @ bitWidth 1 (IrDA low-power)  
        .equ UART3_IREN_Shift, 1   @ bitWidth 1 (IrDA mode enable)  
        .equ UART3_ERRIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ UART3_GP, UART3_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ UART3_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== UART4 ===========================@
.equ UART4_BASE, 0x40005000 @ (Universal asynchronous receiver  transmitter) 
    .equ UART4_STAT, UART4_BASE + 0x00 @ (Status register ) 
        .equ UART4_LBDF_Shift, 8   @ bitWidth 1 (LIN break detection flag)  
        .equ UART4_TBE_Shift, 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ UART4_TC_Shift, 6   @ bitWidth 1 (Transmission complete)  
        .equ UART4_RBNE_Shift, 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ UART4_IDLEF_Shift, 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ UART4_ORERR_Shift, 3   @ bitWidth 1 (Overrun error)  
        .equ UART4_NERR_Shift, 2   @ bitWidth 1 (Noise error flag)  
        .equ UART4_FERR_Shift, 1   @ bitWidth 1 (Frame error flag)  
        .equ UART4_PERR_Shift, 0   @ bitWidth 1 (Parity error flag)  
 
    .equ UART4_DATA, UART4_BASE + 0x04 @ (Data register) 
        .equ UART4_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ UART4_BAUD, UART4_BASE + 0x08 @ (Baud rate register) 
        .equ UART4_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ UART4_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ UART4_CTL0, UART4_BASE + 0x0C @ (Control register 0) 
        .equ UART4_UEN_Shift, 13   @ bitWidth 1 (USART enable)  
        .equ UART4_WL_Shift, 12   @ bitWidth 1 (Word length)  
        .equ UART4_WM_Shift, 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ UART4_PCEN_Shift, 10   @ bitWidth 1 (Parity check function enable)  
        .equ UART4_PM_Shift, 9   @ bitWidth 1 (Parity mode)  
        .equ UART4_PERRIE_Shift, 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ UART4_TBEIE_Shift, 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ UART4_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ UART4_RBNEIE_Shift, 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ UART4_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ UART4_TEN_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ UART4_REN_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ UART4_RWU_Shift, 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ UART4_SBKCMD_Shift, 0   @ bitWidth 1 (Send break command)  
 
    .equ UART4_CTL1, UART4_BASE + 0x10 @ (Control register 1) 
        .equ UART4_LMEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ UART4_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ UART4_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ UART4_LBLEN_Shift, 5   @ bitWidth 1 (LIN break frame length)  
        .equ UART4_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ UART4_CTL2, UART4_BASE + 0x14 @ (Control register 2) 
        .equ UART4_DENT_Shift, 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ UART4_DENR_Shift, 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ UART4_HDEN_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ UART4_IRLP_Shift, 2   @ bitWidth 1 (IrDA low-power)  
        .equ UART4_IREN_Shift, 1   @ bitWidth 1 (IrDA mode enable)  
        .equ UART4_ERRIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ UART4_GP, UART4_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ UART4_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== USBFS_GLOBAL ===========================@
.equ USBFS_GLOBAL_BASE, 0x50000000 @ (USB full speed global registers) 
    .equ USBFS_GLOBAL_GOTGCS, USBFS_GLOBAL_BASE + 0x0 @ (Global OTG control and status register   USBFS_GOTGCS) 
        .equ USBFS_GLOBAL_SRPS_Shift, 0   @ bitWidth 1 (SRP success)  
        .equ USBFS_GLOBAL_SRPREQ_Shift, 1   @ bitWidth 1 (SRP request)  
        .equ USBFS_GLOBAL_HNPS_Shift, 8   @ bitWidth 1 (Host success)  
        .equ USBFS_GLOBAL_HNPREQ_Shift, 9   @ bitWidth 1 (HNP request)  
        .equ USBFS_GLOBAL_HHNPEN_Shift, 10   @ bitWidth 1 (Host HNP enable)  
        .equ USBFS_GLOBAL_DHNPEN_Shift, 11   @ bitWidth 1 (Device HNP enabled)  
        .equ USBFS_GLOBAL_IDPS_Shift, 16   @ bitWidth 1 (ID pin status)  
        .equ USBFS_GLOBAL_DI_Shift, 17   @ bitWidth 1 (Debounce interval)  
        .equ USBFS_GLOBAL_ASV_Shift, 18   @ bitWidth 1 (A-session valid)  
        .equ USBFS_GLOBAL_BSV_Shift, 19   @ bitWidth 1 (B-session valid)  
 
    .equ USBFS_GLOBAL_GOTGINTF, USBFS_GLOBAL_BASE + 0x04 @ (Global OTG interrupt flag register  USBFS_GOTGINTF) 
        .equ USBFS_GLOBAL_SESEND_Shift, 2   @ bitWidth 1 (Session end )  
        .equ USBFS_GLOBAL_SRPEND_Shift, 8   @ bitWidth 1 (Session request success status  change)  
        .equ USBFS_GLOBAL_HNPEND_Shift, 9   @ bitWidth 1 (HNP end)  
        .equ USBFS_GLOBAL_HNPDET_Shift, 17   @ bitWidth 1 (Host negotiation request detected)  
        .equ USBFS_GLOBAL_ADTO_Shift, 18   @ bitWidth 1 (A-device timeout)  
        .equ USBFS_GLOBAL_DF_Shift, 19   @ bitWidth 1 (Debounce finish)  
 
    .equ USBFS_GLOBAL_GAHBCS, USBFS_GLOBAL_BASE + 0x08 @ (Global AHB control and status register  USBFS_GAHBCS) 
        .equ USBFS_GLOBAL_GINTEN_Shift, 0   @ bitWidth 1 (Global interrupt enable)  
        .equ USBFS_GLOBAL_TXFTH_Shift, 7   @ bitWidth 1 (Tx FIFO threshold)  
        .equ USBFS_GLOBAL_PTXFTH_Shift, 8   @ bitWidth 1 (Periodic Tx FIFO threshold)  
 
    .equ USBFS_GLOBAL_GUSBCS, USBFS_GLOBAL_BASE + 0x0C @ (Global USB control and status register  USBFS_GUSBCSR) 
        .equ USBFS_GLOBAL_TOC_Shift, 0   @ bitWidth 3 (Timeout calibration)  
        .equ USBFS_GLOBAL_SRPCEN_Shift, 8   @ bitWidth 1 (SRP capability enable)  
        .equ USBFS_GLOBAL_HNPCEN_Shift, 9   @ bitWidth 1 (HNP capability enable)  
        .equ USBFS_GLOBAL_UTT_Shift, 10   @ bitWidth 4 (USB turnaround time)  
        .equ USBFS_GLOBAL_FHM_Shift, 29   @ bitWidth 1 (Force host mode)  
        .equ USBFS_GLOBAL_FDM_Shift, 30   @ bitWidth 1 (Force device mode)  
 
    .equ USBFS_GLOBAL_GRSTCTL, USBFS_GLOBAL_BASE + 0x10 @ (Global reset control register USBFS_GRSTCTL) 
        .equ USBFS_GLOBAL_CSRST_Shift, 0   @ bitWidth 1 (Core soft reset)  
        .equ USBFS_GLOBAL_HCSRST_Shift, 1   @ bitWidth 1 (HCLK soft reset)  
        .equ USBFS_GLOBAL_HFCRST_Shift, 2   @ bitWidth 1 (Host frame counter reset)  
        .equ USBFS_GLOBAL_RXFF_Shift, 4   @ bitWidth 1 (RxFIFO flush)  
        .equ USBFS_GLOBAL_TXFF_Shift, 5   @ bitWidth 1 (TxFIFO flush)  
        .equ USBFS_GLOBAL_TXFNUM_Shift, 6   @ bitWidth 5 (TxFIFO number)  
 
    .equ USBFS_GLOBAL_GINTF, USBFS_GLOBAL_BASE + 0x14 @ (Global interrupt flag register USBFS_GINTF) 
        .equ USBFS_GLOBAL_COPM_Shift, 0   @ bitWidth 1 (Current operation mode)  
        .equ USBFS_GLOBAL_MFIF_Shift, 1   @ bitWidth 1 (Mode fault interrupt flag)  
        .equ USBFS_GLOBAL_OTGIF_Shift, 2   @ bitWidth 1 (OTG interrupt flag)  
        .equ USBFS_GLOBAL_SOF_Shift, 3   @ bitWidth 1 (Start of frame)  
        .equ USBFS_GLOBAL_RXFNEIF_Shift, 4   @ bitWidth 1 (RxFIFO non-empty interrupt flag)  
        .equ USBFS_GLOBAL_NPTXFEIF_Shift, 5   @ bitWidth 1 (Non-periodic TxFIFO empty interrupt flag)  
        .equ USBFS_GLOBAL_GNPINAK_Shift, 6   @ bitWidth 1 (Global Non-Periodic IN NAK effective)  
        .equ USBFS_GLOBAL_GONAK_Shift, 7   @ bitWidth 1 (Global OUT NAK effective)  
        .equ USBFS_GLOBAL_ESP_Shift, 10   @ bitWidth 1 (Early suspend)  
        .equ USBFS_GLOBAL_SP_Shift, 11   @ bitWidth 1 (USB suspend)  
        .equ USBFS_GLOBAL_RST_Shift, 12   @ bitWidth 1 (USB reset)  
        .equ USBFS_GLOBAL_ENUMF_Shift, 13   @ bitWidth 1 (Enumeration finished)  
        .equ USBFS_GLOBAL_ISOOPDIF_Shift, 14   @ bitWidth 1 (Isochronous OUT packet dropped  interrupt)  
        .equ USBFS_GLOBAL_EOPFIF_Shift, 15   @ bitWidth 1 (End of periodic frame  interrupt flag)  
        .equ USBFS_GLOBAL_IEPIF_Shift, 18   @ bitWidth 1 (IN endpoint interrupt flag)  
        .equ USBFS_GLOBAL_OEPIF_Shift, 19   @ bitWidth 1 (OUT endpoint interrupt flag)  
        .equ USBFS_GLOBAL_ISOINCIF_Shift, 20   @ bitWidth 1 (Isochronous IN transfer Not Complete Interrupt Flag)  
        .equ USBFS_GLOBAL_PXNCIF_ISOONCIF_Shift, 21   @ bitWidth 1 (periodic transfer not complete interrupt flagHost  mode/isochronous OUT transfer not complete interrupt flagDevice  mode)  
        .equ USBFS_GLOBAL_HPIF_Shift, 24   @ bitWidth 1 (Host port interrupt flag)  
        .equ USBFS_GLOBAL_HCIF_Shift, 25   @ bitWidth 1 (Host channels interrupt flag)  
        .equ USBFS_GLOBAL_PTXFEIF_Shift, 26   @ bitWidth 1 (Periodic TxFIFO empty interrupt flag)  
        .equ USBFS_GLOBAL_IDPSC_Shift, 28   @ bitWidth 1 (ID pin status change)  
        .equ USBFS_GLOBAL_DISCIF_Shift, 29   @ bitWidth 1 (Disconnect interrupt flag)  
        .equ USBFS_GLOBAL_SESIF_Shift, 30   @ bitWidth 1 (Session interrupt flag)  
        .equ USBFS_GLOBAL_WKUPIF_Shift, 31   @ bitWidth 1 (Wakeup interrupt flag)  
 
    .equ USBFS_GLOBAL_GINTEN, USBFS_GLOBAL_BASE + 0x18 @ (Global interrupt enable register  USBFS_GINTEN) 
        .equ USBFS_GLOBAL_MFIE_Shift, 1   @ bitWidth 1 (Mode fault interrupt  enable)  
        .equ USBFS_GLOBAL_OTGIE_Shift, 2   @ bitWidth 1 (OTG interrupt enable )  
        .equ USBFS_GLOBAL_SOFIE_Shift, 3   @ bitWidth 1 (Start of frame interrupt enable)  
        .equ USBFS_GLOBAL_RXFNEIE_Shift, 4   @ bitWidth 1 (Receive FIFO non-empty  interrupt enable)  
        .equ USBFS_GLOBAL_NPTXFEIE_Shift, 5   @ bitWidth 1 (Non-periodic TxFIFO empty  interrupt enable)  
        .equ USBFS_GLOBAL_GNPINAKIE_Shift, 6   @ bitWidth 1 (Global non-periodic IN NAK effective interrupt enable)  
        .equ USBFS_GLOBAL_GONAKIE_Shift, 7   @ bitWidth 1 (Global OUT NAK effective  interrupt enable)  
        .equ USBFS_GLOBAL_ESPIE_Shift, 10   @ bitWidth 1 (Early suspend interrupt enable)  
        .equ USBFS_GLOBAL_SPIE_Shift, 11   @ bitWidth 1 (USB suspend interrupt enable)  
        .equ USBFS_GLOBAL_RSTIE_Shift, 12   @ bitWidth 1 (USB reset interrupt enable)  
        .equ USBFS_GLOBAL_ENUMFIE_Shift, 13   @ bitWidth 1 (Enumeration finish interrupt enable)  
        .equ USBFS_GLOBAL_ISOOPDIE_Shift, 14   @ bitWidth 1 (Isochronous OUT packet dropped interrupt enable)  
        .equ USBFS_GLOBAL_EOPFIE_Shift, 15   @ bitWidth 1 (End of periodic frame interrupt enable)  
        .equ USBFS_GLOBAL_IEPIE_Shift, 18   @ bitWidth 1 (IN endpoints interrupt enable)  
        .equ USBFS_GLOBAL_OEPIE_Shift, 19   @ bitWidth 1 (OUT endpoints interrupt enable)  
        .equ USBFS_GLOBAL_ISOINCIE_Shift, 20   @ bitWidth 1 (isochronous IN transfer not complete  interrupt enable)  
        .equ USBFS_GLOBAL_PXNCIE_ISOONCIE_Shift, 21   @ bitWidth 1 (periodic transfer not compelete Interrupt enableHost  mode/isochronous OUT transfer not complete interrupt enableDevice  mode)  
        .equ USBFS_GLOBAL_HPIE_Shift, 24   @ bitWidth 1 (Host port interrupt enable)  
        .equ USBFS_GLOBAL_HCIE_Shift, 25   @ bitWidth 1 (Host channels interrupt enable)  
        .equ USBFS_GLOBAL_PTXFEIE_Shift, 26   @ bitWidth 1 (Periodic TxFIFO empty interrupt enable)  
        .equ USBFS_GLOBAL_IDPSCIE_Shift, 28   @ bitWidth 1 (ID pin status change interrupt enable)  
        .equ USBFS_GLOBAL_DISCIE_Shift, 29   @ bitWidth 1 (Disconnect interrupt enable)  
        .equ USBFS_GLOBAL_SESIE_Shift, 30   @ bitWidth 1 (Session interrupt enable)  
        .equ USBFS_GLOBAL_WKUPIE_Shift, 31   @ bitWidth 1 (Wakeup interrupt enable)  
 
    .equ USBFS_GLOBAL_GRSTATR_Device, USBFS_GLOBAL_BASE + 0x1C @ (Global Receive status readDevice  mode) 
        .equ USBFS_GLOBAL_EPNUM_Shift, 0   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_GLOBAL_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_RPCKST_Shift, 17   @ bitWidth 4 (Recieve packet status)  
 
    .equ USBFS_GLOBAL_GRSTATR_Host, USBFS_GLOBAL_BASE + 0x1C @ (Global Receive status readHost  mode) 
        .equ USBFS_GLOBAL_CNUM_Shift, 0   @ bitWidth 4 (Channel number)  
        .equ USBFS_GLOBAL_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_RPCKST_Shift, 17   @ bitWidth 4 (Reivece packet status)  
 
    .equ USBFS_GLOBAL_GRSTATP_Device, USBFS_GLOBAL_BASE + 0x20 @ (Global Receive status popDevice  mode) 
        .equ USBFS_GLOBAL_EPNUM_Shift, 0   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_GLOBAL_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_RPCKST_Shift, 17   @ bitWidth 4 (Recieve packet status)  
 
    .equ USBFS_GLOBAL_GRSTATP_Host, USBFS_GLOBAL_BASE + 0x20 @ (Global Receive status popHost  mode) 
        .equ USBFS_GLOBAL_CNUM_Shift, 0   @ bitWidth 4 (Channel number)  
        .equ USBFS_GLOBAL_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_RPCKST_Shift, 17   @ bitWidth 4 (Reivece packet status)  
 
    .equ USBFS_GLOBAL_GRFLEN, USBFS_GLOBAL_BASE + 0x24 @ (Global Receive FIFO size register  USBFS_GRFLEN) 
        .equ USBFS_GLOBAL_RXFD_Shift, 0   @ bitWidth 16 (Rx FIFO depth)  
 
    .equ USBFS_GLOBAL_HNPTFLEN, USBFS_GLOBAL_BASE + 0x28 @ (Host non-periodic transmit FIFO length register  Host mode) 
        .equ USBFS_GLOBAL_HNPTXRSAR_Shift, 0   @ bitWidth 16 (host non-periodic transmit Tx RAM start  address)  
        .equ USBFS_GLOBAL_HNPTXFD_Shift, 16   @ bitWidth 16 (host non-periodic TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP0TFLEN, USBFS_GLOBAL_BASE + 0x28 @ (Device IN endpoint 0 transmit FIFO length  Device mode) 
        .equ USBFS_GLOBAL_IEP0TXFD_Shift, 16   @ bitWidth 16 (in endpoint 0 Tx FIFO depth)  
        .equ USBFS_GLOBAL_IEP0TXRSAR_Shift, 0   @ bitWidth 16 (in endpoint 0 Tx RAM start address)  
 
    .equ USBFS_GLOBAL_HNPTFQSTAT, USBFS_GLOBAL_BASE + 0x2C @ (Host non-periodic transmit FIFO/queue  status register HNPTFQSTAT) 
        .equ USBFS_GLOBAL_NPTXFS_Shift, 0   @ bitWidth 16 (Non-periodic TxFIFO space)  
        .equ USBFS_GLOBAL_NPTXRQS_Shift, 16   @ bitWidth 8 (Non-periodic transmit request queue  space )  
        .equ USBFS_GLOBAL_NPTXRQTOP_Shift, 24   @ bitWidth 7 (Top of the non-periodic transmit request  queue)  
 
    .equ USBFS_GLOBAL_GCCFG, USBFS_GLOBAL_BASE + 0x38 @ (Global core configuration register USBFS_GCCFG) 
        .equ USBFS_GLOBAL_PWRON_Shift, 16   @ bitWidth 1 (Power on)  
        .equ USBFS_GLOBAL_VBUSACEN_Shift, 18   @ bitWidth 1 (The VBUS A-device Comparer enable)  
        .equ USBFS_GLOBAL_VBUSBCEN_Shift, 19   @ bitWidth 1 (The VBUS B-device Comparer enable)  
        .equ USBFS_GLOBAL_SOFOEN_Shift, 20   @ bitWidth 1 (SOF output enable)  
        .equ USBFS_GLOBAL_VBUSIG_Shift, 21   @ bitWidth 1 (VBUS ignored)  
 
    .equ USBFS_GLOBAL_CID, USBFS_GLOBAL_BASE + 0x3C @ (core ID register) 
        .equ USBFS_GLOBAL_CID_Shift, 0   @ bitWidth 32 (Core ID)  
 
    .equ USBFS_GLOBAL_HPTFLEN, USBFS_GLOBAL_BASE + 0x100 @ (Host periodic transmit FIFO length register HPTFLEN) 
        .equ USBFS_GLOBAL_HPTXFSAR_Shift, 0   @ bitWidth 16 (Host periodic TxFIFO start  address)  
        .equ USBFS_GLOBAL_HPTXFD_Shift, 16   @ bitWidth 16 (Host periodic TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP1TFLEN, USBFS_GLOBAL_BASE + 0x104 @ (device IN endpoint transmit FIFO size  register DIEP1TFLEN) 
        .equ USBFS_GLOBAL_IEPTXRSAR_Shift, 0   @ bitWidth 16 (IN endpoint FIFO transmit RAM start  address)  
        .equ USBFS_GLOBAL_IEPTXFD_Shift, 16   @ bitWidth 16 (IN endpoint TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP2TFLEN, USBFS_GLOBAL_BASE + 0x108 @ (device IN endpoint transmit FIFO size  register DIEP2TFLEN) 
        .equ USBFS_GLOBAL_IEPTXRSAR_Shift, 0   @ bitWidth 16 (IN endpoint FIFO transmit RAM start  address)  
        .equ USBFS_GLOBAL_IEPTXFD_Shift, 16   @ bitWidth 16 (IN endpoint TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP3TFLEN, USBFS_GLOBAL_BASE + 0x10C @ (device IN endpoint transmit FIFO size  register FS_DIEP3TXFLEN) 
        .equ USBFS_GLOBAL_IEPTXRSAR_Shift, 0   @ bitWidth 16 (IN endpoint FIFO4 transmit RAM start  address)  
        .equ USBFS_GLOBAL_IEPTXFD_Shift, 16   @ bitWidth 16 (IN endpoint TxFIFO depth)  
 

@=========================== USBFS_HOST ===========================@
.equ USBFS_HOST_BASE, 0x50000400 @ (USB on the go full speed host) 
    .equ USBFS_HOST_HCTL, USBFS_HOST_BASE + 0x00 @ (host configuration register  HCTL) 
        .equ USBFS_HOST_CLKSEL_Shift, 0   @ bitWidth 2 (clock select for USB clock)  
 
    .equ USBFS_HOST_HFT, USBFS_HOST_BASE + 0x04 @ (Host frame interval  register) 
        .equ USBFS_HOST_FRI_Shift, 0   @ bitWidth 16 (Frame interval)  
 
    .equ USBFS_HOST_HFINFR, USBFS_HOST_BASE + 0x08 @ (FS host frame number/frame time  remaining register HFINFR) 
        .equ USBFS_HOST_FRNUM_Shift, 0   @ bitWidth 16 (Frame number)  
        .equ USBFS_HOST_FRT_Shift, 16   @ bitWidth 16 (Frame remaining time)  
 
    .equ USBFS_HOST_HPTFQSTAT, USBFS_HOST_BASE + 0x10 @ (Host periodic transmit FIFO/queue  status register HPTFQSTAT) 
        .equ USBFS_HOST_PTXFS_Shift, 0   @ bitWidth 16 (Periodic transmit data FIFO space  available)  
        .equ USBFS_HOST_PTXREQS_Shift, 16   @ bitWidth 8 (Periodic transmit request queue space  available)  
        .equ USBFS_HOST_PTXREQT_Shift, 24   @ bitWidth 8 (Top of the periodic transmit request  queue)  
 
    .equ USBFS_HOST_HACHINT, USBFS_HOST_BASE + 0x14 @ ( Host all channels interrupt  register) 
        .equ USBFS_HOST_HACHINT_Shift, 0   @ bitWidth 8 (Host all channel interrupts)  
 
    .equ USBFS_HOST_HACHINTEN, USBFS_HOST_BASE + 0x18 @ (host all channels interrupt mask  register) 
        .equ USBFS_HOST_CINTEN_Shift, 0   @ bitWidth 8 (Channel interrupt enable)  
 
    .equ USBFS_HOST_HPCS, USBFS_HOST_BASE + 0x40 @ (Host port control and status register USBFS_HPCS) 
        .equ USBFS_HOST_PCST_Shift, 0   @ bitWidth 1 (Port connect status)  
        .equ USBFS_HOST_PCD_Shift, 1   @ bitWidth 1 (Port connect detected)  
        .equ USBFS_HOST_PE_Shift, 2   @ bitWidth 1 (Port enable)  
        .equ USBFS_HOST_PEDC_Shift, 3   @ bitWidth 1 (Port enable/disable change)  
        .equ USBFS_HOST_PREM_Shift, 6   @ bitWidth 1 (Port resume)  
        .equ USBFS_HOST_PSP_Shift, 7   @ bitWidth 1 (Port suspend)  
        .equ USBFS_HOST_PRST_Shift, 8   @ bitWidth 1 (Port reset)  
        .equ USBFS_HOST_PLST_Shift, 10   @ bitWidth 2 (Port line status)  
        .equ USBFS_HOST_PP_Shift, 12   @ bitWidth 1 (Port power)  
        .equ USBFS_HOST_PS_Shift, 17   @ bitWidth 2 (Port speed)  
 
    .equ USBFS_HOST_HCH0CTL, USBFS_HOST_BASE + 0x100 @ (host channel-0 characteristics  register HCH0CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH1CTL, USBFS_HOST_BASE + 0x120 @ ( host channel-1 characteristics  register HCH1CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH2CTL, USBFS_HOST_BASE + 0x140 @ (host channel-2 characteristics  register HCH2CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH3CTL, USBFS_HOST_BASE + 0x160 @ (host channel-3 characteristics  register HCH3CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH4CTL, USBFS_HOST_BASE + 0x180 @ ( host channel-4 characteristics  register HCH4CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH5CTL, USBFS_HOST_BASE + 0x1A0 @ (host channel-5 characteristics  register HCH5CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH6CTL, USBFS_HOST_BASE + 0x1C0 @ (host channel-6 characteristics  register HCH6CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH7CTL, USBFS_HOST_BASE + 0x1E0 @ (host channel-7 characteristics  register HCH7CTL) 
        .equ USBFS_HOST_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_EPDIR_Shift, 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_LSD_Shift, 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_ODDFRM_Shift, 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_CDIS_Shift, 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_CEN_Shift, 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH0INTF, USBFS_HOST_BASE + 0x108 @ (host channel-0 interrupt register  USBFS_HCHxINTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH1INTF, USBFS_HOST_BASE + 0x128 @ (host channel-1 interrupt register  HCH1INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH2INTF, USBFS_HOST_BASE + 0x148 @ (host channel-2 interrupt register  HCH2INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH3INTF, USBFS_HOST_BASE + 0x168 @ (host channel-3 interrupt register  HCH3INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH4INTF, USBFS_HOST_BASE + 0x188 @ (host channel-4 interrupt register  HCH4INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH5INTF, USBFS_HOST_BASE + 0x1A8 @ (host channel-5 interrupt register  HCH5INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH6INTF, USBFS_HOST_BASE + 0x1C8 @ (host channel-6 interrupt register  HCH6INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH7INTF, USBFS_HOST_BASE + 0x1E8 @ (host channel-7 interrupt register  HCH7INTF) 
        .equ USBFS_HOST_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_CH_Shift, 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_STALL_Shift, 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_NAK_Shift, 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_ACK_Shift, 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_USBER_Shift, 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_BBER_Shift, 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_REQOVR_Shift, 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_DTER_Shift, 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH0INTEN, USBFS_HOST_BASE + 0x10C @ (host channel-0 interrupt enable register  HCH0INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH1INTEN, USBFS_HOST_BASE + 0x12C @ (host channel-1 interrupt enable register  HCH1INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH2INTEN, USBFS_HOST_BASE + 0x14C @ (host channel-2 interrupt enable register  HCH2INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH3INTEN, USBFS_HOST_BASE + 0x16C @ (host channel-3 interrupt enable register  HCH3INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH4INTEN, USBFS_HOST_BASE + 0x18C @ (host channel-4 interrupt enable register  HCH4INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH5INTEN, USBFS_HOST_BASE + 0x1AC @ (host channel-5 interrupt enable register  HCH5INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH6INTEN, USBFS_HOST_BASE + 0x1CC @ (host channel-6 interrupt enable register  HCH6INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH7INTEN, USBFS_HOST_BASE + 0x1EC @ (host channel-7 interrupt enable register  HCH7INTEN) 
        .equ USBFS_HOST_TFIE_Shift, 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_CHIE_Shift, 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_STALLIE_Shift, 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_NAKIE_Shift, 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_ACKIE_Shift, 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_USBERIE_Shift, 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_BBERIE_Shift, 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_REQOVRIE_Shift, 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_DTERIE_Shift, 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH0LEN, USBFS_HOST_BASE + 0x110 @ (host channel-0 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH1LEN, USBFS_HOST_BASE + 0x130 @ (host channel-1 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH2LEN, USBFS_HOST_BASE + 0x150 @ ( host channel-2 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH3LEN, USBFS_HOST_BASE + 0x170 @ ( host channel-3 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH4LEN, USBFS_HOST_BASE + 0x190 @ (host channel-4 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH5LEN, USBFS_HOST_BASE + 0x1B0 @ (host channel-5 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH6LEN, USBFS_HOST_BASE + 0x1D0 @ (host channel-6 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH7LEN, USBFS_HOST_BASE + 0x1F0 @ (host channel-7 transfer length  register) 
        .equ USBFS_HOST_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 

@=========================== USBFS_DEVICE ===========================@
.equ USBFS_DEVICE_BASE, 0x50000800 @ (USB on the go full speed device) 
    .equ USBFS_DEVICE_DCFG, USBFS_DEVICE_BASE + 0x0 @ (device configuration register  DCFG) 
        .equ USBFS_DEVICE_DS_Shift, 0   @ bitWidth 2 (Device speed)  
        .equ USBFS_DEVICE_NZLSOH_Shift, 2   @ bitWidth 1 (Non-zero-length status OUT  handshake)  
        .equ USBFS_DEVICE_DAR_Shift, 4   @ bitWidth 7 (Device address)  
        .equ USBFS_DEVICE_EOPFT_Shift, 11   @ bitWidth 2 (end of periodic frame time)  
 
    .equ USBFS_DEVICE_DCTL, USBFS_DEVICE_BASE + 0x04 @ (device control register  DCTL) 
        .equ USBFS_DEVICE_RWKUP_Shift, 0   @ bitWidth 1 (Remote wakeup)  
        .equ USBFS_DEVICE_SD_Shift, 1   @ bitWidth 1 (Soft disconnect)  
        .equ USBFS_DEVICE_GINS_Shift, 2   @ bitWidth 1 (Global IN NAK status)  
        .equ USBFS_DEVICE_GONS_Shift, 3   @ bitWidth 1 (Global OUT NAK status)  
        .equ USBFS_DEVICE_SGINAK_Shift, 7   @ bitWidth 1 (Set global IN NAK)  
        .equ USBFS_DEVICE_CGINAK_Shift, 8   @ bitWidth 1 (Clear global IN NAK)  
        .equ USBFS_DEVICE_SGONAK_Shift, 9   @ bitWidth 1 (Set global OUT NAK)  
        .equ USBFS_DEVICE_CGONAK_Shift, 10   @ bitWidth 1 (Clear global OUT NAK)  
        .equ USBFS_DEVICE_POIF_Shift, 11   @ bitWidth 1 (Power-on initialization flag)  
 
    .equ USBFS_DEVICE_DSTAT, USBFS_DEVICE_BASE + 0x08 @ (device status register  DSTAT) 
        .equ USBFS_DEVICE_SPST_Shift, 0   @ bitWidth 1 (Suspend status)  
        .equ USBFS_DEVICE_ES_Shift, 1   @ bitWidth 2 (Enumerated speed)  
        .equ USBFS_DEVICE_FNRSOF_Shift, 8   @ bitWidth 14 (Frame number of the received  SOF)  
 
    .equ USBFS_DEVICE_DIEPINTEN, USBFS_DEVICE_BASE + 0x10 @ (device IN endpoint common interrupt  mask register DIEPINTEN) 
        .equ USBFS_DEVICE_TFEN_Shift, 0   @ bitWidth 1 (Transfer finished interrupt  enable)  
        .equ USBFS_DEVICE_EPDISEN_Shift, 1   @ bitWidth 1 (Endpoint disabled interrupt  enable)  
        .equ USBFS_DEVICE_CITOEN_Shift, 3   @ bitWidth 1 (Control IN timeout condition interrupt enable Non-isochronous  endpoints)  
        .equ USBFS_DEVICE_EPTXFUDEN_Shift, 4   @ bitWidth 1 (Endpoint Tx FIFO underrun interrupt enable bit)  
        .equ USBFS_DEVICE_IEPNEEN_Shift, 6   @ bitWidth 1 (IN endpoint NAK effective  interrupt enable)  
 
    .equ USBFS_DEVICE_DOEPINTEN, USBFS_DEVICE_BASE + 0x14 @ (device OUT endpoint common interrupt  enable register DOEPINTEN) 
        .equ USBFS_DEVICE_TFEN_Shift, 0   @ bitWidth 1 (Transfer finished interrupt  enable)  
        .equ USBFS_DEVICE_EPDISEN_Shift, 1   @ bitWidth 1 (Endpoint disabled interrupt  enable)  
        .equ USBFS_DEVICE_STPFEN_Shift, 3   @ bitWidth 1 (SETUP phase finished interrupt enable)  
        .equ USBFS_DEVICE_EPRXFOVREN_Shift, 4   @ bitWidth 1 ( Endpoint Rx FIFO overrun interrupt enable)  
        .equ USBFS_DEVICE_BTBSTPEN_Shift, 6   @ bitWidth 1 ( Back-to-back SETUP packets  interrupt enable)  
 
    .equ USBFS_DEVICE_DAEPINT, USBFS_DEVICE_BASE + 0x18 @ (device all endpoints interrupt  register DAEPINT) 
        .equ USBFS_DEVICE_IEPITB_Shift, 0   @ bitWidth 4 (Device all IN endpoint interrupt bits)  
        .equ USBFS_DEVICE_OEPITB_Shift, 16   @ bitWidth 4 (Device all OUT endpoint interrupt bits)  
 
    .equ USBFS_DEVICE_DAEPINTEN, USBFS_DEVICE_BASE + 0x1C @ (Device all endpoints interrupt enable register  DAEPINTEN) 
        .equ USBFS_DEVICE_IEPIE_Shift, 0   @ bitWidth 4 (IN EP interrupt interrupt enable bits)  
        .equ USBFS_DEVICE_OEPIE_Shift, 16   @ bitWidth 4 (OUT endpoint interrupt enable bits)  
 
    .equ USBFS_DEVICE_DVBUSDT, USBFS_DEVICE_BASE + 0x28 @ (device VBUS discharge time  register) 
        .equ USBFS_DEVICE_DVBUSDT_Shift, 0   @ bitWidth 16 (Device VBUS discharge time)  
 
    .equ USBFS_DEVICE_DVBUSPT, USBFS_DEVICE_BASE + 0x2C @ (device VBUS pulsing time  register) 
        .equ USBFS_DEVICE_DVBUSPT_Shift, 0   @ bitWidth 12 (Device VBUS pulsing time)  
 
    .equ USBFS_DEVICE_DIEPFEINTEN, USBFS_DEVICE_BASE + 0x34 @ (device IN endpoint FIFO empty  interrupt enable register) 
        .equ USBFS_DEVICE_IEPTXFEIE_Shift, 0   @ bitWidth 4 (IN EP Tx FIFO empty interrupt enable  bits)  
 
    .equ USBFS_DEVICE_DIEP0CTL, USBFS_DEVICE_BASE + 0x100 @ (device IN endpoint 0 control  register DIEP0CTL) 
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 2 (Maximum packet length)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (endpoint active)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_TXFNUM_Shift, 22   @ bitWidth 4 (TxFIFO number)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
 
    .equ USBFS_DEVICE_DIEP1CTL, USBFS_DEVICE_BASE + 0x120 @ (device in endpoint-1 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SD1PID_SODDFRM_Shift, 29   @ bitWidth 1 (Set DATA1 PID/Set odd frame)  
        .equ USBFS_DEVICE_SD0PID_SEVENFRM_Shift, 28   @ bitWidth 1 (SD0PID/SEVNFRM)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_TXFNUM_Shift, 22   @ bitWidth 4 (Tx FIFO number)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EOFRM_DPID_Shift, 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DIEP2CTL, USBFS_DEVICE_BASE + 0x140 @ (device endpoint-2 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SD1PID_SODDFRM_Shift, 29   @ bitWidth 1 (Set DATA1 PID/Set odd frame)  
        .equ USBFS_DEVICE_SD0PID_SEVENFRM_Shift, 28   @ bitWidth 1 (SD0PID/SEVNFRM)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_TXFNUM_Shift, 22   @ bitWidth 4 (Tx FIFO number)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EOFRM_DPID_Shift, 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DIEP3CTL, USBFS_DEVICE_BASE + 0x160 @ (device endpoint-3 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SD1PID_SODDFRM_Shift, 29   @ bitWidth 1 (Set DATA1 PID/Set odd frame)  
        .equ USBFS_DEVICE_SD0PID_SEVENFRM_Shift, 28   @ bitWidth 1 (SD0PID/SEVNFRM)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_TXFNUM_Shift, 22   @ bitWidth 4 (Tx FIFO number)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EOFRM_DPID_Shift, 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP0CTL, USBFS_DEVICE_BASE + 0x300 @ (device endpoint-0 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_SNOOP_Shift, 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 2 (Maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP1CTL, USBFS_DEVICE_BASE + 0x320 @ (device endpoint-1 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SD1PID_SODDFRM_Shift, 29   @ bitWidth 1 (SD1PID/SODDFRM)  
        .equ USBFS_DEVICE_SD0PID_SEVENFRM_Shift, 28   @ bitWidth 1 (SD0PID/SEVENFRM)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_SNOOP_Shift, 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EOFRM_DPID_Shift, 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP2CTL, USBFS_DEVICE_BASE + 0x340 @ (device endpoint-2 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SD1PID_SODDFRM_Shift, 29   @ bitWidth 1 (SD1PID/SODDFRM)  
        .equ USBFS_DEVICE_SD0PID_SEVENFRM_Shift, 28   @ bitWidth 1 (SD0PID/SEVENFRM)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_SNOOP_Shift, 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EOFRM_DPID_Shift, 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP3CTL, USBFS_DEVICE_BASE + 0x360 @ (device endpoint-3 control  register) 
        .equ USBFS_DEVICE_EPEN_Shift, 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_EPD_Shift, 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_SD1PID_SODDFRM_Shift, 29   @ bitWidth 1 (SD1PID/SODDFRM)  
        .equ USBFS_DEVICE_SD0PID_SEVENFRM_Shift, 28   @ bitWidth 1 (SD0PID/SEVENFRM)  
        .equ USBFS_DEVICE_SNAK_Shift, 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_CNAK_Shift, 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_STALL_Shift, 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_SNOOP_Shift, 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_NAKS_Shift, 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_EOFRM_DPID_Shift, 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_EPACT_Shift, 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DIEP0INTF, USBFS_DEVICE_BASE + 0x108 @ (device endpoint-0 interrupt  register) 
        .equ USBFS_DEVICE_TXFE_Shift, 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_IEPNE_Shift, 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_EPTXFUD_Shift, 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_CITO_Shift, 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP1INTF, USBFS_DEVICE_BASE + 0x128 @ (device endpoint-1 interrupt  register) 
        .equ USBFS_DEVICE_TXFE_Shift, 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_IEPNE_Shift, 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_EPTXFUD_Shift, 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_CITO_Shift, 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP2INTF, USBFS_DEVICE_BASE + 0x148 @ (device endpoint-2 interrupt  register) 
        .equ USBFS_DEVICE_TXFE_Shift, 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_IEPNE_Shift, 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_EPTXFUD_Shift, 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_CITO_Shift, 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP3INTF, USBFS_DEVICE_BASE + 0x168 @ (device endpoint-3 interrupt  register) 
        .equ USBFS_DEVICE_TXFE_Shift, 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_IEPNE_Shift, 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_EPTXFUD_Shift, 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_CITO_Shift, 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP0INTF, USBFS_DEVICE_BASE + 0x308 @ (device out endpoint-0 interrupt flag   register) 
        .equ USBFS_DEVICE_BTBSTP_Shift, 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_EPRXFOVR_Shift, 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_STPF_Shift, 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP1INTF, USBFS_DEVICE_BASE + 0x328 @ (device out endpoint-1 interrupt flag   register) 
        .equ USBFS_DEVICE_BTBSTP_Shift, 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_EPRXFOVR_Shift, 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_STPF_Shift, 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP2INTF, USBFS_DEVICE_BASE + 0x348 @ (device out endpoint-2 interrupt flag   register) 
        .equ USBFS_DEVICE_BTBSTP_Shift, 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_EPRXFOVR_Shift, 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_STPF_Shift, 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP3INTF, USBFS_DEVICE_BASE + 0x368 @ (device out endpoint-3 interrupt flag   register) 
        .equ USBFS_DEVICE_BTBSTP_Shift, 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_EPRXFOVR_Shift, 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_STPF_Shift, 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_EPDIS_Shift, 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_TF_Shift, 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP0LEN, USBFS_DEVICE_BASE + 0x110 @ (device IN endpoint-0 transfer length  register) 
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 2 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 7 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP0LEN, USBFS_DEVICE_BASE + 0x310 @ (device OUT endpoint-0 transfer length  register) 
        .equ USBFS_DEVICE_STPCNT_Shift, 29   @ bitWidth 2 (SETUP packet count)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 1 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 7 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP1LEN, USBFS_DEVICE_BASE + 0x130 @ (device IN endpoint-1 transfer length  register) 
        .equ USBFS_DEVICE_MCPF_Shift, 29   @ bitWidth 2 (Multi packet count per frame)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP2LEN, USBFS_DEVICE_BASE + 0x150 @ (device IN endpoint-2 transfer length  register) 
        .equ USBFS_DEVICE_MCPF_Shift, 29   @ bitWidth 2 (Multi packet count per frame)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP3LEN, USBFS_DEVICE_BASE + 0x170 @ (device IN endpoint-3 transfer length  register) 
        .equ USBFS_DEVICE_MCPF_Shift, 29   @ bitWidth 2 (Multi packet count per frame)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP1LEN, USBFS_DEVICE_BASE + 0x330 @ (device OUT endpoint-1 transfer length  register) 
        .equ USBFS_DEVICE_STPCNT_RXDPID_Shift, 29   @ bitWidth 2 (SETUP packet count/Received data PID)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP2LEN, USBFS_DEVICE_BASE + 0x350 @ (device OUT endpoint-2 transfer length  register) 
        .equ USBFS_DEVICE_STPCNT_RXDPID_Shift, 29   @ bitWidth 2 (SETUP packet count/Received data PID)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP3LEN, USBFS_DEVICE_BASE + 0x370 @ (device OUT endpoint-3 transfer length  register) 
        .equ USBFS_DEVICE_STPCNT_RXDPID_Shift, 29   @ bitWidth 2 (SETUP packet count/Received data PID)  
        .equ USBFS_DEVICE_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP0TFSTAT, USBFS_DEVICE_BASE + 0x118 @ (device IN endpoint 0 transmit FIFO  status register) 
        .equ USBFS_DEVICE_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 
    .equ USBFS_DEVICE_DIEP1TFSTAT, USBFS_DEVICE_BASE + 0x138 @ (device IN endpoint 1 transmit FIFO  status register) 
        .equ USBFS_DEVICE_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 
    .equ USBFS_DEVICE_DIEP2TFSTAT, USBFS_DEVICE_BASE + 0x158 @ (device IN endpoint 2 transmit FIFO  status register) 
        .equ USBFS_DEVICE_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 
    .equ USBFS_DEVICE_DIEP3TFSTAT, USBFS_DEVICE_BASE + 0x178 @ (device IN endpoint 3 transmit FIFO  status register) 
        .equ USBFS_DEVICE_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 

@=========================== USBFS_PWRCLK ===========================@
.equ USBFS_PWRCLK_BASE, 0x50000E00 @ (USB on the go full speed) 
    .equ USBFS_PWRCLK_PWRCLKCTL, USBFS_PWRCLK_BASE + 0x00 @ (power and clock gating control  register PWRCLKCTL) 
        .equ USBFS_PWRCLK_SUCLK_Shift, 0   @ bitWidth 1 (Stop the USB clock)  
        .equ USBFS_PWRCLK_SHCLK_Shift, 1   @ bitWidth 1 (Stop HCLK)  
 

@=========================== WWDGT ===========================@
.equ WWDGT_BASE, 0x40002C00 @ (Window watchdog timer) 
    .equ WWDGT_CTL, WWDGT_BASE + 0x0 @ (Control register) 
        .equ WWDGT_WDGTEN_Shift, 7   @ bitWidth 1 (Activation bit)  
        .equ WWDGT_CNT_Shift, 0   @ bitWidth 7 (7-bit counter)  
 
    .equ WWDGT_CFG, WWDGT_BASE + 0x04 @ (Configuration register) 
        .equ WWDGT_EWIE_Shift, 9   @ bitWidth 1 (Early wakeup interrupt)  
        .equ WWDGT_PSC_Shift, 7   @ bitWidth 2 (Prescaler)  
        .equ WWDGT_WIN_Shift, 0   @ bitWidth 7 (7-bit window value)  
 
    .equ WWDGT_STAT, WWDGT_BASE + 0x08 @ (Status register) 
        .equ WWDGT_EWIF_Shift, 0   @ bitWidth 1 (Early wakeup interrupt  flag)  
 
