This is a generic STM32 SVD2FORTH By Terry Porter <terry@tjporter.com.au> 2019 for Mecrisp_Stellaris by Mathias Koch
Developed on FreeBSD but will run on other BSD's and Linux. 

Purpose:
========
It uses a MCU CMSIS-SVD file to auto generate every Peripheral and Register memory mapped Word, every Register Bitfield manipulation Word, and every GNU Assembler EQUATE for the *ENTIRE* MCU. This should work on all STM32xxxxx.svd files. It probably won't work with non STM32 Cortex-M files which have slightly different SVG's.

One or more STM32Xxxxx.svd may be included in the tarball and configured in the Makefile. Test as is but remember to change the SVD for your MCU in the Makefile.
SVD's may be downloaded from https://github.com/posborne/cmsis-svd/archive/master.zip (39MB) or Googling will usually find your SVD thesedays.

NEW: 22June2019, also produced is a STM32Xxxxx.svd.equates.s for use with the GNU Assembler as used with Mecrisp-Stellaris.

Quick Description
-----------------
This is a 'generic' STM32 release and should work with any STM32Xxxxx.svd.

1) Peripheral and Register Pretty Printing Legends are separated from the XML file and now contained in a "1b.fs" file.
2) 1b.fs MUST be loaded FIRST before anything else.
3) Both bitfields.fs and memmap.fs now contain description fields parsed from the SVD. Hopefully this will reduce the need to have a databook open while coding.

Features:
* memmap.fs file contains all memory mapped peripheral Words and can print all register contents in a group or singly. The print Word for every register has a simple 32 bit legend showing the bit number and current value, this applies to registers which only use 15 bits or different groupings. Bitfields.fs, memmap.fs and STM32Xxxxx.svd.equates.s files now contain description fields parsed from the SVD. Hopefully this will reduce the need to have a databook open while coding.

For instance "rcc." will print every RCC peripheral register.
However "RCC_CFGR." will just print the named register which is part of the RCC group.
Example
-------

rcc. 
RCC_CR () $00000305 
3|3|2|2|2|2|2|2|2|2|2|2|1|1|1|1|1|1|1|1|1|1|
1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1


RCC_ICSCR () $0059B063 
3|3|2|2|2|2|2|2|2|2|2|2|1|1|1|1|1|1|1|1|1|1|
1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0 
0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1


RCC_CRRCR () $00003900 
3|3|2|2|2|2|2|2|2|2|2|2|1|1|1|1|1|1|1|1|1|1|
1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0


RCC_CFGR () $00000005 
3|3|2|2|2|2|2|2|2|2|2|2|1|1|1|1|1|1|1|1|1|1|
1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

* bitfield.fs file contains a Word for each bitfield to be pasted in full or part as desired.
Example
-------

\ RCC_CR ()
: RCC_CR_PLLRDY   %1 25 lshift RCC_CR bis! ;  \ RCC_CR_PLLRDY    PLL clock ready flag
: RCC_CR_PLLON   %1 24 lshift RCC_CR bis! ;  \ RCC_CR_PLLON    PLL enable bit
: RCC_CR_RTCPRE   ( %XX -- ) 20 lshift RCC_CR bis! ;  \ RCC_CR_RTCPRE    TC/LCD prescaler
: RCC_CR_CSSLSEON   %1 19 lshift RCC_CR bis! ;  \ RCC_CR_CSSLSEON    Clock security system on HSE enable  bit
: RCC_CR_HSEBYP   %1 18 lshift RCC_CR bis! ;  \ RCC_CR_HSEBYP    HSE clock bypass bit


The peripherals contained in either file can be de-selected by commenting out the
peripheral in template.xml as shown in the readme.

* STMXxxxx.svd.equates.s is for use with the GNU ASsembler as used in Mecrisp-Stellaris.
Example
-------
.equ GPIOC_BASE, 0x50000800 @ (General-purpose I/Os) 
    .equ GPIOC_MODER, GPIOC_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOC_MODE15_Shift, 30   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE14_Shift, 28   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE13_Shift, 26   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE12_Shift, 24   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE11_Shift, 22   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE10_Shift, 20   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE9_Shift, 18   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE8_Shift, 16   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE7_Shift, 14   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE6_Shift, 12   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE5_Shift, 10   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE4_Shift, 8   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE3_Shift, 6   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE2_Shift, 4   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE1_Shift, 2   @ bitWidth 2 (Port x configuration bits y =  0..15)  
        .equ GPIOC_MODE0_Shift, 0   @ bitWidth 2 (Port x configuration bits y =  0..15)  

Usage Example
-------------
 .equ GPIOC_BASE, 0x50000800 @ (General-purpose I/Os) 
 .equ GPIOC_MODER, GPIOC_BASE + 0x0 @ (GPIO port mode register)
 .equ GPIOC_MODER9_Shift, 18
 .equ GPIOC_MODER8_Shift, 16
 .equ GPIOC_MODER7_Shift, 14

 ldr r1, = GPIOC_MODER		 // R1 now contains address of 	GPIOC_MODER 
 movs r2, 0b01			 // R2 now contains 0b01      
 lsls r2, GPIOC_MODER8_Shift	 // lsls shifts R2 (0b01) 16 places left
 movs r3, 0b01			 // R3 now contains 0b01
 lsls r3, GPIOC_MODER7_Shift	 // lsls shifts R3 (0b01) 14 places left
 orrs r2, r2, r3		 // R2 now contains the logical OR of R2 and R3 

Longer Description
------------------
Memory Map Word Example
-----------------------
$40021000 constant RCC ( Reset and clock control ) 
RCC $0 + constant RCC_CR ( Clock control register ) 
RCC $4 + constant RCC_ICSCR ( Internal clock sources calibration  register ) 
RCC $8 + constant RCC_CRRCR ( Clock recovery RC register ) 
RCC $C + constant RCC_CFGR ( Clock configuration register ) 
RCC $10 + constant RCC_CIER ( Clock interrupt enable  register ) 
RCC $14 + constant RCC_CIFR ( Clock interrupt flag register ) 
RCC $18 + constant RCC_CICR ( Clock interrupt clear register ) 
RCC $1C + constant RCC_IOPRSTR ( GPIO reset register ) 
RCC $20 + constant RCC_AHBRSTR ( AHB peripheral reset register ) 
RCC $24 + constant RCC_APB2RSTR ( APB2 peripheral reset register )


1) Peripheral and Register Pretty Printing Legends are separated from the XML file and now contained in a "1b.fs" file.
2) 1b.fs MUST be loaded first BEFORE memmap.fs
3) Both bitfields.fs and memmap.fs now contain description fields parsed from the SVD. Hopefully this will reduce the need to have a databook open while coding.


Howto
=====
* Include your SVD file in the release directory and edit the SVD name in the Makefile
* run "make everything", this creates template.xml, bitfields.fs, memmap.fs and STMxxxxx.svd.equates.s
* Edit "template.xml" and COMMENT OUT the Peripherals you are NOT using 
   Not commented out:  <name xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">GPIOE</name>
   Commented out:      <!--  <name xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">GPIOE</name> -->   
* run "make mem"
   This will create new bitfields.fs and memmap.fs based on your edited template.xml file.
* Upload 1b.fs then memmap.fs to your MCU. If the Flash or Ram is filled, then perhaps you didn't bother editing template.xml to reduce the size ?
* bitfields.fs are for copy and pasting into your Forth program to configure Register Bitfields.

bitfields.fs
============
There are two types of Bitfields generated:
1) only ONE configuration bit ie
: RCC_CRRCR_HSI48ON   %1 0 lshift RCC-CRRCR bis! ;  \ RCC-CRRCR_HSI48ON    48MHz HSI clock enable bit

This type of bitfield will usually SET or CLEAR the one bit with a "bis!" or "bic!" command, or it may possibly be tested with a "bit@" command.

2) More than one configuration bit, ie:
: RCC_ICSCR_HSI16TRIM   ( %XXXXX -- ) 8 lshift RCC_ICSCR bis! ;  \ RCC_ICSCR_HSI16TRIM    High speed internal clock  trimming

This Bitfield has 5 config bits and can be used this way, which requires the above Word be preloaded:
   %11111 RCC_ICSCR_HSI16TRIM

Or this way for a standalone config:
   %11111 8 lshift RCC_ICSCR bis!  \ RCC_ICSCR_HSI16TRIM


Dependencies
=============
make
xsltproc
sed


template.xml
============
    Initially contains a list of ALL the Peripherals in your ARM svd MCU file. You edit this file by either commenting out, or deleting lines of Peripherals you DON'T want to use in your project. 

* Edit "template.xml" and COMMENT OUT the Peripherals you are NOT using 
   Not commented out:  <name xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">GPIOE</name>
   Commented out:      <!--  <name xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">GPIOE</name> -->

Final Notes:
============
ARM CORE Peripherals such as SYSTICK etc are not contained in the CMSIS-SVD's and will need to be manually created.
