@ arm-none-eabi-as equates file for GD32VF103
@ SVD2GAS Equates Generator, Copyright Terry Porter 2017 "terry@tjporter.com.au" for arm-none-eabi-as 
@ Matthias Koch Complimentary Edition 2017
@ Takes a CMSIS-SVD file plus a hand edited config.xml file as input 
@ Licensed under the GPL, see http://www.gnu.org/licenses/


@=========================== ADC0 ===========================@
.equ ADC0_BASE, 0x40012400 @ (Analog to digital converter) 
    .equ ADC0_STAT, ADC0_BASE + 0x0 @ (status register) 
        .equ ADC0_STAT_STRC, 1 << 4   @ bitWidth 1 (Start flag of regular channel group)  
        .equ ADC0_STAT_STIC, 1 << 3   @ bitWidth 1 (Start flag of inserted channel group)  
        .equ ADC0_STAT_EOIC, 1 << 2   @ bitWidth 1 (End of inserted group conversion flag)  
        .equ ADC0_STAT_EOC, 1 << 1   @ bitWidth 1 (End of group conversion flag)  
        .equ ADC0_STAT_WDE, 1 << 0   @ bitWidth 1 (Analog watchdog event flag)  
 
    .equ ADC0_CTL0, ADC0_BASE + 0x04 @ (control register 0) 
        .equ ADC0_CTL0_RWDEN, 1 << 23   @ bitWidth 1 (Regular channel analog watchdog enable)  
        .equ ADC0_CTL0_IWDEN, 1 << 22   @ bitWidth 1 (Inserted channel analog watchdog  	 enable)  
        .equ ADC0_CTL0_SYNCM_Shift, 16   @ bitWidth 4 (sync mode selection)  
        .equ ADC0_CTL0_DISNUM_Shift, 13   @ bitWidth 3 (Number of conversions in  	 discontinuous mode)  
        .equ ADC0_CTL0_DISIC, 1 << 12   @ bitWidth 1 (Discontinuous mode on  	 inserted channels)  
        .equ ADC0_CTL0_DISRC, 1 << 11   @ bitWidth 1 (Discontinuous mode on regular  channels)  
        .equ ADC0_CTL0_ICA, 1 << 10   @ bitWidth 1 (Inserted channel group convert  	 automatically)  
        .equ ADC0_CTL0_WDSC, 1 << 9   @ bitWidth 1 (When in scan mode, analog watchdog 	 is effective on a single channel)  
        .equ ADC0_CTL0_SM, 1 << 8   @ bitWidth 1 (Scan mode)  
        .equ ADC0_CTL0_EOICIE, 1 << 7   @ bitWidth 1 (Interrupt enable for EOIC)  
        .equ ADC0_CTL0_WDEIE, 1 << 6   @ bitWidth 1 (Interrupt enable for WDE)  
        .equ ADC0_CTL0_EOCIE, 1 << 5   @ bitWidth 1 (Interrupt enable for EOC)  
        .equ ADC0_CTL0_WDCHSEL_Shift, 0   @ bitWidth 5 (Analog watchdog channel select)  
 
    .equ ADC0_CTL1, ADC0_BASE + 0x08 @ (control register 1) 
        .equ ADC0_CTL1_TSVREN, 1 << 23   @ bitWidth 1 (Channel 16 and 17 enable of ADC0)  
        .equ ADC0_CTL1_SWRCST, 1 << 22   @ bitWidth 1 (Start on regular channel)  
        .equ ADC0_CTL1_SWICST, 1 << 21   @ bitWidth 1 (Start on inserted channel)  
        .equ ADC0_CTL1_ETERC, 1 << 20   @ bitWidth 1 (External trigger enable for regular channel)  
        .equ ADC0_CTL1_ETSRC_Shift, 17   @ bitWidth 3 (External trigger select for regular channel)  
        .equ ADC0_CTL1_ETEIC, 1 << 15   @ bitWidth 1 (External trigger select for inserted channel)  
        .equ ADC0_CTL1_ETSIC_Shift, 12   @ bitWidth 3 (External trigger select for inserted channel)  
        .equ ADC0_CTL1_DAL, 1 << 11   @ bitWidth 1 (Data alignment)  
        .equ ADC0_CTL1_DMA, 1 << 8   @ bitWidth 1 (DMA request enable)  
        .equ ADC0_CTL1_RSTCLB, 1 << 3   @ bitWidth 1 (Reset calibration)  
        .equ ADC0_CTL1_CLB, 1 << 2   @ bitWidth 1 (ADC calibration)  
        .equ ADC0_CTL1_CTN, 1 << 1   @ bitWidth 1 (Continuous mode)  
        .equ ADC0_CTL1_ADCON, 1 << 0   @ bitWidth 1 (ADC on)  
 
    .equ ADC0_SAMPT0, ADC0_BASE + 0x0C @ (Sample time register 0) 
        .equ ADC0_SAMPT0_SPT10_Shift, 0   @ bitWidth 3 (Channel 10 sample time  selection)  
        .equ ADC0_SAMPT0_SPT11_Shift, 3   @ bitWidth 3 (Channel 11 sample time  selection)  
        .equ ADC0_SAMPT0_SPT12_Shift, 6   @ bitWidth 3 (Channel 12 sample time  selection)  
        .equ ADC0_SAMPT0_SPT13_Shift, 9   @ bitWidth 3 (Channel 13 sample time  selection)  
        .equ ADC0_SAMPT0_SPT14_Shift, 12   @ bitWidth 3 (Channel 14 sample time  selection)  
        .equ ADC0_SAMPT0_SPT15_Shift, 15   @ bitWidth 3 (Channel 15 sample time  selection)  
        .equ ADC0_SAMPT0_SPT16_Shift, 18   @ bitWidth 3 (Channel 16 sample time  selection)  
        .equ ADC0_SAMPT0_SPT17_Shift, 21   @ bitWidth 3 (Channel 17 sample time  selection)  
 
    .equ ADC0_SAMPT1, ADC0_BASE + 0x10 @ (Sample time register 1) 
        .equ ADC0_SAMPT1_SPT0_Shift, 0   @ bitWidth 3 (Channel 0 sample time  selection)  
        .equ ADC0_SAMPT1_SPT1_Shift, 3   @ bitWidth 3 (Channel 1 sample time  selection)  
        .equ ADC0_SAMPT1_SPT2_Shift, 6   @ bitWidth 3 (Channel 2 sample time  selection)  
        .equ ADC0_SAMPT1_SPT3_Shift, 9   @ bitWidth 3 (Channel 3 sample time  selection)  
        .equ ADC0_SAMPT1_SPT4_Shift, 12   @ bitWidth 3 (Channel 4 sample time  selection)  
        .equ ADC0_SAMPT1_SPT5_Shift, 15   @ bitWidth 3 (Channel 5 sample time  selection)  
        .equ ADC0_SAMPT1_SPT6_Shift, 18   @ bitWidth 3 (Channel 6 sample time  selection)  
        .equ ADC0_SAMPT1_SPT7_Shift, 21   @ bitWidth 3 (Channel 7 sample time  selection)  
        .equ ADC0_SAMPT1_SPT8_Shift, 24   @ bitWidth 3 (Channel 8 sample time  selection)  
        .equ ADC0_SAMPT1_SPT9_Shift, 27   @ bitWidth 3 (Channel 9 sample time  selection)  
 
    .equ ADC0_IOFF0, ADC0_BASE + 0x14 @ (Inserted channel data offset register  0) 
        .equ ADC0_IOFF0_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  0)  
 
    .equ ADC0_IOFF1, ADC0_BASE + 0x18 @ (Inserted channel data offset register  1) 
        .equ ADC0_IOFF1_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  1)  
 
    .equ ADC0_IOFF2, ADC0_BASE + 0x1C @ (Inserted channel data offset register  2) 
        .equ ADC0_IOFF2_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  2)  
 
    .equ ADC0_IOFF3, ADC0_BASE + 0x20 @ (Inserted channel data offset register  3) 
        .equ ADC0_IOFF3_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  3)  
 
    .equ ADC0_WDHT, ADC0_BASE + 0x24 @ (watchdog higher threshold  register) 
        .equ ADC0_WDHT_WDHT_Shift, 0   @ bitWidth 12 (Analog watchdog higher  threshold)  
 
    .equ ADC0_WDLT, ADC0_BASE + 0x28 @ (watchdog lower threshold  register) 
        .equ ADC0_WDLT_WDLT_Shift, 0   @ bitWidth 12 (Analog watchdog lower  threshold)  
 
    .equ ADC0_RSQ0, ADC0_BASE + 0x2C @ (regular sequence register 0) 
        .equ ADC0_RSQ0_RL_Shift, 20   @ bitWidth 4 (Regular channel group  length)  
        .equ ADC0_RSQ0_RSQ15_Shift, 15   @ bitWidth 5 (16th conversion in regular  sequence)  
        .equ ADC0_RSQ0_RSQ14_Shift, 10   @ bitWidth 5 (15th conversion in regular  sequence)  
        .equ ADC0_RSQ0_RSQ13_Shift, 5   @ bitWidth 5 (14th conversion in regular  sequence)  
        .equ ADC0_RSQ0_RSQ12_Shift, 0   @ bitWidth 5 (13th conversion in regular  sequence)  
 
    .equ ADC0_RSQ1, ADC0_BASE + 0x30 @ (regular sequence register 1) 
        .equ ADC0_RSQ1_RSQ11_Shift, 25   @ bitWidth 5 (12th conversion in regular  sequence)  
        .equ ADC0_RSQ1_RSQ10_Shift, 20   @ bitWidth 5 (11th conversion in regular  sequence)  
        .equ ADC0_RSQ1_RSQ9_Shift, 15   @ bitWidth 5 (10th conversion in regular  sequence)  
        .equ ADC0_RSQ1_RSQ8_Shift, 10   @ bitWidth 5 (9th conversion in regular  sequence)  
        .equ ADC0_RSQ1_RSQ7_Shift, 5   @ bitWidth 5 (8th conversion in regular  sequence)  
        .equ ADC0_RSQ1_RSQ6_Shift, 0   @ bitWidth 5 (7th conversion in regular  sequence)  
 
    .equ ADC0_RSQ2, ADC0_BASE + 0x34 @ (regular sequence register 2) 
        .equ ADC0_RSQ2_RSQ5_Shift, 25   @ bitWidth 5 (6th conversion in regular  sequence)  
        .equ ADC0_RSQ2_RSQ4_Shift, 20   @ bitWidth 5 (5th conversion in regular  sequence)  
        .equ ADC0_RSQ2_RSQ3_Shift, 15   @ bitWidth 5 (4th conversion in regular  sequence)  
        .equ ADC0_RSQ2_RSQ2_Shift, 10   @ bitWidth 5 (3rd conversion in regular  sequence)  
        .equ ADC0_RSQ2_RSQ1_Shift, 5   @ bitWidth 5 (2nd conversion in regular  sequence)  
        .equ ADC0_RSQ2_RSQ0_Shift, 0   @ bitWidth 5 (1st conversion in regular  sequence)  
 
    .equ ADC0_ISQ, ADC0_BASE + 0x38 @ (Inserted sequence register) 
        .equ ADC0_ISQ_IL_Shift, 20   @ bitWidth 2 (Inserted channel group length)  
        .equ ADC0_ISQ_ISQ3_Shift, 15   @ bitWidth 5 (4th conversion in inserted  sequence)  
        .equ ADC0_ISQ_ISQ2_Shift, 10   @ bitWidth 5 (3rd conversion in inserted  sequence)  
        .equ ADC0_ISQ_ISQ1_Shift, 5   @ bitWidth 5 (2nd conversion in inserted  sequence)  
        .equ ADC0_ISQ_ISQ0_Shift, 0   @ bitWidth 5 (1st conversion in inserted  sequence)  
 
    .equ ADC0_IDATA0, ADC0_BASE + 0x3C @ (Inserted data register 0) 
        .equ ADC0_IDATA0_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_IDATA1, ADC0_BASE + 0x40 @ (Inserted data register 1) 
        .equ ADC0_IDATA1_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_IDATA2, ADC0_BASE + 0x44 @ (Inserted data register 2) 
        .equ ADC0_IDATA2_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_IDATA3, ADC0_BASE + 0x48 @ (Inserted data register 3) 
        .equ ADC0_IDATA3_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC0_RDATA, ADC0_BASE + 0x4C @ (regular data register) 
        .equ ADC0_RDATA_ADC1RDTR_Shift, 16   @ bitWidth 16 (ADC regular channel data)  
        .equ ADC0_RDATA_RDATA_Shift, 0   @ bitWidth 16 (Regular channel data)  
 
    .equ ADC0_OVSAMPCTL, ADC0_BASE + 0x80 @ (Oversample control register) 
        .equ ADC0_OVSAMPCTL_DRES_Shift, 12   @ bitWidth 2 (ADC resolution)  
        .equ ADC0_OVSAMPCTL_TOVS, 1 << 9   @ bitWidth 1 (Triggered Oversampling)  
        .equ ADC0_OVSAMPCTL_OVSS_Shift, 5   @ bitWidth 4 (Oversampling shift)  
        .equ ADC0_OVSAMPCTL_OVSR_Shift, 2   @ bitWidth 3 (Oversampling ratio)  
        .equ ADC0_OVSAMPCTL_OVSEN, 1 << 0   @ bitWidth 1 (Oversampler Enable)  
 

@=========================== ADC1 ===========================@
.equ ADC1_BASE, 0x40012800 @ (Analog to digital converter) 
    .equ ADC1_STAT, ADC1_BASE + 0x0 @ (status register) 
        .equ ADC1_STAT_STRC, 1 << 4   @ bitWidth 1 (Start flag of regular channel group)  
        .equ ADC1_STAT_STIC, 1 << 3   @ bitWidth 1 (Start flag of inserted channel group)  
        .equ ADC1_STAT_EOIC, 1 << 2   @ bitWidth 1 (End of inserted group conversion flag)  
        .equ ADC1_STAT_EOC, 1 << 1   @ bitWidth 1 (End of group conversion flag)  
        .equ ADC1_STAT_WDE, 1 << 0   @ bitWidth 1 (Analog watchdog event flag)  
 
    .equ ADC1_CTL0, ADC1_BASE + 0x4 @ (control register 0) 
        .equ ADC1_CTL0_RWDEN, 1 << 23   @ bitWidth 1 (Regular channel analog watchdog  	 enable)  
        .equ ADC1_CTL0_IWDEN, 1 << 22   @ bitWidth 1 (Inserted channel analog watchdog  	 enable)  
        .equ ADC1_CTL0_DISNUM_Shift, 13   @ bitWidth 3 (Number of conversions in  	 discontinuous mode)  
        .equ ADC1_CTL0_DISIC, 1 << 12   @ bitWidth 1 (Discontinuous mode on  	 inserted channels)  
        .equ ADC1_CTL0_DISRC, 1 << 11   @ bitWidth 1 (Discontinuous mode on regular  channels)  
        .equ ADC1_CTL0_ICA, 1 << 10   @ bitWidth 1 (Inserted channel group convert  	 automatically)  
        .equ ADC1_CTL0_WDSC, 1 << 9   @ bitWidth 1 (When in scan mode, analog watchdog 	 is effective on a single channel)  
        .equ ADC1_CTL0_SM, 1 << 8   @ bitWidth 1 (Scan mode)  
        .equ ADC1_CTL0_EOICIE, 1 << 7   @ bitWidth 1 (Interrupt enable for EOIC)  
        .equ ADC1_CTL0_WDEIE, 1 << 6   @ bitWidth 1 (Interrupt enable for WDE)  
        .equ ADC1_CTL0_EOCIE, 1 << 5   @ bitWidth 1 (Interrupt enable for EOC)  
        .equ ADC1_CTL0_WDCHSEL_Shift, 0   @ bitWidth 5 (Analog watchdog channel select)  
 
    .equ ADC1_CTL1, ADC1_BASE + 0x08 @ (control register 1) 
        .equ ADC1_CTL1_SWRCST, 1 << 22   @ bitWidth 1 (Start on regular channel)  
        .equ ADC1_CTL1_SWICST, 1 << 21   @ bitWidth 1 (Start on inserted channel)  
        .equ ADC1_CTL1_ETERC, 1 << 20   @ bitWidth 1 (External trigger enable for regular channel)  
        .equ ADC1_CTL1_ETSRC_Shift, 17   @ bitWidth 3 (External trigger select for regular channel)  
        .equ ADC1_CTL1_ETEIC, 1 << 15   @ bitWidth 1 (External trigger enable for inserted channel)  
        .equ ADC1_CTL1_ETSIC_Shift, 12   @ bitWidth 3 (External trigger select for inserted channel)  
        .equ ADC1_CTL1_DAL, 1 << 11   @ bitWidth 1 (Data alignment)  
        .equ ADC1_CTL1_DMA, 1 << 8   @ bitWidth 1 (DMA request enable)  
        .equ ADC1_CTL1_RSTCLB, 1 << 3   @ bitWidth 1 (Reset calibration)  
        .equ ADC1_CTL1_CLB, 1 << 2   @ bitWidth 1 (ADC calibration)  
        .equ ADC1_CTL1_CTN, 1 << 1   @ bitWidth 1 (Continuous mode)  
        .equ ADC1_CTL1_ADCON, 1 << 0   @ bitWidth 1 (ADC on)  
 
    .equ ADC1_SAMPT0, ADC1_BASE + 0x0C @ (Sample time register 0) 
        .equ ADC1_SAMPT0_SPT10_Shift, 0   @ bitWidth 3 (Channel 10 sample time  selection)  
        .equ ADC1_SAMPT0_SPT11_Shift, 3   @ bitWidth 3 (Channel 11 sample time  selection)  
        .equ ADC1_SAMPT0_SPT12_Shift, 6   @ bitWidth 3 (Channel 12 sample time  selection)  
        .equ ADC1_SAMPT0_SPT13_Shift, 9   @ bitWidth 3 (Channel 13 sample time  selection)  
        .equ ADC1_SAMPT0_SPT14_Shift, 12   @ bitWidth 3 (Channel 14 sample time  selection)  
        .equ ADC1_SAMPT0_SPT15_Shift, 15   @ bitWidth 3 (Channel 15 sample time  selection)  
        .equ ADC1_SAMPT0_SPT16_Shift, 18   @ bitWidth 3 (Channel 16 sample time  selection)  
        .equ ADC1_SAMPT0_SPT17_Shift, 21   @ bitWidth 3 (Channel 17 sample time  selection)  
 
    .equ ADC1_SAMPT1, ADC1_BASE + 0x10 @ (Sample time register 1) 
        .equ ADC1_SAMPT1_SPT0_Shift, 0   @ bitWidth 3 (Channel 0 sample time  selection)  
        .equ ADC1_SAMPT1_SPT1_Shift, 3   @ bitWidth 3 (Channel 1 sample time  selection)  
        .equ ADC1_SAMPT1_SPT2_Shift, 6   @ bitWidth 3 (Channel 2 sample time  selection)  
        .equ ADC1_SAMPT1_SPT3_Shift, 9   @ bitWidth 3 (Channel 3 sample time  selection)  
        .equ ADC1_SAMPT1_SPT4_Shift, 12   @ bitWidth 3 (Channel 4 sample time  selection)  
        .equ ADC1_SAMPT1_SPT5_Shift, 15   @ bitWidth 3 (Channel 5 sample time  selection)  
        .equ ADC1_SAMPT1_SPT6_Shift, 18   @ bitWidth 3 (Channel 6 sample time  selection)  
        .equ ADC1_SAMPT1_SPT7_Shift, 21   @ bitWidth 3 (Channel 7 sample time  selection)  
        .equ ADC1_SAMPT1_SPT8_Shift, 24   @ bitWidth 3 (Channel 8 sample time  selection)  
        .equ ADC1_SAMPT1_SPT9_Shift, 27   @ bitWidth 3 (Channel 9 sample time  selection)  
 
    .equ ADC1_IOFF0, ADC1_BASE + 0x14 @ (Inserted channel data offset register  0) 
        .equ ADC1_IOFF0_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  0)  
 
    .equ ADC1_IOFF1, ADC1_BASE + 0x18 @ (Inserted channel data offset register  1) 
        .equ ADC1_IOFF1_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  1)  
 
    .equ ADC1_IOFF2, ADC1_BASE + 0x1C @ (Inserted channel data offset register  2) 
        .equ ADC1_IOFF2_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  2)  
 
    .equ ADC1_IOFF3, ADC1_BASE + 0x20 @ (Inserted channel data offset register  3) 
        .equ ADC1_IOFF3_IOFF_Shift, 0   @ bitWidth 12 (Data offset for inserted channel  3)  
 
    .equ ADC1_WDHT, ADC1_BASE + 0x24 @ (watchdog higher threshold  register) 
        .equ ADC1_WDHT_WDHT_Shift, 0   @ bitWidth 12 (Analog watchdog higher  threshold)  
 
    .equ ADC1_WDLT, ADC1_BASE + 0x28 @ (watchdog lower threshold  register) 
        .equ ADC1_WDLT_WDLT_Shift, 0   @ bitWidth 12 (Analog watchdog lower  threshold)  
 
    .equ ADC1_RSQ0, ADC1_BASE + 0x2C @ (regular sequence register 0) 
        .equ ADC1_RSQ0_RL_Shift, 20   @ bitWidth 4 (Regular channel group  length)  
        .equ ADC1_RSQ0_RSQ15_Shift, 15   @ bitWidth 5 (16th conversion in regular  sequence)  
        .equ ADC1_RSQ0_RSQ14_Shift, 10   @ bitWidth 5 (15th conversion in regular  sequence)  
        .equ ADC1_RSQ0_RSQ13_Shift, 5   @ bitWidth 5 (14th conversion in regular  sequence)  
        .equ ADC1_RSQ0_RSQ12_Shift, 0   @ bitWidth 5 (13th conversion in regular  sequence)  
 
    .equ ADC1_RSQ1, ADC1_BASE + 0x30 @ (regular sequence register 1) 
        .equ ADC1_RSQ1_RSQ11_Shift, 25   @ bitWidth 5 (12th conversion in regular  sequence)  
        .equ ADC1_RSQ1_RSQ10_Shift, 20   @ bitWidth 5 (11th conversion in regular  sequence)  
        .equ ADC1_RSQ1_RSQ9_Shift, 15   @ bitWidth 5 (10th conversion in regular  sequence)  
        .equ ADC1_RSQ1_RSQ8_Shift, 10   @ bitWidth 5 (9th conversion in regular  sequence)  
        .equ ADC1_RSQ1_RSQ7_Shift, 5   @ bitWidth 5 (8th conversion in regular  sequence)  
        .equ ADC1_RSQ1_RSQ6_Shift, 0   @ bitWidth 5 (7th conversion in regular  sequence)  
 
    .equ ADC1_RSQ2, ADC1_BASE + 0x34 @ (regular sequence register 2) 
        .equ ADC1_RSQ2_RSQ5_Shift, 25   @ bitWidth 5 (6th conversion in regular  sequence)  
        .equ ADC1_RSQ2_RSQ4_Shift, 20   @ bitWidth 5 (5th conversion in regular  sequence)  
        .equ ADC1_RSQ2_RSQ3_Shift, 15   @ bitWidth 5 (4th conversion in regular  sequence)  
        .equ ADC1_RSQ2_RSQ2_Shift, 10   @ bitWidth 5 (3rd conversion in regular  sequence)  
        .equ ADC1_RSQ2_RSQ1_Shift, 5   @ bitWidth 5 (2nd conversion in regular  sequence)  
        .equ ADC1_RSQ2_RSQ0_Shift, 0   @ bitWidth 5 (1st conversion in regular  sequence)  
 
    .equ ADC1_ISQ, ADC1_BASE + 0x38 @ (Inserted sequence register) 
        .equ ADC1_ISQ_IL_Shift, 20   @ bitWidth 2 (Inserted channel group length)  
        .equ ADC1_ISQ_ISQ3_Shift, 15   @ bitWidth 5 (4th conversion in inserted  sequence)  
        .equ ADC1_ISQ_ISQ2_Shift, 10   @ bitWidth 5 (3rd conversion in inserted  sequence)  
        .equ ADC1_ISQ_ISQ1_Shift, 5   @ bitWidth 5 (2nd conversion in inserted  sequence)  
        .equ ADC1_ISQ_ISQ0_Shift, 0   @ bitWidth 5 (1st conversion in inserted  sequence)  
 
    .equ ADC1_IDATA0, ADC1_BASE + 0x3C @ (Inserted data register 0) 
        .equ ADC1_IDATA0_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_IDATA1, ADC1_BASE + 0x40 @ (Inserted data register 1) 
        .equ ADC1_IDATA1_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_IDATA2, ADC1_BASE + 0x44 @ (Inserted data register 2) 
        .equ ADC1_IDATA2_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_IDATA3, ADC1_BASE + 0x48 @ (Inserted data register 3) 
        .equ ADC1_IDATA3_IDATAn_Shift, 0   @ bitWidth 16 (Inserted number n conversion data)  
 
    .equ ADC1_RDATA, ADC1_BASE + 0x4C @ (regular data register) 
        .equ ADC1_RDATA_RDATA_Shift, 0   @ bitWidth 16 (Regular channel data)  
 

@=========================== AFIO ===========================@
.equ AFIO_BASE, 0x40010000 @ (Alternate-function I/Os) 
    .equ AFIO_EC, AFIO_BASE + 0x0 @ (Event control register) 
        .equ AFIO_EC_EOE, 1 << 7   @ bitWidth 1 (Event output enable)  
        .equ AFIO_EC_PORT_Shift, 4   @ bitWidth 3 (Event output port selection)  
        .equ AFIO_EC_PIN_Shift, 0   @ bitWidth 4 (Event output pin selection)  
 
    .equ AFIO_PCF0, AFIO_BASE + 0x04 @ (AFIO port configuration register 0) 
        .equ AFIO_PCF0_TIMER1ITI1_REMAP, 1 << 29   @ bitWidth 1 (TIMER1 internal trigger 1 remapping)  
        .equ AFIO_PCF0_SPI2_REMAP, 1 << 28   @ bitWidth 1 ( SPI2/I2S2 remapping)  
        .equ AFIO_PCF0_SWJ_CFG_Shift, 24   @ bitWidth 3 (Serial wire JTAG configuration)  
        .equ AFIO_PCF0_CAN1_REMAP, 1 << 22   @ bitWidth 1 (CAN1 I/O remapping)  
        .equ AFIO_PCF0_TIMER4CH3_IREMAP, 1 << 16   @ bitWidth 1 (TIMER4 channel3 internal remapping)  
        .equ AFIO_PCF0_PD01_REMAP, 1 << 15   @ bitWidth 1 (Port D0/Port D1 mapping on OSC_IN/OSC_OUT)  
        .equ AFIO_PCF0_CAN0_REMAP_Shift, 13   @ bitWidth 2 (CAN0 alternate interface remapping)  
        .equ AFIO_PCF0_TIMER3_REMAP, 1 << 12   @ bitWidth 1 (TIMER3 remapping)  
        .equ AFIO_PCF0_TIMER2_REMAP_Shift, 10   @ bitWidth 2 (TIMER2 remapping)  
        .equ AFIO_PCF0_TIMER1_REMAP_Shift, 8   @ bitWidth 2 (TIMER1 remapping)  
        .equ AFIO_PCF0_TIMER0_REMAP_Shift, 6   @ bitWidth 2 (TIMER0 remapping)  
        .equ AFIO_PCF0_USART2_REMAP_Shift, 4   @ bitWidth 2 (USART2 remapping)  
        .equ AFIO_PCF0_USART1_REMAP, 1 << 3   @ bitWidth 1 (USART1 remapping)  
        .equ AFIO_PCF0_USART0_REMAP, 1 << 2   @ bitWidth 1 (USART0 remapping)  
        .equ AFIO_PCF0_I2C0_REMAP, 1 << 1   @ bitWidth 1 (I2C0 remapping)  
        .equ AFIO_PCF0_SPI0_REMAP, 1 << 0   @ bitWidth 1 (SPI0 remapping)  
 
    .equ AFIO_EXTISS0, AFIO_BASE + 0x08 @ (EXTI sources selection register 0) 
        .equ AFIO_EXTISS0_EXTI3_SS_Shift, 12   @ bitWidth 4 (EXTI 3 sources selection)  
        .equ AFIO_EXTISS0_EXTI2_SS_Shift, 8   @ bitWidth 4 (EXTI 2 sources selection)  
        .equ AFIO_EXTISS0_EXTI1_SS_Shift, 4   @ bitWidth 4 (EXTI 1 sources selection)  
        .equ AFIO_EXTISS0_EXTI0_SS_Shift, 0   @ bitWidth 4 (EXTI 0 sources selection)  
 
    .equ AFIO_EXTISS1, AFIO_BASE + 0x0C @ (EXTI sources selection register 1) 
        .equ AFIO_EXTISS1_EXTI7_SS_Shift, 12   @ bitWidth 4 (EXTI 7 sources selection)  
        .equ AFIO_EXTISS1_EXTI6_SS_Shift, 8   @ bitWidth 4 (EXTI 6 sources selection)  
        .equ AFIO_EXTISS1_EXTI5_SS_Shift, 4   @ bitWidth 4 (EXTI 5 sources selection)  
        .equ AFIO_EXTISS1_EXTI4_SS_Shift, 0   @ bitWidth 4 (EXTI 4 sources selection)  
 
    .equ AFIO_EXTISS2, AFIO_BASE + 0x10 @ (EXTI sources selection register 2) 
        .equ AFIO_EXTISS2_EXTI11_SS_Shift, 12   @ bitWidth 4 (EXTI 11 sources selection)  
        .equ AFIO_EXTISS2_EXTI10_SS_Shift, 8   @ bitWidth 4 (EXTI 10 sources selection)  
        .equ AFIO_EXTISS2_EXTI9_SS_Shift, 4   @ bitWidth 4 (EXTI 9 sources selection)  
        .equ AFIO_EXTISS2_EXTI8_SS_Shift, 0   @ bitWidth 4 (EXTI 8 sources selection)  
 
    .equ AFIO_EXTISS3, AFIO_BASE + 0x14 @ (EXTI sources selection register 3) 
        .equ AFIO_EXTISS3_EXTI15_SS_Shift, 12   @ bitWidth 4 (EXTI 15 sources selection)  
        .equ AFIO_EXTISS3_EXTI14_SS_Shift, 8   @ bitWidth 4 (EXTI 14 sources selection)  
        .equ AFIO_EXTISS3_EXTI13_SS_Shift, 4   @ bitWidth 4 (EXTI 13 sources selection)  
        .equ AFIO_EXTISS3_EXTI12_SS_Shift, 0   @ bitWidth 4 (EXTI 12 sources selection)  
 
    .equ AFIO_PCF1, AFIO_BASE + 0x1C @ (AFIO port configuration register 1) 
        .equ AFIO_PCF1_EXMC_NADV, 1 << 10   @ bitWidth 1 (EXMC_NADV connect/disconnect)  
 

@=========================== BKP ===========================@
.equ BKP_BASE, 0x40006C00 @ (Backup registers) 
    .equ BKP_DATA0, BKP_BASE + 0x4 @ (Backup data register 0) 
        .equ BKP_DATA0_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA1, BKP_BASE + 0x8 @ (Backup data register 1) 
        .equ BKP_DATA1_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA2, BKP_BASE + 0xC @ (Backup data register 2) 
        .equ BKP_DATA2_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA3, BKP_BASE + 0x10 @ (Backup data register 3) 
        .equ BKP_DATA3_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA4, BKP_BASE + 0x14 @ (Backup data register 4) 
        .equ BKP_DATA4_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA5, BKP_BASE + 0x18 @ (Backup data register 5) 
        .equ BKP_DATA5_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA6, BKP_BASE + 0x1C @ (Backup data register 6) 
        .equ BKP_DATA6_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA7, BKP_BASE + 0x20 @ (Backup data register 7) 
        .equ BKP_DATA7_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA8, BKP_BASE + 0x24 @ (Backup data register 8) 
        .equ BKP_DATA8_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA9, BKP_BASE + 0x28 @ (Backup data register 9) 
        .equ BKP_DATA9_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA10, BKP_BASE + 0x40 @ (Backup data register 10) 
        .equ BKP_DATA10_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA11, BKP_BASE + 0x44 @ (Backup data register 11) 
        .equ BKP_DATA11_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA12, BKP_BASE + 0x48 @ (Backup data register 12) 
        .equ BKP_DATA12_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA13, BKP_BASE + 0x4C @ (Backup data register 13) 
        .equ BKP_DATA13_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA14, BKP_BASE + 0x50 @ (Backup data register 14) 
        .equ BKP_DATA14_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA15, BKP_BASE + 0x54 @ (Backup data register 15) 
        .equ BKP_DATA15_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA16, BKP_BASE + 0x58 @ (Backup data register 16) 
        .equ BKP_DATA16_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA17, BKP_BASE + 0x5C @ (Backup data register 17) 
        .equ BKP_DATA17_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA18, BKP_BASE + 0x60 @ (Backup data register 18) 
        .equ BKP_DATA18_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA19, BKP_BASE + 0x64 @ (Backup data register 19) 
        .equ BKP_DATA19_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA20, BKP_BASE + 0x68 @ (Backup data register 20) 
        .equ BKP_DATA20_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA21, BKP_BASE + 0x6C @ (Backup data register 21) 
        .equ BKP_DATA21_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA22, BKP_BASE + 0x70 @ (Backup data register 22) 
        .equ BKP_DATA22_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA23, BKP_BASE + 0x74 @ (Backup data register 23) 
        .equ BKP_DATA23_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA24, BKP_BASE + 0x78 @ (Backup data register 24) 
        .equ BKP_DATA24_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA25, BKP_BASE + 0x7C @ (Backup data register 25) 
        .equ BKP_DATA25_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA26, BKP_BASE + 0x80 @ (Backup data register 26) 
        .equ BKP_DATA26_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA27, BKP_BASE + 0x84 @ (Backup data register 27) 
        .equ BKP_DATA27_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA28, BKP_BASE + 0x88 @ (Backup data register 28) 
        .equ BKP_DATA28_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA29, BKP_BASE + 0x8C @ (Backup data register 29) 
        .equ BKP_DATA29_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA30, BKP_BASE + 0x90 @ (Backup data register 30) 
        .equ BKP_DATA30_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA31, BKP_BASE + 0x94 @ (Backup data register 31) 
        .equ BKP_DATA31_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA32, BKP_BASE + 0x98 @ (Backup data register 32) 
        .equ BKP_DATA32_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA33, BKP_BASE + 0x9C @ (Backup data register 33) 
        .equ BKP_DATA33_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA34, BKP_BASE + 0xA0 @ (Backup data register 34) 
        .equ BKP_DATA34_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA35, BKP_BASE + 0xA4 @ (Backup data register 35) 
        .equ BKP_DATA35_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA36, BKP_BASE + 0xA8 @ (Backup data register 36) 
        .equ BKP_DATA36_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA37, BKP_BASE + 0xAC @ (Backup data register 37) 
        .equ BKP_DATA37_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA38, BKP_BASE + 0xB0 @ (Backup data register 38) 
        .equ BKP_DATA38_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA39, BKP_BASE + 0xB4 @ (Backup data register 39) 
        .equ BKP_DATA39_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA40, BKP_BASE + 0xB8 @ (Backup data register 40) 
        .equ BKP_DATA40_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_DATA41, BKP_BASE + 0xBC @ (Backup data register 41) 
        .equ BKP_DATA41_DATA_Shift, 0   @ bitWidth 16 (Backup data)  
 
    .equ BKP_OCTL, BKP_BASE + 0x2C @ (RTC signal output control register) 
        .equ BKP_OCTL_ROSEL, 1 << 9   @ bitWidth 1 (RTC output selection)  
        .equ BKP_OCTL_ASOEN, 1 << 8   @ bitWidth 1 (RTC alarm or second signal output enable)  
        .equ BKP_OCTL_COEN, 1 << 7   @ bitWidth 1 (RTC clock calibration output enable)  
        .equ BKP_OCTL_RCCV_Shift, 0   @ bitWidth 7 (RTC clock calibration value)  
 
    .equ BKP_TPCTL, BKP_BASE + 0x30 @ (Tamper pin control register) 
        .equ BKP_TPCTL_TPAL, 1 << 1   @ bitWidth 1 (TAMPER pin active level)  
        .equ BKP_TPCTL_TPEN, 1 << 0   @ bitWidth 1 (TAMPER detection enable)  
 
    .equ BKP_TPCS, BKP_BASE + 0x34 @ (Tamper control and status register) 
        .equ BKP_TPCS_TIF, 1 << 9   @ bitWidth 1 (Tamper interrupt flag)  
        .equ BKP_TPCS_TEF, 1 << 8   @ bitWidth 1 (Tamper event flag)  
        .equ BKP_TPCS_TPIE, 1 << 2   @ bitWidth 1 (Tamper interrupt enable)  
        .equ BKP_TPCS_TIR, 1 << 1   @ bitWidth 1 (Tamper interrupt reset)  
        .equ BKP_TPCS_TER, 1 << 0   @ bitWidth 1 (Tamper event reset)  
 

@=========================== CAN0 ===========================@
.equ CAN0_BASE, 0x40006400 @ (Controller area network) 
    .equ CAN0_CTL, CAN0_BASE + 0x0 @ (Control register) 
        .equ CAN0_CTL_DFZ, 1 << 16   @ bitWidth 1 (Debug freeze)  
        .equ CAN0_CTL_SWRST, 1 << 15   @ bitWidth 1 (Software reset)  
        .equ CAN0_CTL_TTC, 1 << 7   @ bitWidth 1 (Time-triggered communication)  
        .equ CAN0_CTL_ABOR, 1 << 6   @ bitWidth 1 (Automatic bus-off recovery)  
        .equ CAN0_CTL_AWU, 1 << 5   @ bitWidth 1 (Automatic wakeup)  
        .equ CAN0_CTL_ARD, 1 << 4   @ bitWidth 1 (Automatic retransmission disable)  
        .equ CAN0_CTL_RFOD, 1 << 3   @ bitWidth 1 (Receive FIFO overwrite disable)  
        .equ CAN0_CTL_TFO, 1 << 2   @ bitWidth 1 (Transmit FIFO order)  
        .equ CAN0_CTL_SLPWMOD, 1 << 1   @ bitWidth 1 (Sleep working mode)  
        .equ CAN0_CTL_IWMOD, 1 << 0   @ bitWidth 1 (Initial working mode)  
 
    .equ CAN0_STAT, CAN0_BASE + 0x04 @ (Status register) 
        .equ CAN0_STAT_RXL, 1 << 11   @ bitWidth 1 (RX level)  
        .equ CAN0_STAT_LASTRX, 1 << 10   @ bitWidth 1 (Last sample value of RX pin)  
        .equ CAN0_STAT_RS, 1 << 9   @ bitWidth 1 (Receiving state)  
        .equ CAN0_STAT_TS, 1 << 8   @ bitWidth 1 (Transmitting state)  
        .equ CAN0_STAT_SLPIF, 1 << 4   @ bitWidth 1 (Status change interrupt flag of sleep  	 working mode entering)  
        .equ CAN0_STAT_WUIF, 1 << 3   @ bitWidth 1 (Status change interrupt flag of wakeup  	 from sleep working mode)  
        .equ CAN0_STAT_ERRIF, 1 << 2   @ bitWidth 1 (Error interrupt flag)  
        .equ CAN0_STAT_SLPWS, 1 << 1   @ bitWidth 1 (Sleep working state)  
        .equ CAN0_STAT_IWS, 1 << 0   @ bitWidth 1 (Initial working state)  
 
    .equ CAN0_TSTAT, CAN0_BASE + 0x8 @ (Transmit status register) 
        .equ CAN0_TSTAT_TMLS2, 1 << 31   @ bitWidth 1 (Transmit mailbox 2 last sending  	 in transmit FIFO)  
        .equ CAN0_TSTAT_TMLS1, 1 << 30   @ bitWidth 1 (Transmit mailbox 1 last sending  	 in transmit FIFO)  
        .equ CAN0_TSTAT_TMLS0, 1 << 29   @ bitWidth 1 (Transmit mailbox 0 last sending  	 in transmit FIFO)  
        .equ CAN0_TSTAT_TME2, 1 << 28   @ bitWidth 1 (Transmit mailbox 2 empty)  
        .equ CAN0_TSTAT_TME1, 1 << 27   @ bitWidth 1 (Transmit mailbox 1 empty)  
        .equ CAN0_TSTAT_TME0, 1 << 26   @ bitWidth 1 (Transmit mailbox 0 empty)  
        .equ CAN0_TSTAT_NUM_Shift, 24   @ bitWidth 2 (number of the transmit FIFO mailbox in  	 which the frame will be transmitted if at least one mailbox is empty)  
        .equ CAN0_TSTAT_MST2, 1 << 23   @ bitWidth 1 (Mailbox 2 stop transmitting)  
        .equ CAN0_TSTAT_MTE2, 1 << 19   @ bitWidth 1 (Mailbox 2 transmit error)  
        .equ CAN0_TSTAT_MAL2, 1 << 18   @ bitWidth 1 (Mailbox 2 arbitration lost)  
        .equ CAN0_TSTAT_MTFNERR2, 1 << 17   @ bitWidth 1 (Mailbox 2 transmit finished and no error)  
        .equ CAN0_TSTAT_MTF2, 1 << 16   @ bitWidth 1 (Mailbox 2 transmit finished)  
        .equ CAN0_TSTAT_MST1, 1 << 15   @ bitWidth 1 (Mailbox 1 stop transmitting)  
        .equ CAN0_TSTAT_MTE1, 1 << 11   @ bitWidth 1 (Mailbox 1 transmit error)  
        .equ CAN0_TSTAT_MAL1, 1 << 10   @ bitWidth 1 (Mailbox 1 arbitration lost)  
        .equ CAN0_TSTAT_MTFNERR1, 1 << 9   @ bitWidth 1 (Mailbox 1 transmit finished and no error)  
        .equ CAN0_TSTAT_MTF1, 1 << 8   @ bitWidth 1 (Mailbox 1 transmit finished)  
        .equ CAN0_TSTAT_MST0, 1 << 7   @ bitWidth 1 (Mailbox 0 stop transmitting)  
        .equ CAN0_TSTAT_MTE0, 1 << 3   @ bitWidth 1 (Mailbox 0 transmit error)  
        .equ CAN0_TSTAT_MAL0, 1 << 2   @ bitWidth 1 (Mailbox 0 arbitration lost)  
        .equ CAN0_TSTAT_MTFNERR0, 1 << 1   @ bitWidth 1 (Mailbox 0 transmit finished and no error)  
        .equ CAN0_TSTAT_MTF0, 1 << 0   @ bitWidth 1 (Mailbox 0 transmit finished)  
 
    .equ CAN0_RFIFO0, CAN0_BASE + 0x0C @ (Receive message FIFO0 register) 
        .equ CAN0_RFIFO0_RFD0, 1 << 5   @ bitWidth 1 (Receive FIFO0 dequeue)  
        .equ CAN0_RFIFO0_RFO0, 1 << 4   @ bitWidth 1 (Receive FIFO0 overfull)  
        .equ CAN0_RFIFO0_RFF0, 1 << 3   @ bitWidth 1 (Receive FIFO0 full)  
        .equ CAN0_RFIFO0_RFL0_Shift, 0   @ bitWidth 2 (Receive FIFO0 length)  
 
    .equ CAN0_RFIFO1, CAN0_BASE + 0x10 @ (Receive message FIFO1 register) 
        .equ CAN0_RFIFO1_RFD1, 1 << 5   @ bitWidth 1 (Receive FIFO1 dequeue)  
        .equ CAN0_RFIFO1_RFO1, 1 << 4   @ bitWidth 1 (Receive FIFO1 overfull)  
        .equ CAN0_RFIFO1_RFF1, 1 << 3   @ bitWidth 1 (Receive FIFO1 full)  
        .equ CAN0_RFIFO1_RFL1_Shift, 0   @ bitWidth 2 (Receive FIFO1 length)  
 
    .equ CAN0_INTEN, CAN0_BASE + 0x14 @ (Interrupt enable register) 
        .equ CAN0_INTEN_SLPWIE, 1 << 17   @ bitWidth 1 (Sleep working interrupt enable)  
        .equ CAN0_INTEN_WIE, 1 << 16   @ bitWidth 1 (Wakeup interrupt enable)  
        .equ CAN0_INTEN_ERRIE, 1 << 15   @ bitWidth 1 (Error interrupt enable)  
        .equ CAN0_INTEN_ERRNIE, 1 << 11   @ bitWidth 1 (Error number interrupt enable)  
        .equ CAN0_INTEN_BOIE, 1 << 10   @ bitWidth 1 (Bus-off interrupt enable)  
        .equ CAN0_INTEN_PERRIE, 1 << 9   @ bitWidth 1 (Passive error interrupt enable)  
        .equ CAN0_INTEN_WERRIE, 1 << 8   @ bitWidth 1 (Warning error interrupt enable)  
        .equ CAN0_INTEN_RFOIE1, 1 << 6   @ bitWidth 1 (Receive FIFO1 overfull interrupt enable)  
        .equ CAN0_INTEN_RFFIE1, 1 << 5   @ bitWidth 1 (Receive FIFO1 full interrupt enable)  
        .equ CAN0_INTEN_RFNEIE1, 1 << 4   @ bitWidth 1 (Receive FIFO1 not empty interrupt enable)  
        .equ CAN0_INTEN_RFOIE0, 1 << 3   @ bitWidth 1 (Receive FIFO0 overfull interrupt enable)  
        .equ CAN0_INTEN_RFFIE0, 1 << 2   @ bitWidth 1 (Receive FIFO0 full interrupt enable)  
        .equ CAN0_INTEN_RFNEIE0, 1 << 1   @ bitWidth 1 (Receive FIFO0 not empty interrupt enable)  
        .equ CAN0_INTEN_TMEIE, 1 << 0   @ bitWidth 1 (Transmit mailbox empty interrupt enable)  
 
    .equ CAN0_ERR, CAN0_BASE + 0x18 @ (Error register) 
        .equ CAN0_ERR_RECNT_Shift, 24   @ bitWidth 8 (Receive Error Count defined  	 by the CAN standard)  
        .equ CAN0_ERR_TECNT_Shift, 16   @ bitWidth 8 (Transmit Error Count defined  	 by the CAN standard)  
        .equ CAN0_ERR_ERRN_Shift, 4   @ bitWidth 3 (Error number)  
        .equ CAN0_ERR_BOERR, 1 << 2   @ bitWidth 1 (Bus-off error)  
        .equ CAN0_ERR_PERR, 1 << 1   @ bitWidth 1 (Passive error)  
        .equ CAN0_ERR_WERR, 1 << 0   @ bitWidth 1 (Warning error)  
 
    .equ CAN0_BT, CAN0_BASE + 0x1C @ (Bit timing register) 
        .equ CAN0_BT_SCMOD, 1 << 31   @ bitWidth 1 (Silent communication mode)  
        .equ CAN0_BT_LCMOD, 1 << 30   @ bitWidth 1 (Loopback communication mode)  
        .equ CAN0_BT_SJW_Shift, 24   @ bitWidth 2 (Resynchronization jump width)  
        .equ CAN0_BT_BS2_Shift, 20   @ bitWidth 3 (Bit segment 2)  
        .equ CAN0_BT_BS1_Shift, 16   @ bitWidth 4 (Bit segment 1)  
        .equ CAN0_BT_BAUDPSC_Shift, 0   @ bitWidth 10 (Baud rate prescaler)  
 
    .equ CAN0_TMI0, CAN0_BASE + 0x180 @ (Transmit mailbox identifier register 0) 
        .equ CAN0_TMI0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_TMI0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_TMI0_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_TMI0_FT, 1 << 1   @ bitWidth 1 (Frame type)  
        .equ CAN0_TMI0_TEN, 1 << 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN0_TMP0, CAN0_BASE + 0x184 @ (Transmit mailbox property register 0) 
        .equ CAN0_TMP0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_TMP0_TSEN, 1 << 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN0_TMP0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_TMDATA00, CAN0_BASE + 0x188 @ (Transmit mailbox data0 register) 
        .equ CAN0_TMDATA00_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_TMDATA00_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_TMDATA00_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_TMDATA00_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_TMDATA10, CAN0_BASE + 0x18C @ (Transmit mailbox data1 register) 
        .equ CAN0_TMDATA10_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_TMDATA10_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_TMDATA10_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_TMDATA10_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_TMI1, CAN0_BASE + 0x190 @ (Transmit mailbox identifier register 1) 
        .equ CAN0_TMI1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_TMI1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_TMI1_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_TMI1_FT, 1 << 1   @ bitWidth 1 (Frame type)  
        .equ CAN0_TMI1_TEN, 1 << 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN0_TMP1, CAN0_BASE + 0x194 @ (Transmit mailbox property register 1) 
        .equ CAN0_TMP1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_TMP1_TSEN, 1 << 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN0_TMP1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_TMDATA01, CAN0_BASE + 0x198 @ (Transmit mailbox data0 register) 
        .equ CAN0_TMDATA01_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_TMDATA01_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_TMDATA01_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_TMDATA01_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_TMDATA11, CAN0_BASE + 0x19C @ (Transmit mailbox data1 register) 
        .equ CAN0_TMDATA11_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_TMDATA11_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_TMDATA11_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_TMDATA11_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_TMI2, CAN0_BASE + 0x1A0 @ (Transmit mailbox identifier register 2) 
        .equ CAN0_TMI2_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_TMI2_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_TMI2_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_TMI2_FT, 1 << 1   @ bitWidth 1 (Frame type)  
        .equ CAN0_TMI2_TEN, 1 << 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN0_TMP2, CAN0_BASE + 0x1A4 @ (Transmit mailbox property register 2) 
        .equ CAN0_TMP2_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_TMP2_TSEN, 1 << 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN0_TMP2_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_TMDATA02, CAN0_BASE + 0x1A8 @ (Transmit mailbox data0 register) 
        .equ CAN0_TMDATA02_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_TMDATA02_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_TMDATA02_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_TMDATA02_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_TMDATA12, CAN0_BASE + 0x1AC @ (Transmit mailbox data1 register) 
        .equ CAN0_TMDATA12_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_TMDATA12_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_TMDATA12_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_TMDATA12_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_RFIFOMI0, CAN0_BASE + 0x1B0 @ (Receive FIFO mailbox identifier register) 
        .equ CAN0_RFIFOMI0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_RFIFOMI0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_RFIFOMI0_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_RFIFOMI0_FT, 1 << 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN0_RFIFOMP0, CAN0_BASE + 0x1B4 @ (Receive FIFO0 mailbox property register) 
        .equ CAN0_RFIFOMP0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_RFIFOMP0_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN0_RFIFOMP0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_RFIFOMDATA00, CAN0_BASE + 0x1B8 @ (Receive FIFO0 mailbox data0 register) 
        .equ CAN0_RFIFOMDATA00_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_RFIFOMDATA00_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_RFIFOMDATA00_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_RFIFOMDATA00_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_RFIFOMDATA10, CAN0_BASE + 0x1BC @ (Receive FIFO0 mailbox data1 register) 
        .equ CAN0_RFIFOMDATA10_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_RFIFOMDATA10_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_RFIFOMDATA10_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_RFIFOMDATA10_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_RFIFOMI1, CAN0_BASE + 0x1C0 @ (Receive FIFO1 mailbox identifier register) 
        .equ CAN0_RFIFOMI1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN0_RFIFOMI1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN0_RFIFOMI1_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN0_RFIFOMI1_FT, 1 << 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN0_RFIFOMP1, CAN0_BASE + 0x1C4 @ (Receive FIFO1 mailbox property register) 
        .equ CAN0_RFIFOMP1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN0_RFIFOMP1_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN0_RFIFOMP1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN0_RFIFOMDATA01, CAN0_BASE + 0x1C8 @ (Receive FIFO1 mailbox data0 register) 
        .equ CAN0_RFIFOMDATA01_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN0_RFIFOMDATA01_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN0_RFIFOMDATA01_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN0_RFIFOMDATA01_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN0_RFIFOMDATA11, CAN0_BASE + 0x1CC @ (Receive FIFO1 mailbox data1 register) 
        .equ CAN0_RFIFOMDATA11_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN0_RFIFOMDATA11_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN0_RFIFOMDATA11_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN0_RFIFOMDATA11_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN0_FCTL, CAN0_BASE + 0x200 @ (Filter control register) 
        .equ CAN0_FCTL_HBC1F_Shift, 8   @ bitWidth 6 (Header bank of CAN1 filter)  
        .equ CAN0_FCTL_FLD, 1 << 0   @ bitWidth 1 (Filter lock disable)  
 
    .equ CAN0_FMCFG, CAN0_BASE + 0x204 @ (Filter mode configuration register) 
        .equ CAN0_FMCFG_FMOD27, 1 << 27   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD26, 1 << 26   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD25, 1 << 25   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD24, 1 << 24   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD23, 1 << 23   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD22, 1 << 22   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD21, 1 << 21   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD20, 1 << 20   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD19, 1 << 19   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD18, 1 << 18   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD17, 1 << 17   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD16, 1 << 16   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD15, 1 << 15   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD14, 1 << 14   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD13, 1 << 13   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD12, 1 << 12   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD11, 1 << 11   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD10, 1 << 10   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD9, 1 << 9   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD8, 1 << 8   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD7, 1 << 7   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD6, 1 << 6   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD5, 1 << 5   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD4, 1 << 4   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD3, 1 << 3   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD2, 1 << 2   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD1, 1 << 1   @ bitWidth 1 (Filter mode)  
        .equ CAN0_FMCFG_FMOD0, 1 << 0   @ bitWidth 1 (Filter mode)  
 
    .equ CAN0_FSCFG, CAN0_BASE + 0x20C @ (Filter scale configuration register) 
        .equ CAN0_FSCFG_FS0, 1 << 0   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS1, 1 << 1   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS2, 1 << 2   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS3, 1 << 3   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS4, 1 << 4   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS5, 1 << 5   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS6, 1 << 6   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS7, 1 << 7   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS8, 1 << 8   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS9, 1 << 9   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS10, 1 << 10   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS11, 1 << 11   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS12, 1 << 12   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS13, 1 << 13   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS14, 1 << 14   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS15, 1 << 15   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS16, 1 << 16   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS17, 1 << 17   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS18, 1 << 18   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS19, 1 << 19   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS20, 1 << 20   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS21, 1 << 21   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS22, 1 << 22   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS23, 1 << 23   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS24, 1 << 24   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS25, 1 << 25   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS26, 1 << 26   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN0_FSCFG_FS27, 1 << 27   @ bitWidth 1 (Filter scale configuration)  
 
    .equ CAN0_FAFIFO, CAN0_BASE + 0x214 @ (Filter associated FIFO register) 
        .equ CAN0_FAFIFO_FAF0, 1 << 0   @ bitWidth 1 (Filter 0 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF1, 1 << 1   @ bitWidth 1 (Filter 1 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF2, 1 << 2   @ bitWidth 1 (Filter 2 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF3, 1 << 3   @ bitWidth 1 (Filter 3 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF4, 1 << 4   @ bitWidth 1 (Filter 4 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF5, 1 << 5   @ bitWidth 1 (Filter 5 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF6, 1 << 6   @ bitWidth 1 (Filter 6 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF7, 1 << 7   @ bitWidth 1 (Filter 7 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF8, 1 << 8   @ bitWidth 1 (Filter 8 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF9, 1 << 9   @ bitWidth 1 (Filter 9 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF10, 1 << 10   @ bitWidth 1 (Filter 10 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF11, 1 << 11   @ bitWidth 1 (Filter 11 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF12, 1 << 12   @ bitWidth 1 (Filter 12 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF13, 1 << 13   @ bitWidth 1 (Filter 13 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF14, 1 << 14   @ bitWidth 1 (Filter 14 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF15, 1 << 15   @ bitWidth 1 (Filter 15 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF16, 1 << 16   @ bitWidth 1 (Filter 16 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF17, 1 << 17   @ bitWidth 1 (Filter 17 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF18, 1 << 18   @ bitWidth 1 (Filter 18 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF19, 1 << 19   @ bitWidth 1 (Filter 19 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF20, 1 << 20   @ bitWidth 1 (Filter 20 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF21, 1 << 21   @ bitWidth 1 (Filter 21 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF22, 1 << 22   @ bitWidth 1 (Filter 22 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF23, 1 << 23   @ bitWidth 1 (Filter 23 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF24, 1 << 24   @ bitWidth 1 (Filter 24 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF25, 1 << 25   @ bitWidth 1 (Filter 25 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF26, 1 << 26   @ bitWidth 1 (Filter 26 associated with FIFO)  
        .equ CAN0_FAFIFO_FAF27, 1 << 27   @ bitWidth 1 (Filter 27 associated with FIFO)  
 
    .equ CAN0_FW, CAN0_BASE + 0x21C @ (Filter working register) 
        .equ CAN0_FW_FW0, 1 << 0   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW1, 1 << 1   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW2, 1 << 2   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW3, 1 << 3   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW4, 1 << 4   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW5, 1 << 5   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW6, 1 << 6   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW7, 1 << 7   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW8, 1 << 8   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW9, 1 << 9   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW10, 1 << 10   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW11, 1 << 11   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW12, 1 << 12   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW13, 1 << 13   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW14, 1 << 14   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW15, 1 << 15   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW16, 1 << 16   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW17, 1 << 17   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW18, 1 << 18   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW19, 1 << 19   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW20, 1 << 20   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW21, 1 << 21   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW22, 1 << 22   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW23, 1 << 23   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW24, 1 << 24   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW25, 1 << 25   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW26, 1 << 26   @ bitWidth 1 (Filter working)  
        .equ CAN0_FW_FW27, 1 << 27   @ bitWidth 1 (Filter working)  
 
    .equ CAN0_F0DATA0, CAN0_BASE + 0x240 @ (Filter 0 data 0 register) 
        .equ CAN0_F0DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F0DATA1, CAN0_BASE + 0x244 @ (Filter 0 data 1 register) 
        .equ CAN0_F0DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F0DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F1DATA0, CAN0_BASE + 0x248 @ (Filter 1 data 0 register) 
        .equ CAN0_F1DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F1DATA1, CAN0_BASE + 0x24C @ (Filter 1 data 1 register) 
        .equ CAN0_F1DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F1DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F2DATA0, CAN0_BASE + 0x250 @ (Filter 2 data 0 register) 
        .equ CAN0_F2DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F2DATA1, CAN0_BASE + 0x254 @ (Filter 2 data 1 register) 
        .equ CAN0_F2DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F2DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F3DATA0, CAN0_BASE + 0x258 @ (Filter 3 data 0 register) 
        .equ CAN0_F3DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F3DATA1, CAN0_BASE + 0x25C @ (Filter 3 data 1 register) 
        .equ CAN0_F3DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F3DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F4DATA0, CAN0_BASE + 0x260 @ (Filter 4 data 0 register) 
        .equ CAN0_F4DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F4DATA1, CAN0_BASE + 0x264 @ (Filter 4 data 1 register) 
        .equ CAN0_F4DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F4DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F5DATA0, CAN0_BASE + 0x268 @ (Filter 5 data 0 register) 
        .equ CAN0_F5DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F5DATA1, CAN0_BASE + 0x26C @ (Filter 5 data 1 register) 
        .equ CAN0_F5DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F5DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F6DATA0, CAN0_BASE + 0x270 @ (Filter 6 data 0 register) 
        .equ CAN0_F6DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F6DATA1, CAN0_BASE + 0x274 @ (Filter 6 data 1 register) 
        .equ CAN0_F6DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F6DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F7DATA0, CAN0_BASE + 0x278 @ (Filter 7 data 0 register) 
        .equ CAN0_F7DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F7DATA1, CAN0_BASE + 0x27C @ (Filter 7 data 1 register) 
        .equ CAN0_F7DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F7DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F8DATA0, CAN0_BASE + 0x280 @ (Filter 8 data 0 register) 
        .equ CAN0_F8DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F8DATA1, CAN0_BASE + 0x284 @ (Filter 8 data 1 register) 
        .equ CAN0_F8DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F8DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F9DATA0, CAN0_BASE + 0x288 @ (Filter 9 data 0 register) 
        .equ CAN0_F9DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F9DATA1, CAN0_BASE + 0x28C @ (Filter 9 data 1 register) 
        .equ CAN0_F9DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F9DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F10DATA0, CAN0_BASE + 0x290 @ (Filter 10 data 0 register) 
        .equ CAN0_F10DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F10DATA1, CAN0_BASE + 0x294 @ (Filter 10 data 1 register) 
        .equ CAN0_F10DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F10DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F11DATA0, CAN0_BASE + 0x298 @ (Filter 11 data 0 register) 
        .equ CAN0_F11DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F11DATA1, CAN0_BASE + 0x29C @ (Filter 11 data 1 register) 
        .equ CAN0_F11DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F11DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F12DATA0, CAN0_BASE + 0x2A0 @ (Filter 12 data 0 register) 
        .equ CAN0_F12DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F12DATA1, CAN0_BASE + 0x2A4 @ (Filter 12 data 1 register) 
        .equ CAN0_F12DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F12DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F13DATA0, CAN0_BASE + 0x2A8 @ (Filter 13 data 0 register) 
        .equ CAN0_F13DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F13DATA1, CAN0_BASE + 0x2AC @ (Filter 13 data 1 register) 
        .equ CAN0_F13DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F13DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F14DATA0, CAN0_BASE + 0x2B0 @ (Filter 14 data 0 register) 
        .equ CAN0_F14DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F14DATA1, CAN0_BASE + 0x2B4 @ (Filter 14 data 1 register) 
        .equ CAN0_F14DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F14DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F15DATA0, CAN0_BASE + 0x2B8 @ (Filter 15 data 0 register) 
        .equ CAN0_F15DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F15DATA1, CAN0_BASE + 0x2BC @ (Filter 15 data 1 register) 
        .equ CAN0_F15DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F15DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F16DATA0, CAN0_BASE + 0x2C0 @ (Filter 16 data 0 register) 
        .equ CAN0_F16DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F16DATA1, CAN0_BASE + 0x2C4 @ (Filter 16 data 1 register) 
        .equ CAN0_F16DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F16DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F17DATA0, CAN0_BASE + 0x2C8 @ (Filter 17 data 0 register) 
        .equ CAN0_F17DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F17DATA1, CAN0_BASE + 0x2CC @ (Filter 17 data 1 register) 
        .equ CAN0_F17DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F17DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F18DATA0, CAN0_BASE + 0x2D0 @ (Filter 18 data 0 register) 
        .equ CAN0_F18DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F18DATA1, CAN0_BASE + 0x2D4 @ (Filter 18 data 1 register) 
        .equ CAN0_F18DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F18DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F19DATA0, CAN0_BASE + 0x2D8 @ (Filter 19 data 0 register) 
        .equ CAN0_F19DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F19DATA1, CAN0_BASE + 0x2DC @ (Filter 19 data 1 register) 
        .equ CAN0_F19DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F19DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F20DATA0, CAN0_BASE + 0x2E0 @ (Filter 20 data 0 register) 
        .equ CAN0_F20DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F20DATA1, CAN0_BASE + 0x2E4 @ (Filter 20 data 1 register) 
        .equ CAN0_F20DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F20DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F21DATA0, CAN0_BASE + 0x2E8 @ (Filter 21 data 0 register) 
        .equ CAN0_F21DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F21DATA1, CAN0_BASE + 0x2EC @ (Filter 21 data 1 register) 
        .equ CAN0_F21DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F21DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F22DATA0, CAN0_BASE + 0x2F0 @ (Filter 22 data 0 register) 
        .equ CAN0_F22DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F22DATA1, CAN0_BASE + 0x2F4 @ (Filter 22 data 1 register) 
        .equ CAN0_F22DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F22DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F23DATA0, CAN0_BASE + 0x2F8 @ (Filter 23 data 0 register) 
        .equ CAN0_F23DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F23DATA1, CAN0_BASE + 0x2FC @ (Filter 23 data 1 register) 
        .equ CAN0_F23DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F23DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F24DATA0, CAN0_BASE + 0x300 @ (Filter 24 data 0 register) 
        .equ CAN0_F24DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F24DATA1, CAN0_BASE + 0x304 @ (Filter 24 data 1 register) 
        .equ CAN0_F24DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F24DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F25DATA0, CAN0_BASE + 0x308 @ (Filter 25 data 0 register) 
        .equ CAN0_F25DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F25DATA1, CAN0_BASE + 0x30C @ (Filter 25 data 1 register) 
        .equ CAN0_F25DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F25DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F26DATA0, CAN0_BASE + 0x310 @ (Filter 26 data 0 register) 
        .equ CAN0_F26DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F26DATA1, CAN0_BASE + 0x314 @ (Filter 26 data 1 register) 
        .equ CAN0_F26DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F26DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F27DATA0, CAN0_BASE + 0x318 @ (Filter 27 data 0 register) 
        .equ CAN0_F27DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN0_F27DATA1, CAN0_BASE + 0x31C @ (Filter 27 data 1 register) 
        .equ CAN0_F27DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN0_F27DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 

@=========================== CAN1 ===========================@
.equ CAN1_BASE, 0x40006800 @ (Controller area network) 
    .equ CAN1_CTL, CAN1_BASE + 0x0 @ (Control register) 
        .equ CAN1_CTL_DFZ, 1 << 16   @ bitWidth 1 (Debug freeze)  
        .equ CAN1_CTL_SWRST, 1 << 15   @ bitWidth 1 (Software reset)  
        .equ CAN1_CTL_TTC, 1 << 7   @ bitWidth 1 (Time-triggered communication)  
        .equ CAN1_CTL_ABOR, 1 << 6   @ bitWidth 1 (Automatic bus-off recovery)  
        .equ CAN1_CTL_AWU, 1 << 5   @ bitWidth 1 (Automatic wakeup)  
        .equ CAN1_CTL_ARD, 1 << 4   @ bitWidth 1 (Automatic retransmission disable)  
        .equ CAN1_CTL_RFOD, 1 << 3   @ bitWidth 1 (Receive FIFO overwrite disable)  
        .equ CAN1_CTL_TFO, 1 << 2   @ bitWidth 1 (Transmit FIFO order)  
        .equ CAN1_CTL_SLPWMOD, 1 << 1   @ bitWidth 1 (Sleep working mode)  
        .equ CAN1_CTL_IWMOD, 1 << 0   @ bitWidth 1 (Initial working mode)  
 
    .equ CAN1_STAT, CAN1_BASE + 0x04 @ (Status register) 
        .equ CAN1_STAT_RXL, 1 << 11   @ bitWidth 1 (RX level)  
        .equ CAN1_STAT_LASTRX, 1 << 10   @ bitWidth 1 (Last sample value of RX pin)  
        .equ CAN1_STAT_RS, 1 << 9   @ bitWidth 1 (Receiving state)  
        .equ CAN1_STAT_TS, 1 << 8   @ bitWidth 1 (Transmitting state)  
        .equ CAN1_STAT_SLPIF, 1 << 4   @ bitWidth 1 (Status change interrupt flag of sleep  	 working mode entering)  
        .equ CAN1_STAT_WUIF, 1 << 3   @ bitWidth 1 (Status change interrupt flag of wakeup  	 from sleep working mode)  
        .equ CAN1_STAT_ERRIF, 1 << 2   @ bitWidth 1 (Error interrupt flag)  
        .equ CAN1_STAT_SLPWS, 1 << 1   @ bitWidth 1 (Sleep working state)  
        .equ CAN1_STAT_IWS, 1 << 0   @ bitWidth 1 (Initial working state)  
 
    .equ CAN1_TSTAT, CAN1_BASE + 0x8 @ (Transmit status register) 
        .equ CAN1_TSTAT_TMLS2, 1 << 31   @ bitWidth 1 (Transmit mailbox 2 last sending  	 in transmit FIFO)  
        .equ CAN1_TSTAT_TMLS1, 1 << 30   @ bitWidth 1 (Transmit mailbox 1 last sending  	 in transmit FIFO)  
        .equ CAN1_TSTAT_TMLS0, 1 << 29   @ bitWidth 1 (Transmit mailbox 0 last sending  	 in transmit FIFO)  
        .equ CAN1_TSTAT_TME2, 1 << 28   @ bitWidth 1 (Transmit mailbox 2 empty)  
        .equ CAN1_TSTAT_TME1, 1 << 27   @ bitWidth 1 (Transmit mailbox 1 empty)  
        .equ CAN1_TSTAT_TME0, 1 << 26   @ bitWidth 1 (Transmit mailbox 0 empty)  
        .equ CAN1_TSTAT_NUM_Shift, 24   @ bitWidth 2 (number of the transmit FIFO mailbox in  	 which the frame will be transmitted if at least one mailbox is empty)  
        .equ CAN1_TSTAT_MST2, 1 << 23   @ bitWidth 1 (Mailbox 2 stop transmitting)  
        .equ CAN1_TSTAT_MTE2, 1 << 19   @ bitWidth 1 (Mailbox 2 transmit error)  
        .equ CAN1_TSTAT_MAL2, 1 << 18   @ bitWidth 1 (Mailbox 2 arbitration lost)  
        .equ CAN1_TSTAT_MTFNERR2, 1 << 17   @ bitWidth 1 (Mailbox 2 transmit finished and no error)  
        .equ CAN1_TSTAT_MTF2, 1 << 16   @ bitWidth 1 (Mailbox 2 transmit finished)  
        .equ CAN1_TSTAT_MST1, 1 << 15   @ bitWidth 1 (Mailbox 1 stop transmitting)  
        .equ CAN1_TSTAT_MTE1, 1 << 11   @ bitWidth 1 (Mailbox 1 transmit error)  
        .equ CAN1_TSTAT_MAL1, 1 << 10   @ bitWidth 1 (Mailbox 1 arbitration lost)  
        .equ CAN1_TSTAT_MTFNERR1, 1 << 9   @ bitWidth 1 (Mailbox 1 transmit finished and no error)  
        .equ CAN1_TSTAT_MTF1, 1 << 8   @ bitWidth 1 (Mailbox 1 transmit finished)  
        .equ CAN1_TSTAT_MST0, 1 << 7   @ bitWidth 1 (Mailbox 0 stop transmitting)  
        .equ CAN1_TSTAT_MTE0, 1 << 3   @ bitWidth 1 (Mailbox 0 transmit error)  
        .equ CAN1_TSTAT_MAL0, 1 << 2   @ bitWidth 1 (Mailbox 0 arbitration lost)  
        .equ CAN1_TSTAT_MTFNERR0, 1 << 1   @ bitWidth 1 (Mailbox 0 transmit finished and no error)  
        .equ CAN1_TSTAT_MTF0, 1 << 0   @ bitWidth 1 (Mailbox 0 transmit finished)  
 
    .equ CAN1_RFIFO0, CAN1_BASE + 0x0C @ (Receive message FIFO0 register) 
        .equ CAN1_RFIFO0_RFD0, 1 << 5   @ bitWidth 1 (Receive FIFO0 dequeue)  
        .equ CAN1_RFIFO0_RFO0, 1 << 4   @ bitWidth 1 (Receive FIFO0 overfull)  
        .equ CAN1_RFIFO0_RFF0, 1 << 3   @ bitWidth 1 (Receive FIFO0 full)  
        .equ CAN1_RFIFO0_RFL0_Shift, 0   @ bitWidth 2 (Receive FIFO0 length)  
 
    .equ CAN1_RFIFO1, CAN1_BASE + 0x10 @ (Receive message FIFO1 register) 
        .equ CAN1_RFIFO1_RFD1, 1 << 5   @ bitWidth 1 (Receive FIFO1 dequeue)  
        .equ CAN1_RFIFO1_RFO1, 1 << 4   @ bitWidth 1 (Receive FIFO1 overfull)  
        .equ CAN1_RFIFO1_RFF1, 1 << 3   @ bitWidth 1 (Receive FIFO1 full)  
        .equ CAN1_RFIFO1_RFL1_Shift, 0   @ bitWidth 2 (Receive FIFO1 length)  
 
    .equ CAN1_INTEN, CAN1_BASE + 0x14 @ (Interrupt enable register) 
        .equ CAN1_INTEN_SLPWIE, 1 << 17   @ bitWidth 1 (Sleep working interrupt enable)  
        .equ CAN1_INTEN_WIE, 1 << 16   @ bitWidth 1 (Wakeup interrupt enable)  
        .equ CAN1_INTEN_ERRIE, 1 << 15   @ bitWidth 1 (Error interrupt enable)  
        .equ CAN1_INTEN_ERRNIE, 1 << 11   @ bitWidth 1 (Error number interrupt enable)  
        .equ CAN1_INTEN_BOIE, 1 << 10   @ bitWidth 1 (Bus-off interrupt enable)  
        .equ CAN1_INTEN_PERRIE, 1 << 9   @ bitWidth 1 (Passive error interrupt enable)  
        .equ CAN1_INTEN_WERRIE, 1 << 8   @ bitWidth 1 (Warning error interrupt enable)  
        .equ CAN1_INTEN_RFOIE1, 1 << 6   @ bitWidth 1 (Receive FIFO1 overfull interrupt enable)  
        .equ CAN1_INTEN_RFFIE1, 1 << 5   @ bitWidth 1 (Receive FIFO1 full interrupt enable)  
        .equ CAN1_INTEN_RFNEIE1, 1 << 4   @ bitWidth 1 (Receive FIFO1 not empty interrupt enable)  
        .equ CAN1_INTEN_RFOIE0, 1 << 3   @ bitWidth 1 (Receive FIFO0 overfull interrupt enable)  
        .equ CAN1_INTEN_RFFIE0, 1 << 2   @ bitWidth 1 (Receive FIFO0 full interrupt enable)  
        .equ CAN1_INTEN_RFNEIE0, 1 << 1   @ bitWidth 1 (Receive FIFO0 not empty interrupt enable)  
        .equ CAN1_INTEN_TMEIE, 1 << 0   @ bitWidth 1 (Transmit mailbox empty interrupt enable)  
 
    .equ CAN1_ERR, CAN1_BASE + 0x18 @ (Error register) 
        .equ CAN1_ERR_RECNT_Shift, 24   @ bitWidth 8 (Receive Error Count defined  	 by the CAN standard)  
        .equ CAN1_ERR_TECNT_Shift, 16   @ bitWidth 8 (Transmit Error Count defined  	 by the CAN standard)  
        .equ CAN1_ERR_ERRN_Shift, 4   @ bitWidth 3 (Error number)  
        .equ CAN1_ERR_BOERR, 1 << 2   @ bitWidth 1 (Bus-off error)  
        .equ CAN1_ERR_PERR, 1 << 1   @ bitWidth 1 (Passive error)  
        .equ CAN1_ERR_WERR, 1 << 0   @ bitWidth 1 (Warning error)  
 
    .equ CAN1_BT, CAN1_BASE + 0x1C @ (Bit timing register) 
        .equ CAN1_BT_SCMOD, 1 << 31   @ bitWidth 1 (Silent communication mode)  
        .equ CAN1_BT_LCMOD, 1 << 30   @ bitWidth 1 (Loopback communication mode)  
        .equ CAN1_BT_SJW_Shift, 24   @ bitWidth 2 (Resynchronization jump width)  
        .equ CAN1_BT_BS2_Shift, 20   @ bitWidth 3 (Bit segment 2)  
        .equ CAN1_BT_BS1_Shift, 16   @ bitWidth 4 (Bit segment 1)  
        .equ CAN1_BT_BAUDPSC_Shift, 0   @ bitWidth 10 (Baud rate prescaler)  
 
    .equ CAN1_TMI0, CAN1_BASE + 0x180 @ (Transmit mailbox identifier register 0) 
        .equ CAN1_TMI0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_TMI0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_TMI0_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_TMI0_FT, 1 << 1   @ bitWidth 1 (Frame type)  
        .equ CAN1_TMI0_TEN, 1 << 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN1_TMP0, CAN1_BASE + 0x184 @ (Transmit mailbox property register 0) 
        .equ CAN1_TMP0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_TMP0_TSEN, 1 << 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN1_TMP0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_TMDATA00, CAN1_BASE + 0x188 @ (Transmit mailbox data0 register) 
        .equ CAN1_TMDATA00_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_TMDATA00_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_TMDATA00_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_TMDATA00_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_TMDATA10, CAN1_BASE + 0x18C @ (Transmit mailbox data1 register) 
        .equ CAN1_TMDATA10_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_TMDATA10_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_TMDATA10_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_TMDATA10_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_TMI1, CAN1_BASE + 0x190 @ (Transmit mailbox identifier register 1) 
        .equ CAN1_TMI1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_TMI1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_TMI1_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_TMI1_FT, 1 << 1   @ bitWidth 1 (Frame type)  
        .equ CAN1_TMI1_TEN, 1 << 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN1_TMP1, CAN1_BASE + 0x194 @ (Transmit mailbox property register 1) 
        .equ CAN1_TMP1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_TMP1_TSEN, 1 << 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN1_TMP1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_TMDATA01, CAN1_BASE + 0x198 @ (Transmit mailbox data0 register) 
        .equ CAN1_TMDATA01_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_TMDATA01_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_TMDATA01_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_TMDATA01_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_TMDATA11, CAN1_BASE + 0x19C @ (Transmit mailbox data1 register) 
        .equ CAN1_TMDATA11_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_TMDATA11_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_TMDATA11_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_TMDATA11_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_TMI2, CAN1_BASE + 0x1A0 @ (Transmit mailbox identifier register 2) 
        .equ CAN1_TMI2_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_TMI2_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_TMI2_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_TMI2_FT, 1 << 1   @ bitWidth 1 (Frame type)  
        .equ CAN1_TMI2_TEN, 1 << 0   @ bitWidth 1 (Transmit enable)  
 
    .equ CAN1_TMP2, CAN1_BASE + 0x1A4 @ (Transmit mailbox property register 2) 
        .equ CAN1_TMP2_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_TMP2_TSEN, 1 << 8   @ bitWidth 1 (Time stamp enable)  
        .equ CAN1_TMP2_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_TMDATA02, CAN1_BASE + 0x1A8 @ (Transmit mailbox data0 register) 
        .equ CAN1_TMDATA02_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_TMDATA02_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_TMDATA02_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_TMDATA02_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_TMDATA12, CAN1_BASE + 0x1AC @ (Transmit mailbox data1 register) 
        .equ CAN1_TMDATA12_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_TMDATA12_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_TMDATA12_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_TMDATA12_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_RFIFOMI0, CAN1_BASE + 0x1B0 @ (Receive FIFO mailbox identifier register) 
        .equ CAN1_RFIFOMI0_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_RFIFOMI0_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_RFIFOMI0_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_RFIFOMI0_FT, 1 << 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN1_RFIFOMP0, CAN1_BASE + 0x1B4 @ (Receive FIFO0 mailbox property register) 
        .equ CAN1_RFIFOMP0_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_RFIFOMP0_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN1_RFIFOMP0_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_RFIFOMDATA00, CAN1_BASE + 0x1B8 @ (Receive FIFO0 mailbox data0 register) 
        .equ CAN1_RFIFOMDATA00_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_RFIFOMDATA00_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_RFIFOMDATA00_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_RFIFOMDATA00_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_RFIFOMDATA10, CAN1_BASE + 0x1BC @ (Receive FIFO0 mailbox data1 register) 
        .equ CAN1_RFIFOMDATA10_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_RFIFOMDATA10_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_RFIFOMDATA10_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_RFIFOMDATA10_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_RFIFOMI1, CAN1_BASE + 0x1C0 @ (Receive FIFO1 mailbox identifier register) 
        .equ CAN1_RFIFOMI1_SFID_EFID_Shift, 21   @ bitWidth 11 (The frame identifier)  
        .equ CAN1_RFIFOMI1_EFID_Shift, 3   @ bitWidth 18 (The frame identifier)  
        .equ CAN1_RFIFOMI1_FF, 1 << 2   @ bitWidth 1 (Frame format)  
        .equ CAN1_RFIFOMI1_FT, 1 << 1   @ bitWidth 1 (Frame type)  
 
    .equ CAN1_RFIFOMP1, CAN1_BASE + 0x1C4 @ (Receive FIFO1 mailbox property register) 
        .equ CAN1_RFIFOMP1_TS_Shift, 16   @ bitWidth 16 (Time stamp)  
        .equ CAN1_RFIFOMP1_FI_Shift, 8   @ bitWidth 8 (Filtering index)  
        .equ CAN1_RFIFOMP1_DLENC_Shift, 0   @ bitWidth 4 (Data length code)  
 
    .equ CAN1_RFIFOMDATA01, CAN1_BASE + 0x1C8 @ (Receive FIFO1 mailbox data0 register) 
        .equ CAN1_RFIFOMDATA01_DB3_Shift, 24   @ bitWidth 8 (Data byte 3)  
        .equ CAN1_RFIFOMDATA01_DB2_Shift, 16   @ bitWidth 8 (Data byte 2)  
        .equ CAN1_RFIFOMDATA01_DB1_Shift, 8   @ bitWidth 8 (Data byte 1)  
        .equ CAN1_RFIFOMDATA01_DB0_Shift, 0   @ bitWidth 8 (Data byte 0)  
 
    .equ CAN1_RFIFOMDATA11, CAN1_BASE + 0x1CC @ (Receive FIFO1 mailbox data1 register) 
        .equ CAN1_RFIFOMDATA11_DB7_Shift, 24   @ bitWidth 8 (Data byte 7)  
        .equ CAN1_RFIFOMDATA11_DB6_Shift, 16   @ bitWidth 8 (Data byte 6)  
        .equ CAN1_RFIFOMDATA11_DB5_Shift, 8   @ bitWidth 8 (Data byte 5)  
        .equ CAN1_RFIFOMDATA11_DB4_Shift, 0   @ bitWidth 8 (Data byte 4)  
 
    .equ CAN1_FCTL, CAN1_BASE + 0x200 @ (Filter control register) 
        .equ CAN1_FCTL_HBC1F_Shift, 8   @ bitWidth 6 (Header bank of CAN1 filter)  
        .equ CAN1_FCTL_FLD, 1 << 0   @ bitWidth 1 (Filter lock disable)  
 
    .equ CAN1_FMCFG, CAN1_BASE + 0x204 @ (Filter mode configuration register) 
        .equ CAN1_FMCFG_FMOD27, 1 << 27   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD26, 1 << 26   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD25, 1 << 25   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD24, 1 << 24   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD23, 1 << 23   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD22, 1 << 22   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD21, 1 << 21   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD20, 1 << 20   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD19, 1 << 19   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD18, 1 << 18   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD17, 1 << 17   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD16, 1 << 16   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD15, 1 << 15   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD14, 1 << 14   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD13, 1 << 13   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD12, 1 << 12   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD11, 1 << 11   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD10, 1 << 10   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD9, 1 << 9   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD8, 1 << 8   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD7, 1 << 7   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD6, 1 << 6   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD5, 1 << 5   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD4, 1 << 4   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD3, 1 << 3   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD2, 1 << 2   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD1, 1 << 1   @ bitWidth 1 (Filter mode)  
        .equ CAN1_FMCFG_FMOD0, 1 << 0   @ bitWidth 1 (Filter mode)  
 
    .equ CAN1_FSCFG, CAN1_BASE + 0x20C @ (Filter scale configuration register) 
        .equ CAN1_FSCFG_FS0, 1 << 0   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS1, 1 << 1   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS2, 1 << 2   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS3, 1 << 3   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS4, 1 << 4   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS5, 1 << 5   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS6, 1 << 6   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS7, 1 << 7   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS8, 1 << 8   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS9, 1 << 9   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS10, 1 << 10   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS11, 1 << 11   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS12, 1 << 12   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS13, 1 << 13   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS14, 1 << 14   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS15, 1 << 15   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS16, 1 << 16   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS17, 1 << 17   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS18, 1 << 18   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS19, 1 << 19   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS20, 1 << 20   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS21, 1 << 21   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS22, 1 << 22   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS23, 1 << 23   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS24, 1 << 24   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS25, 1 << 25   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS26, 1 << 26   @ bitWidth 1 (Filter scale configuration)  
        .equ CAN1_FSCFG_FS27, 1 << 27   @ bitWidth 1 (Filter scale configuration)  
 
    .equ CAN1_FAFIFO, CAN1_BASE + 0x214 @ (Filter associated FIFO register) 
        .equ CAN1_FAFIFO_FAF0, 1 << 0   @ bitWidth 1 (Filter 0 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF1, 1 << 1   @ bitWidth 1 (Filter 1 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF2, 1 << 2   @ bitWidth 1 (Filter 2 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF3, 1 << 3   @ bitWidth 1 (Filter 3 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF4, 1 << 4   @ bitWidth 1 (Filter 4 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF5, 1 << 5   @ bitWidth 1 (Filter 5 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF6, 1 << 6   @ bitWidth 1 (Filter 6 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF7, 1 << 7   @ bitWidth 1 (Filter 7 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF8, 1 << 8   @ bitWidth 1 (Filter 8 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF9, 1 << 9   @ bitWidth 1 (Filter 9 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF10, 1 << 10   @ bitWidth 1 (Filter 10 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF11, 1 << 11   @ bitWidth 1 (Filter 11 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF12, 1 << 12   @ bitWidth 1 (Filter 12 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF13, 1 << 13   @ bitWidth 1 (Filter 13 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF14, 1 << 14   @ bitWidth 1 (Filter 14 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF15, 1 << 15   @ bitWidth 1 (Filter 15 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF16, 1 << 16   @ bitWidth 1 (Filter 16 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF17, 1 << 17   @ bitWidth 1 (Filter 17 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF18, 1 << 18   @ bitWidth 1 (Filter 18 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF19, 1 << 19   @ bitWidth 1 (Filter 19 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF20, 1 << 20   @ bitWidth 1 (Filter 20 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF21, 1 << 21   @ bitWidth 1 (Filter 21 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF22, 1 << 22   @ bitWidth 1 (Filter 22 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF23, 1 << 23   @ bitWidth 1 (Filter 23 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF24, 1 << 24   @ bitWidth 1 (Filter 24 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF25, 1 << 25   @ bitWidth 1 (Filter 25 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF26, 1 << 26   @ bitWidth 1 (Filter 26 associated with FIFO)  
        .equ CAN1_FAFIFO_FAF27, 1 << 27   @ bitWidth 1 (Filter 27 associated with FIFO)  
 
    .equ CAN1_FW, CAN1_BASE + 0x21C @ (Filter working register) 
        .equ CAN1_FW_FW0, 1 << 0   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW1, 1 << 1   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW2, 1 << 2   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW3, 1 << 3   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW4, 1 << 4   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW5, 1 << 5   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW6, 1 << 6   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW7, 1 << 7   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW8, 1 << 8   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW9, 1 << 9   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW10, 1 << 10   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW11, 1 << 11   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW12, 1 << 12   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW13, 1 << 13   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW14, 1 << 14   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW15, 1 << 15   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW16, 1 << 16   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW17, 1 << 17   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW18, 1 << 18   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW19, 1 << 19   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW20, 1 << 20   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW21, 1 << 21   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW22, 1 << 22   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW23, 1 << 23   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW24, 1 << 24   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW25, 1 << 25   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW26, 1 << 26   @ bitWidth 1 (Filter working)  
        .equ CAN1_FW_FW27, 1 << 27   @ bitWidth 1 (Filter working)  
 
    .equ CAN1_F0DATA0, CAN1_BASE + 0x240 @ (Filter 0 data 0 register) 
        .equ CAN1_F0DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F0DATA1, CAN1_BASE + 0x244 @ (Filter 0 data 1 register) 
        .equ CAN1_F0DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F0DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F1DATA0, CAN1_BASE + 0x248 @ (Filter 1 data 0 register) 
        .equ CAN1_F1DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F1DATA1, CAN1_BASE + 0x24C @ (Filter 1 data 1 register) 
        .equ CAN1_F1DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F1DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F2DATA0, CAN1_BASE + 0x250 @ (Filter 2 data 0 register) 
        .equ CAN1_F2DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F2DATA1, CAN1_BASE + 0x254 @ (Filter 2 data 1 register) 
        .equ CAN1_F2DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F2DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F3DATA0, CAN1_BASE + 0x258 @ (Filter 3 data 0 register) 
        .equ CAN1_F3DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F3DATA1, CAN1_BASE + 0x25C @ (Filter 3 data 1 register) 
        .equ CAN1_F3DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F3DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F4DATA0, CAN1_BASE + 0x260 @ (Filter 4 data 0 register) 
        .equ CAN1_F4DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F4DATA1, CAN1_BASE + 0x264 @ (Filter 4 data 1 register) 
        .equ CAN1_F4DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F4DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F5DATA0, CAN1_BASE + 0x268 @ (Filter 5 data 0 register) 
        .equ CAN1_F5DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F5DATA1, CAN1_BASE + 0x26C @ (Filter 5 data 1 register) 
        .equ CAN1_F5DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F5DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F6DATA0, CAN1_BASE + 0x270 @ (Filter 6 data 0 register) 
        .equ CAN1_F6DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F6DATA1, CAN1_BASE + 0x274 @ (Filter 6 data 1 register) 
        .equ CAN1_F6DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F6DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F7DATA0, CAN1_BASE + 0x278 @ (Filter 7 data 0 register) 
        .equ CAN1_F7DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F7DATA1, CAN1_BASE + 0x27C @ (Filter 7 data 1 register) 
        .equ CAN1_F7DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F7DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F8DATA0, CAN1_BASE + 0x280 @ (Filter 8 data 0 register) 
        .equ CAN1_F8DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F8DATA1, CAN1_BASE + 0x284 @ (Filter 8 data 1 register) 
        .equ CAN1_F8DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F8DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F9DATA0, CAN1_BASE + 0x288 @ (Filter 9 data 0 register) 
        .equ CAN1_F9DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F9DATA1, CAN1_BASE + 0x28C @ (Filter 9 data 1 register) 
        .equ CAN1_F9DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F9DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F10DATA0, CAN1_BASE + 0x290 @ (Filter 10 data 0 register) 
        .equ CAN1_F10DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F10DATA1, CAN1_BASE + 0x294 @ (Filter 10 data 1 register) 
        .equ CAN1_F10DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F10DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F11DATA0, CAN1_BASE + 0x298 @ (Filter 11 data 0 register) 
        .equ CAN1_F11DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F11DATA1, CAN1_BASE + 0x29C @ (Filter 11 data 1 register) 
        .equ CAN1_F11DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F11DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F12DATA0, CAN1_BASE + 0x2A0 @ (Filter 12 data 0 register) 
        .equ CAN1_F12DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F12DATA1, CAN1_BASE + 0x2A4 @ (Filter 12 data 1 register) 
        .equ CAN1_F12DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F12DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F13DATA0, CAN1_BASE + 0x2A8 @ (Filter 13 data 0 register) 
        .equ CAN1_F13DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F13DATA1, CAN1_BASE + 0x2AC @ (Filter 13 data 1 register) 
        .equ CAN1_F13DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F13DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F14DATA0, CAN1_BASE + 0x2B0 @ (Filter 14 data 0 register) 
        .equ CAN1_F14DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F14DATA1, CAN1_BASE + 0x2B4 @ (Filter 14 data 1 register) 
        .equ CAN1_F14DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F14DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F15DATA0, CAN1_BASE + 0x2B8 @ (Filter 15 data 0 register) 
        .equ CAN1_F15DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F15DATA1, CAN1_BASE + 0x2BC @ (Filter 15 data 1 register) 
        .equ CAN1_F15DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F15DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F16DATA0, CAN1_BASE + 0x2C0 @ (Filter 16 data 0 register) 
        .equ CAN1_F16DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F16DATA1, CAN1_BASE + 0x2C4 @ (Filter 16 data 1 register) 
        .equ CAN1_F16DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F16DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F17DATA0, CAN1_BASE + 0x2C8 @ (Filter 17 data 0 register) 
        .equ CAN1_F17DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F17DATA1, CAN1_BASE + 0x2CC @ (Filter 17 data 1 register) 
        .equ CAN1_F17DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F17DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F18DATA0, CAN1_BASE + 0x2D0 @ (Filter 18 data 0 register) 
        .equ CAN1_F18DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F18DATA1, CAN1_BASE + 0x2D4 @ (Filter 18 data 1 register) 
        .equ CAN1_F18DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F18DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F19DATA0, CAN1_BASE + 0x2D8 @ (Filter 19 data 0 register) 
        .equ CAN1_F19DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F19DATA1, CAN1_BASE + 0x2DC @ (Filter 19 data 1 register) 
        .equ CAN1_F19DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F19DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F20DATA0, CAN1_BASE + 0x2E0 @ (Filter 20 data 0 register) 
        .equ CAN1_F20DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F20DATA1, CAN1_BASE + 0x2E4 @ (Filter 20 data 1 register) 
        .equ CAN1_F20DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F20DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F21DATA0, CAN1_BASE + 0x2E8 @ (Filter 21 data 0 register) 
        .equ CAN1_F21DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F21DATA1, CAN1_BASE + 0x2EC @ (Filter 21 data 1 register) 
        .equ CAN1_F21DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F21DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F22DATA0, CAN1_BASE + 0x2F0 @ (Filter 22 data 0 register) 
        .equ CAN1_F22DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F22DATA1, CAN1_BASE + 0x2F4 @ (Filter 22 data 1 register) 
        .equ CAN1_F22DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F22DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F23DATA0, CAN1_BASE + 0x2F8 @ (Filter 23 data 0 register) 
        .equ CAN1_F23DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F23DATA1, CAN1_BASE + 0x2FC @ (Filter 23 data 1 register) 
        .equ CAN1_F23DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F23DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F24DATA0, CAN1_BASE + 0x300 @ (Filter 24 data 0 register) 
        .equ CAN1_F24DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F24DATA1, CAN1_BASE + 0x304 @ (Filter 24 data 1 register) 
        .equ CAN1_F24DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F24DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F25DATA0, CAN1_BASE + 0x308 @ (Filter 25 data 0 register) 
        .equ CAN1_F25DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F25DATA1, CAN1_BASE + 0x30C @ (Filter 25 data 1 register) 
        .equ CAN1_F25DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F25DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F26DATA0, CAN1_BASE + 0x310 @ (Filter 26 data 0 register) 
        .equ CAN1_F26DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F26DATA1, CAN1_BASE + 0x314 @ (Filter 26 data 1 register) 
        .equ CAN1_F26DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F26DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F27DATA0, CAN1_BASE + 0x318 @ (Filter 27 data 0 register) 
        .equ CAN1_F27DATA0_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA0_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 
    .equ CAN1_F27DATA1, CAN1_BASE + 0x31C @ (Filter 27 data 1 register) 
        .equ CAN1_F27DATA1_FD0, 1 << 0   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD1, 1 << 1   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD2, 1 << 2   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD3, 1 << 3   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD4, 1 << 4   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD5, 1 << 5   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD6, 1 << 6   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD7, 1 << 7   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD8, 1 << 8   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD9, 1 << 9   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD10, 1 << 10   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD11, 1 << 11   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD12, 1 << 12   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD13, 1 << 13   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD14, 1 << 14   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD15, 1 << 15   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD16, 1 << 16   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD17, 1 << 17   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD18, 1 << 18   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD19, 1 << 19   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD20, 1 << 20   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD21, 1 << 21   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD22, 1 << 22   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD23, 1 << 23   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD24, 1 << 24   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD25, 1 << 25   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD26, 1 << 26   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD27, 1 << 27   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD28, 1 << 28   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD29, 1 << 29   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD30, 1 << 30   @ bitWidth 1 (Filter bits)  
        .equ CAN1_F27DATA1_FD31, 1 << 31   @ bitWidth 1 (Filter bits)  
 

@=========================== CRC ===========================@
.equ CRC_BASE, 0x40023000 @ (cyclic redundancy check calculation unit) 
    .equ CRC_DATA, CRC_BASE + 0x0 @ (Data register) 
        .equ CRC_DATA_DATA_Shift, 0   @ bitWidth 32 (CRC calculation result bits)  
 
    .equ CRC_FDATA, CRC_BASE + 0x04 @ (Free data register) 
        .equ CRC_FDATA_FDATA_Shift, 0   @ bitWidth 8 (Free Data Register bits)  
 
    .equ CRC_CTL, CRC_BASE + 0x08 @ (Control register) 
        .equ CRC_CTL_RST, 1 << 0   @ bitWidth 1 (reset bit)  
 

@=========================== DAC ===========================@
.equ DAC_BASE, 0x40007400 @ (Digital-to-analog converter) 
    .equ DAC_CTL, DAC_BASE + 0x0 @ (control register) 
        .equ DAC_CTL_DEN0, 1 << 0   @ bitWidth 1 (DAC0 enable)  
        .equ DAC_CTL_DBOFF0, 1 << 1   @ bitWidth 1 (DAC0 output buffer turn off)  
        .equ DAC_CTL_DTEN0, 1 << 2   @ bitWidth 1 (DAC0 trigger enable)  
        .equ DAC_CTL_DTSEL0_Shift, 3   @ bitWidth 3 (DAC0 trigger selection)  
        .equ DAC_CTL_DWM0_Shift, 6   @ bitWidth 2 (DAC0 noise wave mode)  
        .equ DAC_CTL_DWBW0_Shift, 8   @ bitWidth 4 (DAC0 noise wave bit width)  
        .equ DAC_CTL_DDMAEN0, 1 << 12   @ bitWidth 1 (DAC0 DMA enable)  
        .equ DAC_CTL_DEN1, 1 << 16   @ bitWidth 1 (DAC1 enable)  
        .equ DAC_CTL_DBOFF1, 1 << 17   @ bitWidth 1 (DAC1 output buffer turn off)  
        .equ DAC_CTL_DTEN1, 1 << 18   @ bitWidth 1 (DAC1 trigger enable)  
        .equ DAC_CTL_DTSEL1_Shift, 19   @ bitWidth 3 (DAC1 trigger selection)  
        .equ DAC_CTL_DWM1_Shift, 22   @ bitWidth 2 (DAC1 noise wave mode)  
        .equ DAC_CTL_DWBW1_Shift, 24   @ bitWidth 4 (DAC1 noise wave bit width)  
        .equ DAC_CTL_DDMAEN1, 1 << 28   @ bitWidth 1 (DAC1 DMA enable)  
 
    .equ DAC_SWT, DAC_BASE + 0x04 @ (software trigger register) 
        .equ DAC_SWT_SWTR0, 1 << 0   @ bitWidth 1 (DAC0 software trigger)  
        .equ DAC_SWT_SWTR1, 1 << 1   @ bitWidth 1 (DAC1 software trigger)  
 
    .equ DAC_DAC0_R12DH, DAC_BASE + 0x08 @ (DAC0 12-bit right-aligned data holding register) 
        .equ DAC_DAC0_R12DH_DAC0_DH_Shift, 0   @ bitWidth 12 (DAC0 12-bit right-aligned  data)  
 
    .equ DAC_DAC0_L12DH, DAC_BASE + 0x0C @ (DAC0 12-bit left-aligned data holding register) 
        .equ DAC_DAC0_L12DH_DAC0_DH_Shift, 4   @ bitWidth 12 (DAC0 12-bit left-aligned  data)  
 
    .equ DAC_DAC0_R8DH, DAC_BASE + 0x10 @ (DAC0 8-bit right aligned data holding  register) 
        .equ DAC_DAC0_R8DH_DAC0_DH_Shift, 0   @ bitWidth 8 (DAC0 8-bit right-aligned  data)  
 
    .equ DAC_DAC1_R12DH, DAC_BASE + 0x14 @ (DAC1 12-bit right-aligned data holding  register) 
        .equ DAC_DAC1_R12DH_DAC1_DH_Shift, 0   @ bitWidth 12 (DAC1 12-bit right-aligned  data)  
 
    .equ DAC_DAC1_L12DH, DAC_BASE + 0x18 @ (DAC1 12-bit left aligned data holding  register) 
        .equ DAC_DAC1_L12DH_DAC1_DH_Shift, 4   @ bitWidth 12 (DAC1 12-bit left-aligned  data)  
 
    .equ DAC_DAC1_R8DH, DAC_BASE + 0x1C @ (DAC1 8-bit right aligned data holding  register) 
        .equ DAC_DAC1_R8DH_DAC1_DH_Shift, 0   @ bitWidth 8 (DAC1 8-bit right-aligned  data)  
 
    .equ DAC_DACC_R12DH, DAC_BASE + 0x20 @ (DAC concurrent mode 12-bit right-aligned data holding  register) 
        .equ DAC_DACC_R12DH_DAC0_DH_Shift, 0   @ bitWidth 12 (DAC0 12-bit right-aligned  data)  
        .equ DAC_DACC_R12DH_DAC1_DH_Shift, 16   @ bitWidth 12 (DAC1 12-bit right-aligned  data)  
 
    .equ DAC_DACC_L12DH, DAC_BASE + 0x24 @ (DAC concurrent mode 12-bit left aligned data holding  register) 
        .equ DAC_DACC_L12DH_DAC0_DH_Shift, 4   @ bitWidth 12 (DAC0 12-bit left-aligned  data)  
        .equ DAC_DACC_L12DH_DAC1_DH_Shift, 20   @ bitWidth 12 (DAC1 12-bit left-aligned  data)  
 
    .equ DAC_DACC_R8DH, DAC_BASE + 0x28 @ (DAC concurrent mode 8-bit right aligned data holding  register) 
        .equ DAC_DACC_R8DH_DAC0_DH_Shift, 0   @ bitWidth 8 (DAC0 8-bit right-aligned  data)  
        .equ DAC_DACC_R8DH_DAC1_DH_Shift, 8   @ bitWidth 8 (DAC1 8-bit right-aligned  data)  
 
    .equ DAC_DAC0_DO, DAC_BASE + 0x2C @ (DAC0 data output register) 
        .equ DAC_DAC0_DO_DAC0_DO_Shift, 0   @ bitWidth 12 (DAC0 data output)  
 
    .equ DAC_DAC1_DO, DAC_BASE + 0x30 @ (DAC1 data output register) 
        .equ DAC_DAC1_DO_DAC1_DO_Shift, 0   @ bitWidth 12 (DAC1 data output)  
 

@=========================== DBG ===========================@
.equ DBG_BASE, 0xE0042000 @ (Debug support) 
    .equ DBG_ID, DBG_BASE + 0x0 @ (ID code register) 
        .equ DBG_ID_ID_CODE_Shift, 0   @ bitWidth 32 (DBG ID code register)  
 
    .equ DBG_CTL, DBG_BASE + 0x4 @ (Control register 0) 
        .equ DBG_CTL_SLP_HOLD, 1 << 0   @ bitWidth 1 (Sleep mode hold register)  
        .equ DBG_CTL_DSLP_HOLD, 1 << 1   @ bitWidth 1 (Deep-sleep mode hold register)  
        .equ DBG_CTL_STB_HOLD, 1 << 2   @ bitWidth 1 (Standby mode hold register)  
        .equ DBG_CTL_FWDGT_HOLD, 1 << 8   @ bitWidth 1 (FWDGT hold bit)  
        .equ DBG_CTL_WWDGT_HOLD, 1 << 9   @ bitWidth 1 (WWDGT hold bit)  
        .equ DBG_CTL_TIMER0_HOLD, 1 << 10   @ bitWidth 1 (TIMER 0 hold bit)  
        .equ DBG_CTL_TIMER1_HOLD, 1 << 11   @ bitWidth 1 (TIMER 1 hold bit)  
        .equ DBG_CTL_TIMER2_HOLD, 1 << 12   @ bitWidth 1 (TIMER 2 hold bit)  
        .equ DBG_CTL_TIMER3_HOLD, 1 << 13   @ bitWidth 1 (TIMER 23 hold bit)  
        .equ DBG_CTL_CAN0_HOLD, 1 << 14   @ bitWidth 1 (CAN0 hold bit)  
        .equ DBG_CTL_I2C0_HOLD, 1 << 15   @ bitWidth 1 (I2C0 hold bit)  
        .equ DBG_CTL_I2C1_HOLD, 1 << 16   @ bitWidth 1 (I2C1 hold bit)  
        .equ DBG_CTL_TIMER4_HOLD, 1 << 18   @ bitWidth 1 (TIMER4_HOLD)  
        .equ DBG_CTL_TIMER5_HOLD, 1 << 19   @ bitWidth 1 (TIMER 5 hold bit)  
        .equ DBG_CTL_TIMER6_HOLD, 1 << 20   @ bitWidth 1 (TIMER 6 hold bit)  
        .equ DBG_CTL_CAN1_HOLD, 1 << 21   @ bitWidth 1 (CAN1 hold bit)  
 

@=========================== DMA0 ===========================@
.equ DMA0_BASE, 0x40020000 @ (DMA controller) 
    .equ DMA0_INTF, DMA0_BASE + 0x0 @ (Interrupt flag register ) 
        .equ DMA0_INTF_GIF0, 1 << 0   @ bitWidth 1 (Global interrupt flag of channel 0)  
        .equ DMA0_INTF_FTFIF0, 1 << 1   @ bitWidth 1 (Full Transfer finish flag of channe 0)  
        .equ DMA0_INTF_HTFIF0, 1 << 2   @ bitWidth 1 (Half transfer finish flag of channel 0)  
        .equ DMA0_INTF_ERRIF0, 1 << 3   @ bitWidth 1 (Error flag of channel 0)  
        .equ DMA0_INTF_GIF1, 1 << 4   @ bitWidth 1 (Global interrupt flag of channel 1)  
        .equ DMA0_INTF_FTFIF1, 1 << 5   @ bitWidth 1 (Full Transfer finish flag of channe 1)  
        .equ DMA0_INTF_HTFIF1, 1 << 6   @ bitWidth 1 (Half transfer finish flag of channel 1)  
        .equ DMA0_INTF_ERRIF1, 1 << 7   @ bitWidth 1 (Error flag of channel 1)  
        .equ DMA0_INTF_GIF2, 1 << 8   @ bitWidth 1 (Global interrupt flag of channel 2)  
        .equ DMA0_INTF_FTFIF2, 1 << 9   @ bitWidth 1 (Full Transfer finish flag of channe 2)  
        .equ DMA0_INTF_HTFIF2, 1 << 10   @ bitWidth 1 (Half transfer finish flag of channel 2)  
        .equ DMA0_INTF_ERRIF2, 1 << 11   @ bitWidth 1 (Error flag of channel 2)  
        .equ DMA0_INTF_GIF3, 1 << 12   @ bitWidth 1 (Global interrupt flag of channel 3)  
        .equ DMA0_INTF_FTFIF3, 1 << 13   @ bitWidth 1 (Full Transfer finish flag of channe 3)  
        .equ DMA0_INTF_HTFIF3, 1 << 14   @ bitWidth 1 (Half transfer finish flag of channel 3)  
        .equ DMA0_INTF_ERRIF3, 1 << 15   @ bitWidth 1 (Error flag of channel 3)  
        .equ DMA0_INTF_GIF4, 1 << 16   @ bitWidth 1 (Global interrupt flag of channel 4)  
        .equ DMA0_INTF_FTFIF4, 1 << 17   @ bitWidth 1 (Full Transfer finish flag of channe 4)  
        .equ DMA0_INTF_HTFIF4, 1 << 18   @ bitWidth 1 (Half transfer finish flag of channel 4)  
        .equ DMA0_INTF_ERRIF4, 1 << 19   @ bitWidth 1 (Error flag of channel 4)  
        .equ DMA0_INTF_GIF5, 1 << 20   @ bitWidth 1 (Global interrupt flag of channel 5)  
        .equ DMA0_INTF_FTFIF5, 1 << 21   @ bitWidth 1 (Full Transfer finish flag of channe 5)  
        .equ DMA0_INTF_HTFIF5, 1 << 22   @ bitWidth 1 (Half transfer finish flag of channel 5)  
        .equ DMA0_INTF_ERRIF5, 1 << 23   @ bitWidth 1 (Error flag of channel 5)  
        .equ DMA0_INTF_GIF6, 1 << 24   @ bitWidth 1 (Global interrupt flag of channel 6)  
        .equ DMA0_INTF_FTFIF6, 1 << 25   @ bitWidth 1 (Full Transfer finish flag of channe 6)  
        .equ DMA0_INTF_HTFIF6, 1 << 26   @ bitWidth 1 (Half transfer finish flag of channel 6)  
        .equ DMA0_INTF_ERRIF6, 1 << 27   @ bitWidth 1 (Error flag of channel 6)  
 
    .equ DMA0_INTC, DMA0_BASE + 0x04 @ (Interrupt flag clear register ) 
        .equ DMA0_INTC_GIFC0, 1 << 0   @ bitWidth 1 (Clear global interrupt flag of channel 0)  
        .equ DMA0_INTC_FTFIFC0, 1 << 1   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 0)  
        .equ DMA0_INTC_HTFIFC0, 1 << 2   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 0)  
        .equ DMA0_INTC_ERRIFC0, 1 << 3   @ bitWidth 1 (Clear bit for error flag of channel 0)  
        .equ DMA0_INTC_GIFC1, 1 << 4   @ bitWidth 1 (Clear global interrupt flag of channel 1)  
        .equ DMA0_INTC_FTFIFC1, 1 << 5   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 1)  
        .equ DMA0_INTC_HTFIFC1, 1 << 6   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 1)  
        .equ DMA0_INTC_ERRIFC1, 1 << 7   @ bitWidth 1 (Clear bit for error flag of channel 1)  
        .equ DMA0_INTC_GIFC2, 1 << 8   @ bitWidth 1 (Clear global interrupt flag of channel 2)  
        .equ DMA0_INTC_FTFIFC2, 1 << 9   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 2)  
        .equ DMA0_INTC_HTFIFC2, 1 << 10   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 2)  
        .equ DMA0_INTC_ERRIFC2, 1 << 11   @ bitWidth 1 (Clear bit for error flag of channel 2)  
        .equ DMA0_INTC_GIFC3, 1 << 12   @ bitWidth 1 (Clear global interrupt flag of channel 3)  
        .equ DMA0_INTC_FTFIFC3, 1 << 13   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 3)  
        .equ DMA0_INTC_HTFIFC3, 1 << 14   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 3)  
        .equ DMA0_INTC_ERRIFC3, 1 << 15   @ bitWidth 1 (Clear bit for error flag of channel 3)  
        .equ DMA0_INTC_GIFC4, 1 << 16   @ bitWidth 1 (Clear global interrupt flag of channel 4)  
        .equ DMA0_INTC_FTFIFC4, 1 << 17   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 4)  
        .equ DMA0_INTC_HTFIFC4, 1 << 18   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 4)  
        .equ DMA0_INTC_ERRIFC4, 1 << 19   @ bitWidth 1 (Clear bit for error flag of channel 4)  
        .equ DMA0_INTC_GIFC5, 1 << 20   @ bitWidth 1 (Clear global interrupt flag of channel 5)  
        .equ DMA0_INTC_FTFIFC5, 1 << 21   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 5)  
        .equ DMA0_INTC_HTFIFC5, 1 << 22   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 5)  
        .equ DMA0_INTC_ERRIFC5, 1 << 23   @ bitWidth 1 (Clear bit for error flag of channel 5)  
        .equ DMA0_INTC_GIFC6, 1 << 24   @ bitWidth 1 (Clear global interrupt flag of channel 6)  
        .equ DMA0_INTC_FTFIFC6, 1 << 25   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 6)  
        .equ DMA0_INTC_HTFIFC6, 1 << 26   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 6)  
        .equ DMA0_INTC_ERRIFC6, 1 << 27   @ bitWidth 1 (Clear bit for error flag of channel 6)  
 
    .equ DMA0_CH0CTL, DMA0_BASE + 0x08 @ (Channel 0 control register) 
        .equ DMA0_CH0CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH0CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH0CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH0CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH0CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH0CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH0CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH0CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH0CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH0CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH0CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH0CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH0CNT, DMA0_BASE + 0x0C @ (Channel 0 counter register) 
        .equ DMA0_CH0CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH0PADDR, DMA0_BASE + 0x10 @ (Channel 0 peripheral base address register) 
        .equ DMA0_CH0PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH0MADDR, DMA0_BASE + 0x14 @ (Channel 0 memory base address register) 
        .equ DMA0_CH0MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH1CTL, DMA0_BASE + 0x1C @ (Channel 1 control register) 
        .equ DMA0_CH1CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH1CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH1CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH1CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH1CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH1CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH1CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH1CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH1CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH1CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH1CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH1CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH1CNT, DMA0_BASE + 0x20 @ (Channel 1 counter register) 
        .equ DMA0_CH1CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH1PADDR, DMA0_BASE + 0x24 @ (Channel 1 peripheral base address register) 
        .equ DMA0_CH1PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH1MADDR, DMA0_BASE + 0x28 @ (Channel 1 memory base address register) 
        .equ DMA0_CH1MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH2CTL, DMA0_BASE + 0x30 @ (Channel 2 control register) 
        .equ DMA0_CH2CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH2CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH2CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH2CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH2CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH2CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH2CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH2CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH2CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH2CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH2CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH2CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH2CNT, DMA0_BASE + 0x34 @ (Channel 2 counter register) 
        .equ DMA0_CH2CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH2PADDR, DMA0_BASE + 0x38 @ (Channel 2 peripheral base address register) 
        .equ DMA0_CH2PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH2MADDR, DMA0_BASE + 0x3C @ (Channel 2 memory base address register) 
        .equ DMA0_CH2MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH3CTL, DMA0_BASE + 0x44 @ (Channel 3 control register) 
        .equ DMA0_CH3CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH3CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH3CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH3CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH3CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH3CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH3CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH3CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH3CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH3CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH3CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH3CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH3CNT, DMA0_BASE + 0x48 @ (Channel 3 counter register) 
        .equ DMA0_CH3CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH3PADDR, DMA0_BASE + 0x4C @ (Channel 3 peripheral base address register) 
        .equ DMA0_CH3PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH3MADDR, DMA0_BASE + 0x50 @ (Channel 3 memory base address register) 
        .equ DMA0_CH3MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH4CTL, DMA0_BASE + 0x58 @ (Channel 4 control register) 
        .equ DMA0_CH4CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH4CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH4CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH4CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH4CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH4CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH4CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH4CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH4CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH4CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH4CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH4CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH4CNT, DMA0_BASE + 0x5C @ (Channel 4 counter register) 
        .equ DMA0_CH4CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH4PADDR, DMA0_BASE + 0x60 @ (Channel 4 peripheral base address register) 
        .equ DMA0_CH4PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH4MADDR, DMA0_BASE + 0x64 @ (Channel 4 memory base address register) 
        .equ DMA0_CH4MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH5CTL, DMA0_BASE + 0x6C @ (Channel 5 control register) 
        .equ DMA0_CH5CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH5CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH5CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH5CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH5CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH5CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH5CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH5CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH5CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH5CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH5CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH5CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH5CNT, DMA0_BASE + 0x70 @ (Channel 5 counter register) 
        .equ DMA0_CH5CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH5PADDR, DMA0_BASE + 0x74 @ (Channel 5 peripheral base address register) 
        .equ DMA0_CH5PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH5MADDR, DMA0_BASE + 0x78 @ (Channel 5 memory base address register) 
        .equ DMA0_CH5MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA0_CH6CTL, DMA0_BASE + 0x80 @ (Channel 6 control register) 
        .equ DMA0_CH6CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA0_CH6CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA0_CH6CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA0_CH6CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA0_CH6CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA0_CH6CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA0_CH6CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA0_CH6CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA0_CH6CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA0_CH6CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA0_CH6CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA0_CH6CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA0_CH6CNT, DMA0_BASE + 0x84 @ (Channel 6 counter register) 
        .equ DMA0_CH6CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA0_CH6PADDR, DMA0_BASE + 0x88 @ (Channel 6 peripheral base address register) 
        .equ DMA0_CH6PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA0_CH6MADDR, DMA0_BASE + 0x8C @ (Channel 6 memory base address register) 
        .equ DMA0_CH6MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 

@=========================== DMA1 ===========================@
.equ DMA1_BASE, 0x40020000 @ (Direct memory access controller) 
    .equ DMA1_INTF, DMA1_BASE + 0x0 @ (Interrupt flag register ) 
        .equ DMA1_INTF_GIF0, 1 << 0   @ bitWidth 1 (Global interrupt flag of channel 0)  
        .equ DMA1_INTF_FTFIF0, 1 << 1   @ bitWidth 1 (Full Transfer finish flag of channe 0)  
        .equ DMA1_INTF_HTFIF0, 1 << 2   @ bitWidth 1 (Half transfer finish flag of channel 0)  
        .equ DMA1_INTF_ERRIF0, 1 << 3   @ bitWidth 1 (Error flag of channel 0)  
        .equ DMA1_INTF_GIF1, 1 << 4   @ bitWidth 1 (Global interrupt flag of channel 1)  
        .equ DMA1_INTF_FTFIF1, 1 << 5   @ bitWidth 1 (Full Transfer finish flag of channe 1)  
        .equ DMA1_INTF_HTFIF1, 1 << 6   @ bitWidth 1 (Half transfer finish flag of channel 1)  
        .equ DMA1_INTF_ERRIF1, 1 << 7   @ bitWidth 1 (Error flag of channel 1)  
        .equ DMA1_INTF_GIF2, 1 << 8   @ bitWidth 1 (Global interrupt flag of channel 2)  
        .equ DMA1_INTF_FTFIF2, 1 << 9   @ bitWidth 1 (Full Transfer finish flag of channe 2)  
        .equ DMA1_INTF_HTFIF2, 1 << 10   @ bitWidth 1 (Half transfer finish flag of channel 2)  
        .equ DMA1_INTF_ERRIF2, 1 << 11   @ bitWidth 1 (Error flag of channel 2)  
        .equ DMA1_INTF_GIF3, 1 << 12   @ bitWidth 1 (Global interrupt flag of channel 3)  
        .equ DMA1_INTF_FTFIF3, 1 << 13   @ bitWidth 1 (Full Transfer finish flag of channe 3)  
        .equ DMA1_INTF_HTFIF3, 1 << 14   @ bitWidth 1 (Half transfer finish flag of channel 3)  
        .equ DMA1_INTF_ERRIF3, 1 << 15   @ bitWidth 1 (Error flag of channel 3)  
        .equ DMA1_INTF_GIF4, 1 << 16   @ bitWidth 1 (Global interrupt flag of channel 4)  
        .equ DMA1_INTF_FTFIF4, 1 << 17   @ bitWidth 1 (Full Transfer finish flag of channe 4)  
        .equ DMA1_INTF_HTFIF4, 1 << 18   @ bitWidth 1 (Half transfer finish flag of channel 4)  
        .equ DMA1_INTF_ERRIF4, 1 << 19   @ bitWidth 1 (Error flag of channel 4)  
 
    .equ DMA1_INTC, DMA1_BASE + 0x04 @ (Interrupt flag clear register ) 
        .equ DMA1_INTC_GIFC0, 1 << 0   @ bitWidth 1 (Clear global interrupt flag of channel 0)  
        .equ DMA1_INTC_FTFIFC0, 1 << 1   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 0)  
        .equ DMA1_INTC_HTFIFC0, 1 << 2   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 0)  
        .equ DMA1_INTC_ERRIFC0, 1 << 3   @ bitWidth 1 (Clear bit for error flag of channel 0)  
        .equ DMA1_INTC_GIFC1, 1 << 4   @ bitWidth 1 (Clear global interrupt flag of channel 1)  
        .equ DMA1_INTC_FTFIFC1, 1 << 5   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 1)  
        .equ DMA1_INTC_HTFIFC1, 1 << 6   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 1)  
        .equ DMA1_INTC_ERRIFC1, 1 << 7   @ bitWidth 1 (Clear bit for error flag of channel 1)  
        .equ DMA1_INTC_GIFC2, 1 << 8   @ bitWidth 1 (Clear global interrupt flag of channel 2)  
        .equ DMA1_INTC_FTFIFC2, 1 << 9   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 2)  
        .equ DMA1_INTC_HTFIFC2, 1 << 10   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 2)  
        .equ DMA1_INTC_ERRIFC2, 1 << 11   @ bitWidth 1 (Clear bit for error flag of channel 2)  
        .equ DMA1_INTC_GIFC3, 1 << 12   @ bitWidth 1 (Clear global interrupt flag of channel 3)  
        .equ DMA1_INTC_FTFIFC3, 1 << 13   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 3)  
        .equ DMA1_INTC_HTFIFC3, 1 << 14   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 3)  
        .equ DMA1_INTC_ERRIFC3, 1 << 15   @ bitWidth 1 (Clear bit for error flag of channel 3)  
        .equ DMA1_INTC_GIFC4, 1 << 16   @ bitWidth 1 (Clear global interrupt flag of channel 4)  
        .equ DMA1_INTC_FTFIFC4, 1 << 17   @ bitWidth 1 (Clear bit for full transfer finish flag of channel 4)  
        .equ DMA1_INTC_HTFIFC4, 1 << 18   @ bitWidth 1 (Clear bit for half transfer finish flag of channel 4)  
        .equ DMA1_INTC_ERRIFC4, 1 << 19   @ bitWidth 1 (Clear bit for error flag of channel 4)  
 
    .equ DMA1_CH0CTL, DMA1_BASE + 0x08 @ (Channel 0 control register) 
        .equ DMA1_CH0CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_CH0CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_CH0CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_CH0CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_CH0CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CH0CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_CH0CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_CH0CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_CH0CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_CH0CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_CH0CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_CH0CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH0CNT, DMA1_BASE + 0x0C @ (Channel 0 counter register) 
        .equ DMA1_CH0CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH0PADDR, DMA1_BASE + 0x10 @ (Channel 0 peripheral base address register) 
        .equ DMA1_CH0PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH0MADDR, DMA1_BASE + 0x14 @ (Channel 0 memory base address register) 
        .equ DMA1_CH0MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH1CTL, DMA1_BASE + 0x1C @ (Channel 1 control register) 
        .equ DMA1_CH1CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_CH1CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_CH1CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_CH1CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_CH1CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CH1CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_CH1CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_CH1CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_CH1CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_CH1CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_CH1CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_CH1CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH1CNT, DMA1_BASE + 0x20 @ (Channel 1 counter register) 
        .equ DMA1_CH1CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH1PADDR, DMA1_BASE + 0x24 @ (Channel 1 peripheral base address register) 
        .equ DMA1_CH1PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH1MADDR, DMA1_BASE + 0x28 @ (Channel 1 memory base address register) 
        .equ DMA1_CH1MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH2CTL, DMA1_BASE + 0x30 @ (Channel 2 control register) 
        .equ DMA1_CH2CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_CH2CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_CH2CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_CH2CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_CH2CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CH2CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_CH2CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_CH2CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_CH2CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_CH2CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_CH2CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_CH2CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH2CNT, DMA1_BASE + 0x34 @ (Channel 2 counter register) 
        .equ DMA1_CH2CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH2PADDR, DMA1_BASE + 0x38 @ (Channel 2 peripheral base address register) 
        .equ DMA1_CH2PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH2MADDR, DMA1_BASE + 0x3C @ (Channel 2 memory base address register) 
        .equ DMA1_CH2MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH3CTL, DMA1_BASE + 0x44 @ (Channel 3 control register) 
        .equ DMA1_CH3CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_CH3CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_CH3CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_CH3CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_CH3CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CH3CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_CH3CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_CH3CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_CH3CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_CH3CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_CH3CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_CH3CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH3CNT, DMA1_BASE + 0x48 @ (Channel 3 counter register) 
        .equ DMA1_CH3CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH3PADDR, DMA1_BASE + 0x4C @ (Channel 3 peripheral base address register) 
        .equ DMA1_CH3PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH3MADDR, DMA1_BASE + 0x50 @ (Channel 3 memory base address register) 
        .equ DMA1_CH3MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 
    .equ DMA1_CH4CTL, DMA1_BASE + 0x58 @ (Channel 4 control register) 
        .equ DMA1_CH4CTL_CHEN, 1 << 0   @ bitWidth 1 (Channel enable)  
        .equ DMA1_CH4CTL_FTFIE, 1 << 1   @ bitWidth 1 (Enable bit for channel full transfer finish interrupt)  
        .equ DMA1_CH4CTL_HTFIE, 1 << 2   @ bitWidth 1 (Enable bit for channel half transfer finish interrupt)  
        .equ DMA1_CH4CTL_ERRIE, 1 << 3   @ bitWidth 1 (Enable bit for channel error interrupt)  
        .equ DMA1_CH4CTL_DIR, 1 << 4   @ bitWidth 1 (Transfer direction)  
        .equ DMA1_CH4CTL_CMEN, 1 << 5   @ bitWidth 1 (Circular mode enable)  
        .equ DMA1_CH4CTL_PNAGA, 1 << 6   @ bitWidth 1 (Next address generation algorithm of peripheral)  
        .equ DMA1_CH4CTL_MNAGA, 1 << 7   @ bitWidth 1 (Next address generation algorithm of memory)  
        .equ DMA1_CH4CTL_PWIDTH_Shift, 8   @ bitWidth 2 (Transfer data size of peripheral)  
        .equ DMA1_CH4CTL_MWIDTH_Shift, 10   @ bitWidth 2 (Transfer data size of memory)  
        .equ DMA1_CH4CTL_PRIO_Shift, 12   @ bitWidth 2 (Priority level)  
        .equ DMA1_CH4CTL_M2M, 1 << 14   @ bitWidth 1 (Memory to Memory Mode)  
 
    .equ DMA1_CH4CNT, DMA1_BASE + 0x5C @ (Channel 4 counter register) 
        .equ DMA1_CH4CNT_CNT_Shift, 0   @ bitWidth 16 (Transfer counter)  
 
    .equ DMA1_CH4PADDR, DMA1_BASE + 0x60 @ (Channel 4 peripheral base address register) 
        .equ DMA1_CH4PADDR_PADDR_Shift, 0   @ bitWidth 32 (Peripheral base address)  
 
    .equ DMA1_CH4MADDR, DMA1_BASE + 0x64 @ (Channel 4 memory base address register) 
        .equ DMA1_CH4MADDR_MADDR_Shift, 0   @ bitWidth 32 (Memory base address)  
 

@=========================== EXMC ===========================@
.equ EXMC_BASE, 0xA0000000 @ (External memory controller) 
    .equ EXMC_SNCTL0, EXMC_BASE + 0x0 @ (SRAM/NOR flash control register 0) 
        .equ EXMC_SNCTL0_ASYNCWAIT, 1 << 15   @ bitWidth 1 (Asynchronous wait)  
        .equ EXMC_SNCTL0_NRWTEN, 1 << 13   @ bitWidth 1 (NWAIT signal enable)  
        .equ EXMC_SNCTL0_WREN, 1 << 12   @ bitWidth 1 (Write enable)  
        .equ EXMC_SNCTL0_NRWTPOL, 1 << 9   @ bitWidth 1 (NWAIT signal polarity)  
        .equ EXMC_SNCTL0_NREN, 1 << 6   @ bitWidth 1 (NOR Flash access enable)  
        .equ EXMC_SNCTL0_NRW_Shift, 4   @ bitWidth 2 (NOR bank memory data bus width)  
        .equ EXMC_SNCTL0_NRTP_Shift, 2   @ bitWidth 2 (NOR bank memory type)  
        .equ EXMC_SNCTL0_NRMUX, 1 << 1   @ bitWidth 1 (NOR bank memory address/data multiplexing)  
        .equ EXMC_SNCTL0_NRBKEN, 1 << 0   @ bitWidth 1 (NOR bank enable)  
 
    .equ EXMC_SNTCFG0, EXMC_BASE + 0x4 @ (SRAM/NOR flash timing configuration register 0) 
        .equ EXMC_SNTCFG0_BUSLAT_Shift, 16   @ bitWidth 4 (Bus latency)  
        .equ EXMC_SNTCFG0_DSET_Shift, 8   @ bitWidth 8 (Data setup time)  
        .equ EXMC_SNTCFG0_AHLD_Shift, 4   @ bitWidth 4 (Address hold time)  
        .equ EXMC_SNTCFG0_ASET_Shift, 0   @ bitWidth 4 (Address setup time)  
 
    .equ EXMC_SNCTL1, EXMC_BASE + 0x8 @ (SRAM/NOR flash control register 1) 
        .equ EXMC_SNCTL1_ASYNCWAIT, 1 << 15   @ bitWidth 1 (Asynchronous wait)  
        .equ EXMC_SNCTL1_NRWTEN, 1 << 13   @ bitWidth 1 (NWAIT signal enable)  
        .equ EXMC_SNCTL1_WREN, 1 << 12   @ bitWidth 1 (Write enable)  
        .equ EXMC_SNCTL1_NRWTPOL, 1 << 9   @ bitWidth 1 (NWAIT signal polarity)  
        .equ EXMC_SNCTL1_NREN, 1 << 6   @ bitWidth 1 (NOR Flash access enable)  
        .equ EXMC_SNCTL1_NRW_Shift, 4   @ bitWidth 2 (NOR bank memory data bus width)  
        .equ EXMC_SNCTL1_NRTP_Shift, 2   @ bitWidth 2 (NOR bank memory type)  
        .equ EXMC_SNCTL1_NRMUX, 1 << 1   @ bitWidth 1 (NOR bank memory address/data multiplexing)  
        .equ EXMC_SNCTL1_NRBKEN, 1 << 0   @ bitWidth 1 (NOR bank enable)  
 

@=========================== EXTI ===========================@
.equ EXTI_BASE, 0x40010400 @ (External interrupt/event  controller) 
    .equ EXTI_INTEN, EXTI_BASE + 0x0 @ (Interrupt enable register  EXTI_INTEN) 
        .equ EXTI_INTEN_INTEN0, 1 << 0   @ bitWidth 1 (Enable Interrupt on line 0)  
        .equ EXTI_INTEN_INTEN1, 1 << 1   @ bitWidth 1 (Enable Interrupt on line 1)  
        .equ EXTI_INTEN_INTEN2, 1 << 2   @ bitWidth 1 (Enable Interrupt on line 2)  
        .equ EXTI_INTEN_INTEN3, 1 << 3   @ bitWidth 1 (Enable Interrupt on line 3)  
        .equ EXTI_INTEN_INTEN4, 1 << 4   @ bitWidth 1 (Enable Interrupt on line 4)  
        .equ EXTI_INTEN_INTEN5, 1 << 5   @ bitWidth 1 (Enable Interrupt on line 5)  
        .equ EXTI_INTEN_INTEN6, 1 << 6   @ bitWidth 1 (Enable Interrupt on line 6)  
        .equ EXTI_INTEN_INTEN7, 1 << 7   @ bitWidth 1 (Enable Interrupt on line 7)  
        .equ EXTI_INTEN_INTEN8, 1 << 8   @ bitWidth 1 (Enable Interrupt on line 8)  
        .equ EXTI_INTEN_INTEN9, 1 << 9   @ bitWidth 1 (Enable Interrupt on line 9)  
        .equ EXTI_INTEN_INTEN10, 1 << 10   @ bitWidth 1 (Enable Interrupt on line 10)  
        .equ EXTI_INTEN_INTEN11, 1 << 11   @ bitWidth 1 (Enable Interrupt on line 11)  
        .equ EXTI_INTEN_INTEN12, 1 << 12   @ bitWidth 1 (Enable Interrupt on line 12)  
        .equ EXTI_INTEN_INTEN13, 1 << 13   @ bitWidth 1 (Enable Interrupt on line 13)  
        .equ EXTI_INTEN_INTEN14, 1 << 14   @ bitWidth 1 (Enable Interrupt on line 14)  
        .equ EXTI_INTEN_INTEN15, 1 << 15   @ bitWidth 1 (Enable Interrupt on line 15)  
        .equ EXTI_INTEN_INTEN16, 1 << 16   @ bitWidth 1 (Enable Interrupt on line 16)  
        .equ EXTI_INTEN_INTEN17, 1 << 17   @ bitWidth 1 (Enable Interrupt on line 17)  
        .equ EXTI_INTEN_INTEN18, 1 << 18   @ bitWidth 1 (Enable Interrupt on line 18)  
 
    .equ EXTI_EVEN, EXTI_BASE + 0x04 @ (Event enable register EXTI_EVEN) 
        .equ EXTI_EVEN_EVEN0, 1 << 0   @ bitWidth 1 (Enable Event on line 0)  
        .equ EXTI_EVEN_EVEN1, 1 << 1   @ bitWidth 1 (Enable Event on line 1)  
        .equ EXTI_EVEN_EVEN2, 1 << 2   @ bitWidth 1 (Enable Event on line 2)  
        .equ EXTI_EVEN_EVEN3, 1 << 3   @ bitWidth 1 (Enable Event on line 3)  
        .equ EXTI_EVEN_EVEN4, 1 << 4   @ bitWidth 1 (Enable Event on line 4)  
        .equ EXTI_EVEN_EVEN5, 1 << 5   @ bitWidth 1 (Enable Event on line 5)  
        .equ EXTI_EVEN_EVEN6, 1 << 6   @ bitWidth 1 (Enable Event on line 6)  
        .equ EXTI_EVEN_EVEN7, 1 << 7   @ bitWidth 1 (Enable Event on line 7)  
        .equ EXTI_EVEN_EVEN8, 1 << 8   @ bitWidth 1 (Enable Event on line 8)  
        .equ EXTI_EVEN_EVEN9, 1 << 9   @ bitWidth 1 (Enable Event on line 9)  
        .equ EXTI_EVEN_EVEN10, 1 << 10   @ bitWidth 1 (Enable Event on line 10)  
        .equ EXTI_EVEN_EVEN11, 1 << 11   @ bitWidth 1 (Enable Event on line 11)  
        .equ EXTI_EVEN_EVEN12, 1 << 12   @ bitWidth 1 (Enable Event on line 12)  
        .equ EXTI_EVEN_EVEN13, 1 << 13   @ bitWidth 1 (Enable Event on line 13)  
        .equ EXTI_EVEN_EVEN14, 1 << 14   @ bitWidth 1 (Enable Event on line 14)  
        .equ EXTI_EVEN_EVEN15, 1 << 15   @ bitWidth 1 (Enable Event on line 15)  
        .equ EXTI_EVEN_EVEN16, 1 << 16   @ bitWidth 1 (Enable Event on line 16)  
        .equ EXTI_EVEN_EVEN17, 1 << 17   @ bitWidth 1 (Enable Event on line 17)  
        .equ EXTI_EVEN_EVEN18, 1 << 18   @ bitWidth 1 (Enable Event on line 18)  
 
    .equ EXTI_RTEN, EXTI_BASE + 0x08 @ (Rising Edge Trigger Enable register  EXTI_RTEN) 
        .equ EXTI_RTEN_RTEN0, 1 << 0   @ bitWidth 1 (Rising edge trigger enable of  line 0)  
        .equ EXTI_RTEN_RTEN1, 1 << 1   @ bitWidth 1 (Rising edge trigger enable of  line 1)  
        .equ EXTI_RTEN_RTEN2, 1 << 2   @ bitWidth 1 (Rising edge trigger enable of  line 2)  
        .equ EXTI_RTEN_RTEN3, 1 << 3   @ bitWidth 1 (Rising edge trigger enable of  line 3)  
        .equ EXTI_RTEN_RTEN4, 1 << 4   @ bitWidth 1 (Rising edge trigger enable of  line 4)  
        .equ EXTI_RTEN_RTEN5, 1 << 5   @ bitWidth 1 (Rising edge trigger enable of  line 5)  
        .equ EXTI_RTEN_RTEN6, 1 << 6   @ bitWidth 1 (Rising edge trigger enable of  line 6)  
        .equ EXTI_RTEN_RTEN7, 1 << 7   @ bitWidth 1 (Rising edge trigger enable of  line 7)  
        .equ EXTI_RTEN_RTEN8, 1 << 8   @ bitWidth 1 (Rising edge trigger enable of  line 8)  
        .equ EXTI_RTEN_RTEN9, 1 << 9   @ bitWidth 1 (Rising edge trigger enable of  line 9)  
        .equ EXTI_RTEN_RTEN10, 1 << 10   @ bitWidth 1 (Rising edge trigger enable of  line 10)  
        .equ EXTI_RTEN_RTEN11, 1 << 11   @ bitWidth 1 (Rising edge trigger enable of  line 11)  
        .equ EXTI_RTEN_RTEN12, 1 << 12   @ bitWidth 1 (Rising edge trigger enable of  line 12)  
        .equ EXTI_RTEN_RTEN13, 1 << 13   @ bitWidth 1 (Rising edge trigger enable of  line 13)  
        .equ EXTI_RTEN_RTEN14, 1 << 14   @ bitWidth 1 (Rising edge trigger enable of  line 14)  
        .equ EXTI_RTEN_RTEN15, 1 << 15   @ bitWidth 1 (Rising edge trigger enable of  line 15)  
        .equ EXTI_RTEN_RTEN16, 1 << 16   @ bitWidth 1 (Rising edge trigger enable of  line 16)  
        .equ EXTI_RTEN_RTEN17, 1 << 17   @ bitWidth 1 (Rising edge trigger enable of  line 17)  
        .equ EXTI_RTEN_RTEN18, 1 << 18   @ bitWidth 1 (Rising edge trigger enable of  line 18)  
 
    .equ EXTI_FTEN, EXTI_BASE + 0x0C @ (Falling Egde Trigger Enable register  EXTI_FTEN) 
        .equ EXTI_FTEN_FTEN0, 1 << 0   @ bitWidth 1 (Falling edge trigger enable of  line 0)  
        .equ EXTI_FTEN_FTEN1, 1 << 1   @ bitWidth 1 (Falling edge trigger enable of  line 1)  
        .equ EXTI_FTEN_FTEN2, 1 << 2   @ bitWidth 1 (Falling edge trigger enable of  line 2)  
        .equ EXTI_FTEN_FTEN3, 1 << 3   @ bitWidth 1 (Falling edge trigger enable of  line 3)  
        .equ EXTI_FTEN_FTEN4, 1 << 4   @ bitWidth 1 (Falling edge trigger enable of  line 4)  
        .equ EXTI_FTEN_FTEN5, 1 << 5   @ bitWidth 1 (Falling edge trigger enable of  line 5)  
        .equ EXTI_FTEN_FTEN6, 1 << 6   @ bitWidth 1 (Falling edge trigger enable of  line 6)  
        .equ EXTI_FTEN_FTEN7, 1 << 7   @ bitWidth 1 (Falling edge trigger enable of  line 7)  
        .equ EXTI_FTEN_FTEN8, 1 << 8   @ bitWidth 1 (Falling edge trigger enable of  line 8)  
        .equ EXTI_FTEN_FTEN9, 1 << 9   @ bitWidth 1 (Falling edge trigger enable of  line 9)  
        .equ EXTI_FTEN_FTEN10, 1 << 10   @ bitWidth 1 (Falling edge trigger enable of  line 10)  
        .equ EXTI_FTEN_FTEN11, 1 << 11   @ bitWidth 1 (Falling edge trigger enable of  line 11)  
        .equ EXTI_FTEN_FTEN12, 1 << 12   @ bitWidth 1 (Falling edge trigger enable of  line 12)  
        .equ EXTI_FTEN_FTEN13, 1 << 13   @ bitWidth 1 (Falling edge trigger enable of  line 13)  
        .equ EXTI_FTEN_FTEN14, 1 << 14   @ bitWidth 1 (Falling edge trigger enable of  line 14)  
        .equ EXTI_FTEN_FTEN15, 1 << 15   @ bitWidth 1 (Falling edge trigger enable of  line 15)  
        .equ EXTI_FTEN_FTEN16, 1 << 16   @ bitWidth 1 (Falling edge trigger enable of  line 16)  
        .equ EXTI_FTEN_FTEN17, 1 << 17   @ bitWidth 1 (Falling edge trigger enable of  line 17)  
        .equ EXTI_FTEN_FTEN18, 1 << 18   @ bitWidth 1 (Falling edge trigger enable of  line 18)  
 
    .equ EXTI_SWIEV, EXTI_BASE + 0x10 @ (Software interrupt event register  EXTI_SWIEV) 
        .equ EXTI_SWIEV_SWIEV0, 1 << 0   @ bitWidth 1 (Interrupt/Event software trigger on line  0)  
        .equ EXTI_SWIEV_SWIEV1, 1 << 1   @ bitWidth 1 (Interrupt/Event software trigger on line  1)  
        .equ EXTI_SWIEV_SWIEV2, 1 << 2   @ bitWidth 1 (Interrupt/Event software trigger on line  2)  
        .equ EXTI_SWIEV_SWIEV3, 1 << 3   @ bitWidth 1 (Interrupt/Event software trigger on line  3)  
        .equ EXTI_SWIEV_SWIEV4, 1 << 4   @ bitWidth 1 (Interrupt/Event software trigger on line  4)  
        .equ EXTI_SWIEV_SWIEV5, 1 << 5   @ bitWidth 1 (Interrupt/Event software trigger on line  5)  
        .equ EXTI_SWIEV_SWIEV6, 1 << 6   @ bitWidth 1 (Interrupt/Event software trigger on line  6)  
        .equ EXTI_SWIEV_SWIEV7, 1 << 7   @ bitWidth 1 (Interrupt/Event software trigger on line  7)  
        .equ EXTI_SWIEV_SWIEV8, 1 << 8   @ bitWidth 1 (Interrupt/Event software trigger on line  8)  
        .equ EXTI_SWIEV_SWIEV9, 1 << 9   @ bitWidth 1 (Interrupt/Event software trigger on line  9)  
        .equ EXTI_SWIEV_SWIEV10, 1 << 10   @ bitWidth 1 (Interrupt/Event software trigger on line  10)  
        .equ EXTI_SWIEV_SWIEV11, 1 << 11   @ bitWidth 1 (Interrupt/Event software trigger on line  11)  
        .equ EXTI_SWIEV_SWIEV12, 1 << 12   @ bitWidth 1 (Interrupt/Event software trigger on line  12)  
        .equ EXTI_SWIEV_SWIEV13, 1 << 13   @ bitWidth 1 (Interrupt/Event software trigger on line  13)  
        .equ EXTI_SWIEV_SWIEV14, 1 << 14   @ bitWidth 1 (Interrupt/Event software trigger on line  14)  
        .equ EXTI_SWIEV_SWIEV15, 1 << 15   @ bitWidth 1 (Interrupt/Event software trigger on line  15)  
        .equ EXTI_SWIEV_SWIEV16, 1 << 16   @ bitWidth 1 (Interrupt/Event software trigger on line  16)  
        .equ EXTI_SWIEV_SWIEV17, 1 << 17   @ bitWidth 1 (Interrupt/Event software trigger on line  17)  
        .equ EXTI_SWIEV_SWIEV18, 1 << 18   @ bitWidth 1 (Interrupt/Event software trigger on line  18)  
 
    .equ EXTI_PD, EXTI_BASE + 0x14 @ (Pending register EXTI_PD) 
        .equ EXTI_PD_PD0, 1 << 0   @ bitWidth 1 (Interrupt pending status of line 0)  
        .equ EXTI_PD_PD1, 1 << 1   @ bitWidth 1 (Interrupt pending status of line 1)  
        .equ EXTI_PD_PD2, 1 << 2   @ bitWidth 1 (Interrupt pending status of line 2)  
        .equ EXTI_PD_PD3, 1 << 3   @ bitWidth 1 (Interrupt pending status of line 3)  
        .equ EXTI_PD_PD4, 1 << 4   @ bitWidth 1 (Interrupt pending status of line 4)  
        .equ EXTI_PD_PD5, 1 << 5   @ bitWidth 1 (Interrupt pending status of line 5)  
        .equ EXTI_PD_PD6, 1 << 6   @ bitWidth 1 (Interrupt pending status of line 6)  
        .equ EXTI_PD_PD7, 1 << 7   @ bitWidth 1 (Interrupt pending status of line 7)  
        .equ EXTI_PD_PD8, 1 << 8   @ bitWidth 1 (Interrupt pending status of line 8)  
        .equ EXTI_PD_PD9, 1 << 9   @ bitWidth 1 (Interrupt pending status of line 9)  
        .equ EXTI_PD_PD10, 1 << 10   @ bitWidth 1 (Interrupt pending status of line 10)  
        .equ EXTI_PD_PD11, 1 << 11   @ bitWidth 1 (Interrupt pending status of line 11)  
        .equ EXTI_PD_PD12, 1 << 12   @ bitWidth 1 (Interrupt pending status of line 12)  
        .equ EXTI_PD_PD13, 1 << 13   @ bitWidth 1 (Interrupt pending status of line 13)  
        .equ EXTI_PD_PD14, 1 << 14   @ bitWidth 1 (Interrupt pending status of line 14)  
        .equ EXTI_PD_PD15, 1 << 15   @ bitWidth 1 (Interrupt pending status of line 15)  
        .equ EXTI_PD_PD16, 1 << 16   @ bitWidth 1 (Interrupt pending status of line 16)  
        .equ EXTI_PD_PD17, 1 << 17   @ bitWidth 1 (Interrupt pending status of line 17)  
        .equ EXTI_PD_PD18, 1 << 18   @ bitWidth 1 (Interrupt pending status of line 18)  
 

@=========================== FMC ===========================@
.equ FMC_BASE, 0x40022000 @ (FMC) 
    .equ FMC_WS, FMC_BASE + 0x0 @ (wait state counter register) 
        .equ FMC_WS_WSCNT_Shift, 0   @ bitWidth 3 (wait state counter register)  
 
    .equ FMC_KEY0, FMC_BASE + 0x04 @ (Unlock key register 0) 
        .equ FMC_KEY0_KEY_Shift, 0   @ bitWidth 32 (FMC_CTL0 unlock key)  
 
    .equ FMC_OBKEY, FMC_BASE + 0x08 @ (Option byte unlock key register) 
        .equ FMC_OBKEY_OBKEY_Shift, 0   @ bitWidth 32 (FMC_ CTL0 option byte operation unlock register)  
 
    .equ FMC_STAT0, FMC_BASE + 0x0C @ (Status register 0) 
        .equ FMC_STAT0_ENDF, 1 << 5   @ bitWidth 1 (End of operation flag bit)  
        .equ FMC_STAT0_WPERR, 1 << 4   @ bitWidth 1 (Erase/Program protection error flag bit)  
        .equ FMC_STAT0_PGERR, 1 << 2   @ bitWidth 1 (Program error flag bit)  
        .equ FMC_STAT0_BUSY, 1 << 0   @ bitWidth 1 (The flash is busy bit)  
 
    .equ FMC_CTL0, FMC_BASE + 0x10 @ (Control register 0) 
        .equ FMC_CTL0_ENDIE, 1 << 12   @ bitWidth 1 (End of operation interrupt enable bit)  
        .equ FMC_CTL0_ERRIE, 1 << 10   @ bitWidth 1 (Error interrupt enable bit)  
        .equ FMC_CTL0_OBWEN, 1 << 9   @ bitWidth 1 (Option byte erase/program enable bit)  
        .equ FMC_CTL0_LK, 1 << 7   @ bitWidth 1 (FMC_CTL0 lock bit)  
        .equ FMC_CTL0_START, 1 << 6   @ bitWidth 1 (Send erase command to FMC bit)  
        .equ FMC_CTL0_OBER, 1 << 5   @ bitWidth 1 (Option bytes erase command bit)  
        .equ FMC_CTL0_OBPG, 1 << 4   @ bitWidth 1 (Option bytes program command bit)  
        .equ FMC_CTL0_MER, 1 << 2   @ bitWidth 1 (Main flash mass erase for bank0 command bit)  
        .equ FMC_CTL0_PER, 1 << 1   @ bitWidth 1 (Main flash page erase for bank0 command bit)  
        .equ FMC_CTL0_PG, 1 << 0   @ bitWidth 1 (Main flash program for bank0 command bit)  
 
    .equ FMC_ADDR0, FMC_BASE + 0x14 @ (Address register 0) 
        .equ FMC_ADDR0_ADDR_Shift, 0   @ bitWidth 32 (Flash erase/program command address bits)  
 
    .equ FMC_OBSTAT, FMC_BASE + 0x1C @ (Option byte status register) 
        .equ FMC_OBSTAT_OBERR, 1 << 0   @ bitWidth 1 (Option bytes read error bit)  
        .equ FMC_OBSTAT_SPC, 1 << 1   @ bitWidth 1 (Option bytes security protection code)  
        .equ FMC_OBSTAT_USER_Shift, 2   @ bitWidth 8 (Store USER of option bytes block after system reset)  
        .equ FMC_OBSTAT_DATA_Shift, 10   @ bitWidth 16 (Store DATA[15:0] of option bytes block after system reset)  
 
    .equ FMC_WP, FMC_BASE + 0x20 @ (Erase/Program Protection register) 
        .equ FMC_WP_WP_Shift, 0   @ bitWidth 32 (Store WP[31:0] of option bytes block after system reset)  
 
    .equ FMC_PID, FMC_BASE + 0x100 @ (Product ID register) 
        .equ FMC_PID_PID_Shift, 0   @ bitWidth 32 (Product reserved ID code register)  
 

@=========================== FWDGT ===========================@
.equ FWDGT_BASE, 0x40003000 @ (free watchdog timer) 
    .equ FWDGT_CTL, FWDGT_BASE + 0x00 @ (Control register) 
        .equ FWDGT_CTL_CMD_Shift, 0   @ bitWidth 16 (Key value)  
 
    .equ FWDGT_PSC, FWDGT_BASE + 0x04 @ (Prescaler register) 
        .equ FWDGT_PSC_PSC_Shift, 0   @ bitWidth 3 (Free watchdog timer prescaler selection)  
 
    .equ FWDGT_RLD, FWDGT_BASE + 0x08 @ (Reload register) 
        .equ FWDGT_RLD_RLD_Shift, 0   @ bitWidth 12 (Free watchdog timer counter reload value)  
 
    .equ FWDGT_STAT, FWDGT_BASE + 0x0C @ (Status register) 
        .equ FWDGT_STAT_PUD, 1 << 0   @ bitWidth 1 (Free watchdog timer prescaler value update)  
        .equ FWDGT_STAT_RUD, 1 << 1   @ bitWidth 1 (Free watchdog timer counter reload value update)  
 

@=========================== GPIOA ===========================@
.equ GPIOA_BASE, 0x40010800 @ (General-purpose I/Os) 
    .equ GPIOA_CTL0, GPIOA_BASE + 0x0 @ (port control register 0) 
        .equ GPIOA_CTL0_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOA_CTL0_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOA_CTL0_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOA_CTL0_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOA_CTL0_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOA_CTL0_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOA_CTL0_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOA_CTL0_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOA_CTL0_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOA_CTL0_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOA_CTL0_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOA_CTL0_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOA_CTL0_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOA_CTL0_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOA_CTL0_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOA_CTL0_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOA_CTL1, GPIOA_BASE + 0x04 @ (port control register 1) 
        .equ GPIOA_CTL1_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOA_CTL1_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOA_CTL1_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOA_CTL1_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOA_CTL1_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOA_CTL1_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOA_CTL1_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOA_CTL1_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOA_CTL1_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOA_CTL1_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOA_CTL1_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOA_CTL1_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOA_CTL1_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOA_CTL1_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOA_CTL1_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOA_CTL1_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOA_ISTAT, GPIOA_BASE + 0x08 @ (Port input status register) 
        .equ GPIOA_ISTAT_ISTAT15, 1 << 15   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT14, 1 << 14   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT13, 1 << 13   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT12, 1 << 12   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT11, 1 << 11   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT10, 1 << 10   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT9, 1 << 9   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT8, 1 << 8   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT7, 1 << 7   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT6, 1 << 6   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT5, 1 << 5   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT4, 1 << 4   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT3, 1 << 3   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT2, 1 << 2   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT1, 1 << 1   @ bitWidth 1 (Port input status)  
        .equ GPIOA_ISTAT_ISTAT0, 1 << 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOA_OCTL, GPIOA_BASE + 0x0C @ (Port output control register) 
        .equ GPIOA_OCTL_OCTL15, 1 << 15   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL14, 1 << 14   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL13, 1 << 13   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL12, 1 << 12   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL11, 1 << 11   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL10, 1 << 10   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL9, 1 << 9   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL8, 1 << 8   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL7, 1 << 7   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL6, 1 << 6   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL5, 1 << 5   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL4, 1 << 4   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL3, 1 << 3   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL2, 1 << 2   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL1, 1 << 1   @ bitWidth 1 (Port output control)  
        .equ GPIOA_OCTL_OCTL0, 1 << 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOA_BOP, GPIOA_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOA_BOP_CR15, 1 << 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOA_BOP_CR14, 1 << 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOA_BOP_CR13, 1 << 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOA_BOP_CR12, 1 << 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOA_BOP_CR11, 1 << 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOA_BOP_CR10, 1 << 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOA_BOP_CR9, 1 << 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOA_BOP_CR8, 1 << 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOA_BOP_CR7, 1 << 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOA_BOP_CR6, 1 << 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOA_BOP_CR5, 1 << 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOA_BOP_CR4, 1 << 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOA_BOP_CR3, 1 << 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOA_BOP_CR2, 1 << 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOA_BOP_CR1, 1 << 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOA_BOP_CR0, 1 << 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOA_BOP_BOP15, 1 << 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOA_BOP_BOP14, 1 << 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOA_BOP_BOP13, 1 << 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOA_BOP_BOP12, 1 << 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOA_BOP_BOP11, 1 << 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOA_BOP_BOP10, 1 << 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOA_BOP_BOP9, 1 << 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOA_BOP_BOP8, 1 << 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOA_BOP_BOP7, 1 << 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOA_BOP_BOP6, 1 << 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOA_BOP_BOP5, 1 << 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOA_BOP_BOP4, 1 << 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOA_BOP_BOP3, 1 << 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOA_BOP_BOP2, 1 << 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOA_BOP_BOP1, 1 << 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOA_BOP_BOP0, 1 << 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOA_BC, GPIOA_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOA_BC_CR15, 1 << 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOA_BC_CR14, 1 << 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOA_BC_CR13, 1 << 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOA_BC_CR12, 1 << 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOA_BC_CR11, 1 << 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOA_BC_CR10, 1 << 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOA_BC_CR9, 1 << 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOA_BC_CR8, 1 << 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOA_BC_CR7, 1 << 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOA_BC_CR6, 1 << 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOA_BC_CR5, 1 << 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOA_BC_CR4, 1 << 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOA_BC_CR3, 1 << 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOA_BC_CR2, 1 << 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOA_BC_CR1, 1 << 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOA_BC_CR0, 1 << 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOA_LOCK, GPIOA_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOA_LOCK_LKK, 1 << 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOA_LOCK_LK15, 1 << 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOA_LOCK_LK14, 1 << 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOA_LOCK_LK13, 1 << 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOA_LOCK_LK12, 1 << 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOA_LOCK_LK11, 1 << 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOA_LOCK_LK10, 1 << 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOA_LOCK_LK9, 1 << 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOA_LOCK_LK8, 1 << 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOA_LOCK_LK7, 1 << 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOA_LOCK_LK6, 1 << 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOA_LOCK_LK5, 1 << 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOA_LOCK_LK4, 1 << 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOA_LOCK_LK3, 1 << 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOA_LOCK_LK2, 1 << 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOA_LOCK_LK1, 1 << 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOA_LOCK_LK0, 1 << 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOB ===========================@
.equ GPIOB_BASE, 0x40010C00 @ (General-purpose I/Os) 
    .equ GPIOB_CTL0, GPIOB_BASE + 0x0 @ (port control register 0) 
        .equ GPIOB_CTL0_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOB_CTL0_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOB_CTL0_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOB_CTL0_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOB_CTL0_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOB_CTL0_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOB_CTL0_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOB_CTL0_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOB_CTL0_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOB_CTL0_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOB_CTL0_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOB_CTL0_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOB_CTL0_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOB_CTL0_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOB_CTL0_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOB_CTL0_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOB_CTL1, GPIOB_BASE + 0x04 @ (port control register 1) 
        .equ GPIOB_CTL1_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOB_CTL1_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOB_CTL1_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOB_CTL1_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOB_CTL1_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOB_CTL1_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOB_CTL1_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOB_CTL1_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOB_CTL1_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOB_CTL1_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOB_CTL1_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOB_CTL1_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOB_CTL1_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOB_CTL1_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOB_CTL1_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOB_CTL1_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOB_ISTAT, GPIOB_BASE + 0x08 @ (Port input status register) 
        .equ GPIOB_ISTAT_ISTAT15, 1 << 15   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT14, 1 << 14   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT13, 1 << 13   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT12, 1 << 12   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT11, 1 << 11   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT10, 1 << 10   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT9, 1 << 9   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT8, 1 << 8   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT7, 1 << 7   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT6, 1 << 6   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT5, 1 << 5   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT4, 1 << 4   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT3, 1 << 3   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT2, 1 << 2   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT1, 1 << 1   @ bitWidth 1 (Port input status)  
        .equ GPIOB_ISTAT_ISTAT0, 1 << 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOB_OCTL, GPIOB_BASE + 0x0C @ (Port output control register) 
        .equ GPIOB_OCTL_OCTL15, 1 << 15   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL14, 1 << 14   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL13, 1 << 13   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL12, 1 << 12   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL11, 1 << 11   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL10, 1 << 10   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL9, 1 << 9   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL8, 1 << 8   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL7, 1 << 7   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL6, 1 << 6   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL5, 1 << 5   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL4, 1 << 4   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL3, 1 << 3   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL2, 1 << 2   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL1, 1 << 1   @ bitWidth 1 (Port output control)  
        .equ GPIOB_OCTL_OCTL0, 1 << 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOB_BOP, GPIOB_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOB_BOP_CR15, 1 << 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOB_BOP_CR14, 1 << 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOB_BOP_CR13, 1 << 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOB_BOP_CR12, 1 << 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOB_BOP_CR11, 1 << 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOB_BOP_CR10, 1 << 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOB_BOP_CR9, 1 << 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOB_BOP_CR8, 1 << 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOB_BOP_CR7, 1 << 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOB_BOP_CR6, 1 << 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOB_BOP_CR5, 1 << 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOB_BOP_CR4, 1 << 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOB_BOP_CR3, 1 << 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOB_BOP_CR2, 1 << 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOB_BOP_CR1, 1 << 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOB_BOP_CR0, 1 << 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOB_BOP_BOP15, 1 << 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOB_BOP_BOP14, 1 << 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOB_BOP_BOP13, 1 << 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOB_BOP_BOP12, 1 << 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOB_BOP_BOP11, 1 << 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOB_BOP_BOP10, 1 << 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOB_BOP_BOP9, 1 << 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOB_BOP_BOP8, 1 << 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOB_BOP_BOP7, 1 << 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOB_BOP_BOP6, 1 << 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOB_BOP_BOP5, 1 << 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOB_BOP_BOP4, 1 << 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOB_BOP_BOP3, 1 << 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOB_BOP_BOP2, 1 << 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOB_BOP_BOP1, 1 << 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOB_BOP_BOP0, 1 << 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOB_BC, GPIOB_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOB_BC_CR15, 1 << 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOB_BC_CR14, 1 << 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOB_BC_CR13, 1 << 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOB_BC_CR12, 1 << 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOB_BC_CR11, 1 << 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOB_BC_CR10, 1 << 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOB_BC_CR9, 1 << 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOB_BC_CR8, 1 << 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOB_BC_CR7, 1 << 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOB_BC_CR6, 1 << 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOB_BC_CR5, 1 << 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOB_BC_CR4, 1 << 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOB_BC_CR3, 1 << 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOB_BC_CR2, 1 << 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOB_BC_CR1, 1 << 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOB_BC_CR0, 1 << 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOB_LOCK, GPIOB_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOB_LOCK_LKK, 1 << 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOB_LOCK_LK15, 1 << 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOB_LOCK_LK14, 1 << 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOB_LOCK_LK13, 1 << 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOB_LOCK_LK12, 1 << 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOB_LOCK_LK11, 1 << 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOB_LOCK_LK10, 1 << 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOB_LOCK_LK9, 1 << 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOB_LOCK_LK8, 1 << 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOB_LOCK_LK7, 1 << 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOB_LOCK_LK6, 1 << 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOB_LOCK_LK5, 1 << 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOB_LOCK_LK4, 1 << 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOB_LOCK_LK3, 1 << 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOB_LOCK_LK2, 1 << 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOB_LOCK_LK1, 1 << 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOB_LOCK_LK0, 1 << 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOC ===========================@
.equ GPIOC_BASE, 0x40011000 @ (General-purpose I/Os) 
    .equ GPIOC_CTL0, GPIOC_BASE + 0x0 @ (port control register 0) 
        .equ GPIOC_CTL0_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOC_CTL0_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOC_CTL0_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOC_CTL0_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOC_CTL0_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOC_CTL0_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOC_CTL0_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOC_CTL0_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOC_CTL0_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOC_CTL0_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOC_CTL0_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOC_CTL0_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOC_CTL0_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOC_CTL0_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOC_CTL0_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOC_CTL0_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOC_CTL1, GPIOC_BASE + 0x04 @ (port control register 1) 
        .equ GPIOC_CTL1_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOC_CTL1_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOC_CTL1_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOC_CTL1_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOC_CTL1_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOC_CTL1_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOC_CTL1_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOC_CTL1_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOC_CTL1_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOC_CTL1_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOC_CTL1_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOC_CTL1_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOC_CTL1_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOC_CTL1_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOC_CTL1_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOC_CTL1_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOC_ISTAT, GPIOC_BASE + 0x08 @ (Port input status register) 
        .equ GPIOC_ISTAT_ISTAT15, 1 << 15   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT14, 1 << 14   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT13, 1 << 13   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT12, 1 << 12   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT11, 1 << 11   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT10, 1 << 10   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT9, 1 << 9   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT8, 1 << 8   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT7, 1 << 7   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT6, 1 << 6   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT5, 1 << 5   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT4, 1 << 4   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT3, 1 << 3   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT2, 1 << 2   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT1, 1 << 1   @ bitWidth 1 (Port input status)  
        .equ GPIOC_ISTAT_ISTAT0, 1 << 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOC_OCTL, GPIOC_BASE + 0x0C @ (Port output control register) 
        .equ GPIOC_OCTL_OCTL15, 1 << 15   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL14, 1 << 14   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL13, 1 << 13   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL12, 1 << 12   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL11, 1 << 11   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL10, 1 << 10   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL9, 1 << 9   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL8, 1 << 8   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL7, 1 << 7   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL6, 1 << 6   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL5, 1 << 5   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL4, 1 << 4   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL3, 1 << 3   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL2, 1 << 2   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL1, 1 << 1   @ bitWidth 1 (Port output control)  
        .equ GPIOC_OCTL_OCTL0, 1 << 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOC_BOP, GPIOC_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOC_BOP_CR15, 1 << 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOC_BOP_CR14, 1 << 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOC_BOP_CR13, 1 << 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOC_BOP_CR12, 1 << 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOC_BOP_CR11, 1 << 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOC_BOP_CR10, 1 << 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOC_BOP_CR9, 1 << 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOC_BOP_CR8, 1 << 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOC_BOP_CR7, 1 << 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOC_BOP_CR6, 1 << 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOC_BOP_CR5, 1 << 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOC_BOP_CR4, 1 << 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOC_BOP_CR3, 1 << 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOC_BOP_CR2, 1 << 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOC_BOP_CR1, 1 << 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOC_BOP_CR0, 1 << 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOC_BOP_BOP15, 1 << 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOC_BOP_BOP14, 1 << 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOC_BOP_BOP13, 1 << 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOC_BOP_BOP12, 1 << 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOC_BOP_BOP11, 1 << 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOC_BOP_BOP10, 1 << 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOC_BOP_BOP9, 1 << 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOC_BOP_BOP8, 1 << 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOC_BOP_BOP7, 1 << 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOC_BOP_BOP6, 1 << 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOC_BOP_BOP5, 1 << 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOC_BOP_BOP4, 1 << 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOC_BOP_BOP3, 1 << 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOC_BOP_BOP2, 1 << 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOC_BOP_BOP1, 1 << 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOC_BOP_BOP0, 1 << 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOC_BC, GPIOC_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOC_BC_CR15, 1 << 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOC_BC_CR14, 1 << 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOC_BC_CR13, 1 << 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOC_BC_CR12, 1 << 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOC_BC_CR11, 1 << 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOC_BC_CR10, 1 << 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOC_BC_CR9, 1 << 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOC_BC_CR8, 1 << 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOC_BC_CR7, 1 << 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOC_BC_CR6, 1 << 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOC_BC_CR5, 1 << 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOC_BC_CR4, 1 << 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOC_BC_CR3, 1 << 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOC_BC_CR2, 1 << 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOC_BC_CR1, 1 << 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOC_BC_CR0, 1 << 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOC_LOCK, GPIOC_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOC_LOCK_LKK, 1 << 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOC_LOCK_LK15, 1 << 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOC_LOCK_LK14, 1 << 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOC_LOCK_LK13, 1 << 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOC_LOCK_LK12, 1 << 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOC_LOCK_LK11, 1 << 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOC_LOCK_LK10, 1 << 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOC_LOCK_LK9, 1 << 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOC_LOCK_LK8, 1 << 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOC_LOCK_LK7, 1 << 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOC_LOCK_LK6, 1 << 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOC_LOCK_LK5, 1 << 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOC_LOCK_LK4, 1 << 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOC_LOCK_LK3, 1 << 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOC_LOCK_LK2, 1 << 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOC_LOCK_LK1, 1 << 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOC_LOCK_LK0, 1 << 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOD ===========================@
.equ GPIOD_BASE, 0x40011400 @ (General-purpose I/Os) 
    .equ GPIOD_CTL0, GPIOD_BASE + 0x0 @ (port control register 0) 
        .equ GPIOD_CTL0_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOD_CTL0_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOD_CTL0_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOD_CTL0_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOD_CTL0_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOD_CTL0_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOD_CTL0_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOD_CTL0_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOD_CTL0_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOD_CTL0_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOD_CTL0_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOD_CTL0_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOD_CTL0_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOD_CTL0_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOD_CTL0_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOD_CTL0_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOD_CTL1, GPIOD_BASE + 0x04 @ (port control register 1) 
        .equ GPIOD_CTL1_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOD_CTL1_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOD_CTL1_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOD_CTL1_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOD_CTL1_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOD_CTL1_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOD_CTL1_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOD_CTL1_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOD_CTL1_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOD_CTL1_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOD_CTL1_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOD_CTL1_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOD_CTL1_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOD_CTL1_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOD_CTL1_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOD_CTL1_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOD_ISTAT, GPIOD_BASE + 0x08 @ (Port input status register) 
        .equ GPIOD_ISTAT_ISTAT15, 1 << 15   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT14, 1 << 14   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT13, 1 << 13   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT12, 1 << 12   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT11, 1 << 11   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT10, 1 << 10   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT9, 1 << 9   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT8, 1 << 8   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT7, 1 << 7   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT6, 1 << 6   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT5, 1 << 5   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT4, 1 << 4   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT3, 1 << 3   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT2, 1 << 2   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT1, 1 << 1   @ bitWidth 1 (Port input status)  
        .equ GPIOD_ISTAT_ISTAT0, 1 << 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOD_OCTL, GPIOD_BASE + 0x0C @ (Port output control register) 
        .equ GPIOD_OCTL_OCTL15, 1 << 15   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL14, 1 << 14   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL13, 1 << 13   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL12, 1 << 12   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL11, 1 << 11   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL10, 1 << 10   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL9, 1 << 9   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL8, 1 << 8   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL7, 1 << 7   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL6, 1 << 6   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL5, 1 << 5   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL4, 1 << 4   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL3, 1 << 3   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL2, 1 << 2   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL1, 1 << 1   @ bitWidth 1 (Port output control)  
        .equ GPIOD_OCTL_OCTL0, 1 << 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOD_BOP, GPIOD_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOD_BOP_CR15, 1 << 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOD_BOP_CR14, 1 << 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOD_BOP_CR13, 1 << 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOD_BOP_CR12, 1 << 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOD_BOP_CR11, 1 << 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOD_BOP_CR10, 1 << 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOD_BOP_CR9, 1 << 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOD_BOP_CR8, 1 << 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOD_BOP_CR7, 1 << 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOD_BOP_CR6, 1 << 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOD_BOP_CR5, 1 << 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOD_BOP_CR4, 1 << 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOD_BOP_CR3, 1 << 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOD_BOP_CR2, 1 << 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOD_BOP_CR1, 1 << 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOD_BOP_CR0, 1 << 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOD_BOP_BOP15, 1 << 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOD_BOP_BOP14, 1 << 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOD_BOP_BOP13, 1 << 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOD_BOP_BOP12, 1 << 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOD_BOP_BOP11, 1 << 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOD_BOP_BOP10, 1 << 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOD_BOP_BOP9, 1 << 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOD_BOP_BOP8, 1 << 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOD_BOP_BOP7, 1 << 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOD_BOP_BOP6, 1 << 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOD_BOP_BOP5, 1 << 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOD_BOP_BOP4, 1 << 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOD_BOP_BOP3, 1 << 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOD_BOP_BOP2, 1 << 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOD_BOP_BOP1, 1 << 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOD_BOP_BOP0, 1 << 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOD_BC, GPIOD_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOD_BC_CR15, 1 << 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOD_BC_CR14, 1 << 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOD_BC_CR13, 1 << 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOD_BC_CR12, 1 << 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOD_BC_CR11, 1 << 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOD_BC_CR10, 1 << 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOD_BC_CR9, 1 << 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOD_BC_CR8, 1 << 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOD_BC_CR7, 1 << 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOD_BC_CR6, 1 << 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOD_BC_CR5, 1 << 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOD_BC_CR4, 1 << 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOD_BC_CR3, 1 << 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOD_BC_CR2, 1 << 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOD_BC_CR1, 1 << 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOD_BC_CR0, 1 << 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOD_LOCK, GPIOD_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOD_LOCK_LKK, 1 << 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOD_LOCK_LK15, 1 << 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOD_LOCK_LK14, 1 << 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOD_LOCK_LK13, 1 << 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOD_LOCK_LK12, 1 << 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOD_LOCK_LK11, 1 << 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOD_LOCK_LK10, 1 << 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOD_LOCK_LK9, 1 << 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOD_LOCK_LK8, 1 << 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOD_LOCK_LK7, 1 << 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOD_LOCK_LK6, 1 << 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOD_LOCK_LK5, 1 << 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOD_LOCK_LK4, 1 << 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOD_LOCK_LK3, 1 << 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOD_LOCK_LK2, 1 << 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOD_LOCK_LK1, 1 << 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOD_LOCK_LK0, 1 << 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== GPIOE ===========================@
.equ GPIOE_BASE, 0x40011800 @ (General-purpose I/Os) 
    .equ GPIOE_CTL0, GPIOE_BASE + 0x0 @ (port control register 0) 
        .equ GPIOE_CTL0_CTL7_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  7)  
        .equ GPIOE_CTL0_MD7_Shift, 28   @ bitWidth 2 (Port x mode bits x =  7)  
        .equ GPIOE_CTL0_CTL6_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  6)  
        .equ GPIOE_CTL0_MD6_Shift, 24   @ bitWidth 2 (Port x mode bits x =  6)  
        .equ GPIOE_CTL0_CTL5_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  5)  
        .equ GPIOE_CTL0_MD5_Shift, 20   @ bitWidth 2 (Port x mode bits x =  5)  
        .equ GPIOE_CTL0_CTL4_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  4)  
        .equ GPIOE_CTL0_MD4_Shift, 16   @ bitWidth 2 (Port x mode bits x =  4)  
        .equ GPIOE_CTL0_CTL3_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  3)  
        .equ GPIOE_CTL0_MD3_Shift, 12   @ bitWidth 2 (Port x mode bits x =  3 )  
        .equ GPIOE_CTL0_CTL2_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  2)  
        .equ GPIOE_CTL0_MD2_Shift, 8   @ bitWidth 2 (Port x mode bits x =  2 )  
        .equ GPIOE_CTL0_CTL1_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  1)  
        .equ GPIOE_CTL0_MD1_Shift, 4   @ bitWidth 2 (Port x mode bits x =  1)  
        .equ GPIOE_CTL0_CTL0_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  0)  
        .equ GPIOE_CTL0_MD0_Shift, 0   @ bitWidth 2 (Port x mode bits x =  0)  
 
    .equ GPIOE_CTL1, GPIOE_BASE + 0x04 @ (port control register 1) 
        .equ GPIOE_CTL1_CTL15_Shift, 30   @ bitWidth 2 (Port x configuration bits x =  15)  
        .equ GPIOE_CTL1_MD15_Shift, 28   @ bitWidth 2 (Port x mode bits x =  15)  
        .equ GPIOE_CTL1_CTL14_Shift, 26   @ bitWidth 2 (Port x configuration bits x =  14)  
        .equ GPIOE_CTL1_MD14_Shift, 24   @ bitWidth 2 (Port x mode bits x =  14)  
        .equ GPIOE_CTL1_CTL13_Shift, 22   @ bitWidth 2 (Port x configuration bits x =  13)  
        .equ GPIOE_CTL1_MD13_Shift, 20   @ bitWidth 2 (Port x mode bits x =  13)  
        .equ GPIOE_CTL1_CTL12_Shift, 18   @ bitWidth 2 (Port x configuration bits x =  12)  
        .equ GPIOE_CTL1_MD12_Shift, 16   @ bitWidth 2 (Port x mode bits x =  12)  
        .equ GPIOE_CTL1_CTL11_Shift, 14   @ bitWidth 2 (Port x configuration bits x =  11)  
        .equ GPIOE_CTL1_MD11_Shift, 12   @ bitWidth 2 (Port x mode bits x =  11 )  
        .equ GPIOE_CTL1_CTL10_Shift, 10   @ bitWidth 2 (Port x configuration bits x =  10)  
        .equ GPIOE_CTL1_MD10_Shift, 8   @ bitWidth 2 (Port x mode bits x =  10 )  
        .equ GPIOE_CTL1_CTL9_Shift, 6   @ bitWidth 2 (Port x configuration bits x =  9)  
        .equ GPIOE_CTL1_MD9_Shift, 4   @ bitWidth 2 (Port x mode bits x =  9)  
        .equ GPIOE_CTL1_CTL8_Shift, 2   @ bitWidth 2 (Port x configuration bits x =  8)  
        .equ GPIOE_CTL1_MD8_Shift, 0   @ bitWidth 2 (Port x mode bits x =  8)  
 
    .equ GPIOE_ISTAT, GPIOE_BASE + 0x08 @ (Port input status register) 
        .equ GPIOE_ISTAT_ISTAT15, 1 << 15   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT14, 1 << 14   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT13, 1 << 13   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT12, 1 << 12   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT11, 1 << 11   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT10, 1 << 10   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT9, 1 << 9   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT8, 1 << 8   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT7, 1 << 7   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT6, 1 << 6   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT5, 1 << 5   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT4, 1 << 4   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT3, 1 << 3   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT2, 1 << 2   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT1, 1 << 1   @ bitWidth 1 (Port input status)  
        .equ GPIOE_ISTAT_ISTAT0, 1 << 0   @ bitWidth 1 (Port input status)  
 
    .equ GPIOE_OCTL, GPIOE_BASE + 0x0C @ (Port output control register) 
        .equ GPIOE_OCTL_OCTL15, 1 << 15   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL14, 1 << 14   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL13, 1 << 13   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL12, 1 << 12   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL11, 1 << 11   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL10, 1 << 10   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL9, 1 << 9   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL8, 1 << 8   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL7, 1 << 7   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL6, 1 << 6   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL5, 1 << 5   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL4, 1 << 4   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL3, 1 << 3   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL2, 1 << 2   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL1, 1 << 1   @ bitWidth 1 (Port output control)  
        .equ GPIOE_OCTL_OCTL0, 1 << 0   @ bitWidth 1 (Port output control)  
 
    .equ GPIOE_BOP, GPIOE_BASE + 0x10 @ (Port bit operate register) 
        .equ GPIOE_BOP_CR15, 1 << 31   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOE_BOP_CR14, 1 << 30   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOE_BOP_CR13, 1 << 29   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOE_BOP_CR12, 1 << 28   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOE_BOP_CR11, 1 << 27   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOE_BOP_CR10, 1 << 26   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOE_BOP_CR9, 1 << 25   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOE_BOP_CR8, 1 << 24   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOE_BOP_CR7, 1 << 23   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOE_BOP_CR6, 1 << 22   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOE_BOP_CR5, 1 << 21   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOE_BOP_CR4, 1 << 20   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOE_BOP_CR3, 1 << 19   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOE_BOP_CR2, 1 << 18   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOE_BOP_CR1, 1 << 17   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOE_BOP_CR0, 1 << 16   @ bitWidth 1 (Port 0 Clear bit)  
        .equ GPIOE_BOP_BOP15, 1 << 15   @ bitWidth 1 (Port 15 Set bit)  
        .equ GPIOE_BOP_BOP14, 1 << 14   @ bitWidth 1 (Port 14 Set bit)  
        .equ GPIOE_BOP_BOP13, 1 << 13   @ bitWidth 1 (Port 13 Set bit)  
        .equ GPIOE_BOP_BOP12, 1 << 12   @ bitWidth 1 (Port 12 Set bit)  
        .equ GPIOE_BOP_BOP11, 1 << 11   @ bitWidth 1 (Port 11 Set bit)  
        .equ GPIOE_BOP_BOP10, 1 << 10   @ bitWidth 1 (Port 10 Set bit)  
        .equ GPIOE_BOP_BOP9, 1 << 9   @ bitWidth 1 (Port 9 Set bit)  
        .equ GPIOE_BOP_BOP8, 1 << 8   @ bitWidth 1 (Port 8 Set bit)  
        .equ GPIOE_BOP_BOP7, 1 << 7   @ bitWidth 1 (Port 7 Set bit)  
        .equ GPIOE_BOP_BOP6, 1 << 6   @ bitWidth 1 (Port 6 Set bit)  
        .equ GPIOE_BOP_BOP5, 1 << 5   @ bitWidth 1 (Port 5 Set bit)  
        .equ GPIOE_BOP_BOP4, 1 << 4   @ bitWidth 1 (Port 4 Set bit)  
        .equ GPIOE_BOP_BOP3, 1 << 3   @ bitWidth 1 (Port 3 Set bit)  
        .equ GPIOE_BOP_BOP2, 1 << 2   @ bitWidth 1 (Port 2 Set bit)  
        .equ GPIOE_BOP_BOP1, 1 << 1   @ bitWidth 1 (Port 1 Set bit)  
        .equ GPIOE_BOP_BOP0, 1 << 0   @ bitWidth 1 (Port 0 Set bit)  
 
    .equ GPIOE_BC, GPIOE_BASE + 0x14 @ (Port bit clear register) 
        .equ GPIOE_BC_CR15, 1 << 15   @ bitWidth 1 (Port 15 Clear bit)  
        .equ GPIOE_BC_CR14, 1 << 14   @ bitWidth 1 (Port 14 Clear bit)  
        .equ GPIOE_BC_CR13, 1 << 13   @ bitWidth 1 (Port 13 Clear bit)  
        .equ GPIOE_BC_CR12, 1 << 12   @ bitWidth 1 (Port 12 Clear bit)  
        .equ GPIOE_BC_CR11, 1 << 11   @ bitWidth 1 (Port 11 Clear bit)  
        .equ GPIOE_BC_CR10, 1 << 10   @ bitWidth 1 (Port 10 Clear bit)  
        .equ GPIOE_BC_CR9, 1 << 9   @ bitWidth 1 (Port 9 Clear bit)  
        .equ GPIOE_BC_CR8, 1 << 8   @ bitWidth 1 (Port 8 Clear bit)  
        .equ GPIOE_BC_CR7, 1 << 7   @ bitWidth 1 (Port 7 Clear bit)  
        .equ GPIOE_BC_CR6, 1 << 6   @ bitWidth 1 (Port 6 Clear bit)  
        .equ GPIOE_BC_CR5, 1 << 5   @ bitWidth 1 (Port 5 Clear bit)  
        .equ GPIOE_BC_CR4, 1 << 4   @ bitWidth 1 (Port 4 Clear bit)  
        .equ GPIOE_BC_CR3, 1 << 3   @ bitWidth 1 (Port 3 Clear bit)  
        .equ GPIOE_BC_CR2, 1 << 2   @ bitWidth 1 (Port 2 Clear bit)  
        .equ GPIOE_BC_CR1, 1 << 1   @ bitWidth 1 (Port 1 Clear bit)  
        .equ GPIOE_BC_CR0, 1 << 0   @ bitWidth 1 (Port 0 Clear bit)  
 
    .equ GPIOE_LOCK, GPIOE_BASE + 0x18 @ (GPIO port configuration lock  register) 
        .equ GPIOE_LOCK_LKK, 1 << 16   @ bitWidth 1 (Lock sequence key  )  
        .equ GPIOE_LOCK_LK15, 1 << 15   @ bitWidth 1 (Port Lock bit 15)  
        .equ GPIOE_LOCK_LK14, 1 << 14   @ bitWidth 1 (Port Lock bit 14)  
        .equ GPIOE_LOCK_LK13, 1 << 13   @ bitWidth 1 (Port Lock bit 13)  
        .equ GPIOE_LOCK_LK12, 1 << 12   @ bitWidth 1 (Port Lock bit 12)  
        .equ GPIOE_LOCK_LK11, 1 << 11   @ bitWidth 1 (Port Lock bit 11)  
        .equ GPIOE_LOCK_LK10, 1 << 10   @ bitWidth 1 (Port Lock bit 10)  
        .equ GPIOE_LOCK_LK9, 1 << 9   @ bitWidth 1 (Port Lock bit 9)  
        .equ GPIOE_LOCK_LK8, 1 << 8   @ bitWidth 1 (Port Lock bit 8)  
        .equ GPIOE_LOCK_LK7, 1 << 7   @ bitWidth 1 (Port Lock bit 7)  
        .equ GPIOE_LOCK_LK6, 1 << 6   @ bitWidth 1 (Port Lock bit 6)  
        .equ GPIOE_LOCK_LK5, 1 << 5   @ bitWidth 1 (Port Lock bit 5)  
        .equ GPIOE_LOCK_LK4, 1 << 4   @ bitWidth 1 (Port Lock bit 4)  
        .equ GPIOE_LOCK_LK3, 1 << 3   @ bitWidth 1 (Port Lock bit 3)  
        .equ GPIOE_LOCK_LK2, 1 << 2   @ bitWidth 1 (Port Lock bit 2)  
        .equ GPIOE_LOCK_LK1, 1 << 1   @ bitWidth 1 (Port Lock bit 1)  
        .equ GPIOE_LOCK_LK0, 1 << 0   @ bitWidth 1 (Port Lock bit 0)  
 

@=========================== I2C0 ===========================@
.equ I2C0_BASE, 0x40005400 @ (Inter integrated circuit) 
    .equ I2C0_CTL0, I2C0_BASE + 0x0 @ (Control register 0) 
        .equ I2C0_CTL0_SRESET, 1 << 15   @ bitWidth 1 (Software reset)  
        .equ I2C0_CTL0_SALT, 1 << 13   @ bitWidth 1 (SMBus alert)  
        .equ I2C0_CTL0_PECTRANS, 1 << 12   @ bitWidth 1 (PEC Transfer)  
        .equ I2C0_CTL0_POAP, 1 << 11   @ bitWidth 1 (Position of ACK and PEC when receiving)  
        .equ I2C0_CTL0_ACKEN, 1 << 10   @ bitWidth 1 (Whether or not to send an ACK)  
        .equ I2C0_CTL0_STOP, 1 << 9   @ bitWidth 1 (Generate a STOP condition on I2C bus)  
        .equ I2C0_CTL0_START, 1 << 8   @ bitWidth 1 (Generate a START condition on I2C bus)  
        .equ I2C0_CTL0_SS, 1 << 7   @ bitWidth 1 (Whether to stretch SCL low when data is not ready in slave mode)  
        .equ I2C0_CTL0_GCEN, 1 << 6   @ bitWidth 1 (Whether or not to response to a General Call 0x00)  
        .equ I2C0_CTL0_PECEN, 1 << 5   @ bitWidth 1 (PEC Calculation Switch)  
        .equ I2C0_CTL0_ARPEN, 1 << 4   @ bitWidth 1 (ARP protocol in SMBus switch)  
        .equ I2C0_CTL0_SMBSEL, 1 << 3   @ bitWidth 1 (SMBusType Selection)  
        .equ I2C0_CTL0_SMBEN, 1 << 1   @ bitWidth 1 (SMBus/I2C mode switch)  
        .equ I2C0_CTL0_I2CEN, 1 << 0   @ bitWidth 1 (I2C peripheral enable)  
 
    .equ I2C0_CTL1, I2C0_BASE + 0x04 @ (Control register 1) 
        .equ I2C0_CTL1_DMALST, 1 << 12   @ bitWidth 1 (Flag indicating DMA last transfer)  
        .equ I2C0_CTL1_DMAON, 1 << 11   @ bitWidth 1 (DMA mode switch)  
        .equ I2C0_CTL1_BUFIE, 1 << 10   @ bitWidth 1 (Buffer interrupt enable)  
        .equ I2C0_CTL1_EVIE, 1 << 9   @ bitWidth 1 (Event interrupt enable)  
        .equ I2C0_CTL1_ERRIE, 1 << 8   @ bitWidth 1 (Error interrupt enable)  
        .equ I2C0_CTL1_I2CCLK_Shift, 0   @ bitWidth 6 (I2C Peripheral clock frequency)  
 
    .equ I2C0_SADDR0, I2C0_BASE + 0x08 @ (Slave address register 0) 
        .equ I2C0_SADDR0_ADDFORMAT, 1 << 15   @ bitWidth 1 (Address mode for the I2C slave)  
        .equ I2C0_SADDR0_ADDRESS9_8_Shift, 8   @ bitWidth 2 (Highest two bits of a 10-bit address)  
        .equ I2C0_SADDR0_ADDRESS7_1_Shift, 1   @ bitWidth 7 (7-bit address or bits 7:1 of a 10-bit address)  
        .equ I2C0_SADDR0_ADDRESS0, 1 << 0   @ bitWidth 1 (Bit 0 of a 10-bit address)  
 
    .equ I2C0_SADDR1, I2C0_BASE + 0x0C @ (Slave address register 1) 
        .equ I2C0_SADDR1_ADDRESS2_Shift, 1   @ bitWidth 7 (Second I2C address for the slave in Dual-Address mode)  
        .equ I2C0_SADDR1_DUADEN, 1 << 0   @ bitWidth 1 (Dual-Address mode switch)  
 
    .equ I2C0_DATA, I2C0_BASE + 0x10 @ (Transfer buffer register) 
        .equ I2C0_DATA_TRB_Shift, 0   @ bitWidth 8 (Transmission or reception data buffer register)  
 
    .equ I2C0_STAT0, I2C0_BASE + 0x14 @ (Transfer status register 0) 
        .equ I2C0_STAT0_SMBALT, 1 << 15   @ bitWidth 1 (SMBus Alert status)  
        .equ I2C0_STAT0_SMBTO, 1 << 14   @ bitWidth 1 (Timeout signal in SMBus mode)  
        .equ I2C0_STAT0_PECERR, 1 << 12   @ bitWidth 1 (PEC error when receiving data)  
        .equ I2C0_STAT0_OUERR, 1 << 11   @ bitWidth 1 (Over-run or under-run situation occurs in slave mode)  
        .equ I2C0_STAT0_AERR, 1 << 10   @ bitWidth 1 (Acknowledge error)  
        .equ I2C0_STAT0_LOSTARB, 1 << 9   @ bitWidth 1 (Arbitration Lost in master mode)  
        .equ I2C0_STAT0_BERR, 1 << 8   @ bitWidth 1 (A bus error occurs indication a unexpected START or STOP condition on I2C bus)  
        .equ I2C0_STAT0_TBE, 1 << 7   @ bitWidth 1 (I2C_DATA is Empty during transmitting)  
        .equ I2C0_STAT0_RBNE, 1 << 6   @ bitWidth 1 (I2C_DATA is not Empty during receiving)  
        .equ I2C0_STAT0_STPDET, 1 << 4   @ bitWidth 1 (STOP condition detected in slave mode)  
        .equ I2C0_STAT0_ADD10SEND, 1 << 3   @ bitWidth 1 (Header of 10-bit address is sent in master mode)  
        .equ I2C0_STAT0_BTC, 1 << 2   @ bitWidth 1 (Byte transmission completed)  
        .equ I2C0_STAT0_ADDSEND, 1 << 1   @ bitWidth 1 (Address is sent in master mode or received and matches in slave mode)  
        .equ I2C0_STAT0_SBSEND, 1 << 0   @ bitWidth 1 (START condition sent out in master mode)  
 
    .equ I2C0_STAT1, I2C0_BASE + 0x18 @ (Transfer status register 1) 
        .equ I2C0_STAT1_PECV_Shift, 8   @ bitWidth 8 (Packet Error Checking Value that calculated by hardware when PEC is enabled)  
        .equ I2C0_STAT1_DUMODF, 1 << 7   @ bitWidth 1 (Dual Flag in slave mode)  
        .equ I2C0_STAT1_HSTSMB, 1 << 6   @ bitWidth 1 (SMBus Host Header detected in slave mode)  
        .equ I2C0_STAT1_DEFSMB, 1 << 5   @ bitWidth 1 (Default address of SMBusDevice)  
        .equ I2C0_STAT1_RXGC, 1 << 4   @ bitWidth 1 (General call address 00h received)  
        .equ I2C0_STAT1_TR, 1 << 2   @ bitWidth 1 (Whether the I2C is a transmitter or a receiver)  
        .equ I2C0_STAT1_I2CBSY, 1 << 1   @ bitWidth 1 (Busy flag)  
        .equ I2C0_STAT1_MASTER, 1 << 0   @ bitWidth 1 (A flag indicating whether I2C block is in master or slave mode)  
 
    .equ I2C0_CKCFG, I2C0_BASE + 0x1C @ (Clock configure register) 
        .equ I2C0_CKCFG_FAST, 1 << 15   @ bitWidth 1 (I2C speed selection in master mode)  
        .equ I2C0_CKCFG_DTCY, 1 << 14   @ bitWidth 1 (Duty cycle in fast mode)  
        .equ I2C0_CKCFG_CLKC_Shift, 0   @ bitWidth 12 (I2C Clock control in master mode)  
 
    .equ I2C0_RT, I2C0_BASE + 0x20 @ (Rise time register) 
        .equ I2C0_RT_RISETIME_Shift, 0   @ bitWidth 6 (Maximum rise time in master mode)  
 

@=========================== I2C1 ===========================@
.equ I2C1_BASE, 0x40005800 @ (Inter integrated circuit) 
    .equ I2C1_CTL0, I2C1_BASE + 0x0 @ (Control register 0) 
        .equ I2C1_CTL0_SRESET, 1 << 15   @ bitWidth 1 (Software reset)  
        .equ I2C1_CTL0_SALT, 1 << 13   @ bitWidth 1 (SMBus alert)  
        .equ I2C1_CTL0_PECTRANS, 1 << 12   @ bitWidth 1 (PEC Transfer)  
        .equ I2C1_CTL0_POAP, 1 << 11   @ bitWidth 1 (Position of ACK and PEC when receiving)  
        .equ I2C1_CTL0_ACKEN, 1 << 10   @ bitWidth 1 (Whether or not to send an ACK)  
        .equ I2C1_CTL0_STOP, 1 << 9   @ bitWidth 1 (Generate a STOP condition on I2C bus)  
        .equ I2C1_CTL0_START, 1 << 8   @ bitWidth 1 (Generate a START condition on I2C bus)  
        .equ I2C1_CTL0_SS, 1 << 7   @ bitWidth 1 (Whether to stretch SCL low when data is not ready in slave mode)  
        .equ I2C1_CTL0_GCEN, 1 << 6   @ bitWidth 1 (Whether or not to response to a General Call 0x00)  
        .equ I2C1_CTL0_PECEN, 1 << 5   @ bitWidth 1 (PEC Calculation Switch)  
        .equ I2C1_CTL0_ARPEN, 1 << 4   @ bitWidth 1 (ARP protocol in SMBus switch)  
        .equ I2C1_CTL0_SMBSEL, 1 << 3   @ bitWidth 1 (SMBusType Selection)  
        .equ I2C1_CTL0_SMBEN, 1 << 1   @ bitWidth 1 (SMBus/I2C mode switch)  
        .equ I2C1_CTL0_I2CEN, 1 << 0   @ bitWidth 1 (I2C peripheral enable)  
 
    .equ I2C1_CTL1, I2C1_BASE + 0x04 @ (Control register 1) 
        .equ I2C1_CTL1_DMALST, 1 << 12   @ bitWidth 1 (Flag indicating DMA last transfer)  
        .equ I2C1_CTL1_DMAON, 1 << 11   @ bitWidth 1 (DMA mode switch)  
        .equ I2C1_CTL1_BUFIE, 1 << 10   @ bitWidth 1 (Buffer interrupt enable)  
        .equ I2C1_CTL1_EVIE, 1 << 9   @ bitWidth 1 (Event interrupt enable)  
        .equ I2C1_CTL1_ERRIE, 1 << 8   @ bitWidth 1 (Error interrupt enable)  
        .equ I2C1_CTL1_I2CCLK_Shift, 0   @ bitWidth 6 (I2C Peripheral clock frequency)  
 
    .equ I2C1_SADDR0, I2C1_BASE + 0x08 @ (Slave address register 0) 
        .equ I2C1_SADDR0_ADDFORMAT, 1 << 15   @ bitWidth 1 (Address mode for the I2C slave)  
        .equ I2C1_SADDR0_ADDRESS9_8_Shift, 8   @ bitWidth 2 (Highest two bits of a 10-bit address)  
        .equ I2C1_SADDR0_ADDRESS7_1_Shift, 1   @ bitWidth 7 (7-bit address or bits 7:1 of a 10-bit address)  
        .equ I2C1_SADDR0_ADDRESS0, 1 << 0   @ bitWidth 1 (Bit 0 of a 10-bit address)  
 
    .equ I2C1_SADDR1, I2C1_BASE + 0x0C @ (Slave address register 1) 
        .equ I2C1_SADDR1_ADDRESS2_Shift, 1   @ bitWidth 7 (Second I2C address for the slave in Dual-Address mode)  
        .equ I2C1_SADDR1_DUADEN, 1 << 0   @ bitWidth 1 (Dual-Address mode switch)  
 
    .equ I2C1_DATA, I2C1_BASE + 0x10 @ (Transfer buffer register) 
        .equ I2C1_DATA_TRB_Shift, 0   @ bitWidth 8 (Transmission or reception data buffer register)  
 
    .equ I2C1_STAT0, I2C1_BASE + 0x14 @ (Transfer status register 0) 
        .equ I2C1_STAT0_SMBALT, 1 << 15   @ bitWidth 1 (SMBus Alert status)  
        .equ I2C1_STAT0_SMBTO, 1 << 14   @ bitWidth 1 (Timeout signal in SMBus mode)  
        .equ I2C1_STAT0_PECERR, 1 << 12   @ bitWidth 1 (PEC error when receiving data)  
        .equ I2C1_STAT0_OUERR, 1 << 11   @ bitWidth 1 (Over-run or under-run situation occurs in slave mode)  
        .equ I2C1_STAT0_AERR, 1 << 10   @ bitWidth 1 (Acknowledge error)  
        .equ I2C1_STAT0_LOSTARB, 1 << 9   @ bitWidth 1 (Arbitration Lost in master mode)  
        .equ I2C1_STAT0_BERR, 1 << 8   @ bitWidth 1 (A bus error occurs indication a unexpected START or STOP condition on I2C bus)  
        .equ I2C1_STAT0_TBE, 1 << 7   @ bitWidth 1 (I2C_DATA is Empty during transmitting)  
        .equ I2C1_STAT0_RBNE, 1 << 6   @ bitWidth 1 (I2C_DATA is not Empty during receiving)  
        .equ I2C1_STAT0_STPDET, 1 << 4   @ bitWidth 1 (STOP condition detected in slave mode)  
        .equ I2C1_STAT0_ADD10SEND, 1 << 3   @ bitWidth 1 (Header of 10-bit address is sent in master mode)  
        .equ I2C1_STAT0_BTC, 1 << 2   @ bitWidth 1 (Byte transmission completed)  
        .equ I2C1_STAT0_ADDSEND, 1 << 1   @ bitWidth 1 (Address is sent in master mode or received and matches in slave mode)  
        .equ I2C1_STAT0_SBSEND, 1 << 0   @ bitWidth 1 (START condition sent out in master mode)  
 
    .equ I2C1_STAT1, I2C1_BASE + 0x18 @ (Transfer status register 1) 
        .equ I2C1_STAT1_PECV_Shift, 8   @ bitWidth 8 (Packet Error Checking Value that calculated by hardware when PEC is enabled)  
        .equ I2C1_STAT1_DUMODF, 1 << 7   @ bitWidth 1 (Dual Flag in slave mode)  
        .equ I2C1_STAT1_HSTSMB, 1 << 6   @ bitWidth 1 (SMBus Host Header detected in slave mode)  
        .equ I2C1_STAT1_DEFSMB, 1 << 5   @ bitWidth 1 (Default address of SMBusDevice)  
        .equ I2C1_STAT1_RXGC, 1 << 4   @ bitWidth 1 (General call address 00h received)  
        .equ I2C1_STAT1_TR, 1 << 2   @ bitWidth 1 (Whether the I2C is a transmitter or a receiver)  
        .equ I2C1_STAT1_I2CBSY, 1 << 1   @ bitWidth 1 (Busy flag)  
        .equ I2C1_STAT1_MASTER, 1 << 0   @ bitWidth 1 (A flag indicating whether I2C block is in master or slave mode)  
 
    .equ I2C1_CKCFG, I2C1_BASE + 0x1C @ (Clock configure register) 
        .equ I2C1_CKCFG_FAST, 1 << 15   @ bitWidth 1 (I2C speed selection in master mode)  
        .equ I2C1_CKCFG_DTCY, 1 << 14   @ bitWidth 1 (Duty cycle in fast mode)  
        .equ I2C1_CKCFG_CLKC_Shift, 0   @ bitWidth 12 (I2C Clock control in master mode)  
 
    .equ I2C1_RT, I2C1_BASE + 0x20 @ (Rise time register) 
        .equ I2C1_RT_RISETIME_Shift, 0   @ bitWidth 6 (Maximum rise time in master mode)  
 

@=========================== ECLIC ===========================@
.equ ECLIC_BASE, 0xD2000000 @ (Enhanced Core Local Interrupt Controller) 
    .equ ECLIC_CLICCFG, ECLIC_BASE + 0x0 @ (cliccfg Register) 
        .equ ECLIC_CLICCFG_NLBITS_Shift, 1   @ bitWidth 4 (NLBITS)  
 
    .equ ECLIC_CLICINFO, ECLIC_BASE + 0x04 @ (clicinfo Register) 
        .equ ECLIC_CLICINFO_NUM_INTERRUPT_Shift, 0   @ bitWidth 13 (NUM_INTERRUPT)  
        .equ ECLIC_CLICINFO_VERSION_Shift, 13   @ bitWidth 8 (VERSION)  
        .equ ECLIC_CLICINFO_CLICINTCTLBITS_Shift, 21   @ bitWidth 4 (CLICINTCTLBITS)  
 
    .equ ECLIC_MTH, ECLIC_BASE + 0x0b @ (MTH Register) 
        .equ ECLIC_MTH_MTH_Shift, 0   @ bitWidth 8 (MTH)  
 
    .equ ECLIC_CLICINTIP_0, ECLIC_BASE + 0x1000 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_0_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_1, ECLIC_BASE + 0x1004 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_1_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_2, ECLIC_BASE + 0x1008 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_2_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_3, ECLIC_BASE + 0x100C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_3_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_4, ECLIC_BASE + 0x1010 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_4_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_5, ECLIC_BASE + 0x1014 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_5_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_6, ECLIC_BASE + 0x1018 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_6_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_7, ECLIC_BASE + 0x101C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_7_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_8, ECLIC_BASE + 0x1020 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_8_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_9, ECLIC_BASE + 0x1024 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_9_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_10, ECLIC_BASE + 0x1028 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_10_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_11, ECLIC_BASE + 0x102C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_11_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_12, ECLIC_BASE + 0x1030 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_12_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_13, ECLIC_BASE + 0x1034 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_13_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_14, ECLIC_BASE + 0x1038 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_14_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_15, ECLIC_BASE + 0x103C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_15_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_16, ECLIC_BASE + 0x1040 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_16_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_17, ECLIC_BASE + 0x1044 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_17_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_18, ECLIC_BASE + 0x1048 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_18_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_19, ECLIC_BASE + 0x104C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_19_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_20, ECLIC_BASE + 0x1050 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_20_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_21, ECLIC_BASE + 0x1054 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_21_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_22, ECLIC_BASE + 0x1058 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_22_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_23, ECLIC_BASE + 0x105C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_23_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_24, ECLIC_BASE + 0x1060 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_24_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_25, ECLIC_BASE + 0x1064 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_25_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_26, ECLIC_BASE + 0x1068 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_26_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_27, ECLIC_BASE + 0x106C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_27_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_28, ECLIC_BASE + 0x1070 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_28_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_29, ECLIC_BASE + 0x1074 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_29_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_30, ECLIC_BASE + 0x1078 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_30_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_31, ECLIC_BASE + 0x107C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_31_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_32, ECLIC_BASE + 0x1080 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_32_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_33, ECLIC_BASE + 0x1084 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_33_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_34, ECLIC_BASE + 0x1088 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_34_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_35, ECLIC_BASE + 0x108C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_35_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_36, ECLIC_BASE + 0x1090 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_36_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_37, ECLIC_BASE + 0x1094 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_37_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_38, ECLIC_BASE + 0x1098 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_38_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_39, ECLIC_BASE + 0x109C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_39_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_40, ECLIC_BASE + 0x10A0 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_40_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_41, ECLIC_BASE + 0x10A4 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_41_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_42, ECLIC_BASE + 0x10A8 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_42_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_43, ECLIC_BASE + 0x10AC @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_43_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_44, ECLIC_BASE + 0x10B0 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_44_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_45, ECLIC_BASE + 0x10B4 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_45_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_46, ECLIC_BASE + 0x10B8 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_46_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_47, ECLIC_BASE + 0x10BC @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_47_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_48, ECLIC_BASE + 0x10C0 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_48_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_49, ECLIC_BASE + 0x10C4 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_49_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_50, ECLIC_BASE + 0x10C8 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_50_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_51, ECLIC_BASE + 0x10CC @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_51_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_52, ECLIC_BASE + 0x10D0 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_52_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_53, ECLIC_BASE + 0x10D4 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_53_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_54, ECLIC_BASE + 0x10D8 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_54_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_55, ECLIC_BASE + 0x10DC @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_55_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_56, ECLIC_BASE + 0x10E0 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_56_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_57, ECLIC_BASE + 0x10E4 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_57_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_58, ECLIC_BASE + 0x10E8 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_58_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_59, ECLIC_BASE + 0x10EC @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_59_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_60, ECLIC_BASE + 0x10F0 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_60_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_61, ECLIC_BASE + 0x10F4 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_61_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_62, ECLIC_BASE + 0x10F8 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_62_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_63, ECLIC_BASE + 0x10FC @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_63_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_64, ECLIC_BASE + 0x1100 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_64_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_65, ECLIC_BASE + 0x1104 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_65_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_66, ECLIC_BASE + 0x1108 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_66_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_67, ECLIC_BASE + 0x110C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_67_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_68, ECLIC_BASE + 0x1110 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_68_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_69, ECLIC_BASE + 0x1114 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_69_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_70, ECLIC_BASE + 0x1118 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_70_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_71, ECLIC_BASE + 0x111C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_71_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_72, ECLIC_BASE + 0x1120 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_72_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_73, ECLIC_BASE + 0x1124 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_73_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_74, ECLIC_BASE + 0x1128 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_74_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_75, ECLIC_BASE + 0x112C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_75_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_76, ECLIC_BASE + 0x1130 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_76_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_77, ECLIC_BASE + 0x1134 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_77_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_78, ECLIC_BASE + 0x1138 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_78_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_79, ECLIC_BASE + 0x113C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_79_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_80, ECLIC_BASE + 0x1140 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_80_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_81, ECLIC_BASE + 0x1144 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_81_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_82, ECLIC_BASE + 0x1148 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_82_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_83, ECLIC_BASE + 0x114C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_83_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_84, ECLIC_BASE + 0x1150 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_84_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_85, ECLIC_BASE + 0x1158 @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_85_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIP_86, ECLIC_BASE + 0x115C @ (clicintip Register) 
        .equ ECLIC_CLICINTIP_86_IP, 1 << 0   @ bitWidth 1 (IP)  
 
    .equ ECLIC_CLICINTIE_0, ECLIC_BASE + 0x1001 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_0_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_1, ECLIC_BASE + 0x1005 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_1_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_2, ECLIC_BASE + 0x1009 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_2_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_3, ECLIC_BASE + 0x100D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_3_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_4, ECLIC_BASE + 0x1011 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_4_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_5, ECLIC_BASE + 0x1015 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_5_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_6, ECLIC_BASE + 0x1019 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_6_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_7, ECLIC_BASE + 0x101D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_7_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_8, ECLIC_BASE + 0x1021 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_8_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_9, ECLIC_BASE + 0x1025 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_9_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_10, ECLIC_BASE + 0x1029 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_10_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_11, ECLIC_BASE + 0x102D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_11_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_12, ECLIC_BASE + 0x1031 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_12_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_13, ECLIC_BASE + 0x1035 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_13_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_14, ECLIC_BASE + 0x1039 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_14_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_15, ECLIC_BASE + 0x103D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_15_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_16, ECLIC_BASE + 0x1041 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_16_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_17, ECLIC_BASE + 0x1045 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_17_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_18, ECLIC_BASE + 0x1049 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_18_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_19, ECLIC_BASE + 0x104D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_19_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_20, ECLIC_BASE + 0x1051 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_20_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_21, ECLIC_BASE + 0x1055 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_21_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_22, ECLIC_BASE + 0x1059 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_22_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_23, ECLIC_BASE + 0x105D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_23_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_24, ECLIC_BASE + 0x1061 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_24_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_25, ECLIC_BASE + 0x1065 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_25_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_26, ECLIC_BASE + 0x1069 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_26_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_27, ECLIC_BASE + 0x106D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_27_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_28, ECLIC_BASE + 0x1071 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_28_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_29, ECLIC_BASE + 0x1075 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_29_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_30, ECLIC_BASE + 0x1079 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_30_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_31, ECLIC_BASE + 0x107D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_31_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_32, ECLIC_BASE + 0x1081 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_32_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_33, ECLIC_BASE + 0x1085 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_33_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_34, ECLIC_BASE + 0x1089 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_34_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_35, ECLIC_BASE + 0x108D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_35_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_36, ECLIC_BASE + 0x1091 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_36_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_37, ECLIC_BASE + 0x1095 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_37_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_38, ECLIC_BASE + 0x1099 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_38_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_39, ECLIC_BASE + 0x109D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_39_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_40, ECLIC_BASE + 0x10A1 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_40_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_41, ECLIC_BASE + 0x10A5 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_41_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_42, ECLIC_BASE + 0x10A9 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_42_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_43, ECLIC_BASE + 0x10AD @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_43_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_44, ECLIC_BASE + 0x10B1 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_44_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_45, ECLIC_BASE + 0x10B5 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_45_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_46, ECLIC_BASE + 0x10B9 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_46_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_47, ECLIC_BASE + 0x10BD @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_47_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_48, ECLIC_BASE + 0x10C1 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_48_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_49, ECLIC_BASE + 0x10C5 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_49_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_50, ECLIC_BASE + 0x10C9 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_50_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_51, ECLIC_BASE + 0x10CD @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_51_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_52, ECLIC_BASE + 0x10D1 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_52_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_53, ECLIC_BASE + 0x10D5 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_53_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_54, ECLIC_BASE + 0x10D9 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_54_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_55, ECLIC_BASE + 0x10DD @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_55_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_56, ECLIC_BASE + 0x10E1 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_56_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_57, ECLIC_BASE + 0x10E5 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_57_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_58, ECLIC_BASE + 0x10E9 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_58_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_59, ECLIC_BASE + 0x10ED @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_59_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_60, ECLIC_BASE + 0x10F1 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_60_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_61, ECLIC_BASE + 0x10F5 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_61_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_62, ECLIC_BASE + 0x10F9 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_62_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_63, ECLIC_BASE + 0x10FD @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_63_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_64, ECLIC_BASE + 0x1101 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_64_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_65, ECLIC_BASE + 0x1105 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_65_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_66, ECLIC_BASE + 0x1109 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_66_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_67, ECLIC_BASE + 0x110D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_67_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_68, ECLIC_BASE + 0x1111 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_68_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_69, ECLIC_BASE + 0x1115 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_69_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_70, ECLIC_BASE + 0x1119 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_70_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_71, ECLIC_BASE + 0x111D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_71_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_72, ECLIC_BASE + 0x1121 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_72_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_73, ECLIC_BASE + 0x1125 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_73_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_74, ECLIC_BASE + 0x1129 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_74_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_75, ECLIC_BASE + 0x112D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_75_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_76, ECLIC_BASE + 0x1131 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_76_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_77, ECLIC_BASE + 0x1135 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_77_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_78, ECLIC_BASE + 0x1139 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_78_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_79, ECLIC_BASE + 0x113D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_79_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_80, ECLIC_BASE + 0x1141 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_80_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_81, ECLIC_BASE + 0x1145 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_81_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_82, ECLIC_BASE + 0x1149 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_82_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_83, ECLIC_BASE + 0x114D @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_83_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_84, ECLIC_BASE + 0x1151 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_84_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_85, ECLIC_BASE + 0x1155 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_85_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTIE_86, ECLIC_BASE + 0x1159 @ (clicintie Register) 
        .equ ECLIC_CLICINTIE_86_IE, 1 << 0   @ bitWidth 1 (IE)  
 
    .equ ECLIC_CLICINTATTR_0, ECLIC_BASE + 0x1002 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_0_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_0_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_1, ECLIC_BASE + 0x1006 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_1_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_1_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_2, ECLIC_BASE + 0x100A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_2_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_2_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_3, ECLIC_BASE + 0x100E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_3_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_3_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_4, ECLIC_BASE + 0x1012 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_4_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_4_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_5, ECLIC_BASE + 0x1016 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_5_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_5_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_6, ECLIC_BASE + 0x101A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_6_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_6_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_7, ECLIC_BASE + 0x101E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_7_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_7_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_8, ECLIC_BASE + 0x1022 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_8_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_8_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_9, ECLIC_BASE + 0x1026 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_9_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_9_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_10, ECLIC_BASE + 0x102A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_10_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_10_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_11, ECLIC_BASE + 0x102E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_11_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_11_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_12, ECLIC_BASE + 0x1032 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_12_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_12_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_13, ECLIC_BASE + 0x1036 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_13_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_13_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_14, ECLIC_BASE + 0x103A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_14_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_14_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_15, ECLIC_BASE + 0x103E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_15_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_15_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_16, ECLIC_BASE + 0x1042 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_16_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_16_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_17, ECLIC_BASE + 0x1046 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_17_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_17_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_18, ECLIC_BASE + 0x104A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_18_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_18_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_19, ECLIC_BASE + 0x104E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_19_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_19_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_20, ECLIC_BASE + 0x1052 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_20_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_20_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_21, ECLIC_BASE + 0x1056 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_21_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_21_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_22, ECLIC_BASE + 0x105A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_22_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_22_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_23, ECLIC_BASE + 0x105E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_23_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_23_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_24, ECLIC_BASE + 0x1062 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_24_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_24_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_25, ECLIC_BASE + 0x1066 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_25_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_25_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_26, ECLIC_BASE + 0x106A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_26_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_26_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_27, ECLIC_BASE + 0x106E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_27_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_27_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_28, ECLIC_BASE + 0x1072 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_28_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_28_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_29, ECLIC_BASE + 0x1076 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_29_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_29_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_30, ECLIC_BASE + 0x107A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_30_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_30_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_31, ECLIC_BASE + 0x107E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_31_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_31_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_32, ECLIC_BASE + 0x1082 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_32_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_32_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_33, ECLIC_BASE + 0x1086 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_33_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_33_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_34, ECLIC_BASE + 0x108A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_34_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_34_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_35, ECLIC_BASE + 0x108E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_35_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_35_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_36, ECLIC_BASE + 0x1092 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_36_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_36_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_37, ECLIC_BASE + 0x1096 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_37_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_37_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_38, ECLIC_BASE + 0x109A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_38_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_38_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_39, ECLIC_BASE + 0x109E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_39_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_39_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_40, ECLIC_BASE + 0x10A2 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_40_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_40_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_41, ECLIC_BASE + 0x10A6 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_41_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_41_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_42, ECLIC_BASE + 0x10AA @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_42_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_42_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_43, ECLIC_BASE + 0x10AE @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_43_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_43_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_44, ECLIC_BASE + 0x10B2 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_44_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_44_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_45, ECLIC_BASE + 0x10B6 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_45_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_45_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_46, ECLIC_BASE + 0x10BA @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_46_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_46_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_47, ECLIC_BASE + 0x10BE @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_47_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_47_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_48, ECLIC_BASE + 0x10C2 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_48_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_48_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_49, ECLIC_BASE + 0x10C6 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_49_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_49_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_50, ECLIC_BASE + 0x10CA @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_50_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_50_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_51, ECLIC_BASE + 0x10CE @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_51_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_51_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_52, ECLIC_BASE + 0x10D2 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_52_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_52_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_53, ECLIC_BASE + 0x10D6 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_53_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_53_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_54, ECLIC_BASE + 0x10DA @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_54_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_54_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_55, ECLIC_BASE + 0x10DE @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_55_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_55_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_56, ECLIC_BASE + 0x10E2 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_56_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_56_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_57, ECLIC_BASE + 0x10E6 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_57_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_57_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_58, ECLIC_BASE + 0x10EA @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_58_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_58_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_59, ECLIC_BASE + 0x10EE @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_59_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_59_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_60, ECLIC_BASE + 0x10F2 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_60_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_60_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_61, ECLIC_BASE + 0x10F6 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_61_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_61_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_62, ECLIC_BASE + 0x10FA @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_62_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_62_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_63, ECLIC_BASE + 0x10FE @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_63_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_63_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_64, ECLIC_BASE + 0x1102 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_64_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_64_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_65, ECLIC_BASE + 0x1106 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_65_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_65_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_66, ECLIC_BASE + 0x110A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_66_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_66_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_67, ECLIC_BASE + 0x110E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_67_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_67_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_68, ECLIC_BASE + 0x1112 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_68_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_68_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_69, ECLIC_BASE + 0x1116 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_69_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_69_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_70, ECLIC_BASE + 0x111A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_70_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_70_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_71, ECLIC_BASE + 0x111E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_71_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_71_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_72, ECLIC_BASE + 0x1122 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_72_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_72_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_73, ECLIC_BASE + 0x1126 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_73_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_73_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_74, ECLIC_BASE + 0x112A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_74_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_74_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_75, ECLIC_BASE + 0x112E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_75_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_75_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_76, ECLIC_BASE + 0x1132 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_76_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_76_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_77, ECLIC_BASE + 0x1136 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_77_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_77_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_78, ECLIC_BASE + 0x113A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_78_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_78_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_79, ECLIC_BASE + 0x113E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_79_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_79_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_80, ECLIC_BASE + 0x1142 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_80_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_80_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_81, ECLIC_BASE + 0x1146 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_81_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_81_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_82, ECLIC_BASE + 0x114A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_82_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_82_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_83, ECLIC_BASE + 0x114E @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_83_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_83_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_84, ECLIC_BASE + 0x1152 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_84_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_84_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_85, ECLIC_BASE + 0x1156 @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_85_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_85_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTATTR_86, ECLIC_BASE + 0x115A @ (clicintattr Register) 
        .equ ECLIC_CLICINTATTR_86_SHV, 1 << 0   @ bitWidth 1 (SHV)  
        .equ ECLIC_CLICINTATTR_86_TRIG_Shift, 1   @ bitWidth 2 (TRIG)  
 
    .equ ECLIC_CLICINTCTL_0, ECLIC_BASE + 0x1003 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_0_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_1, ECLIC_BASE + 0x1007 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_1_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_2, ECLIC_BASE + 0x100B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_2_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_3, ECLIC_BASE + 0x100F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_3_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_4, ECLIC_BASE + 0x1013 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_4_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_5, ECLIC_BASE + 0x1017 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_5_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_6, ECLIC_BASE + 0x101B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_6_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_7, ECLIC_BASE + 0x101F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_7_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_8, ECLIC_BASE + 0x1023 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_8_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_9, ECLIC_BASE + 0x1027 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_9_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_10, ECLIC_BASE + 0x102B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_10_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_11, ECLIC_BASE + 0x102F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_11_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_12, ECLIC_BASE + 0x1033 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_12_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_13, ECLIC_BASE + 0x1037 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_13_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_14, ECLIC_BASE + 0x103B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_14_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_15, ECLIC_BASE + 0x103F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_15_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_16, ECLIC_BASE + 0x1043 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_16_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_17, ECLIC_BASE + 0x1047 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_17_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_18, ECLIC_BASE + 0x104B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_18_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_19, ECLIC_BASE + 0x104F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_19_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_20, ECLIC_BASE + 0x1053 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_20_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_21, ECLIC_BASE + 0x1057 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_21_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_22, ECLIC_BASE + 0x105B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_22_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_23, ECLIC_BASE + 0x105F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_23_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_24, ECLIC_BASE + 0x1063 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_24_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_25, ECLIC_BASE + 0x1067 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_25_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_26, ECLIC_BASE + 0x106B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_26_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_27, ECLIC_BASE + 0x106F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_27_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_28, ECLIC_BASE + 0x1073 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_28_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_29, ECLIC_BASE + 0x1077 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_29_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_30, ECLIC_BASE + 0x107B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_30_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_31, ECLIC_BASE + 0x107F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_31_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_32, ECLIC_BASE + 0x1083 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_32_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_33, ECLIC_BASE + 0x1087 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_33_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_34, ECLIC_BASE + 0x108B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_34_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_35, ECLIC_BASE + 0x108F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_35_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_36, ECLIC_BASE + 0x1093 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_36_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_37, ECLIC_BASE + 0x1097 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_37_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_38, ECLIC_BASE + 0x109B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_38_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_39, ECLIC_BASE + 0x109F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_39_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_40, ECLIC_BASE + 0x10A3 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_40_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_41, ECLIC_BASE + 0x10A7 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_41_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_42, ECLIC_BASE + 0x10AB @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_42_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_43, ECLIC_BASE + 0x10AF @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_43_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_44, ECLIC_BASE + 0x10B3 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_44_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_45, ECLIC_BASE + 0x10B7 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_45_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_46, ECLIC_BASE + 0x10BB @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_46_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_47, ECLIC_BASE + 0x10BF @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_47_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_48, ECLIC_BASE + 0x10C3 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_48_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_49, ECLIC_BASE + 0x10C7 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_49_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_50, ECLIC_BASE + 0x10CB @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_50_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_51, ECLIC_BASE + 0x10CF @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_51_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_52, ECLIC_BASE + 0x10D3 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_52_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_53, ECLIC_BASE + 0x10D7 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_53_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_54, ECLIC_BASE + 0x10DB @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_54_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_55, ECLIC_BASE + 0x10DF @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_55_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_56, ECLIC_BASE + 0x10E3 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_56_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_57, ECLIC_BASE + 0x10E7 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_57_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_58, ECLIC_BASE + 0x10EB @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_58_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_59, ECLIC_BASE + 0x10EF @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_59_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_60, ECLIC_BASE + 0x10F3 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_60_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_61, ECLIC_BASE + 0x10F7 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_61_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_62, ECLIC_BASE + 0x10FB @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_62_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_63, ECLIC_BASE + 0x10FF @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_63_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_64, ECLIC_BASE + 0x1103 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_64_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_65, ECLIC_BASE + 0x1107 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_65_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_66, ECLIC_BASE + 0x110B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_66_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_67, ECLIC_BASE + 0x110F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_67_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_68, ECLIC_BASE + 0x1113 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_68_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_69, ECLIC_BASE + 0x1117 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_69_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_70, ECLIC_BASE + 0x111B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_70_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_71, ECLIC_BASE + 0x111F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_71_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_72, ECLIC_BASE + 0x1123 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_72_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_73, ECLIC_BASE + 0x1127 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_73_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_74, ECLIC_BASE + 0x112B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_74_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_75, ECLIC_BASE + 0x112F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_75_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_76, ECLIC_BASE + 0x1133 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_76_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_77, ECLIC_BASE + 0x1137 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_77_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_78, ECLIC_BASE + 0x113B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_78_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_79, ECLIC_BASE + 0x113F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_79_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_80, ECLIC_BASE + 0x1143 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_80_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_81, ECLIC_BASE + 0x1147 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_81_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_82, ECLIC_BASE + 0x114B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_82_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_83, ECLIC_BASE + 0x114F @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_83_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_84, ECLIC_BASE + 0x1153 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_84_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_85, ECLIC_BASE + 0x1157 @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_85_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 
    .equ ECLIC_CLICINTCTL_86, ECLIC_BASE + 0x115B @ (clicintctl Register) 
        .equ ECLIC_CLICINTCTL_86_LEVEL_PRIORITY_Shift, 0   @ bitWidth 8 (LEVEL_PRIORITY)  
 

@=========================== PMU ===========================@
.equ PMU_BASE, 0x40007000 @ (Power management unit) 
    .equ PMU_CTL, PMU_BASE + 0x00 @ (power control register) 
        .equ PMU_CTL_BKPWEN, 1 << 8   @ bitWidth 1 (Backup Domain Write Enable)  
        .equ PMU_CTL_LVDT_Shift, 5   @ bitWidth 3 (Low Voltage Detector Threshold)  
        .equ PMU_CTL_LVDEN, 1 << 4   @ bitWidth 1 (Low Voltage Detector Enable)  
        .equ PMU_CTL_STBRST, 1 << 3   @ bitWidth 1 (Standby Flag Reset)  
        .equ PMU_CTL_WURST, 1 << 2   @ bitWidth 1 (Wakeup Flag Reset)  
        .equ PMU_CTL_STBMOD, 1 << 1   @ bitWidth 1 (Standby Mode)  
        .equ PMU_CTL_LDOLP, 1 << 0   @ bitWidth 1 (LDO Low Power Mode)  
 
    .equ PMU_CS, PMU_BASE + 0x04 @ (power control/status register) 
        .equ PMU_CS_WUPEN, 1 << 8   @ bitWidth 1 (Enable WKUP pin)  
        .equ PMU_CS_LVDF, 1 << 2   @ bitWidth 1 (Low Voltage Detector Status Flag)  
        .equ PMU_CS_STBF, 1 << 1   @ bitWidth 1 (Standby flag)  
        .equ PMU_CS_WUF, 1 << 0   @ bitWidth 1 (Wakeup flag)  
 

@=========================== RCU ===========================@
.equ RCU_BASE, 0x40021000 @ (Reset and clock unit) 
    .equ RCU_CTL, RCU_BASE + 0x0 @ (Control register) 
        .equ RCU_CTL_IRC8MEN, 1 << 0   @ bitWidth 1 (Internal 8MHz RC oscillator Enable)  
        .equ RCU_CTL_IRC8MSTB, 1 << 1   @ bitWidth 1 (IRC8M Internal 8MHz RC Oscillator stabilization Flag)  
        .equ RCU_CTL_IRC8MADJ_Shift, 3   @ bitWidth 5 (Internal 8MHz RC Oscillator clock trim adjust value)  
        .equ RCU_CTL_IRC8MCALIB_Shift, 8   @ bitWidth 8 (Internal 8MHz RC Oscillator calibration value register)  
        .equ RCU_CTL_HXTALEN, 1 << 16   @ bitWidth 1 (External High Speed oscillator Enable)  
        .equ RCU_CTL_HXTALSTB, 1 << 17   @ bitWidth 1 (External crystal oscillator HXTAL clock stabilization flag)  
        .equ RCU_CTL_HXTALBPS, 1 << 18   @ bitWidth 1 (External crystal oscillator HXTAL clock bypass mode enable)  
        .equ RCU_CTL_CKMEN, 1 << 19   @ bitWidth 1 (HXTAL Clock Monitor Enable)  
        .equ RCU_CTL_PLLEN, 1 << 24   @ bitWidth 1 (PLL enable)  
        .equ RCU_CTL_PLLSTB, 1 << 25   @ bitWidth 1 (PLL Clock Stabilization Flag)  
        .equ RCU_CTL_PLL1EN, 1 << 26   @ bitWidth 1 (PLL1 enable)  
        .equ RCU_CTL_PLL1STB, 1 << 27   @ bitWidth 1 (PLL1 Clock Stabilization Flag)  
        .equ RCU_CTL_PLL2EN, 1 << 28   @ bitWidth 1 (PLL2 enable)  
        .equ RCU_CTL_PLL2STB, 1 << 29   @ bitWidth 1 (PLL2 Clock Stabilization Flag)  
 
    .equ RCU_CFG0, RCU_BASE + 0x04 @ (Clock configuration register 0  RCU_CFG0) 
        .equ RCU_CFG0_SCS_Shift, 0   @ bitWidth 2 (System clock switch)  
        .equ RCU_CFG0_SCSS_Shift, 2   @ bitWidth 2 (System clock switch status)  
        .equ RCU_CFG0_AHBPSC_Shift, 4   @ bitWidth 4 (AHB prescaler selection)  
        .equ RCU_CFG0_APB1PSC_Shift, 8   @ bitWidth 3 (APB1 prescaler selection)  
        .equ RCU_CFG0_APB2PSC_Shift, 11   @ bitWidth 3 (APB2 prescaler selection)  
        .equ RCU_CFG0_ADCPSC_1_0_Shift, 14   @ bitWidth 2 (ADC clock prescaler selection)  
        .equ RCU_CFG0_PLLSEL, 1 << 16   @ bitWidth 1 (PLL Clock Source Selection)  
        .equ RCU_CFG0_PREDV0_LSB, 1 << 17   @ bitWidth 1 (The LSB of PREDV0 division factor)  
        .equ RCU_CFG0_PLLMF_3_0_Shift, 18   @ bitWidth 4 (The PLL clock multiplication factor)  
        .equ RCU_CFG0_USBFSPSC_Shift, 22   @ bitWidth 2 (USBFS clock prescaler selection)  
        .equ RCU_CFG0_CKOUT0SEL_Shift, 24   @ bitWidth 4 (CKOUT0 Clock Source Selection)  
        .equ RCU_CFG0_ADCPSC_2, 1 << 28   @ bitWidth 1 (Bit 2 of ADCPSC)  
        .equ RCU_CFG0_PLLMF_4, 1 << 29   @ bitWidth 1 (Bit 4 of PLLMF)  
 
    .equ RCU_INT, RCU_BASE + 0x08 @ (Clock interrupt register  RCU_INT) 
        .equ RCU_INT_IRC40KSTBIF, 1 << 0   @ bitWidth 1 (IRC40K stabilization interrupt flag)  
        .equ RCU_INT_LXTALSTBIF, 1 << 1   @ bitWidth 1 (LXTAL stabilization interrupt flag)  
        .equ RCU_INT_IRC8MSTBIF, 1 << 2   @ bitWidth 1 (IRC8M stabilization interrupt flag)  
        .equ RCU_INT_HXTALSTBIF, 1 << 3   @ bitWidth 1 (HXTAL stabilization interrupt flag)  
        .equ RCU_INT_PLLSTBIF, 1 << 4   @ bitWidth 1 (PLL stabilization interrupt flag)  
        .equ RCU_INT_PLL1STBIF, 1 << 5   @ bitWidth 1 (PLL1 stabilization interrupt flag)  
        .equ RCU_INT_PLL2STBIF, 1 << 6   @ bitWidth 1 (PLL2 stabilization interrupt flag)  
        .equ RCU_INT_CKMIF, 1 << 7   @ bitWidth 1 (HXTAL Clock Stuck Interrupt Flag)  
        .equ RCU_INT_IRC40KSTBIE, 1 << 8   @ bitWidth 1 (IRC40K Stabilization interrupt enable)  
        .equ RCU_INT_LXTALSTBIE, 1 << 9   @ bitWidth 1 (LXTAL Stabilization Interrupt Enable)  
        .equ RCU_INT_IRC8MSTBIE, 1 << 10   @ bitWidth 1 (IRC8M Stabilization Interrupt Enable)  
        .equ RCU_INT_HXTALSTBIE, 1 << 11   @ bitWidth 1 (HXTAL Stabilization Interrupt Enable)  
        .equ RCU_INT_PLLSTBIE, 1 << 12   @ bitWidth 1 (PLL Stabilization Interrupt Enable)  
        .equ RCU_INT_PLL1STBIE, 1 << 13   @ bitWidth 1 (PLL1 Stabilization Interrupt Enable)  
        .equ RCU_INT_PLL2STBIE, 1 << 14   @ bitWidth 1 (PLL2 Stabilization Interrupt Enable)  
        .equ RCU_INT_IRC40KSTBIC, 1 << 16   @ bitWidth 1 (IRC40K Stabilization Interrupt Clear)  
        .equ RCU_INT_LXTALSTBIC, 1 << 17   @ bitWidth 1 (LXTAL Stabilization Interrupt Clear)  
        .equ RCU_INT_IRC8MSTBIC, 1 << 18   @ bitWidth 1 (IRC8M Stabilization Interrupt Clear)  
        .equ RCU_INT_HXTALSTBIC, 1 << 19   @ bitWidth 1 (HXTAL Stabilization Interrupt Clear)  
        .equ RCU_INT_PLLSTBIC, 1 << 20   @ bitWidth 1 (PLL stabilization Interrupt Clear)  
        .equ RCU_INT_PLL1STBIC, 1 << 21   @ bitWidth 1 (PLL1 stabilization Interrupt Clear)  
        .equ RCU_INT_PLL2STBIC, 1 << 22   @ bitWidth 1 (PLL2 stabilization Interrupt Clear)  
        .equ RCU_INT_CKMIC, 1 << 23   @ bitWidth 1 (HXTAL Clock Stuck Interrupt Clear)  
 
    .equ RCU_APB2RST, RCU_BASE + 0x0C @ (APB2 reset register  RCU_APB2RST) 
        .equ RCU_APB2RST_AFRST, 1 << 0   @ bitWidth 1 (Alternate function I/O reset)  
        .equ RCU_APB2RST_PARST, 1 << 2   @ bitWidth 1 (GPIO port A reset)  
        .equ RCU_APB2RST_PBRST, 1 << 3   @ bitWidth 1 (GPIO port B reset)  
        .equ RCU_APB2RST_PCRST, 1 << 4   @ bitWidth 1 (GPIO port C reset)  
        .equ RCU_APB2RST_PDRST, 1 << 5   @ bitWidth 1 (GPIO port D reset)  
        .equ RCU_APB2RST_PERST, 1 << 6   @ bitWidth 1 (GPIO port E reset)  
        .equ RCU_APB2RST_ADC0RST, 1 << 9   @ bitWidth 1 (ADC0 reset)  
        .equ RCU_APB2RST_ADC1RST, 1 << 10   @ bitWidth 1 (ADC1 reset)  
        .equ RCU_APB2RST_TIMER0RST, 1 << 11   @ bitWidth 1 (Timer 0 reset)  
        .equ RCU_APB2RST_SPI0RST, 1 << 12   @ bitWidth 1 (SPI0 reset)  
        .equ RCU_APB2RST_USART0RST, 1 << 14   @ bitWidth 1 (USART0 Reset)  
 
    .equ RCU_APB1RST, RCU_BASE + 0x10 @ (APB1 reset register  RCU_APB1RST) 
        .equ RCU_APB1RST_TIMER1RST, 1 << 0   @ bitWidth 1 (TIMER1 timer reset)  
        .equ RCU_APB1RST_TIMER2RST, 1 << 1   @ bitWidth 1 (TIMER2 timer reset)  
        .equ RCU_APB1RST_TIMER3RST, 1 << 2   @ bitWidth 1 (TIMER3 timer reset)  
        .equ RCU_APB1RST_TIMER4RST, 1 << 3   @ bitWidth 1 (TIMER4 timer reset)  
        .equ RCU_APB1RST_TIMER5RST, 1 << 4   @ bitWidth 1 (TIMER5 timer reset)  
        .equ RCU_APB1RST_TIMER6RST, 1 << 5   @ bitWidth 1 (TIMER6 timer reset)  
        .equ RCU_APB1RST_WWDGTRST, 1 << 11   @ bitWidth 1 (Window watchdog timer reset)  
        .equ RCU_APB1RST_SPI1RST, 1 << 14   @ bitWidth 1 (SPI1 reset)  
        .equ RCU_APB1RST_SPI2RST, 1 << 15   @ bitWidth 1 (SPI2 reset)  
        .equ RCU_APB1RST_USART1RST, 1 << 17   @ bitWidth 1 (USART1 reset)  
        .equ RCU_APB1RST_USART2RST, 1 << 18   @ bitWidth 1 (USART2 reset)  
        .equ RCU_APB1RST_UART3RST, 1 << 19   @ bitWidth 1 (UART3 reset)  
        .equ RCU_APB1RST_UART4RST, 1 << 20   @ bitWidth 1 (UART4 reset)  
        .equ RCU_APB1RST_I2C0RST, 1 << 21   @ bitWidth 1 (I2C0 reset)  
        .equ RCU_APB1RST_I2C1RST, 1 << 22   @ bitWidth 1 (I2C1 reset)  
        .equ RCU_APB1RST_CAN0RST, 1 << 25   @ bitWidth 1 (CAN0 reset)  
        .equ RCU_APB1RST_CAN1RST, 1 << 26   @ bitWidth 1 (CAN1 reset)  
        .equ RCU_APB1RST_BKPIRST, 1 << 27   @ bitWidth 1 (Backup interface reset)  
        .equ RCU_APB1RST_PMURST, 1 << 28   @ bitWidth 1 (Power control reset)  
        .equ RCU_APB1RST_DACRST, 1 << 29   @ bitWidth 1 (DAC reset)  
 
    .equ RCU_AHBEN, RCU_BASE + 0x14 @ (AHB enable register) 
        .equ RCU_AHBEN_DMA0EN, 1 << 0   @ bitWidth 1 (DMA0 clock enable)  
        .equ RCU_AHBEN_DMA1EN, 1 << 1   @ bitWidth 1 (DMA1 clock enable)  
        .equ RCU_AHBEN_SRAMSPEN, 1 << 2   @ bitWidth 1 (SRAM interface clock enable when sleep mode)  
        .equ RCU_AHBEN_FMCSPEN, 1 << 4   @ bitWidth 1 (FMC clock enable when sleep mode)  
        .equ RCU_AHBEN_CRCEN, 1 << 6   @ bitWidth 1 (CRC clock enable)  
        .equ RCU_AHBEN_EXMCEN, 1 << 8   @ bitWidth 1 (EXMC clock enable)  
        .equ RCU_AHBEN_USBFSEN, 1 << 12   @ bitWidth 1 (USBFS clock enable)  
 
    .equ RCU_APB2EN, RCU_BASE + 0x18 @ (APB2 clock enable register  RCU_APB2EN) 
        .equ RCU_APB2EN_AFEN, 1 << 0   @ bitWidth 1 (Alternate function IO clock enable )  
        .equ RCU_APB2EN_PAEN, 1 << 2   @ bitWidth 1 (GPIO port A clock enable)  
        .equ RCU_APB2EN_PBEN, 1 << 3   @ bitWidth 1 (GPIO port B clock enable)  
        .equ RCU_APB2EN_PCEN, 1 << 4   @ bitWidth 1 (GPIO port C clock enable)  
        .equ RCU_APB2EN_PDEN, 1 << 5   @ bitWidth 1 (GPIO port D clock enable )  
        .equ RCU_APB2EN_PEEN, 1 << 6   @ bitWidth 1 (GPIO port E clock enable )  
        .equ RCU_APB2EN_ADC0EN, 1 << 9   @ bitWidth 1 (ADC0 clock enable)  
        .equ RCU_APB2EN_ADC1EN, 1 << 10   @ bitWidth 1 (ADC1 clock enable)  
        .equ RCU_APB2EN_TIMER0EN, 1 << 11   @ bitWidth 1 (TIMER0 clock enable )  
        .equ RCU_APB2EN_SPI0EN, 1 << 12   @ bitWidth 1 (SPI0 clock enable)  
        .equ RCU_APB2EN_USART0EN, 1 << 14   @ bitWidth 1 (USART0 clock enable)  
 
    .equ RCU_APB1EN, RCU_BASE + 0x1C @ (APB1 clock enable register  RCU_APB1EN) 
        .equ RCU_APB1EN_TIMER1EN, 1 << 0   @ bitWidth 1 (TIMER1 timer clock enable)  
        .equ RCU_APB1EN_TIMER2EN, 1 << 1   @ bitWidth 1 (TIMER2 timer clock enable)  
        .equ RCU_APB1EN_TIMER3EN, 1 << 2   @ bitWidth 1 (TIMER3 timer clock enable)  
        .equ RCU_APB1EN_TIMER4EN, 1 << 3   @ bitWidth 1 (TIMER4 timer clock enable)  
        .equ RCU_APB1EN_TIMER5EN, 1 << 4   @ bitWidth 1 (TIMER5 timer clock enable)  
        .equ RCU_APB1EN_TIMER6EN, 1 << 5   @ bitWidth 1 (TIMER6 timer clock enable)  
        .equ RCU_APB1EN_WWDGTEN, 1 << 11   @ bitWidth 1 (Window watchdog timer clock enable)  
        .equ RCU_APB1EN_SPI1EN, 1 << 14   @ bitWidth 1 (SPI1 clock enable)  
        .equ RCU_APB1EN_SPI2EN, 1 << 15   @ bitWidth 1 (SPI2 clock enable)  
        .equ RCU_APB1EN_USART1EN, 1 << 17   @ bitWidth 1 (USART1 clock enable)  
        .equ RCU_APB1EN_USART2EN, 1 << 18   @ bitWidth 1 (USART2 clock enable)  
        .equ RCU_APB1EN_UART3EN, 1 << 19   @ bitWidth 1 (UART3 clock enable)  
        .equ RCU_APB1EN_UART4EN, 1 << 20   @ bitWidth 1 (UART4 clock enable)  
        .equ RCU_APB1EN_I2C0EN, 1 << 21   @ bitWidth 1 (I2C0 clock enable)  
        .equ RCU_APB1EN_I2C1EN, 1 << 22   @ bitWidth 1 (I2C1 clock enable)  
        .equ RCU_APB1EN_CAN0EN, 1 << 25   @ bitWidth 1 (CAN0 clock enable)  
        .equ RCU_APB1EN_CAN1EN, 1 << 26   @ bitWidth 1 (CAN1 clock enable)  
        .equ RCU_APB1EN_BKPIEN, 1 << 27   @ bitWidth 1 (Backup interface clock enable )  
        .equ RCU_APB1EN_PMUEN, 1 << 28   @ bitWidth 1 (Power control clock enable )  
        .equ RCU_APB1EN_DACEN, 1 << 29   @ bitWidth 1 (DAC clock enable)  
 
    .equ RCU_BDCTL, RCU_BASE + 0x20 @ (Backup domain control register  RCU_BDCTL) 
        .equ RCU_BDCTL_LXTALEN, 1 << 0   @ bitWidth 1 (LXTAL enable)  
        .equ RCU_BDCTL_LXTALSTB, 1 << 1   @ bitWidth 1 (External low-speed oscillator stabilization)  
        .equ RCU_BDCTL_LXTALBPS, 1 << 2   @ bitWidth 1 (LXTAL bypass mode enable)  
        .equ RCU_BDCTL_RTCSRC_Shift, 8   @ bitWidth 2 (RTC clock entry selection)  
        .equ RCU_BDCTL_RTCEN, 1 << 15   @ bitWidth 1 (RTC clock enable)  
        .equ RCU_BDCTL_BKPRST, 1 << 16   @ bitWidth 1 (Backup domain reset)  
 
    .equ RCU_RSTSCK, RCU_BASE + 0x24 @ (Reset source /clock register  RCU_RSTSCK) 
        .equ RCU_RSTSCK_IRC40KEN, 1 << 0   @ bitWidth 1 (IRC40K enable)  
        .equ RCU_RSTSCK_IRC40KSTB, 1 << 1   @ bitWidth 1 (IRC40K stabilization)  
        .equ RCU_RSTSCK_RSTFC, 1 << 24   @ bitWidth 1 (Reset flag clear)  
        .equ RCU_RSTSCK_EPRSTF, 1 << 26   @ bitWidth 1 (External PIN reset flag)  
        .equ RCU_RSTSCK_PORRSTF, 1 << 27   @ bitWidth 1 (Power reset flag)  
        .equ RCU_RSTSCK_SWRSTF, 1 << 28   @ bitWidth 1 (Software reset flag)  
        .equ RCU_RSTSCK_FWDGTRSTF, 1 << 29   @ bitWidth 1 (Free Watchdog timer reset flag)  
        .equ RCU_RSTSCK_WWDGTRSTF, 1 << 30   @ bitWidth 1 (Window watchdog timer reset flag)  
        .equ RCU_RSTSCK_LPRSTF, 1 << 31   @ bitWidth 1 (Low-power reset flag)  
 
    .equ RCU_AHBRST, RCU_BASE + 0x28 @ (AHB reset register) 
        .equ RCU_AHBRST_USBFSRST, 1 << 12   @ bitWidth 1 (USBFS reset)  
 
    .equ RCU_CFG1, RCU_BASE + 0x2C @ (Clock Configuration register 1) 
        .equ RCU_CFG1_PREDV0_Shift, 0   @ bitWidth 4 (PREDV0 division factor)  
        .equ RCU_CFG1_PREDV1_Shift, 4   @ bitWidth 4 (PREDV1 division factor)  
        .equ RCU_CFG1_PLL1MF_Shift, 8   @ bitWidth 4 (The PLL1 clock multiplication factor)  
        .equ RCU_CFG1_PLL2MF_Shift, 12   @ bitWidth 4 (The PLL2 clock multiplication factor)  
        .equ RCU_CFG1_PREDV0SEL, 1 << 16   @ bitWidth 1 (PREDV0 input Clock Source Selection)  
        .equ RCU_CFG1_I2S1SEL, 1 << 17   @ bitWidth 1 (I2S1 Clock Source Selection)  
        .equ RCU_CFG1_I2S2SEL, 1 << 18   @ bitWidth 1 (I2S2 Clock Source Selection)  
 
    .equ RCU_DSV, RCU_BASE + 0x34 @ (Deep sleep mode Voltage register) 
        .equ RCU_DSV_DSLPVS_Shift, 0   @ bitWidth 2 (Deep-sleep mode voltage select)  
 

@=========================== RTC ===========================@
.equ RTC_BASE, 0x40002800 @ (Real-time clock) 
    .equ RTC_INTEN, RTC_BASE + 0x0 @ (RTC interrupt enable register) 
        .equ RTC_INTEN_OVIE, 1 << 2   @ bitWidth 1 (Overflow interrupt enable)  
        .equ RTC_INTEN_ALRMIE, 1 << 1   @ bitWidth 1 (Alarm interrupt enable)  
        .equ RTC_INTEN_SCIE, 1 << 0   @ bitWidth 1 (Second interrupt)  
 
    .equ RTC_CTL, RTC_BASE + 0x04 @ (control register) 
        .equ RTC_CTL_LWOFF, 1 << 5   @ bitWidth 1 (Last write operation finished flag)  
        .equ RTC_CTL_CMF, 1 << 4   @ bitWidth 1 (Configuration mode flag)  
        .equ RTC_CTL_RSYNF, 1 << 3   @ bitWidth 1 (Registers synchronized flag)  
        .equ RTC_CTL_OVIF, 1 << 2   @ bitWidth 1 (Overflow interrupt flag)  
        .equ RTC_CTL_ALRMIF, 1 << 1   @ bitWidth 1 (Alarm interrupt flag)  
        .equ RTC_CTL_SCIF, 1 << 0   @ bitWidth 1 (Sencond interrupt flag)  
 
    .equ RTC_PSCH, RTC_BASE + 0x08 @ (RTC prescaler high register) 
        .equ RTC_PSCH_PSC_Shift, 0   @ bitWidth 4 (RTC prescaler value high)  
 
    .equ RTC_PSCL, RTC_BASE + 0x0C @ ( RTC prescaler low  register) 
        .equ RTC_PSCL_PSC_Shift, 0   @ bitWidth 16 (RTC prescaler value low)  
 
    .equ RTC_DIVH, RTC_BASE + 0x10 @ (RTC divider high register) 
        .equ RTC_DIVH_DIV_Shift, 0   @ bitWidth 4 (RTC divider value high)  
 
    .equ RTC_DIVL, RTC_BASE + 0x14 @ (RTC divider low register) 
        .equ RTC_DIVL_DIV_Shift, 0   @ bitWidth 16 (RTC divider value low)  
 
    .equ RTC_CNTH, RTC_BASE + 0x18 @ (RTC counter high register) 
        .equ RTC_CNTH_CNT_Shift, 0   @ bitWidth 16 (RTC counter value high)  
 
    .equ RTC_CNTL, RTC_BASE + 0x1C @ (RTC counter low register) 
        .equ RTC_CNTL_CNT_Shift, 0   @ bitWidth 16 (RTC counter value low)  
 
    .equ RTC_ALRMH, RTC_BASE + 0x20 @ (Alarm high register) 
        .equ RTC_ALRMH_ALRM_Shift, 0   @ bitWidth 16 (Alarm value high)  
 
    .equ RTC_ALRML, RTC_BASE + 0x24 @ (RTC alarm low register) 
        .equ RTC_ALRML_ALRM_Shift, 0   @ bitWidth 16 (alarm value low)  
 

@=========================== SPI0 ===========================@
.equ SPI0_BASE, 0x40013000 @ (Serial peripheral interface) 
    .equ SPI0_CTL0, SPI0_BASE + 0x0 @ (control register 0) 
        .equ SPI0_CTL0_BDEN, 1 << 15   @ bitWidth 1 (Bidirectional   enable)  
        .equ SPI0_CTL0_BDOEN, 1 << 14   @ bitWidth 1 (Bidirectional Transmit output enable  )  
        .equ SPI0_CTL0_CRCEN, 1 << 13   @ bitWidth 1 (CRC Calculation Enable)  
        .equ SPI0_CTL0_CRCNT, 1 << 12   @ bitWidth 1 (CRC Next Transfer)  
        .equ SPI0_CTL0_FF16, 1 << 11   @ bitWidth 1 (Data frame format)  
        .equ SPI0_CTL0_RO, 1 << 10   @ bitWidth 1 (Receive only)  
        .equ SPI0_CTL0_SWNSSEN, 1 << 9   @ bitWidth 1 (NSS Software Mode Selection)  
        .equ SPI0_CTL0_SWNSS, 1 << 8   @ bitWidth 1 (NSS Pin Selection In NSS Software Mode)  
        .equ SPI0_CTL0_LF, 1 << 7   @ bitWidth 1 (LSB First Mode)  
        .equ SPI0_CTL0_SPIEN, 1 << 6   @ bitWidth 1 (SPI enable)  
        .equ SPI0_CTL0_PSC_Shift, 3   @ bitWidth 3 (Master Clock Prescaler Selection)  
        .equ SPI0_CTL0_MSTMOD, 1 << 2   @ bitWidth 1 (Master Mode Enable)  
        .equ SPI0_CTL0_CKPL, 1 << 1   @ bitWidth 1 (Clock polarity Selection)  
        .equ SPI0_CTL0_CKPH, 1 << 0   @ bitWidth 1 (Clock Phase Selection)  
 
    .equ SPI0_CTL1, SPI0_BASE + 0x04 @ (control register 1) 
        .equ SPI0_CTL1_TBEIE, 1 << 7   @ bitWidth 1 (Tx buffer empty interrupt  enable)  
        .equ SPI0_CTL1_RBNEIE, 1 << 6   @ bitWidth 1 (RX buffer not empty interrupt  enable)  
        .equ SPI0_CTL1_ERRIE, 1 << 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI0_CTL1_TMOD, 1 << 4   @ bitWidth 1 (SPI TI mode enable)  
        .equ SPI0_CTL1_NSSP, 1 << 3   @ bitWidth 1 (SPI NSS pulse mode enable)  
        .equ SPI0_CTL1_NSSDRV, 1 << 2   @ bitWidth 1 (Drive NSS Output)  
        .equ SPI0_CTL1_DMATEN, 1 << 1   @ bitWidth 1 (Transmit Buffer DMA Enable)  
        .equ SPI0_CTL1_DMAREN, 1 << 0   @ bitWidth 1 (Rx buffer DMA enable)  
 
    .equ SPI0_STAT, SPI0_BASE + 0x08 @ (status register) 
        .equ SPI0_STAT_FERR, 1 << 8   @ bitWidth 1 (Format error)  
        .equ SPI0_STAT_TRANS, 1 << 7   @ bitWidth 1 (Transmitting On-going Bit)  
        .equ SPI0_STAT_RXORERR, 1 << 6   @ bitWidth 1 (Reception Overrun Error Bit)  
        .equ SPI0_STAT_CONFERR, 1 << 5   @ bitWidth 1 (SPI Configuration error)  
        .equ SPI0_STAT_CRCERR, 1 << 4   @ bitWidth 1 (SPI CRC Error Bit)  
        .equ SPI0_STAT_TXURERR, 1 << 3   @ bitWidth 1 (Transmission underrun error bit)  
        .equ SPI0_STAT_I2SCH, 1 << 2   @ bitWidth 1 (I2S channel side)  
        .equ SPI0_STAT_TBE, 1 << 1   @ bitWidth 1 (Transmit Buffer Empty)  
        .equ SPI0_STAT_RBNE, 1 << 0   @ bitWidth 1 (Receive Buffer Not Empty)  
 
    .equ SPI0_DATA, SPI0_BASE + 0x0C @ (data register) 
        .equ SPI0_DATA_SPI_DATA_Shift, 0   @ bitWidth 16 (Data transfer register)  
 
    .equ SPI0_CRCPOLY, SPI0_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI0_CRCPOLY_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial value)  
 
    .equ SPI0_RCRC, SPI0_BASE + 0x14 @ (RX CRC register) 
        .equ SPI0_RCRC_RCRC_Shift, 0   @ bitWidth 16 (RX CRC value)  
 
    .equ SPI0_TCRC, SPI0_BASE + 0x18 @ (TX CRC register) 
        .equ SPI0_TCRC_TCRC_Shift, 0   @ bitWidth 16 (Tx CRC value)  
 
    .equ SPI0_I2SCTL, SPI0_BASE + 0x1C @ (I2S control register) 
        .equ SPI0_I2SCTL_I2SSEL, 1 << 11   @ bitWidth 1 (I2S mode selection)  
        .equ SPI0_I2SCTL_I2SEN, 1 << 10   @ bitWidth 1 (I2S Enable)  
        .equ SPI0_I2SCTL_I2SOPMOD_Shift, 8   @ bitWidth 2 (I2S operation mode)  
        .equ SPI0_I2SCTL_PCMSMOD, 1 << 7   @ bitWidth 1 (PCM frame synchronization mode)  
        .equ SPI0_I2SCTL_I2SSTD_Shift, 4   @ bitWidth 2 (I2S standard selection)  
        .equ SPI0_I2SCTL_CKPL, 1 << 3   @ bitWidth 1 (Idle state clock polarity)  
        .equ SPI0_I2SCTL_DTLEN_Shift, 1   @ bitWidth 2 (Data length)  
        .equ SPI0_I2SCTL_CHLEN, 1 << 0   @ bitWidth 1 (Channel length number of bits per audio  channel)  
 
    .equ SPI0_I2SPSC, SPI0_BASE + 0x20 @ (I2S prescaler register) 
        .equ SPI0_I2SPSC_MCKOEN, 1 << 9   @ bitWidth 1 (I2S_MCK output enable)  
        .equ SPI0_I2SPSC_OF, 1 << 8   @ bitWidth 1 (Odd factor for the  prescaler)  
        .equ SPI0_I2SPSC_DIV_Shift, 0   @ bitWidth 8 (Dividing factor for the prescaler)  
 

@=========================== SPI1 ===========================@
.equ SPI1_BASE, 0x40003800 @ (Serial peripheral interface) 
    .equ SPI1_CTL0, SPI1_BASE + 0x0 @ (control register 0) 
        .equ SPI1_CTL0_BDEN, 1 << 15   @ bitWidth 1 (Bidirectional   enable)  
        .equ SPI1_CTL0_BDOEN, 1 << 14   @ bitWidth 1 (Bidirectional Transmit output enable  )  
        .equ SPI1_CTL0_CRCEN, 1 << 13   @ bitWidth 1 (CRC Calculation Enable)  
        .equ SPI1_CTL0_CRCNT, 1 << 12   @ bitWidth 1 (CRC Next Transfer)  
        .equ SPI1_CTL0_FF16, 1 << 11   @ bitWidth 1 (Data frame format)  
        .equ SPI1_CTL0_RO, 1 << 10   @ bitWidth 1 (Receive only)  
        .equ SPI1_CTL0_SWNSSEN, 1 << 9   @ bitWidth 1 (NSS Software Mode Selection)  
        .equ SPI1_CTL0_SWNSS, 1 << 8   @ bitWidth 1 (NSS Pin Selection In NSS Software Mode)  
        .equ SPI1_CTL0_LF, 1 << 7   @ bitWidth 1 (LSB First Mode)  
        .equ SPI1_CTL0_SPIEN, 1 << 6   @ bitWidth 1 (SPI enable)  
        .equ SPI1_CTL0_PSC_Shift, 3   @ bitWidth 3 (Master Clock Prescaler Selection)  
        .equ SPI1_CTL0_MSTMOD, 1 << 2   @ bitWidth 1 (Master Mode Enable)  
        .equ SPI1_CTL0_CKPL, 1 << 1   @ bitWidth 1 (Clock polarity Selection)  
        .equ SPI1_CTL0_CKPH, 1 << 0   @ bitWidth 1 (Clock Phase Selection)  
 
    .equ SPI1_CTL1, SPI1_BASE + 0x04 @ (control register 1) 
        .equ SPI1_CTL1_TBEIE, 1 << 7   @ bitWidth 1 (Tx buffer empty interrupt  enable)  
        .equ SPI1_CTL1_RBNEIE, 1 << 6   @ bitWidth 1 (RX buffer not empty interrupt  enable)  
        .equ SPI1_CTL1_ERRIE, 1 << 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI1_CTL1_TMOD, 1 << 4   @ bitWidth 1 (SPI TI mode enable)  
        .equ SPI1_CTL1_NSSP, 1 << 3   @ bitWidth 1 (SPI NSS pulse mode enable)  
        .equ SPI1_CTL1_NSSDRV, 1 << 2   @ bitWidth 1 (Drive NSS Output)  
        .equ SPI1_CTL1_DMATEN, 1 << 1   @ bitWidth 1 (Transmit Buffer DMA Enable)  
        .equ SPI1_CTL1_DMAREN, 1 << 0   @ bitWidth 1 (Rx buffer DMA enable)  
 
    .equ SPI1_STAT, SPI1_BASE + 0x08 @ (status register) 
        .equ SPI1_STAT_FERR, 1 << 8   @ bitWidth 1 (Format error)  
        .equ SPI1_STAT_TRANS, 1 << 7   @ bitWidth 1 (Transmitting On-going Bit)  
        .equ SPI1_STAT_RXORERR, 1 << 6   @ bitWidth 1 (Reception Overrun Error Bit)  
        .equ SPI1_STAT_CONFERR, 1 << 5   @ bitWidth 1 (SPI Configuration error)  
        .equ SPI1_STAT_CRCERR, 1 << 4   @ bitWidth 1 (SPI CRC Error Bit)  
        .equ SPI1_STAT_TXURERR, 1 << 3   @ bitWidth 1 (Transmission underrun error bit)  
        .equ SPI1_STAT_I2SCH, 1 << 2   @ bitWidth 1 (I2S channel side)  
        .equ SPI1_STAT_TBE, 1 << 1   @ bitWidth 1 (Transmit Buffer Empty)  
        .equ SPI1_STAT_RBNE, 1 << 0   @ bitWidth 1 (Receive Buffer Not Empty)  
 
    .equ SPI1_DATA, SPI1_BASE + 0x0C @ (data register) 
        .equ SPI1_DATA_SPI_DATA_Shift, 0   @ bitWidth 16 (Data transfer register)  
 
    .equ SPI1_CRCPOLY, SPI1_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI1_CRCPOLY_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial value)  
 
    .equ SPI1_RCRC, SPI1_BASE + 0x14 @ (RX CRC register) 
        .equ SPI1_RCRC_RCRC_Shift, 0   @ bitWidth 16 (RX CRC value)  
 
    .equ SPI1_TCRC, SPI1_BASE + 0x18 @ (TX CRC register) 
        .equ SPI1_TCRC_TCRC_Shift, 0   @ bitWidth 16 (Tx CRC value)  
 
    .equ SPI1_I2SCTL, SPI1_BASE + 0x1C @ (I2S control register) 
        .equ SPI1_I2SCTL_I2SSEL, 1 << 11   @ bitWidth 1 (I2S mode selection)  
        .equ SPI1_I2SCTL_I2SEN, 1 << 10   @ bitWidth 1 (I2S Enable)  
        .equ SPI1_I2SCTL_I2SOPMOD_Shift, 8   @ bitWidth 2 (I2S operation mode)  
        .equ SPI1_I2SCTL_PCMSMOD, 1 << 7   @ bitWidth 1 (PCM frame synchronization mode)  
        .equ SPI1_I2SCTL_I2SSTD_Shift, 4   @ bitWidth 2 (I2S standard selection)  
        .equ SPI1_I2SCTL_CKPL, 1 << 3   @ bitWidth 1 (Idle state clock polarity)  
        .equ SPI1_I2SCTL_DTLEN_Shift, 1   @ bitWidth 2 (Data length)  
        .equ SPI1_I2SCTL_CHLEN, 1 << 0   @ bitWidth 1 (Channel length number of bits per audio  channel)  
 
    .equ SPI1_I2SPSC, SPI1_BASE + 0x20 @ (I2S prescaler register) 
        .equ SPI1_I2SPSC_MCKOEN, 1 << 9   @ bitWidth 1 (I2S_MCK output enable)  
        .equ SPI1_I2SPSC_OF, 1 << 8   @ bitWidth 1 (Odd factor for the  prescaler)  
        .equ SPI1_I2SPSC_DIV_Shift, 0   @ bitWidth 8 (Dividing factor for the prescaler)  
 

@=========================== SPI2 ===========================@
.equ SPI2_BASE, 0x40003C00 @ (Serial peripheral interface) 
    .equ SPI2_CTL0, SPI2_BASE + 0x0 @ (control register 0) 
        .equ SPI2_CTL0_BDEN, 1 << 15   @ bitWidth 1 (Bidirectional   enable)  
        .equ SPI2_CTL0_BDOEN, 1 << 14   @ bitWidth 1 (Bidirectional Transmit output enable  )  
        .equ SPI2_CTL0_CRCEN, 1 << 13   @ bitWidth 1 (CRC Calculation Enable)  
        .equ SPI2_CTL0_CRCNT, 1 << 12   @ bitWidth 1 (CRC Next Transfer)  
        .equ SPI2_CTL0_FF16, 1 << 11   @ bitWidth 1 (Data frame format)  
        .equ SPI2_CTL0_RO, 1 << 10   @ bitWidth 1 (Receive only)  
        .equ SPI2_CTL0_SWNSSEN, 1 << 9   @ bitWidth 1 (NSS Software Mode Selection)  
        .equ SPI2_CTL0_SWNSS, 1 << 8   @ bitWidth 1 (NSS Pin Selection In NSS Software Mode)  
        .equ SPI2_CTL0_LF, 1 << 7   @ bitWidth 1 (LSB First Mode)  
        .equ SPI2_CTL0_SPIEN, 1 << 6   @ bitWidth 1 (SPI enable)  
        .equ SPI2_CTL0_PSC_Shift, 3   @ bitWidth 3 (Master Clock Prescaler Selection)  
        .equ SPI2_CTL0_MSTMOD, 1 << 2   @ bitWidth 1 (Master Mode Enable)  
        .equ SPI2_CTL0_CKPL, 1 << 1   @ bitWidth 1 (Clock polarity Selection)  
        .equ SPI2_CTL0_CKPH, 1 << 0   @ bitWidth 1 (Clock Phase Selection)  
 
    .equ SPI2_CTL1, SPI2_BASE + 0x04 @ (control register 1) 
        .equ SPI2_CTL1_TBEIE, 1 << 7   @ bitWidth 1 (Tx buffer empty interrupt  enable)  
        .equ SPI2_CTL1_RBNEIE, 1 << 6   @ bitWidth 1 (RX buffer not empty interrupt  enable)  
        .equ SPI2_CTL1_ERRIE, 1 << 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI2_CTL1_TMOD, 1 << 4   @ bitWidth 1 (SPI TI mode enable)  
        .equ SPI2_CTL1_NSSP, 1 << 3   @ bitWidth 1 (SPI NSS pulse mode enable)  
        .equ SPI2_CTL1_NSSDRV, 1 << 2   @ bitWidth 1 (Drive NSS Output)  
        .equ SPI2_CTL1_DMATEN, 1 << 1   @ bitWidth 1 (Transmit Buffer DMA Enable)  
        .equ SPI2_CTL1_DMAREN, 1 << 0   @ bitWidth 1 (Rx buffer DMA enable)  
 
    .equ SPI2_STAT, SPI2_BASE + 0x08 @ (status register) 
        .equ SPI2_STAT_FERR, 1 << 8   @ bitWidth 1 (Format error)  
        .equ SPI2_STAT_TRANS, 1 << 7   @ bitWidth 1 (Transmitting On-going Bit)  
        .equ SPI2_STAT_RXORERR, 1 << 6   @ bitWidth 1 (Reception Overrun Error Bit)  
        .equ SPI2_STAT_CONFERR, 1 << 5   @ bitWidth 1 (SPI Configuration error)  
        .equ SPI2_STAT_CRCERR, 1 << 4   @ bitWidth 1 (SPI CRC Error Bit)  
        .equ SPI2_STAT_TXURERR, 1 << 3   @ bitWidth 1 (Transmission underrun error bit)  
        .equ SPI2_STAT_I2SCH, 1 << 2   @ bitWidth 1 (I2S channel side)  
        .equ SPI2_STAT_TBE, 1 << 1   @ bitWidth 1 (Transmit Buffer Empty)  
        .equ SPI2_STAT_RBNE, 1 << 0   @ bitWidth 1 (Receive Buffer Not Empty)  
 
    .equ SPI2_DATA, SPI2_BASE + 0x0C @ (data register) 
        .equ SPI2_DATA_SPI_DATA_Shift, 0   @ bitWidth 16 (Data transfer register)  
 
    .equ SPI2_CRCPOLY, SPI2_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI2_CRCPOLY_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial value)  
 
    .equ SPI2_RCRC, SPI2_BASE + 0x14 @ (RX CRC register) 
        .equ SPI2_RCRC_RCRC_Shift, 0   @ bitWidth 16 (RX CRC value)  
 
    .equ SPI2_TCRC, SPI2_BASE + 0x18 @ (TX CRC register) 
        .equ SPI2_TCRC_TCRC_Shift, 0   @ bitWidth 16 (Tx CRC value)  
 
    .equ SPI2_I2SCTL, SPI2_BASE + 0x1C @ (I2S control register) 
        .equ SPI2_I2SCTL_I2SSEL, 1 << 11   @ bitWidth 1 (I2S mode selection)  
        .equ SPI2_I2SCTL_I2SEN, 1 << 10   @ bitWidth 1 (I2S Enable)  
        .equ SPI2_I2SCTL_I2SOPMOD_Shift, 8   @ bitWidth 2 (I2S operation mode)  
        .equ SPI2_I2SCTL_PCMSMOD, 1 << 7   @ bitWidth 1 (PCM frame synchronization mode)  
        .equ SPI2_I2SCTL_I2SSTD_Shift, 4   @ bitWidth 2 (I2S standard selection)  
        .equ SPI2_I2SCTL_CKPL, 1 << 3   @ bitWidth 1 (Idle state clock polarity)  
        .equ SPI2_I2SCTL_DTLEN_Shift, 1   @ bitWidth 2 (Data length)  
        .equ SPI2_I2SCTL_CHLEN, 1 << 0   @ bitWidth 1 (Channel length number of bits per audio  channel)  
 
    .equ SPI2_I2SPSC, SPI2_BASE + 0x20 @ (I2S prescaler register) 
        .equ SPI2_I2SPSC_MCKOEN, 1 << 9   @ bitWidth 1 (I2S_MCK output enable)  
        .equ SPI2_I2SPSC_OF, 1 << 8   @ bitWidth 1 (Odd factor for the  prescaler)  
        .equ SPI2_I2SPSC_DIV_Shift, 0   @ bitWidth 8 (Dividing factor for the prescaler)  
 

@=========================== TIMER0 ===========================@
.equ TIMER0_BASE, 0x40012c00 @ (Advanced-timers) 
    .equ TIMER0_CTL0, TIMER0_BASE + 0x0 @ (control register 0) 
        .equ TIMER0_CTL0_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER0_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER0_CTL0_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode  selection)  
        .equ TIMER0_CTL0_DIR, 1 << 4   @ bitWidth 1 (Direction)  
        .equ TIMER0_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER0_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER0_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER0_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER0_CTL1, TIMER0_BASE + 0x04 @ (control register 1) 
        .equ TIMER0_CTL1_ISO3, 1 << 14   @ bitWidth 1 (Idle state of channel 3 output)  
        .equ TIMER0_CTL1_ISO2N, 1 << 13   @ bitWidth 1 (Idle state of channel 2 complementary output)  
        .equ TIMER0_CTL1_ISO2, 1 << 12   @ bitWidth 1 (Idle state of channel 2 output)  
        .equ TIMER0_CTL1_ISO1N, 1 << 11   @ bitWidth 1 (Idle state of channel 1 complementary output)  
        .equ TIMER0_CTL1_ISO1, 1 << 10   @ bitWidth 1 (Idle state of channel 1 output)  
        .equ TIMER0_CTL1_ISO0N, 1 << 9   @ bitWidth 1 (Idle state of channel 0 complementary output)  
        .equ TIMER0_CTL1_ISO0, 1 << 8   @ bitWidth 1 (Idle state of channel 0 output)  
        .equ TIMER0_CTL1_TI0S, 1 << 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER0_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER0_CTL1_DMAS, 1 << 3   @ bitWidth 1 (DMA request source selection)  
        .equ TIMER0_CTL1_CCUC, 1 << 2   @ bitWidth 1 (Commutation control shadow register update control)  
        .equ TIMER0_CTL1_CCSE, 1 << 0   @ bitWidth 1 (Commutation control shadow enable)  
 
    .equ TIMER0_SMCFG, TIMER0_BASE + 0x08 @ (slave mode configuration register) 
        .equ TIMER0_SMCFG_ETP, 1 << 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER0_SMCFG_SMC1, 1 << 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER0_SMCFG_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER0_SMCFG_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER0_SMCFG_MSM, 1 << 7   @ bitWidth 1 (Master/Slave mode)  
        .equ TIMER0_SMCFG_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER0_SMCFG_SMC_Shift, 0   @ bitWidth 3 (Slave mode selection)  
 
    .equ TIMER0_DMAINTEN, TIMER0_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER0_DMAINTEN_TRGDEN, 1 << 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER0_DMAINTEN_CMTDEN, 1 << 13   @ bitWidth 1 (Commutation DMA request enable)  
        .equ TIMER0_DMAINTEN_CH3DEN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER0_DMAINTEN_CH2DEN, 1 << 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER0_DMAINTEN_CH1DEN, 1 << 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER0_DMAINTEN_CH0DEN, 1 << 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER0_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER0_DMAINTEN_BRKIE, 1 << 7   @ bitWidth 1 (Break interrupt enable)  
        .equ TIMER0_DMAINTEN_TRGIE, 1 << 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER0_DMAINTEN_CMTIE, 1 << 5   @ bitWidth 1 (commutation interrupt enable)  
        .equ TIMER0_DMAINTEN_CH3IE, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER0_DMAINTEN_CH2IE, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER0_DMAINTEN_CH1IE, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER0_DMAINTEN_CH0IE, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER0_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER0_INTF, TIMER0_BASE + 0x10 @ (Interrupt flag register) 
        .equ TIMER0_INTF_CH3OF, 1 << 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER0_INTF_CH2OF, 1 << 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER0_INTF_CH1OF, 1 << 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER0_INTF_CH0OF, 1 << 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER0_INTF_BRKIF, 1 << 7   @ bitWidth 1 (Break interrupt flag)  
        .equ TIMER0_INTF_TRGIF, 1 << 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER0_INTF_CMTIF, 1 << 5   @ bitWidth 1 (Channel commutation interrupt flag)  
        .equ TIMER0_INTF_CH3IF, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt flag)  
        .equ TIMER0_INTF_CH2IF, 1 << 3   @ bitWidth 1 ( Channel 2 capture/compare interrupt flag)  
        .equ TIMER0_INTF_CH1IF, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER0_INTF_CH0IF, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER0_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER0_SWEVG, TIMER0_BASE + 0x14 @ (Software event generation register) 
        .equ TIMER0_SWEVG_BRKG, 1 << 7   @ bitWidth 1 (Break event generation)  
        .equ TIMER0_SWEVG_TRGG, 1 << 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER0_SWEVG_CMTG, 1 << 5   @ bitWidth 1 (Channel commutation event generation)  
        .equ TIMER0_SWEVG_CH3G, 1 << 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER0_SWEVG_CH2G, 1 << 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER0_SWEVG_CH1G, 1 << 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER0_SWEVG_CH0G, 1 << 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER0_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update event generation)  
 
    .equ TIMER0_CHCTL0_Output, TIMER0_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER0_CHCTL0_Output_CH1COMCEN, 1 << 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER0_CHCTL0_Output_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER0_CHCTL0_Output_CH1COMSEN, 1 << 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER0_CHCTL0_Output_CH1COMFEN, 1 << 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER0_CHCTL0_Output_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER0_CHCTL0_Output_CH0COMCEN, 1 << 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER0_CHCTL0_Output_CH0COMCTL_Shift, 4   @ bitWidth 3 (Channel 0 compare output control)  
        .equ TIMER0_CHCTL0_Output_CH0COMSEN, 1 << 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER0_CHCTL0_Output_CH0COMFEN, 1 << 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER0_CHCTL0_Output_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER0_CHCTL0_Input, TIMER0_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER0_CHCTL0_Input_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER0_CHCTL0_Input_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER0_CHCTL0_Input_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER0_CHCTL0_Input_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER0_CHCTL0_Input_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER0_CHCTL0_Input_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER0_CHCTL1_Output, TIMER0_BASE + 0x1C @ (Channel control register 1 output  mode) 
        .equ TIMER0_CHCTL1_Output_CH3COMCEN, 1 << 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER0_CHCTL1_Output_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER0_CHCTL1_Output_CH3COMSEN, 1 << 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER0_CHCTL1_Output_CH3COMFEN, 1 << 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER0_CHCTL1_Output_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER0_CHCTL1_Output_CH2COMCEN, 1 << 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER0_CHCTL1_Output_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER0_CHCTL1_Output_CH2COMSEN, 1 << 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER0_CHCTL1_Output_CH2COMFEN, 1 << 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER0_CHCTL1_Output_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER0_CHCTL1_Input, TIMER0_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER0_CHCTL1_Input_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER0_CHCTL1_Input_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER0_CHCTL1_Input_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER0_CHCTL1_Input_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER0_CHCTL1_Input_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER0_CHCTL1_Input_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER0_CHCTL2, TIMER0_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER0_CHCTL2_CH3P, 1 << 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER0_CHCTL2_CH3EN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER0_CHCTL2_CH2NP, 1 << 11   @ bitWidth 1 (Channel 2 complementary output polarity)  
        .equ TIMER0_CHCTL2_CH2NEN, 1 << 10   @ bitWidth 1 (Channel 2 complementary output enable)  
        .equ TIMER0_CHCTL2_CH2P, 1 << 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER0_CHCTL2_CH2EN, 1 << 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER0_CHCTL2_CH1NP, 1 << 7   @ bitWidth 1 (Channel 1 complementary output polarity)  
        .equ TIMER0_CHCTL2_CH1NEN, 1 << 6   @ bitWidth 1 (Channel 1 complementary output enable)  
        .equ TIMER0_CHCTL2_CH1P, 1 << 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER0_CHCTL2_CH1EN, 1 << 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER0_CHCTL2_CH0NP, 1 << 3   @ bitWidth 1 (Channel 0 complementary output polarity)  
        .equ TIMER0_CHCTL2_CH0NEN, 1 << 2   @ bitWidth 1 (Channel 0 complementary output enable)  
        .equ TIMER0_CHCTL2_CH0P, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER0_CHCTL2_CH0EN, 1 << 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER0_CNT, TIMER0_BASE + 0x24 @ (counter) 
        .equ TIMER0_CNT_CNT_Shift, 0   @ bitWidth 16 (current counter value)  
 
    .equ TIMER0_PSC, TIMER0_BASE + 0x28 @ (prescaler) 
        .equ TIMER0_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER0_CAR, TIMER0_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER0_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER0_CREP, TIMER0_BASE + 0x30 @ (Counter repetition register) 
        .equ TIMER0_CREP_CREP_Shift, 0   @ bitWidth 8 (Counter repetition value)  
 
    .equ TIMER0_CH0CV, TIMER0_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER0_CH0CV_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel0)  
 
    .equ TIMER0_CH1CV, TIMER0_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER0_CH1CV_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER0_CH2CV, TIMER0_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER0_CH2CV_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER0_CH3CV, TIMER0_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER0_CH3CV_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER0_CCHP, TIMER0_BASE + 0x44 @ (channel complementary protection register) 
        .equ TIMER0_CCHP_POEN, 1 << 15   @ bitWidth 1 (Primary output enable)  
        .equ TIMER0_CCHP_OAEN, 1 << 14   @ bitWidth 1 (Output automatic enable)  
        .equ TIMER0_CCHP_BRKP, 1 << 13   @ bitWidth 1 (Break polarity)  
        .equ TIMER0_CCHP_BRKEN, 1 << 12   @ bitWidth 1 (Break enable)  
        .equ TIMER0_CCHP_ROS, 1 << 11   @ bitWidth 1 (Run mode off-state configure)  
        .equ TIMER0_CCHP_IOS, 1 << 10   @ bitWidth 1 (Idle mode off-state configure)  
        .equ TIMER0_CCHP_PROT_Shift, 8   @ bitWidth 2 (Complementary register protect control)  
        .equ TIMER0_CCHP_DTCFG_Shift, 0   @ bitWidth 8 (Dead time configure)  
 
    .equ TIMER0_DMACFG, TIMER0_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER0_DMACFG_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER0_DMACFG_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER0_DMATB, TIMER0_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER0_DMATB_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER1 ===========================@
.equ TIMER1_BASE, 0x40000000 @ (General-purpose-timers) 
    .equ TIMER1_CTL0, TIMER1_BASE + 0x0 @ (control register 0) 
        .equ TIMER1_CTL0_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER1_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER1_CTL0_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER1_CTL0_DIR, 1 << 4   @ bitWidth 1 (Direction)  
        .equ TIMER1_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER1_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER1_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER1_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER1_CTL1, TIMER1_BASE + 0x04 @ (control register 1) 
        .equ TIMER1_CTL1_TI0S, 1 << 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER1_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER1_CTL1_DMAS, 1 << 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER1_SMCFG, TIMER1_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER1_SMCFG_ETP, 1 << 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER1_SMCFG_SMC1, 1 << 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER1_SMCFG_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER1_SMCFG_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER1_SMCFG_MSM, 1 << 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER1_SMCFG_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER1_SMCFG_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER1_DMAINTEN, TIMER1_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER1_DMAINTEN_TRGDEN, 1 << 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER1_DMAINTEN_CH3DEN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER1_DMAINTEN_CH2DEN, 1 << 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER1_DMAINTEN_CH1DEN, 1 << 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER1_DMAINTEN_CH0DEN, 1 << 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER1_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER1_DMAINTEN_TRGIE, 1 << 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER1_DMAINTEN_CH3IE, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER1_DMAINTEN_CH2IE, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER1_DMAINTEN_CH1IE, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER1_DMAINTEN_CH0IE, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER1_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER1_INTF, TIMER1_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER1_INTF_CH3OF, 1 << 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER1_INTF_CH2OF, 1 << 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER1_INTF_CH1OF, 1 << 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER1_INTF_CH0OF, 1 << 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER1_INTF_TRGIF, 1 << 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER1_INTF_CH3IF, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER1_INTF_CH2IF, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER1_INTF_CH1IF, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER1_INTF_CH0IF, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER1_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER1_SWEVG, TIMER1_BASE + 0x14 @ (event generation register) 
        .equ TIMER1_SWEVG_TRGG, 1 << 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER1_SWEVG_CH3G, 1 << 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER1_SWEVG_CH2G, 1 << 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER1_SWEVG_CH1G, 1 << 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER1_SWEVG_CH0G, 1 << 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER1_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER1_CHCTL0_Output, TIMER1_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER1_CHCTL0_Output_CH1COMCEN, 1 << 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER1_CHCTL0_Output_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER1_CHCTL0_Output_CH1COMSEN, 1 << 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER1_CHCTL0_Output_CH1COMFEN, 1 << 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER1_CHCTL0_Output_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER1_CHCTL0_Output_CH0COMCEN, 1 << 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER1_CHCTL0_Output_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER1_CHCTL0_Output_CH0COMSEN, 1 << 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER1_CHCTL0_Output_CH0COMFEN, 1 << 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER1_CHCTL0_Output_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER1_CHCTL0_Input, TIMER1_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER1_CHCTL0_Input_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER1_CHCTL0_Input_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER1_CHCTL0_Input_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER1_CHCTL0_Input_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER1_CHCTL0_Input_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER1_CHCTL0_Input_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER1_CHCTL1_Output, TIMER1_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER1_CHCTL1_Output_CH3COMCEN, 1 << 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER1_CHCTL1_Output_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER1_CHCTL1_Output_CH3COMSEN, 1 << 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER1_CHCTL1_Output_CH3COMFEN, 1 << 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER1_CHCTL1_Output_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER1_CHCTL1_Output_CH2COMCEN, 1 << 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER1_CHCTL1_Output_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER1_CHCTL1_Output_CH2COMSEN, 1 << 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER1_CHCTL1_Output_CH2COMFEN, 1 << 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER1_CHCTL1_Output_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER1_CHCTL1_Input, TIMER1_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER1_CHCTL1_Input_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER1_CHCTL1_Input_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER1_CHCTL1_Input_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER1_CHCTL1_Input_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER1_CHCTL1_Input_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER1_CHCTL1_Input_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER1_CHCTL2, TIMER1_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER1_CHCTL2_CH3P, 1 << 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER1_CHCTL2_CH3EN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER1_CHCTL2_CH2P, 1 << 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER1_CHCTL2_CH2EN, 1 << 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER1_CHCTL2_CH1P, 1 << 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER1_CHCTL2_CH1EN, 1 << 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER1_CHCTL2_CH0P, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER1_CHCTL2_CH0EN, 1 << 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER1_CNT, TIMER1_BASE + 0x24 @ (Counter register) 
        .equ TIMER1_CNT_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER1_PSC, TIMER1_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER1_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER1_CAR, TIMER1_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER1_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER1_CH0CV, TIMER1_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER1_CH0CV_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER1_CH1CV, TIMER1_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER1_CH1CV_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER1_CH2CV, TIMER1_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER1_CH2CV_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER1_CH3CV, TIMER1_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER1_CH3CV_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER1_DMACFG, TIMER1_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER1_DMACFG_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER1_DMACFG_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER1_DMATB, TIMER1_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER1_DMATB_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER2 ===========================@
.equ TIMER2_BASE, 0x40000400 @ (General-purpose-timers) 
    .equ TIMER2_CTL0, TIMER2_BASE + 0x0 @ (control register 0) 
        .equ TIMER2_CTL0_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER2_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER2_CTL0_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER2_CTL0_DIR, 1 << 4   @ bitWidth 1 (Direction)  
        .equ TIMER2_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER2_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER2_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER2_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER2_CTL1, TIMER2_BASE + 0x04 @ (control register 1) 
        .equ TIMER2_CTL1_TI0S, 1 << 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER2_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER2_CTL1_DMAS, 1 << 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER2_SMCFG, TIMER2_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER2_SMCFG_ETP, 1 << 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER2_SMCFG_SMC1, 1 << 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER2_SMCFG_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER2_SMCFG_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER2_SMCFG_MSM, 1 << 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER2_SMCFG_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER2_SMCFG_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER2_DMAINTEN, TIMER2_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER2_DMAINTEN_TRGDEN, 1 << 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER2_DMAINTEN_CH3DEN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER2_DMAINTEN_CH2DEN, 1 << 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER2_DMAINTEN_CH1DEN, 1 << 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER2_DMAINTEN_CH0DEN, 1 << 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER2_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER2_DMAINTEN_TRGIE, 1 << 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER2_DMAINTEN_CH3IE, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER2_DMAINTEN_CH2IE, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER2_DMAINTEN_CH1IE, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER2_DMAINTEN_CH0IE, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER2_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER2_INTF, TIMER2_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER2_INTF_CH3OF, 1 << 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER2_INTF_CH2OF, 1 << 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER2_INTF_CH1OF, 1 << 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER2_INTF_CH0OF, 1 << 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER2_INTF_TRGIF, 1 << 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER2_INTF_CH3IF, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER2_INTF_CH2IF, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER2_INTF_CH1IF, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER2_INTF_CH0IF, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER2_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER2_SWEVG, TIMER2_BASE + 0x14 @ (event generation register) 
        .equ TIMER2_SWEVG_TRGG, 1 << 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER2_SWEVG_CH3G, 1 << 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER2_SWEVG_CH2G, 1 << 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER2_SWEVG_CH1G, 1 << 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER2_SWEVG_CH0G, 1 << 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER2_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER2_CHCTL0_Output, TIMER2_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER2_CHCTL0_Output_CH1COMCEN, 1 << 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER2_CHCTL0_Output_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER2_CHCTL0_Output_CH1COMSEN, 1 << 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER2_CHCTL0_Output_CH1COMFEN, 1 << 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER2_CHCTL0_Output_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER2_CHCTL0_Output_CH0COMCEN, 1 << 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER2_CHCTL0_Output_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER2_CHCTL0_Output_CH0COMSEN, 1 << 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER2_CHCTL0_Output_CH0COMFEN, 1 << 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER2_CHCTL0_Output_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER2_CHCTL0_Input, TIMER2_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER2_CHCTL0_Input_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER2_CHCTL0_Input_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER2_CHCTL0_Input_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER2_CHCTL0_Input_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER2_CHCTL0_Input_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER2_CHCTL0_Input_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER2_CHCTL1_Output, TIMER2_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER2_CHCTL1_Output_CH3COMCEN, 1 << 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER2_CHCTL1_Output_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER2_CHCTL1_Output_CH3COMSEN, 1 << 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER2_CHCTL1_Output_CH3COMFEN, 1 << 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER2_CHCTL1_Output_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER2_CHCTL1_Output_CH2COMCEN, 1 << 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER2_CHCTL1_Output_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER2_CHCTL1_Output_CH2COMSEN, 1 << 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER2_CHCTL1_Output_CH2COMFEN, 1 << 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER2_CHCTL1_Output_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER2_CHCTL1_Input, TIMER2_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER2_CHCTL1_Input_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER2_CHCTL1_Input_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER2_CHCTL1_Input_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER2_CHCTL1_Input_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER2_CHCTL1_Input_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER2_CHCTL1_Input_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER2_CHCTL2, TIMER2_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER2_CHCTL2_CH3P, 1 << 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER2_CHCTL2_CH3EN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER2_CHCTL2_CH2P, 1 << 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER2_CHCTL2_CH2EN, 1 << 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER2_CHCTL2_CH1P, 1 << 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER2_CHCTL2_CH1EN, 1 << 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER2_CHCTL2_CH0P, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER2_CHCTL2_CH0EN, 1 << 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER2_CNT, TIMER2_BASE + 0x24 @ (Counter register) 
        .equ TIMER2_CNT_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER2_PSC, TIMER2_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER2_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER2_CAR, TIMER2_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER2_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER2_CH0CV, TIMER2_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER2_CH0CV_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER2_CH1CV, TIMER2_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER2_CH1CV_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER2_CH2CV, TIMER2_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER2_CH2CV_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER2_CH3CV, TIMER2_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER2_CH3CV_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER2_DMACFG, TIMER2_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER2_DMACFG_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER2_DMACFG_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER2_DMATB, TIMER2_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER2_DMATB_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER3 ===========================@
.equ TIMER3_BASE, 0x40000800 @ (General-purpose-timers) 
    .equ TIMER3_CTL0, TIMER3_BASE + 0x0 @ (control register 0) 
        .equ TIMER3_CTL0_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER3_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER3_CTL0_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER3_CTL0_DIR, 1 << 4   @ bitWidth 1 (Direction)  
        .equ TIMER3_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER3_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER3_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER3_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER3_CTL1, TIMER3_BASE + 0x04 @ (control register 1) 
        .equ TIMER3_CTL1_TI0S, 1 << 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER3_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER3_CTL1_DMAS, 1 << 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER3_SMCFG, TIMER3_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER3_SMCFG_ETP, 1 << 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER3_SMCFG_SMC1, 1 << 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER3_SMCFG_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER3_SMCFG_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER3_SMCFG_MSM, 1 << 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER3_SMCFG_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER3_SMCFG_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER3_DMAINTEN, TIMER3_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER3_DMAINTEN_TRGDEN, 1 << 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER3_DMAINTEN_CH3DEN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER3_DMAINTEN_CH2DEN, 1 << 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER3_DMAINTEN_CH1DEN, 1 << 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER3_DMAINTEN_CH0DEN, 1 << 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER3_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER3_DMAINTEN_TRGIE, 1 << 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER3_DMAINTEN_CH3IE, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER3_DMAINTEN_CH2IE, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER3_DMAINTEN_CH1IE, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER3_DMAINTEN_CH0IE, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER3_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER3_INTF, TIMER3_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER3_INTF_CH3OF, 1 << 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER3_INTF_CH2OF, 1 << 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER3_INTF_CH1OF, 1 << 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER3_INTF_CH0OF, 1 << 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER3_INTF_TRGIF, 1 << 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER3_INTF_CH3IF, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER3_INTF_CH2IF, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER3_INTF_CH1IF, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER3_INTF_CH0IF, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER3_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER3_SWEVG, TIMER3_BASE + 0x14 @ (event generation register) 
        .equ TIMER3_SWEVG_TRGG, 1 << 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER3_SWEVG_CH3G, 1 << 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER3_SWEVG_CH2G, 1 << 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER3_SWEVG_CH1G, 1 << 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER3_SWEVG_CH0G, 1 << 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER3_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER3_CHCTL0_Output, TIMER3_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER3_CHCTL0_Output_CH1COMCEN, 1 << 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER3_CHCTL0_Output_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER3_CHCTL0_Output_CH1COMSEN, 1 << 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER3_CHCTL0_Output_CH1COMFEN, 1 << 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER3_CHCTL0_Output_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER3_CHCTL0_Output_CH0COMCEN, 1 << 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER3_CHCTL0_Output_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER3_CHCTL0_Output_CH0COMSEN, 1 << 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER3_CHCTL0_Output_CH0COMFEN, 1 << 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER3_CHCTL0_Output_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER3_CHCTL0_Input, TIMER3_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER3_CHCTL0_Input_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER3_CHCTL0_Input_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER3_CHCTL0_Input_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER3_CHCTL0_Input_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER3_CHCTL0_Input_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER3_CHCTL0_Input_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER3_CHCTL1_Output, TIMER3_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER3_CHCTL1_Output_CH3COMCEN, 1 << 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER3_CHCTL1_Output_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER3_CHCTL1_Output_CH3COMSEN, 1 << 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER3_CHCTL1_Output_CH3COMFEN, 1 << 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER3_CHCTL1_Output_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER3_CHCTL1_Output_CH2COMCEN, 1 << 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER3_CHCTL1_Output_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER3_CHCTL1_Output_CH2COMSEN, 1 << 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER3_CHCTL1_Output_CH2COMFEN, 1 << 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER3_CHCTL1_Output_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER3_CHCTL1_Input, TIMER3_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER3_CHCTL1_Input_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER3_CHCTL1_Input_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER3_CHCTL1_Input_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER3_CHCTL1_Input_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER3_CHCTL1_Input_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER3_CHCTL1_Input_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER3_CHCTL2, TIMER3_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER3_CHCTL2_CH3P, 1 << 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER3_CHCTL2_CH3EN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER3_CHCTL2_CH2P, 1 << 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER3_CHCTL2_CH2EN, 1 << 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER3_CHCTL2_CH1P, 1 << 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER3_CHCTL2_CH1EN, 1 << 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER3_CHCTL2_CH0P, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER3_CHCTL2_CH0EN, 1 << 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER3_CNT, TIMER3_BASE + 0x24 @ (Counter register) 
        .equ TIMER3_CNT_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER3_PSC, TIMER3_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER3_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER3_CAR, TIMER3_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER3_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER3_CH0CV, TIMER3_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER3_CH0CV_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER3_CH1CV, TIMER3_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER3_CH1CV_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER3_CH2CV, TIMER3_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER3_CH2CV_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER3_CH3CV, TIMER3_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER3_CH3CV_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER3_DMACFG, TIMER3_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER3_DMACFG_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER3_DMACFG_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER3_DMATB, TIMER3_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER3_DMATB_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER4 ===========================@
.equ TIMER4_BASE, 0x40000C00 @ (General-purpose-timers) 
    .equ TIMER4_CTL0, TIMER4_BASE + 0x0 @ (control register 0) 
        .equ TIMER4_CTL0_CKDIV_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIMER4_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER4_CTL0_CAM_Shift, 5   @ bitWidth 2 (Counter aligns mode selection)  
        .equ TIMER4_CTL0_DIR, 1 << 4   @ bitWidth 1 (Direction)  
        .equ TIMER4_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER4_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER4_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER4_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER4_CTL1, TIMER4_BASE + 0x04 @ (control register 1) 
        .equ TIMER4_CTL1_TI0S, 1 << 7   @ bitWidth 1 (Channel 0 trigger input selection)  
        .equ TIMER4_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
        .equ TIMER4_CTL1_DMAS, 1 << 3   @ bitWidth 1 (DMA request source selection)  
 
    .equ TIMER4_SMCFG, TIMER4_BASE + 0x08 @ (slave mode control register) 
        .equ TIMER4_SMCFG_ETP, 1 << 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIMER4_SMCFG_SMC1, 1 << 14   @ bitWidth 1 (Part of SMC for enable External clock mode1)  
        .equ TIMER4_SMCFG_ETPSC_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIMER4_SMCFG_ETFC_Shift, 8   @ bitWidth 4 (External trigger filter control)  
        .equ TIMER4_SMCFG_MSM, 1 << 7   @ bitWidth 1 (Master-slave mode)  
        .equ TIMER4_SMCFG_TRGS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIMER4_SMCFG_SMC_Shift, 0   @ bitWidth 3 (Slave mode control)  
 
    .equ TIMER4_DMAINTEN, TIMER4_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER4_DMAINTEN_TRGDEN, 1 << 14   @ bitWidth 1 (Trigger DMA request enable)  
        .equ TIMER4_DMAINTEN_CH3DEN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare DMA request enable)  
        .equ TIMER4_DMAINTEN_CH2DEN, 1 << 11   @ bitWidth 1 (Channel 2 capture/compare DMA request enable)  
        .equ TIMER4_DMAINTEN_CH1DEN, 1 << 10   @ bitWidth 1 (Channel 1 capture/compare DMA request enable)  
        .equ TIMER4_DMAINTEN_CH0DEN, 1 << 9   @ bitWidth 1 (Channel 0 capture/compare DMA request enable)  
        .equ TIMER4_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER4_DMAINTEN_TRGIE, 1 << 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIMER4_DMAINTEN_CH3IE, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER4_DMAINTEN_CH2IE, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER4_DMAINTEN_CH1IE, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt enable)  
        .equ TIMER4_DMAINTEN_CH0IE, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt enable)  
        .equ TIMER4_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER4_INTF, TIMER4_BASE + 0x10 @ (interrupt flag register) 
        .equ TIMER4_INTF_CH3OF, 1 << 12   @ bitWidth 1 (Channel 3 over capture flag)  
        .equ TIMER4_INTF_CH2OF, 1 << 11   @ bitWidth 1 (Channel 2 over capture flag)  
        .equ TIMER4_INTF_CH1OF, 1 << 10   @ bitWidth 1 (Channel 1 over capture flag)  
        .equ TIMER4_INTF_CH0OF, 1 << 9   @ bitWidth 1 (Channel 0 over capture flag)  
        .equ TIMER4_INTF_TRGIF, 1 << 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIMER4_INTF_CH3IF, 1 << 4   @ bitWidth 1 (Channel 3 capture/compare interrupt enable)  
        .equ TIMER4_INTF_CH2IF, 1 << 3   @ bitWidth 1 (Channel 2 capture/compare interrupt enable)  
        .equ TIMER4_INTF_CH1IF, 1 << 2   @ bitWidth 1 (Channel 1 capture/compare interrupt flag)  
        .equ TIMER4_INTF_CH0IF, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare interrupt flag)  
        .equ TIMER4_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER4_SWEVG, TIMER4_BASE + 0x14 @ (event generation register) 
        .equ TIMER4_SWEVG_TRGG, 1 << 6   @ bitWidth 1 (Trigger event generation)  
        .equ TIMER4_SWEVG_CH3G, 1 << 4   @ bitWidth 1 (Channel 3 capture or compare event generation)  
        .equ TIMER4_SWEVG_CH2G, 1 << 3   @ bitWidth 1 (Channel 2 capture or compare event generation)  
        .equ TIMER4_SWEVG_CH1G, 1 << 2   @ bitWidth 1 (Channel 1 capture or compare event generation)  
        .equ TIMER4_SWEVG_CH0G, 1 << 1   @ bitWidth 1 (Channel 0 capture or compare event generation)  
        .equ TIMER4_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER4_CHCTL0_Output, TIMER4_BASE + 0x18 @ (Channel control register 0 output  mode) 
        .equ TIMER4_CHCTL0_Output_CH1COMCEN, 1 << 15   @ bitWidth 1 (Channel 1 output compare clear enable)  
        .equ TIMER4_CHCTL0_Output_CH1COMCTL_Shift, 12   @ bitWidth 3 (Channel 1 compare output control)  
        .equ TIMER4_CHCTL0_Output_CH1COMSEN, 1 << 11   @ bitWidth 1 (Channel 1 output compare shadow enable)  
        .equ TIMER4_CHCTL0_Output_CH1COMFEN, 1 << 10   @ bitWidth 1 (Channel 1 output compare fast enable)  
        .equ TIMER4_CHCTL0_Output_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER4_CHCTL0_Output_CH0COMCEN, 1 << 7   @ bitWidth 1 (Channel 0 output compare clear enable)  
        .equ TIMER4_CHCTL0_Output_CH0COMCTL_Shift, 4   @ bitWidth 3 ( Channel 0 compare output control)  
        .equ TIMER4_CHCTL0_Output_CH0COMSEN, 1 << 3   @ bitWidth 1 (Channel 0 compare output shadow enable)  
        .equ TIMER4_CHCTL0_Output_CH0COMFEN, 1 << 2   @ bitWidth 1 (Channel 0 output compare fast enable)  
        .equ TIMER4_CHCTL0_Output_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 I/O mode selection)  
 
    .equ TIMER4_CHCTL0_Input, TIMER4_BASE + 0x18 @ (Channel control register 0 input  mode) 
        .equ TIMER4_CHCTL0_Input_CH1CAPFLT_Shift, 12   @ bitWidth 4 (Channel 1 input capture filter control)  
        .equ TIMER4_CHCTL0_Input_CH1CAPPSC_Shift, 10   @ bitWidth 2 (Channel 1 input capture prescaler)  
        .equ TIMER4_CHCTL0_Input_CH1MS_Shift, 8   @ bitWidth 2 (Channel 1 mode selection)  
        .equ TIMER4_CHCTL0_Input_CH0CAPFLT_Shift, 4   @ bitWidth 4 (Channel 0 input capture filter control)  
        .equ TIMER4_CHCTL0_Input_CH0CAPPSC_Shift, 2   @ bitWidth 2 (Channel 0 input capture prescaler)  
        .equ TIMER4_CHCTL0_Input_CH0MS_Shift, 0   @ bitWidth 2 (Channel 0 mode selection)  
 
    .equ TIMER4_CHCTL1_Output, TIMER4_BASE + 0x1C @ (Channel control register 1 output mode) 
        .equ TIMER4_CHCTL1_Output_CH3COMCEN, 1 << 15   @ bitWidth 1 (Channel 3 output compare clear enable)  
        .equ TIMER4_CHCTL1_Output_CH3COMCTL_Shift, 12   @ bitWidth 3 (Channel 3 compare output control)  
        .equ TIMER4_CHCTL1_Output_CH3COMSEN, 1 << 11   @ bitWidth 1 (Channel 3 output compare shadow enable)  
        .equ TIMER4_CHCTL1_Output_CH3COMFEN, 1 << 10   @ bitWidth 1 (Channel 3 output compare fast enable)  
        .equ TIMER4_CHCTL1_Output_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER4_CHCTL1_Output_CH2COMCEN, 1 << 7   @ bitWidth 1 (Channel 2 output compare clear enable)  
        .equ TIMER4_CHCTL1_Output_CH2COMCTL_Shift, 4   @ bitWidth 3 (Channel 2 compare output control)  
        .equ TIMER4_CHCTL1_Output_CH2COMSEN, 1 << 3   @ bitWidth 1 (Channel 2 compare output shadow enable)  
        .equ TIMER4_CHCTL1_Output_CH2COMFEN, 1 << 2   @ bitWidth 1 (Channel 2 output compare fast enable)  
        .equ TIMER4_CHCTL1_Output_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 I/O mode selection)  
 
    .equ TIMER4_CHCTL1_Input, TIMER4_BASE + 0x1C @ (Channel control register 1 input  mode) 
        .equ TIMER4_CHCTL1_Input_CH3CAPFLT_Shift, 12   @ bitWidth 4 (Channel 3 input capture filter control)  
        .equ TIMER4_CHCTL1_Input_CH3CAPPSC_Shift, 10   @ bitWidth 2 (Channel 3 input capture prescaler)  
        .equ TIMER4_CHCTL1_Input_CH3MS_Shift, 8   @ bitWidth 2 (Channel 3 mode selection)  
        .equ TIMER4_CHCTL1_Input_CH2CAPFLT_Shift, 4   @ bitWidth 4 (Channel 2 input capture filter control)  
        .equ TIMER4_CHCTL1_Input_CH2CAPPSC_Shift, 2   @ bitWidth 2 (Channel 2 input capture prescaler)  
        .equ TIMER4_CHCTL1_Input_CH2MS_Shift, 0   @ bitWidth 2 (Channel 2 mode selection)  
 
    .equ TIMER4_CHCTL2, TIMER4_BASE + 0x20 @ (Channel control register 2) 
        .equ TIMER4_CHCTL2_CH3P, 1 << 13   @ bitWidth 1 (Channel 3 capture/compare function polarity)  
        .equ TIMER4_CHCTL2_CH3EN, 1 << 12   @ bitWidth 1 (Channel 3 capture/compare function enable)  
        .equ TIMER4_CHCTL2_CH2P, 1 << 9   @ bitWidth 1 (Channel 2 capture/compare function polarity)  
        .equ TIMER4_CHCTL2_CH2EN, 1 << 8   @ bitWidth 1 (Channel 2 capture/compare function enable)  
        .equ TIMER4_CHCTL2_CH1P, 1 << 5   @ bitWidth 1 (Channel 1 capture/compare function polarity)  
        .equ TIMER4_CHCTL2_CH1EN, 1 << 4   @ bitWidth 1 (Channel 1 capture/compare function enable)  
        .equ TIMER4_CHCTL2_CH0P, 1 << 1   @ bitWidth 1 (Channel 0 capture/compare function polarity)  
        .equ TIMER4_CHCTL2_CH0EN, 1 << 0   @ bitWidth 1 (Channel 0 capture/compare function enable)  
 
    .equ TIMER4_CNT, TIMER4_BASE + 0x24 @ (Counter register) 
        .equ TIMER4_CNT_CNT_Shift, 0   @ bitWidth 16 (counter value)  
 
    .equ TIMER4_PSC, TIMER4_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER4_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER4_CAR, TIMER4_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER4_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 
    .equ TIMER4_CH0CV, TIMER4_BASE + 0x34 @ (Channel 0 capture/compare value register) 
        .equ TIMER4_CH0CV_CH0VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 0)  
 
    .equ TIMER4_CH1CV, TIMER4_BASE + 0x38 @ (Channel 1 capture/compare value register) 
        .equ TIMER4_CH1CV_CH1VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel1)  
 
    .equ TIMER4_CH2CV, TIMER4_BASE + 0x3C @ (Channel 2 capture/compare value register) 
        .equ TIMER4_CH2CV_CH2VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 2)  
 
    .equ TIMER4_CH3CV, TIMER4_BASE + 0x40 @ (Channel 3 capture/compare value register) 
        .equ TIMER4_CH3CV_CH3VAL_Shift, 0   @ bitWidth 16 (Capture or compare value of channel 3)  
 
    .equ TIMER4_DMACFG, TIMER4_BASE + 0x48 @ (DMA configuration register) 
        .equ TIMER4_DMACFG_DMATC_Shift, 8   @ bitWidth 5 (DMA transfer count)  
        .equ TIMER4_DMACFG_DMATA_Shift, 0   @ bitWidth 5 (DMA transfer access start address)  
 
    .equ TIMER4_DMATB, TIMER4_BASE + 0x4C @ (DMA transfer buffer register) 
        .equ TIMER4_DMATB_DMATB_Shift, 0   @ bitWidth 16 (DMA transfer buffer)  
 

@=========================== TIMER5 ===========================@
.equ TIMER5_BASE, 0x40001000 @ (Basic-timers) 
    .equ TIMER5_CTL0, TIMER5_BASE + 0x0 @ (control register 0) 
        .equ TIMER5_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER5_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER5_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER5_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER5_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER5_CTL1, TIMER5_BASE + 0x04 @ (control register 1) 
        .equ TIMER5_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
 
    .equ TIMER5_DMAINTEN, TIMER5_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER5_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER5_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER5_INTF, TIMER5_BASE + 0x10 @ (Interrupt flag register) 
        .equ TIMER5_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER5_SWEVG, TIMER5_BASE + 0x14 @ (event generation register) 
        .equ TIMER5_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER5_CNT, TIMER5_BASE + 0x24 @ (Counter register) 
        .equ TIMER5_CNT_CNT_Shift, 0   @ bitWidth 16 (Low counter value)  
 
    .equ TIMER5_PSC, TIMER5_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER5_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER5_CAR, TIMER5_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER5_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 

@=========================== TIMER6 ===========================@
.equ TIMER6_BASE, 0x40001400 @ (Basic-timers) 
    .equ TIMER6_CTL0, TIMER6_BASE + 0x0 @ (control register 0) 
        .equ TIMER6_CTL0_ARSE, 1 << 7   @ bitWidth 1 (Auto-reload shadow enable)  
        .equ TIMER6_CTL0_SPM, 1 << 3   @ bitWidth 1 (Single pulse mode)  
        .equ TIMER6_CTL0_UPS, 1 << 2   @ bitWidth 1 (Update source)  
        .equ TIMER6_CTL0_UPDIS, 1 << 1   @ bitWidth 1 (Update disable)  
        .equ TIMER6_CTL0_CEN, 1 << 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIMER6_CTL1, TIMER6_BASE + 0x04 @ (control register 1) 
        .equ TIMER6_CTL1_MMC_Shift, 4   @ bitWidth 3 (Master mode control)  
 
    .equ TIMER6_DMAINTEN, TIMER6_BASE + 0x0C @ (DMA/Interrupt enable register) 
        .equ TIMER6_DMAINTEN_UPDEN, 1 << 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIMER6_DMAINTEN_UPIE, 1 << 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIMER6_INTF, TIMER6_BASE + 0x10 @ (Interrupt flag register) 
        .equ TIMER6_INTF_UPIF, 1 << 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIMER6_SWEVG, TIMER6_BASE + 0x14 @ (event generation register) 
        .equ TIMER6_SWEVG_UPG, 1 << 0   @ bitWidth 1 (Update generation)  
 
    .equ TIMER6_CNT, TIMER6_BASE + 0x24 @ (Counter register) 
        .equ TIMER6_CNT_CNT_Shift, 0   @ bitWidth 16 (Low counter value)  
 
    .equ TIMER6_PSC, TIMER6_BASE + 0x28 @ (Prescaler register) 
        .equ TIMER6_PSC_PSC_Shift, 0   @ bitWidth 16 (Prescaler value of the counter clock)  
 
    .equ TIMER6_CAR, TIMER6_BASE + 0x2C @ (Counter auto reload register) 
        .equ TIMER6_CAR_CARL_Shift, 0   @ bitWidth 16 (Counter auto reload value)  
 

@=========================== USART0 ===========================@
.equ USART0_BASE, 0x40013800 @ (Universal synchronous asynchronous receiver  transmitter) 
    .equ USART0_STAT, USART0_BASE + 0x00 @ (Status register ) 
        .equ USART0_STAT_CTSF, 1 << 9   @ bitWidth 1 (CTS change flag)  
        .equ USART0_STAT_LBDF, 1 << 8   @ bitWidth 1 (LIN break detection flag)  
        .equ USART0_STAT_TBE, 1 << 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ USART0_STAT_TC, 1 << 6   @ bitWidth 1 (Transmission complete)  
        .equ USART0_STAT_RBNE, 1 << 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ USART0_STAT_IDLEF, 1 << 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ USART0_STAT_ORERR, 1 << 3   @ bitWidth 1 (Overrun error)  
        .equ USART0_STAT_NERR, 1 << 2   @ bitWidth 1 (Noise error flag)  
        .equ USART0_STAT_FERR, 1 << 1   @ bitWidth 1 (Frame error flag)  
        .equ USART0_STAT_PERR, 1 << 0   @ bitWidth 1 (Parity error flag)  
 
    .equ USART0_DATA, USART0_BASE + 0x04 @ (Data register) 
        .equ USART0_DATA_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ USART0_BAUD, USART0_BASE + 0x08 @ (Baud rate register) 
        .equ USART0_BAUD_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ USART0_BAUD_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ USART0_CTL0, USART0_BASE + 0x0C @ (Control register 0) 
        .equ USART0_CTL0_UEN, 1 << 13   @ bitWidth 1 (USART enable)  
        .equ USART0_CTL0_WL, 1 << 12   @ bitWidth 1 (Word length)  
        .equ USART0_CTL0_WM, 1 << 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ USART0_CTL0_PCEN, 1 << 10   @ bitWidth 1 (Parity check function enable)  
        .equ USART0_CTL0_PM, 1 << 9   @ bitWidth 1 (Parity mode)  
        .equ USART0_CTL0_PERRIE, 1 << 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ USART0_CTL0_TBEIE, 1 << 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ USART0_CTL0_TCIE, 1 << 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART0_CTL0_RBNEIE, 1 << 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ USART0_CTL0_IDLEIE, 1 << 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ USART0_CTL0_TEN, 1 << 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART0_CTL0_REN, 1 << 2   @ bitWidth 1 (Receiver enable)  
        .equ USART0_CTL0_RWU, 1 << 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ USART0_CTL0_SBKCMD, 1 << 0   @ bitWidth 1 (Send break command)  
 
    .equ USART0_CTL1, USART0_BASE + 0x10 @ (Control register 1) 
        .equ USART0_CTL1_LMEN, 1 << 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART0_CTL1_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ USART0_CTL1_CKEN, 1 << 11   @ bitWidth 1 (CK pin enable)  
        .equ USART0_CTL1_CPL, 1 << 10   @ bitWidth 1 (Clock polarity)  
        .equ USART0_CTL1_CPH, 1 << 9   @ bitWidth 1 (Clock phase)  
        .equ USART0_CTL1_CLEN, 1 << 8   @ bitWidth 1 (CK Length)  
        .equ USART0_CTL1_LBDIE, 1 << 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ USART0_CTL1_LBLEN, 1 << 5   @ bitWidth 1 (LIN break frame length)  
        .equ USART0_CTL1_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ USART0_CTL2, USART0_BASE + 0x14 @ (Control register 2) 
        .equ USART0_CTL2_CTSIE, 1 << 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART0_CTL2_CTSEN, 1 << 9   @ bitWidth 1 (CTS enable)  
        .equ USART0_CTL2_RTSEN, 1 << 8   @ bitWidth 1 (RTS enable)  
        .equ USART0_CTL2_DENT, 1 << 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ USART0_CTL2_DENR, 1 << 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ USART0_CTL2_SCEN, 1 << 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART0_CTL2_NKEN, 1 << 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART0_CTL2_HDEN, 1 << 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART0_CTL2_IRLP, 1 << 2   @ bitWidth 1 (IrDA low-power)  
        .equ USART0_CTL2_IREN, 1 << 1   @ bitWidth 1 (IrDA mode enable)  
        .equ USART0_CTL2_ERRIE, 1 << 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART0_GP, USART0_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ USART0_GP_GUAT_Shift, 8   @ bitWidth 8 (Guard time value in Smartcard mode)  
        .equ USART0_GP_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== USART1 ===========================@
.equ USART1_BASE, 0x40004400 @ (Universal synchronous asynchronous receiver  transmitter) 
    .equ USART1_STAT, USART1_BASE + 0x00 @ (Status register ) 
        .equ USART1_STAT_CTSF, 1 << 9   @ bitWidth 1 (CTS change flag)  
        .equ USART1_STAT_LBDF, 1 << 8   @ bitWidth 1 (LIN break detection flag)  
        .equ USART1_STAT_TBE, 1 << 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ USART1_STAT_TC, 1 << 6   @ bitWidth 1 (Transmission complete)  
        .equ USART1_STAT_RBNE, 1 << 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ USART1_STAT_IDLEF, 1 << 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ USART1_STAT_ORERR, 1 << 3   @ bitWidth 1 (Overrun error)  
        .equ USART1_STAT_NERR, 1 << 2   @ bitWidth 1 (Noise error flag)  
        .equ USART1_STAT_FERR, 1 << 1   @ bitWidth 1 (Frame error flag)  
        .equ USART1_STAT_PERR, 1 << 0   @ bitWidth 1 (Parity error flag)  
 
    .equ USART1_DATA, USART1_BASE + 0x04 @ (Data register) 
        .equ USART1_DATA_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ USART1_BAUD, USART1_BASE + 0x08 @ (Baud rate register) 
        .equ USART1_BAUD_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ USART1_BAUD_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ USART1_CTL0, USART1_BASE + 0x0C @ (Control register 0) 
        .equ USART1_CTL0_UEN, 1 << 13   @ bitWidth 1 (USART enable)  
        .equ USART1_CTL0_WL, 1 << 12   @ bitWidth 1 (Word length)  
        .equ USART1_CTL0_WM, 1 << 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ USART1_CTL0_PCEN, 1 << 10   @ bitWidth 1 (Parity check function enable)  
        .equ USART1_CTL0_PM, 1 << 9   @ bitWidth 1 (Parity mode)  
        .equ USART1_CTL0_PERRIE, 1 << 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ USART1_CTL0_TBEIE, 1 << 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ USART1_CTL0_TCIE, 1 << 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART1_CTL0_RBNEIE, 1 << 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ USART1_CTL0_IDLEIE, 1 << 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ USART1_CTL0_TEN, 1 << 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART1_CTL0_REN, 1 << 2   @ bitWidth 1 (Receiver enable)  
        .equ USART1_CTL0_RWU, 1 << 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ USART1_CTL0_SBKCMD, 1 << 0   @ bitWidth 1 (Send break command)  
 
    .equ USART1_CTL1, USART1_BASE + 0x10 @ (Control register 1) 
        .equ USART1_CTL1_LMEN, 1 << 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART1_CTL1_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ USART1_CTL1_CKEN, 1 << 11   @ bitWidth 1 (CK pin enable)  
        .equ USART1_CTL1_CPL, 1 << 10   @ bitWidth 1 (Clock polarity)  
        .equ USART1_CTL1_CPH, 1 << 9   @ bitWidth 1 (Clock phase)  
        .equ USART1_CTL1_CLEN, 1 << 8   @ bitWidth 1 (CK Length)  
        .equ USART1_CTL1_LBDIE, 1 << 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ USART1_CTL1_LBLEN, 1 << 5   @ bitWidth 1 (LIN break frame length)  
        .equ USART1_CTL1_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ USART1_CTL2, USART1_BASE + 0x14 @ (Control register 2) 
        .equ USART1_CTL2_CTSIE, 1 << 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART1_CTL2_CTSEN, 1 << 9   @ bitWidth 1 (CTS enable)  
        .equ USART1_CTL2_RTSEN, 1 << 8   @ bitWidth 1 (RTS enable)  
        .equ USART1_CTL2_DENT, 1 << 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ USART1_CTL2_DENR, 1 << 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ USART1_CTL2_SCEN, 1 << 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART1_CTL2_NKEN, 1 << 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART1_CTL2_HDEN, 1 << 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART1_CTL2_IRLP, 1 << 2   @ bitWidth 1 (IrDA low-power)  
        .equ USART1_CTL2_IREN, 1 << 1   @ bitWidth 1 (IrDA mode enable)  
        .equ USART1_CTL2_ERRIE, 1 << 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART1_GP, USART1_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ USART1_GP_GUAT_Shift, 8   @ bitWidth 8 (Guard time value in Smartcard mode)  
        .equ USART1_GP_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== USART2 ===========================@
.equ USART2_BASE, 0x40004800 @ (Universal synchronous asynchronous receiver  transmitter) 
    .equ USART2_STAT, USART2_BASE + 0x00 @ (Status register ) 
        .equ USART2_STAT_CTSF, 1 << 9   @ bitWidth 1 (CTS change flag)  
        .equ USART2_STAT_LBDF, 1 << 8   @ bitWidth 1 (LIN break detection flag)  
        .equ USART2_STAT_TBE, 1 << 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ USART2_STAT_TC, 1 << 6   @ bitWidth 1 (Transmission complete)  
        .equ USART2_STAT_RBNE, 1 << 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ USART2_STAT_IDLEF, 1 << 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ USART2_STAT_ORERR, 1 << 3   @ bitWidth 1 (Overrun error)  
        .equ USART2_STAT_NERR, 1 << 2   @ bitWidth 1 (Noise error flag)  
        .equ USART2_STAT_FERR, 1 << 1   @ bitWidth 1 (Frame error flag)  
        .equ USART2_STAT_PERR, 1 << 0   @ bitWidth 1 (Parity error flag)  
 
    .equ USART2_DATA, USART2_BASE + 0x04 @ (Data register) 
        .equ USART2_DATA_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ USART2_BAUD, USART2_BASE + 0x08 @ (Baud rate register) 
        .equ USART2_BAUD_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ USART2_BAUD_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ USART2_CTL0, USART2_BASE + 0x0C @ (Control register 0) 
        .equ USART2_CTL0_UEN, 1 << 13   @ bitWidth 1 (USART enable)  
        .equ USART2_CTL0_WL, 1 << 12   @ bitWidth 1 (Word length)  
        .equ USART2_CTL0_WM, 1 << 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ USART2_CTL0_PCEN, 1 << 10   @ bitWidth 1 (Parity check function enable)  
        .equ USART2_CTL0_PM, 1 << 9   @ bitWidth 1 (Parity mode)  
        .equ USART2_CTL0_PERRIE, 1 << 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ USART2_CTL0_TBEIE, 1 << 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ USART2_CTL0_TCIE, 1 << 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART2_CTL0_RBNEIE, 1 << 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ USART2_CTL0_IDLEIE, 1 << 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ USART2_CTL0_TEN, 1 << 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART2_CTL0_REN, 1 << 2   @ bitWidth 1 (Receiver enable)  
        .equ USART2_CTL0_RWU, 1 << 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ USART2_CTL0_SBKCMD, 1 << 0   @ bitWidth 1 (Send break command)  
 
    .equ USART2_CTL1, USART2_BASE + 0x10 @ (Control register 1) 
        .equ USART2_CTL1_LMEN, 1 << 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART2_CTL1_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ USART2_CTL1_CKEN, 1 << 11   @ bitWidth 1 (CK pin enable)  
        .equ USART2_CTL1_CPL, 1 << 10   @ bitWidth 1 (Clock polarity)  
        .equ USART2_CTL1_CPH, 1 << 9   @ bitWidth 1 (Clock phase)  
        .equ USART2_CTL1_CLEN, 1 << 8   @ bitWidth 1 (CK Length)  
        .equ USART2_CTL1_LBDIE, 1 << 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ USART2_CTL1_LBLEN, 1 << 5   @ bitWidth 1 (LIN break frame length)  
        .equ USART2_CTL1_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ USART2_CTL2, USART2_BASE + 0x14 @ (Control register 2) 
        .equ USART2_CTL2_CTSIE, 1 << 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART2_CTL2_CTSEN, 1 << 9   @ bitWidth 1 (CTS enable)  
        .equ USART2_CTL2_RTSEN, 1 << 8   @ bitWidth 1 (RTS enable)  
        .equ USART2_CTL2_DENT, 1 << 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ USART2_CTL2_DENR, 1 << 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ USART2_CTL2_SCEN, 1 << 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART2_CTL2_NKEN, 1 << 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART2_CTL2_HDEN, 1 << 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART2_CTL2_IRLP, 1 << 2   @ bitWidth 1 (IrDA low-power)  
        .equ USART2_CTL2_IREN, 1 << 1   @ bitWidth 1 (IrDA mode enable)  
        .equ USART2_CTL2_ERRIE, 1 << 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART2_GP, USART2_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ USART2_GP_GUAT_Shift, 8   @ bitWidth 8 (Guard time value in Smartcard mode)  
        .equ USART2_GP_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== UART3 ===========================@
.equ UART3_BASE, 0x40004C00 @ (Universal asynchronous receiver  transmitter) 
    .equ UART3_STAT, UART3_BASE + 0x00 @ (Status register ) 
        .equ UART3_STAT_LBDF, 1 << 8   @ bitWidth 1 (LIN break detection flag)  
        .equ UART3_STAT_TBE, 1 << 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ UART3_STAT_TC, 1 << 6   @ bitWidth 1 (Transmission complete)  
        .equ UART3_STAT_RBNE, 1 << 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ UART3_STAT_IDLEF, 1 << 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ UART3_STAT_ORERR, 1 << 3   @ bitWidth 1 (Overrun error)  
        .equ UART3_STAT_NERR, 1 << 2   @ bitWidth 1 (Noise error flag)  
        .equ UART3_STAT_FERR, 1 << 1   @ bitWidth 1 (Frame error flag)  
        .equ UART3_STAT_PERR, 1 << 0   @ bitWidth 1 (Parity error flag)  
 
    .equ UART3_DATA, UART3_BASE + 0x04 @ (Data register) 
        .equ UART3_DATA_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ UART3_BAUD, UART3_BASE + 0x08 @ (Baud rate register) 
        .equ UART3_BAUD_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ UART3_BAUD_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ UART3_CTL0, UART3_BASE + 0x0C @ (Control register 0) 
        .equ UART3_CTL0_UEN, 1 << 13   @ bitWidth 1 (USART enable)  
        .equ UART3_CTL0_WL, 1 << 12   @ bitWidth 1 (Word length)  
        .equ UART3_CTL0_WM, 1 << 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ UART3_CTL0_PCEN, 1 << 10   @ bitWidth 1 (Parity check function enable)  
        .equ UART3_CTL0_PM, 1 << 9   @ bitWidth 1 (Parity mode)  
        .equ UART3_CTL0_PERRIE, 1 << 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ UART3_CTL0_TBEIE, 1 << 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ UART3_CTL0_TCIE, 1 << 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ UART3_CTL0_RBNEIE, 1 << 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ UART3_CTL0_IDLEIE, 1 << 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ UART3_CTL0_TEN, 1 << 3   @ bitWidth 1 (Transmitter enable)  
        .equ UART3_CTL0_REN, 1 << 2   @ bitWidth 1 (Receiver enable)  
        .equ UART3_CTL0_RWU, 1 << 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ UART3_CTL0_SBKCMD, 1 << 0   @ bitWidth 1 (Send break command)  
 
    .equ UART3_CTL1, UART3_BASE + 0x10 @ (Control register 1) 
        .equ UART3_CTL1_LMEN, 1 << 14   @ bitWidth 1 (LIN mode enable)  
        .equ UART3_CTL1_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ UART3_CTL1_LBDIE, 1 << 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ UART3_CTL1_LBLEN, 1 << 5   @ bitWidth 1 (LIN break frame length)  
        .equ UART3_CTL1_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ UART3_CTL2, UART3_BASE + 0x14 @ (Control register 2) 
        .equ UART3_CTL2_DENT, 1 << 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ UART3_CTL2_DENR, 1 << 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ UART3_CTL2_HDEN, 1 << 3   @ bitWidth 1 (Half-duplex selection)  
        .equ UART3_CTL2_IRLP, 1 << 2   @ bitWidth 1 (IrDA low-power)  
        .equ UART3_CTL2_IREN, 1 << 1   @ bitWidth 1 (IrDA mode enable)  
        .equ UART3_CTL2_ERRIE, 1 << 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ UART3_GP, UART3_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ UART3_GP_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== UART4 ===========================@
.equ UART4_BASE, 0x40005000 @ (Universal asynchronous receiver  transmitter) 
    .equ UART4_STAT, UART4_BASE + 0x00 @ (Status register ) 
        .equ UART4_STAT_LBDF, 1 << 8   @ bitWidth 1 (LIN break detection flag)  
        .equ UART4_STAT_TBE, 1 << 7   @ bitWidth 1 (Transmit data buffer empty)  
        .equ UART4_STAT_TC, 1 << 6   @ bitWidth 1 (Transmission complete)  
        .equ UART4_STAT_RBNE, 1 << 5   @ bitWidth 1 (Read data buffer not empty)  
        .equ UART4_STAT_IDLEF, 1 << 4   @ bitWidth 1 (IDLE frame detected flag)  
        .equ UART4_STAT_ORERR, 1 << 3   @ bitWidth 1 (Overrun error)  
        .equ UART4_STAT_NERR, 1 << 2   @ bitWidth 1 (Noise error flag)  
        .equ UART4_STAT_FERR, 1 << 1   @ bitWidth 1 (Frame error flag)  
        .equ UART4_STAT_PERR, 1 << 0   @ bitWidth 1 (Parity error flag)  
 
    .equ UART4_DATA, UART4_BASE + 0x04 @ (Data register) 
        .equ UART4_DATA_DATA_Shift, 0   @ bitWidth 9 (Transmit or read data value)  
 
    .equ UART4_BAUD, UART4_BASE + 0x08 @ (Baud rate register) 
        .equ UART4_BAUD_INTDIV_Shift, 4   @ bitWidth 12 (Integer part of baud-rate divider)  
        .equ UART4_BAUD_FRADIV_Shift, 0   @ bitWidth 4 (Fraction part of baud-rate divider)  
 
    .equ UART4_CTL0, UART4_BASE + 0x0C @ (Control register 0) 
        .equ UART4_CTL0_UEN, 1 << 13   @ bitWidth 1 (USART enable)  
        .equ UART4_CTL0_WL, 1 << 12   @ bitWidth 1 (Word length)  
        .equ UART4_CTL0_WM, 1 << 11   @ bitWidth 1 (Wakeup method in mute mode)  
        .equ UART4_CTL0_PCEN, 1 << 10   @ bitWidth 1 (Parity check function enable)  
        .equ UART4_CTL0_PM, 1 << 9   @ bitWidth 1 (Parity mode)  
        .equ UART4_CTL0_PERRIE, 1 << 8   @ bitWidth 1 (Parity error interrupt enable)  
        .equ UART4_CTL0_TBEIE, 1 << 7   @ bitWidth 1 (Transmitter buffer empty interrupt enable)  
        .equ UART4_CTL0_TCIE, 1 << 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ UART4_CTL0_RBNEIE, 1 << 5   @ bitWidth 1 (Read data buffer not empty interrupt and overrun error interrupt enable)  
        .equ UART4_CTL0_IDLEIE, 1 << 4   @ bitWidth 1 (IDLE line detected interrupt enable)  
        .equ UART4_CTL0_TEN, 1 << 3   @ bitWidth 1 (Transmitter enable)  
        .equ UART4_CTL0_REN, 1 << 2   @ bitWidth 1 (Receiver enable)  
        .equ UART4_CTL0_RWU, 1 << 1   @ bitWidth 1 (Receiver wakeup from mute mode)  
        .equ UART4_CTL0_SBKCMD, 1 << 0   @ bitWidth 1 (Send break command)  
 
    .equ UART4_CTL1, UART4_BASE + 0x10 @ (Control register 1) 
        .equ UART4_CTL1_LMEN, 1 << 14   @ bitWidth 1 (LIN mode enable)  
        .equ UART4_CTL1_STB_Shift, 12   @ bitWidth 2 (STOP bits length)  
        .equ UART4_CTL1_LBDIE, 1 << 6   @ bitWidth 1 (LIN break detection interrupt  enable)  
        .equ UART4_CTL1_LBLEN, 1 << 5   @ bitWidth 1 (LIN break frame length)  
        .equ UART4_CTL1_ADDR_Shift, 0   @ bitWidth 4 (Address of the USART)  
 
    .equ UART4_CTL2, UART4_BASE + 0x14 @ (Control register 2) 
        .equ UART4_CTL2_DENT, 1 << 7   @ bitWidth 1 (DMA request enable for transmission)  
        .equ UART4_CTL2_DENR, 1 << 6   @ bitWidth 1 (DMA request enable for reception)  
        .equ UART4_CTL2_HDEN, 1 << 3   @ bitWidth 1 (Half-duplex selection)  
        .equ UART4_CTL2_IRLP, 1 << 2   @ bitWidth 1 (IrDA low-power)  
        .equ UART4_CTL2_IREN, 1 << 1   @ bitWidth 1 (IrDA mode enable)  
        .equ UART4_CTL2_ERRIE, 1 << 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ UART4_GP, UART4_BASE + 0x18 @ (Guard time and prescaler  register) 
        .equ UART4_GP_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 

@=========================== USBFS_GLOBAL ===========================@
.equ USBFS_GLOBAL_BASE, 0x50000000 @ (USB full speed global registers) 
    .equ USBFS_GLOBAL_GOTGCS, USBFS_GLOBAL_BASE + 0x0 @ (Global OTG control and status register   USBFS_GOTGCS) 
        .equ USBFS_GLOBAL_GOTGCS_SRPS, 1 << 0   @ bitWidth 1 (SRP success)  
        .equ USBFS_GLOBAL_GOTGCS_SRPREQ, 1 << 1   @ bitWidth 1 (SRP request)  
        .equ USBFS_GLOBAL_GOTGCS_HNPS, 1 << 8   @ bitWidth 1 (Host success)  
        .equ USBFS_GLOBAL_GOTGCS_HNPREQ, 1 << 9   @ bitWidth 1 (HNP request)  
        .equ USBFS_GLOBAL_GOTGCS_HHNPEN, 1 << 10   @ bitWidth 1 (Host HNP enable)  
        .equ USBFS_GLOBAL_GOTGCS_DHNPEN, 1 << 11   @ bitWidth 1 (Device HNP enabled)  
        .equ USBFS_GLOBAL_GOTGCS_IDPS, 1 << 16   @ bitWidth 1 (ID pin status)  
        .equ USBFS_GLOBAL_GOTGCS_DI, 1 << 17   @ bitWidth 1 (Debounce interval)  
        .equ USBFS_GLOBAL_GOTGCS_ASV, 1 << 18   @ bitWidth 1 (A-session valid)  
        .equ USBFS_GLOBAL_GOTGCS_BSV, 1 << 19   @ bitWidth 1 (B-session valid)  
 
    .equ USBFS_GLOBAL_GOTGINTF, USBFS_GLOBAL_BASE + 0x04 @ (Global OTG interrupt flag register  USBFS_GOTGINTF) 
        .equ USBFS_GLOBAL_GOTGINTF_SESEND, 1 << 2   @ bitWidth 1 (Session end )  
        .equ USBFS_GLOBAL_GOTGINTF_SRPEND, 1 << 8   @ bitWidth 1 (Session request success status  change)  
        .equ USBFS_GLOBAL_GOTGINTF_HNPEND, 1 << 9   @ bitWidth 1 (HNP end)  
        .equ USBFS_GLOBAL_GOTGINTF_HNPDET, 1 << 17   @ bitWidth 1 (Host negotiation request detected)  
        .equ USBFS_GLOBAL_GOTGINTF_ADTO, 1 << 18   @ bitWidth 1 (A-device timeout)  
        .equ USBFS_GLOBAL_GOTGINTF_DF, 1 << 19   @ bitWidth 1 (Debounce finish)  
 
    .equ USBFS_GLOBAL_GAHBCS, USBFS_GLOBAL_BASE + 0x08 @ (Global AHB control and status register  USBFS_GAHBCS) 
        .equ USBFS_GLOBAL_GAHBCS_GINTEN, 1 << 0   @ bitWidth 1 (Global interrupt enable)  
        .equ USBFS_GLOBAL_GAHBCS_TXFTH, 1 << 7   @ bitWidth 1 (Tx FIFO threshold)  
        .equ USBFS_GLOBAL_GAHBCS_PTXFTH, 1 << 8   @ bitWidth 1 (Periodic Tx FIFO threshold)  
 
    .equ USBFS_GLOBAL_GUSBCS, USBFS_GLOBAL_BASE + 0x0C @ (Global USB control and status register  USBFS_GUSBCSR) 
        .equ USBFS_GLOBAL_GUSBCS_TOC_Shift, 0   @ bitWidth 3 (Timeout calibration)  
        .equ USBFS_GLOBAL_GUSBCS_SRPCEN, 1 << 8   @ bitWidth 1 (SRP capability enable)  
        .equ USBFS_GLOBAL_GUSBCS_HNPCEN, 1 << 9   @ bitWidth 1 (HNP capability enable)  
        .equ USBFS_GLOBAL_GUSBCS_UTT_Shift, 10   @ bitWidth 4 (USB turnaround time)  
        .equ USBFS_GLOBAL_GUSBCS_FHM, 1 << 29   @ bitWidth 1 (Force host mode)  
        .equ USBFS_GLOBAL_GUSBCS_FDM, 1 << 30   @ bitWidth 1 (Force device mode)  
 
    .equ USBFS_GLOBAL_GRSTCTL, USBFS_GLOBAL_BASE + 0x10 @ (Global reset control register USBFS_GRSTCTL) 
        .equ USBFS_GLOBAL_GRSTCTL_CSRST, 1 << 0   @ bitWidth 1 (Core soft reset)  
        .equ USBFS_GLOBAL_GRSTCTL_HCSRST, 1 << 1   @ bitWidth 1 (HCLK soft reset)  
        .equ USBFS_GLOBAL_GRSTCTL_HFCRST, 1 << 2   @ bitWidth 1 (Host frame counter reset)  
        .equ USBFS_GLOBAL_GRSTCTL_RXFF, 1 << 4   @ bitWidth 1 (RxFIFO flush)  
        .equ USBFS_GLOBAL_GRSTCTL_TXFF, 1 << 5   @ bitWidth 1 (TxFIFO flush)  
        .equ USBFS_GLOBAL_GRSTCTL_TXFNUM_Shift, 6   @ bitWidth 5 (TxFIFO number)  
 
    .equ USBFS_GLOBAL_GINTF, USBFS_GLOBAL_BASE + 0x14 @ (Global interrupt flag register USBFS_GINTF) 
        .equ USBFS_GLOBAL_GINTF_COPM, 1 << 0   @ bitWidth 1 (Current operation mode)  
        .equ USBFS_GLOBAL_GINTF_MFIF, 1 << 1   @ bitWidth 1 (Mode fault interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_OTGIF, 1 << 2   @ bitWidth 1 (OTG interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_SOF, 1 << 3   @ bitWidth 1 (Start of frame)  
        .equ USBFS_GLOBAL_GINTF_RXFNEIF, 1 << 4   @ bitWidth 1 (RxFIFO non-empty interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_NPTXFEIF, 1 << 5   @ bitWidth 1 (Non-periodic TxFIFO empty interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_GNPINAK, 1 << 6   @ bitWidth 1 (Global Non-Periodic IN NAK effective)  
        .equ USBFS_GLOBAL_GINTF_GONAK, 1 << 7   @ bitWidth 1 (Global OUT NAK effective)  
        .equ USBFS_GLOBAL_GINTF_ESP, 1 << 10   @ bitWidth 1 (Early suspend)  
        .equ USBFS_GLOBAL_GINTF_SP, 1 << 11   @ bitWidth 1 (USB suspend)  
        .equ USBFS_GLOBAL_GINTF_RST, 1 << 12   @ bitWidth 1 (USB reset)  
        .equ USBFS_GLOBAL_GINTF_ENUMF, 1 << 13   @ bitWidth 1 (Enumeration finished)  
        .equ USBFS_GLOBAL_GINTF_ISOOPDIF, 1 << 14   @ bitWidth 1 (Isochronous OUT packet dropped  interrupt)  
        .equ USBFS_GLOBAL_GINTF_EOPFIF, 1 << 15   @ bitWidth 1 (End of periodic frame  interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_IEPIF, 1 << 18   @ bitWidth 1 (IN endpoint interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_OEPIF, 1 << 19   @ bitWidth 1 (OUT endpoint interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_ISOINCIF, 1 << 20   @ bitWidth 1 (Isochronous IN transfer Not Complete Interrupt Flag)  
        .equ USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF, 1 << 21   @ bitWidth 1 (periodic transfer not complete interrupt flagHost  mode/isochronous OUT transfer not complete interrupt flagDevice  mode)  
        .equ USBFS_GLOBAL_GINTF_HPIF, 1 << 24   @ bitWidth 1 (Host port interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_HCIF, 1 << 25   @ bitWidth 1 (Host channels interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_PTXFEIF, 1 << 26   @ bitWidth 1 (Periodic TxFIFO empty interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_IDPSC, 1 << 28   @ bitWidth 1 (ID pin status change)  
        .equ USBFS_GLOBAL_GINTF_DISCIF, 1 << 29   @ bitWidth 1 (Disconnect interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_SESIF, 1 << 30   @ bitWidth 1 (Session interrupt flag)  
        .equ USBFS_GLOBAL_GINTF_WKUPIF, 1 << 31   @ bitWidth 1 (Wakeup interrupt flag)  
 
    .equ USBFS_GLOBAL_GINTEN, USBFS_GLOBAL_BASE + 0x18 @ (Global interrupt enable register  USBFS_GINTEN) 
        .equ USBFS_GLOBAL_GINTEN_MFIE, 1 << 1   @ bitWidth 1 (Mode fault interrupt  enable)  
        .equ USBFS_GLOBAL_GINTEN_OTGIE, 1 << 2   @ bitWidth 1 (OTG interrupt enable )  
        .equ USBFS_GLOBAL_GINTEN_SOFIE, 1 << 3   @ bitWidth 1 (Start of frame interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_RXFNEIE, 1 << 4   @ bitWidth 1 (Receive FIFO non-empty  interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_NPTXFEIE, 1 << 5   @ bitWidth 1 (Non-periodic TxFIFO empty  interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_GNPINAKIE, 1 << 6   @ bitWidth 1 (Global non-periodic IN NAK effective interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_GONAKIE, 1 << 7   @ bitWidth 1 (Global OUT NAK effective  interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_ESPIE, 1 << 10   @ bitWidth 1 (Early suspend interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_SPIE, 1 << 11   @ bitWidth 1 (USB suspend interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_RSTIE, 1 << 12   @ bitWidth 1 (USB reset interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_ENUMFIE, 1 << 13   @ bitWidth 1 (Enumeration finish interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_ISOOPDIE, 1 << 14   @ bitWidth 1 (Isochronous OUT packet dropped interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_EOPFIE, 1 << 15   @ bitWidth 1 (End of periodic frame interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_IEPIE, 1 << 18   @ bitWidth 1 (IN endpoints interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_OEPIE, 1 << 19   @ bitWidth 1 (OUT endpoints interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_ISOINCIE, 1 << 20   @ bitWidth 1 (isochronous IN transfer not complete  interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE, 1 << 21   @ bitWidth 1 (periodic transfer not compelete Interrupt enableHost  mode/isochronous OUT transfer not complete interrupt enableDevice  mode)  
        .equ USBFS_GLOBAL_GINTEN_HPIE, 1 << 24   @ bitWidth 1 (Host port interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_HCIE, 1 << 25   @ bitWidth 1 (Host channels interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_PTXFEIE, 1 << 26   @ bitWidth 1 (Periodic TxFIFO empty interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_IDPSCIE, 1 << 28   @ bitWidth 1 (ID pin status change interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_DISCIE, 1 << 29   @ bitWidth 1 (Disconnect interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_SESIE, 1 << 30   @ bitWidth 1 (Session interrupt enable)  
        .equ USBFS_GLOBAL_GINTEN_WKUPIE, 1 << 31   @ bitWidth 1 (Wakeup interrupt enable)  
 
    .equ USBFS_GLOBAL_GRSTATR_Device, USBFS_GLOBAL_BASE + 0x1C @ (Global Receive status readDevice  mode) 
        .equ USBFS_GLOBAL_GRSTATR_Device_EPNUM_Shift, 0   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_GLOBAL_GRSTATR_Device_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_GRSTATR_Device_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_GRSTATR_Device_RPCKST_Shift, 17   @ bitWidth 4 (Recieve packet status)  
 
    .equ USBFS_GLOBAL_GRSTATR_Host, USBFS_GLOBAL_BASE + 0x1C @ (Global Receive status readHost  mode) 
        .equ USBFS_GLOBAL_GRSTATR_Host_CNUM_Shift, 0   @ bitWidth 4 (Channel number)  
        .equ USBFS_GLOBAL_GRSTATR_Host_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_GRSTATR_Host_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_GRSTATR_Host_RPCKST_Shift, 17   @ bitWidth 4 (Reivece packet status)  
 
    .equ USBFS_GLOBAL_GRSTATP_Device, USBFS_GLOBAL_BASE + 0x20 @ (Global Receive status popDevice  mode) 
        .equ USBFS_GLOBAL_GRSTATP_Device_EPNUM_Shift, 0   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_GLOBAL_GRSTATP_Device_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_GRSTATP_Device_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_GRSTATP_Device_RPCKST_Shift, 17   @ bitWidth 4 (Recieve packet status)  
 
    .equ USBFS_GLOBAL_GRSTATP_Host, USBFS_GLOBAL_BASE + 0x20 @ (Global Receive status popHost  mode) 
        .equ USBFS_GLOBAL_GRSTATP_Host_CNUM_Shift, 0   @ bitWidth 4 (Channel number)  
        .equ USBFS_GLOBAL_GRSTATP_Host_BCOUNT_Shift, 4   @ bitWidth 11 (Byte count)  
        .equ USBFS_GLOBAL_GRSTATP_Host_DPID_Shift, 15   @ bitWidth 2 (Data PID)  
        .equ USBFS_GLOBAL_GRSTATP_Host_RPCKST_Shift, 17   @ bitWidth 4 (Reivece packet status)  
 
    .equ USBFS_GLOBAL_GRFLEN, USBFS_GLOBAL_BASE + 0x24 @ (Global Receive FIFO size register  USBFS_GRFLEN) 
        .equ USBFS_GLOBAL_GRFLEN_RXFD_Shift, 0   @ bitWidth 16 (Rx FIFO depth)  
 
    .equ USBFS_GLOBAL_HNPTFLEN, USBFS_GLOBAL_BASE + 0x28 @ (Host non-periodic transmit FIFO length register  Host mode) 
        .equ USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR_Shift, 0   @ bitWidth 16 (host non-periodic transmit Tx RAM start  address)  
        .equ USBFS_GLOBAL_HNPTFLEN_HNPTXFD_Shift, 16   @ bitWidth 16 (host non-periodic TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP0TFLEN, USBFS_GLOBAL_BASE + 0x28 @ (Device IN endpoint 0 transmit FIFO length  Device mode) 
        .equ USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD_Shift, 16   @ bitWidth 16 (in endpoint 0 Tx FIFO depth)  
        .equ USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR_Shift, 0   @ bitWidth 16 (in endpoint 0 Tx RAM start address)  
 
    .equ USBFS_GLOBAL_HNPTFQSTAT, USBFS_GLOBAL_BASE + 0x2C @ (Host non-periodic transmit FIFO/queue  status register HNPTFQSTAT) 
        .equ USBFS_GLOBAL_HNPTFQSTAT_NPTXFS_Shift, 0   @ bitWidth 16 (Non-periodic TxFIFO space)  
        .equ USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS_Shift, 16   @ bitWidth 8 (Non-periodic transmit request queue  space )  
        .equ USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP_Shift, 24   @ bitWidth 7 (Top of the non-periodic transmit request  queue)  
 
    .equ USBFS_GLOBAL_GCCFG, USBFS_GLOBAL_BASE + 0x38 @ (Global core configuration register USBFS_GCCFG) 
        .equ USBFS_GLOBAL_GCCFG_PWRON, 1 << 16   @ bitWidth 1 (Power on)  
        .equ USBFS_GLOBAL_GCCFG_VBUSACEN, 1 << 18   @ bitWidth 1 (The VBUS A-device Comparer enable)  
        .equ USBFS_GLOBAL_GCCFG_VBUSBCEN, 1 << 19   @ bitWidth 1 (The VBUS B-device Comparer enable)  
        .equ USBFS_GLOBAL_GCCFG_SOFOEN, 1 << 20   @ bitWidth 1 (SOF output enable)  
        .equ USBFS_GLOBAL_GCCFG_VBUSIG, 1 << 21   @ bitWidth 1 (VBUS ignored)  
 
    .equ USBFS_GLOBAL_CID, USBFS_GLOBAL_BASE + 0x3C @ (core ID register) 
        .equ USBFS_GLOBAL_CID_CID_Shift, 0   @ bitWidth 32 (Core ID)  
 
    .equ USBFS_GLOBAL_HPTFLEN, USBFS_GLOBAL_BASE + 0x100 @ (Host periodic transmit FIFO length register HPTFLEN) 
        .equ USBFS_GLOBAL_HPTFLEN_HPTXFSAR_Shift, 0   @ bitWidth 16 (Host periodic TxFIFO start  address)  
        .equ USBFS_GLOBAL_HPTFLEN_HPTXFD_Shift, 16   @ bitWidth 16 (Host periodic TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP1TFLEN, USBFS_GLOBAL_BASE + 0x104 @ (device IN endpoint transmit FIFO size  register DIEP1TFLEN) 
        .equ USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR_Shift, 0   @ bitWidth 16 (IN endpoint FIFO transmit RAM start  address)  
        .equ USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD_Shift, 16   @ bitWidth 16 (IN endpoint TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP2TFLEN, USBFS_GLOBAL_BASE + 0x108 @ (device IN endpoint transmit FIFO size  register DIEP2TFLEN) 
        .equ USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR_Shift, 0   @ bitWidth 16 (IN endpoint FIFO transmit RAM start  address)  
        .equ USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD_Shift, 16   @ bitWidth 16 (IN endpoint TxFIFO depth)  
 
    .equ USBFS_GLOBAL_DIEP3TFLEN, USBFS_GLOBAL_BASE + 0x10C @ (device IN endpoint transmit FIFO size  register FS_DIEP3TXFLEN) 
        .equ USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR_Shift, 0   @ bitWidth 16 (IN endpoint FIFO4 transmit RAM start  address)  
        .equ USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD_Shift, 16   @ bitWidth 16 (IN endpoint TxFIFO depth)  
 

@=========================== USBFS_HOST ===========================@
.equ USBFS_HOST_BASE, 0x50000400 @ (USB on the go full speed host) 
    .equ USBFS_HOST_HCTL, USBFS_HOST_BASE + 0x00 @ (host configuration register  HCTL) 
        .equ USBFS_HOST_HCTL_CLKSEL_Shift, 0   @ bitWidth 2 (clock select for USB clock)  
 
    .equ USBFS_HOST_HFT, USBFS_HOST_BASE + 0x04 @ (Host frame interval  register) 
        .equ USBFS_HOST_HFT_FRI_Shift, 0   @ bitWidth 16 (Frame interval)  
 
    .equ USBFS_HOST_HFINFR, USBFS_HOST_BASE + 0x08 @ (FS host frame number/frame time  remaining register HFINFR) 
        .equ USBFS_HOST_HFINFR_FRNUM_Shift, 0   @ bitWidth 16 (Frame number)  
        .equ USBFS_HOST_HFINFR_FRT_Shift, 16   @ bitWidth 16 (Frame remaining time)  
 
    .equ USBFS_HOST_HPTFQSTAT, USBFS_HOST_BASE + 0x10 @ (Host periodic transmit FIFO/queue  status register HPTFQSTAT) 
        .equ USBFS_HOST_HPTFQSTAT_PTXFS_Shift, 0   @ bitWidth 16 (Periodic transmit data FIFO space  available)  
        .equ USBFS_HOST_HPTFQSTAT_PTXREQS_Shift, 16   @ bitWidth 8 (Periodic transmit request queue space  available)  
        .equ USBFS_HOST_HPTFQSTAT_PTXREQT_Shift, 24   @ bitWidth 8 (Top of the periodic transmit request  queue)  
 
    .equ USBFS_HOST_HACHINT, USBFS_HOST_BASE + 0x14 @ ( Host all channels interrupt  register) 
        .equ USBFS_HOST_HACHINT_HACHINT_Shift, 0   @ bitWidth 8 (Host all channel interrupts)  
 
    .equ USBFS_HOST_HACHINTEN, USBFS_HOST_BASE + 0x18 @ (host all channels interrupt mask  register) 
        .equ USBFS_HOST_HACHINTEN_CINTEN_Shift, 0   @ bitWidth 8 (Channel interrupt enable)  
 
    .equ USBFS_HOST_HPCS, USBFS_HOST_BASE + 0x40 @ (Host port control and status register USBFS_HPCS) 
        .equ USBFS_HOST_HPCS_PCST, 1 << 0   @ bitWidth 1 (Port connect status)  
        .equ USBFS_HOST_HPCS_PCD, 1 << 1   @ bitWidth 1 (Port connect detected)  
        .equ USBFS_HOST_HPCS_PE, 1 << 2   @ bitWidth 1 (Port enable)  
        .equ USBFS_HOST_HPCS_PEDC, 1 << 3   @ bitWidth 1 (Port enable/disable change)  
        .equ USBFS_HOST_HPCS_PREM, 1 << 6   @ bitWidth 1 (Port resume)  
        .equ USBFS_HOST_HPCS_PSP, 1 << 7   @ bitWidth 1 (Port suspend)  
        .equ USBFS_HOST_HPCS_PRST, 1 << 8   @ bitWidth 1 (Port reset)  
        .equ USBFS_HOST_HPCS_PLST_Shift, 10   @ bitWidth 2 (Port line status)  
        .equ USBFS_HOST_HPCS_PP, 1 << 12   @ bitWidth 1 (Port power)  
        .equ USBFS_HOST_HPCS_PS_Shift, 17   @ bitWidth 2 (Port speed)  
 
    .equ USBFS_HOST_HCH0CTL, USBFS_HOST_BASE + 0x100 @ (host channel-0 characteristics  register HCH0CTL) 
        .equ USBFS_HOST_HCH0CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH0CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH0CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH0CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH0CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH0CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH0CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH0CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH0CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH1CTL, USBFS_HOST_BASE + 0x120 @ ( host channel-1 characteristics  register HCH1CTL) 
        .equ USBFS_HOST_HCH1CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH1CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH1CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH1CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH1CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH1CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH1CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH1CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH1CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH2CTL, USBFS_HOST_BASE + 0x140 @ (host channel-2 characteristics  register HCH2CTL) 
        .equ USBFS_HOST_HCH2CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH2CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH2CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH2CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH2CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH2CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH2CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH2CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH2CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH3CTL, USBFS_HOST_BASE + 0x160 @ (host channel-3 characteristics  register HCH3CTL) 
        .equ USBFS_HOST_HCH3CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH3CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH3CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH3CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH3CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH3CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH3CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH3CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH3CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH4CTL, USBFS_HOST_BASE + 0x180 @ ( host channel-4 characteristics  register HCH4CTL) 
        .equ USBFS_HOST_HCH4CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH4CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH4CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH4CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH4CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH4CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH4CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH4CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH4CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH5CTL, USBFS_HOST_BASE + 0x1A0 @ (host channel-5 characteristics  register HCH5CTL) 
        .equ USBFS_HOST_HCH5CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH5CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH5CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH5CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH5CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH5CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH5CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH5CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH5CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH6CTL, USBFS_HOST_BASE + 0x1C0 @ (host channel-6 characteristics  register HCH6CTL) 
        .equ USBFS_HOST_HCH6CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH6CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH6CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH6CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH6CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH6CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH6CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH6CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH6CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH7CTL, USBFS_HOST_BASE + 0x1E0 @ (host channel-7 characteristics  register HCH7CTL) 
        .equ USBFS_HOST_HCH7CTL_MPL_Shift, 0   @ bitWidth 11 (Maximum packet size)  
        .equ USBFS_HOST_HCH7CTL_EPNUM_Shift, 11   @ bitWidth 4 (Endpoint number)  
        .equ USBFS_HOST_HCH7CTL_EPDIR, 1 << 15   @ bitWidth 1 (Endpoint direction)  
        .equ USBFS_HOST_HCH7CTL_LSD, 1 << 17   @ bitWidth 1 (Low-speed device)  
        .equ USBFS_HOST_HCH7CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_HOST_HCH7CTL_DAR_Shift, 22   @ bitWidth 7 (Device address)  
        .equ USBFS_HOST_HCH7CTL_ODDFRM, 1 << 29   @ bitWidth 1 (Odd frame)  
        .equ USBFS_HOST_HCH7CTL_CDIS, 1 << 30   @ bitWidth 1 (Channel disable)  
        .equ USBFS_HOST_HCH7CTL_CEN, 1 << 31   @ bitWidth 1 (Channel enable)  
 
    .equ USBFS_HOST_HCH0INTF, USBFS_HOST_BASE + 0x108 @ (host channel-0 interrupt register  USBFS_HCHxINTF) 
        .equ USBFS_HOST_HCH0INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH0INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH0INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH0INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH0INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH0INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH0INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH0INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH0INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH1INTF, USBFS_HOST_BASE + 0x128 @ (host channel-1 interrupt register  HCH1INTF) 
        .equ USBFS_HOST_HCH1INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH1INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH1INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH1INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH1INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH1INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH1INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH1INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH1INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH2INTF, USBFS_HOST_BASE + 0x148 @ (host channel-2 interrupt register  HCH2INTF) 
        .equ USBFS_HOST_HCH2INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH2INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH2INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH2INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH2INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH2INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH2INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH2INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH2INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH3INTF, USBFS_HOST_BASE + 0x168 @ (host channel-3 interrupt register  HCH3INTF) 
        .equ USBFS_HOST_HCH3INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH3INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH3INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH3INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH3INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH3INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH3INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH3INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH3INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH4INTF, USBFS_HOST_BASE + 0x188 @ (host channel-4 interrupt register  HCH4INTF) 
        .equ USBFS_HOST_HCH4INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH4INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH4INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH4INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH4INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH4INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH4INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH4INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH4INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH5INTF, USBFS_HOST_BASE + 0x1A8 @ (host channel-5 interrupt register  HCH5INTF) 
        .equ USBFS_HOST_HCH5INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH5INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH5INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH5INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH5INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH5INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH5INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH5INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH5INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH6INTF, USBFS_HOST_BASE + 0x1C8 @ (host channel-6 interrupt register  HCH6INTF) 
        .equ USBFS_HOST_HCH6INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH6INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH6INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH6INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH6INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH6INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH6INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH6INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH6INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH7INTF, USBFS_HOST_BASE + 0x1E8 @ (host channel-7 interrupt register  HCH7INTF) 
        .equ USBFS_HOST_HCH7INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
        .equ USBFS_HOST_HCH7INTF_CH, 1 << 1   @ bitWidth 1 (Channel halted)  
        .equ USBFS_HOST_HCH7INTF_STALL, 1 << 3   @ bitWidth 1 (STALL response received  interrupt)  
        .equ USBFS_HOST_HCH7INTF_NAK, 1 << 4   @ bitWidth 1 (NAK response received  interrupt)  
        .equ USBFS_HOST_HCH7INTF_ACK, 1 << 5   @ bitWidth 1 (ACK response received/transmitted  interrupt)  
        .equ USBFS_HOST_HCH7INTF_USBER, 1 << 7   @ bitWidth 1 (USB bus error)  
        .equ USBFS_HOST_HCH7INTF_BBER, 1 << 8   @ bitWidth 1 (Babble error)  
        .equ USBFS_HOST_HCH7INTF_REQOVR, 1 << 9   @ bitWidth 1 (Request queue overrun)  
        .equ USBFS_HOST_HCH7INTF_DTER, 1 << 10   @ bitWidth 1 (Data toggle error)  
 
    .equ USBFS_HOST_HCH0INTEN, USBFS_HOST_BASE + 0x10C @ (host channel-0 interrupt enable register  HCH0INTEN) 
        .equ USBFS_HOST_HCH0INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH0INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH1INTEN, USBFS_HOST_BASE + 0x12C @ (host channel-1 interrupt enable register  HCH1INTEN) 
        .equ USBFS_HOST_HCH1INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH1INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH2INTEN, USBFS_HOST_BASE + 0x14C @ (host channel-2 interrupt enable register  HCH2INTEN) 
        .equ USBFS_HOST_HCH2INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH2INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH3INTEN, USBFS_HOST_BASE + 0x16C @ (host channel-3 interrupt enable register  HCH3INTEN) 
        .equ USBFS_HOST_HCH3INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH3INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH4INTEN, USBFS_HOST_BASE + 0x18C @ (host channel-4 interrupt enable register  HCH4INTEN) 
        .equ USBFS_HOST_HCH4INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH4INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH5INTEN, USBFS_HOST_BASE + 0x1AC @ (host channel-5 interrupt enable register  HCH5INTEN) 
        .equ USBFS_HOST_HCH5INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH5INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH6INTEN, USBFS_HOST_BASE + 0x1CC @ (host channel-6 interrupt enable register  HCH6INTEN) 
        .equ USBFS_HOST_HCH6INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH6INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH7INTEN, USBFS_HOST_BASE + 0x1EC @ (host channel-7 interrupt enable register  HCH7INTEN) 
        .equ USBFS_HOST_HCH7INTEN_TFIE, 1 << 0   @ bitWidth 1 (Transfer completed interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_CHIE, 1 << 1   @ bitWidth 1 (Channel halted interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_STALLIE, 1 << 3   @ bitWidth 1 (STALL interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_NAKIE, 1 << 4   @ bitWidth 1 (NAK interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_ACKIE, 1 << 5   @ bitWidth 1 (ACK interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_USBERIE, 1 << 7   @ bitWidth 1 (USB bus error interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_BBERIE, 1 << 8   @ bitWidth 1 (Babble error interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_REQOVRIE, 1 << 9   @ bitWidth 1 (request queue overrun interrupt enable)  
        .equ USBFS_HOST_HCH7INTEN_DTERIE, 1 << 10   @ bitWidth 1 (Data toggle error interrupt enable)  
 
    .equ USBFS_HOST_HCH0LEN, USBFS_HOST_BASE + 0x110 @ (host channel-0 transfer length  register) 
        .equ USBFS_HOST_HCH0LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH0LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH0LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH1LEN, USBFS_HOST_BASE + 0x130 @ (host channel-1 transfer length  register) 
        .equ USBFS_HOST_HCH1LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH1LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH1LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH2LEN, USBFS_HOST_BASE + 0x150 @ ( host channel-2 transfer length  register) 
        .equ USBFS_HOST_HCH2LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH2LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH2LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH3LEN, USBFS_HOST_BASE + 0x170 @ ( host channel-3 transfer length  register) 
        .equ USBFS_HOST_HCH3LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH3LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH3LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH4LEN, USBFS_HOST_BASE + 0x190 @ (host channel-4 transfer length  register) 
        .equ USBFS_HOST_HCH4LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH4LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH4LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH5LEN, USBFS_HOST_BASE + 0x1B0 @ (host channel-5 transfer length  register) 
        .equ USBFS_HOST_HCH5LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH5LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH5LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH6LEN, USBFS_HOST_BASE + 0x1D0 @ (host channel-6 transfer length  register) 
        .equ USBFS_HOST_HCH6LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH6LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH6LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 
    .equ USBFS_HOST_HCH7LEN, USBFS_HOST_BASE + 0x1F0 @ (host channel-7 transfer length  register) 
        .equ USBFS_HOST_HCH7LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
        .equ USBFS_HOST_HCH7LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_HOST_HCH7LEN_DPID_Shift, 29   @ bitWidth 2 (Data PID)  
 

@=========================== USBFS_DEVICE ===========================@
.equ USBFS_DEVICE_BASE, 0x50000800 @ (USB on the go full speed device) 
    .equ USBFS_DEVICE_DCFG, USBFS_DEVICE_BASE + 0x0 @ (device configuration register  DCFG) 
        .equ USBFS_DEVICE_DCFG_DS_Shift, 0   @ bitWidth 2 (Device speed)  
        .equ USBFS_DEVICE_DCFG_NZLSOH, 1 << 2   @ bitWidth 1 (Non-zero-length status OUT  handshake)  
        .equ USBFS_DEVICE_DCFG_DAR_Shift, 4   @ bitWidth 7 (Device address)  
        .equ USBFS_DEVICE_DCFG_EOPFT_Shift, 11   @ bitWidth 2 (end of periodic frame time)  
 
    .equ USBFS_DEVICE_DCTL, USBFS_DEVICE_BASE + 0x04 @ (device control register  DCTL) 
        .equ USBFS_DEVICE_DCTL_RWKUP, 1 << 0   @ bitWidth 1 (Remote wakeup)  
        .equ USBFS_DEVICE_DCTL_SD, 1 << 1   @ bitWidth 1 (Soft disconnect)  
        .equ USBFS_DEVICE_DCTL_GINS, 1 << 2   @ bitWidth 1 (Global IN NAK status)  
        .equ USBFS_DEVICE_DCTL_GONS, 1 << 3   @ bitWidth 1 (Global OUT NAK status)  
        .equ USBFS_DEVICE_DCTL_SGINAK, 1 << 7   @ bitWidth 1 (Set global IN NAK)  
        .equ USBFS_DEVICE_DCTL_CGINAK, 1 << 8   @ bitWidth 1 (Clear global IN NAK)  
        .equ USBFS_DEVICE_DCTL_SGONAK, 1 << 9   @ bitWidth 1 (Set global OUT NAK)  
        .equ USBFS_DEVICE_DCTL_CGONAK, 1 << 10   @ bitWidth 1 (Clear global OUT NAK)  
        .equ USBFS_DEVICE_DCTL_POIF, 1 << 11   @ bitWidth 1 (Power-on initialization flag)  
 
    .equ USBFS_DEVICE_DSTAT, USBFS_DEVICE_BASE + 0x08 @ (device status register  DSTAT) 
        .equ USBFS_DEVICE_DSTAT_SPST, 1 << 0   @ bitWidth 1 (Suspend status)  
        .equ USBFS_DEVICE_DSTAT_ES_Shift, 1   @ bitWidth 2 (Enumerated speed)  
        .equ USBFS_DEVICE_DSTAT_FNRSOF_Shift, 8   @ bitWidth 14 (Frame number of the received  SOF)  
 
    .equ USBFS_DEVICE_DIEPINTEN, USBFS_DEVICE_BASE + 0x10 @ (device IN endpoint common interrupt  mask register DIEPINTEN) 
        .equ USBFS_DEVICE_DIEPINTEN_TFEN, 1 << 0   @ bitWidth 1 (Transfer finished interrupt  enable)  
        .equ USBFS_DEVICE_DIEPINTEN_EPDISEN, 1 << 1   @ bitWidth 1 (Endpoint disabled interrupt  enable)  
        .equ USBFS_DEVICE_DIEPINTEN_CITOEN, 1 << 3   @ bitWidth 1 (Control IN timeout condition interrupt enable Non-isochronous  endpoints)  
        .equ USBFS_DEVICE_DIEPINTEN_EPTXFUDEN, 1 << 4   @ bitWidth 1 (Endpoint Tx FIFO underrun interrupt enable bit)  
        .equ USBFS_DEVICE_DIEPINTEN_IEPNEEN, 1 << 6   @ bitWidth 1 (IN endpoint NAK effective  interrupt enable)  
 
    .equ USBFS_DEVICE_DOEPINTEN, USBFS_DEVICE_BASE + 0x14 @ (device OUT endpoint common interrupt  enable register DOEPINTEN) 
        .equ USBFS_DEVICE_DOEPINTEN_TFEN, 1 << 0   @ bitWidth 1 (Transfer finished interrupt  enable)  
        .equ USBFS_DEVICE_DOEPINTEN_EPDISEN, 1 << 1   @ bitWidth 1 (Endpoint disabled interrupt  enable)  
        .equ USBFS_DEVICE_DOEPINTEN_STPFEN, 1 << 3   @ bitWidth 1 (SETUP phase finished interrupt enable)  
        .equ USBFS_DEVICE_DOEPINTEN_EPRXFOVREN, 1 << 4   @ bitWidth 1 ( Endpoint Rx FIFO overrun interrupt enable)  
        .equ USBFS_DEVICE_DOEPINTEN_BTBSTPEN, 1 << 6   @ bitWidth 1 ( Back-to-back SETUP packets  interrupt enable)  
 
    .equ USBFS_DEVICE_DAEPINT, USBFS_DEVICE_BASE + 0x18 @ (device all endpoints interrupt  register DAEPINT) 
        .equ USBFS_DEVICE_DAEPINT_IEPITB_Shift, 0   @ bitWidth 4 (Device all IN endpoint interrupt bits)  
        .equ USBFS_DEVICE_DAEPINT_OEPITB_Shift, 16   @ bitWidth 4 (Device all OUT endpoint interrupt bits)  
 
    .equ USBFS_DEVICE_DAEPINTEN, USBFS_DEVICE_BASE + 0x1C @ (Device all endpoints interrupt enable register  DAEPINTEN) 
        .equ USBFS_DEVICE_DAEPINTEN_IEPIE_Shift, 0   @ bitWidth 4 (IN EP interrupt interrupt enable bits)  
        .equ USBFS_DEVICE_DAEPINTEN_OEPIE_Shift, 16   @ bitWidth 4 (OUT endpoint interrupt enable bits)  
 
    .equ USBFS_DEVICE_DVBUSDT, USBFS_DEVICE_BASE + 0x28 @ (device VBUS discharge time  register) 
        .equ USBFS_DEVICE_DVBUSDT_DVBUSDT_Shift, 0   @ bitWidth 16 (Device VBUS discharge time)  
 
    .equ USBFS_DEVICE_DVBUSPT, USBFS_DEVICE_BASE + 0x2C @ (device VBUS pulsing time  register) 
        .equ USBFS_DEVICE_DVBUSPT_DVBUSPT_Shift, 0   @ bitWidth 12 (Device VBUS pulsing time)  
 
    .equ USBFS_DEVICE_DIEPFEINTEN, USBFS_DEVICE_BASE + 0x34 @ (device IN endpoint FIFO empty  interrupt enable register) 
        .equ USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE_Shift, 0   @ bitWidth 4 (IN EP Tx FIFO empty interrupt enable  bits)  
 
    .equ USBFS_DEVICE_DIEP0CTL, USBFS_DEVICE_BASE + 0x100 @ (device IN endpoint 0 control  register DIEP0CTL) 
        .equ USBFS_DEVICE_DIEP0CTL_MPL_Shift, 0   @ bitWidth 2 (Maximum packet length)  
        .equ USBFS_DEVICE_DIEP0CTL_EPACT, 1 << 15   @ bitWidth 1 (endpoint active)  
        .equ USBFS_DEVICE_DIEP0CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DIEP0CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DIEP0CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DIEP0CTL_TXFNUM_Shift, 22   @ bitWidth 4 (TxFIFO number)  
        .equ USBFS_DEVICE_DIEP0CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DIEP0CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DIEP0CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DIEP0CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
 
    .equ USBFS_DEVICE_DIEP1CTL, USBFS_DEVICE_BASE + 0x120 @ (device in endpoint-1 control  register) 
        .equ USBFS_DEVICE_DIEP1CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DIEP1CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM, 1 << 29   @ bitWidth 1 (Set DATA1 PID/Set odd frame)  
        .equ USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM, 1 << 28   @ bitWidth 1 (SD0PID/SEVNFRM)  
        .equ USBFS_DEVICE_DIEP1CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DIEP1CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DIEP1CTL_TXFNUM_Shift, 22   @ bitWidth 4 (Tx FIFO number)  
        .equ USBFS_DEVICE_DIEP1CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DIEP1CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DIEP1CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DIEP1CTL_EOFRM_DPID, 1 << 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_DIEP1CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DIEP1CTL_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DIEP2CTL, USBFS_DEVICE_BASE + 0x140 @ (device endpoint-2 control  register) 
        .equ USBFS_DEVICE_DIEP2CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DIEP2CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM, 1 << 29   @ bitWidth 1 (Set DATA1 PID/Set odd frame)  
        .equ USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM, 1 << 28   @ bitWidth 1 (SD0PID/SEVNFRM)  
        .equ USBFS_DEVICE_DIEP2CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DIEP2CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DIEP2CTL_TXFNUM_Shift, 22   @ bitWidth 4 (Tx FIFO number)  
        .equ USBFS_DEVICE_DIEP2CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DIEP2CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DIEP2CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DIEP2CTL_EOFRM_DPID, 1 << 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_DIEP2CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DIEP2CTL_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DIEP3CTL, USBFS_DEVICE_BASE + 0x160 @ (device endpoint-3 control  register) 
        .equ USBFS_DEVICE_DIEP3CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DIEP3CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM, 1 << 29   @ bitWidth 1 (Set DATA1 PID/Set odd frame)  
        .equ USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM, 1 << 28   @ bitWidth 1 (SD0PID/SEVNFRM)  
        .equ USBFS_DEVICE_DIEP3CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DIEP3CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DIEP3CTL_TXFNUM_Shift, 22   @ bitWidth 4 (Tx FIFO number)  
        .equ USBFS_DEVICE_DIEP3CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DIEP3CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DIEP3CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DIEP3CTL_EOFRM_DPID, 1 << 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_DIEP3CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DIEP3CTL_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP0CTL, USBFS_DEVICE_BASE + 0x300 @ (device endpoint-0 control  register) 
        .equ USBFS_DEVICE_DOEP0CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DOEP0CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DOEP0CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DOEP0CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DOEP0CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DOEP0CTL_SNOOP, 1 << 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_DOEP0CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DOEP0CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DOEP0CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DOEP0CTL_MPL_Shift, 0   @ bitWidth 2 (Maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP1CTL, USBFS_DEVICE_BASE + 0x320 @ (device endpoint-1 control  register) 
        .equ USBFS_DEVICE_DOEP1CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DOEP1CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM, 1 << 29   @ bitWidth 1 (SD1PID/SODDFRM)  
        .equ USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM, 1 << 28   @ bitWidth 1 (SD0PID/SEVENFRM)  
        .equ USBFS_DEVICE_DOEP1CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DOEP1CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DOEP1CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DOEP1CTL_SNOOP, 1 << 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_DOEP1CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DOEP1CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DOEP1CTL_EOFRM_DPID, 1 << 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_DOEP1CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DOEP1CTL_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP2CTL, USBFS_DEVICE_BASE + 0x340 @ (device endpoint-2 control  register) 
        .equ USBFS_DEVICE_DOEP2CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DOEP2CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM, 1 << 29   @ bitWidth 1 (SD1PID/SODDFRM)  
        .equ USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM, 1 << 28   @ bitWidth 1 (SD0PID/SEVENFRM)  
        .equ USBFS_DEVICE_DOEP2CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DOEP2CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DOEP2CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DOEP2CTL_SNOOP, 1 << 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_DOEP2CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DOEP2CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DOEP2CTL_EOFRM_DPID, 1 << 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_DOEP2CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DOEP2CTL_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DOEP3CTL, USBFS_DEVICE_BASE + 0x360 @ (device endpoint-3 control  register) 
        .equ USBFS_DEVICE_DOEP3CTL_EPEN, 1 << 31   @ bitWidth 1 (Endpoint enable)  
        .equ USBFS_DEVICE_DOEP3CTL_EPD, 1 << 30   @ bitWidth 1 (Endpoint disable)  
        .equ USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM, 1 << 29   @ bitWidth 1 (SD1PID/SODDFRM)  
        .equ USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM, 1 << 28   @ bitWidth 1 (SD0PID/SEVENFRM)  
        .equ USBFS_DEVICE_DOEP3CTL_SNAK, 1 << 27   @ bitWidth 1 (Set NAK)  
        .equ USBFS_DEVICE_DOEP3CTL_CNAK, 1 << 26   @ bitWidth 1 (Clear NAK)  
        .equ USBFS_DEVICE_DOEP3CTL_STALL, 1 << 21   @ bitWidth 1 (STALL handshake)  
        .equ USBFS_DEVICE_DOEP3CTL_SNOOP, 1 << 20   @ bitWidth 1 (Snoop mode)  
        .equ USBFS_DEVICE_DOEP3CTL_EPTYPE_Shift, 18   @ bitWidth 2 (Endpoint type)  
        .equ USBFS_DEVICE_DOEP3CTL_NAKS, 1 << 17   @ bitWidth 1 (NAK status)  
        .equ USBFS_DEVICE_DOEP3CTL_EOFRM_DPID, 1 << 16   @ bitWidth 1 (EOFRM/DPID)  
        .equ USBFS_DEVICE_DOEP3CTL_EPACT, 1 << 15   @ bitWidth 1 (Endpoint active)  
        .equ USBFS_DEVICE_DOEP3CTL_MPL_Shift, 0   @ bitWidth 11 (maximum packet length)  
 
    .equ USBFS_DEVICE_DIEP0INTF, USBFS_DEVICE_BASE + 0x108 @ (device endpoint-0 interrupt  register) 
        .equ USBFS_DEVICE_DIEP0INTF_TXFE, 1 << 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_DIEP0INTF_IEPNE, 1 << 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_DIEP0INTF_EPTXFUD, 1 << 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_DIEP0INTF_CITO, 1 << 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_DIEP0INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_DIEP0INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP1INTF, USBFS_DEVICE_BASE + 0x128 @ (device endpoint-1 interrupt  register) 
        .equ USBFS_DEVICE_DIEP1INTF_TXFE, 1 << 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_DIEP1INTF_IEPNE, 1 << 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_DIEP1INTF_EPTXFUD, 1 << 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_DIEP1INTF_CITO, 1 << 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_DIEP1INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_DIEP1INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP2INTF, USBFS_DEVICE_BASE + 0x148 @ (device endpoint-2 interrupt  register) 
        .equ USBFS_DEVICE_DIEP2INTF_TXFE, 1 << 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_DIEP2INTF_IEPNE, 1 << 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_DIEP2INTF_EPTXFUD, 1 << 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_DIEP2INTF_CITO, 1 << 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_DIEP2INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_DIEP2INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP3INTF, USBFS_DEVICE_BASE + 0x168 @ (device endpoint-3 interrupt  register) 
        .equ USBFS_DEVICE_DIEP3INTF_TXFE, 1 << 7   @ bitWidth 1 (Transmit FIFO empty)  
        .equ USBFS_DEVICE_DIEP3INTF_IEPNE, 1 << 6   @ bitWidth 1 (IN endpoint NAK effective)  
        .equ USBFS_DEVICE_DIEP3INTF_EPTXFUD, 1 << 4   @ bitWidth 1 (Endpoint Tx FIFO underrun)  
        .equ USBFS_DEVICE_DIEP3INTF_CITO, 1 << 3   @ bitWidth 1 (Control in timeout interrupt)  
        .equ USBFS_DEVICE_DIEP3INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint finished)  
        .equ USBFS_DEVICE_DIEP3INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP0INTF, USBFS_DEVICE_BASE + 0x308 @ (device out endpoint-0 interrupt flag   register) 
        .equ USBFS_DEVICE_DOEP0INTF_BTBSTP, 1 << 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_DOEP0INTF_EPRXFOVR, 1 << 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_DOEP0INTF_STPF, 1 << 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_DOEP0INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_DOEP0INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP1INTF, USBFS_DEVICE_BASE + 0x328 @ (device out endpoint-1 interrupt flag   register) 
        .equ USBFS_DEVICE_DOEP1INTF_BTBSTP, 1 << 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_DOEP1INTF_EPRXFOVR, 1 << 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_DOEP1INTF_STPF, 1 << 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_DOEP1INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_DOEP1INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP2INTF, USBFS_DEVICE_BASE + 0x348 @ (device out endpoint-2 interrupt flag   register) 
        .equ USBFS_DEVICE_DOEP2INTF_BTBSTP, 1 << 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_DOEP2INTF_EPRXFOVR, 1 << 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_DOEP2INTF_STPF, 1 << 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_DOEP2INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_DOEP2INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DOEP3INTF, USBFS_DEVICE_BASE + 0x368 @ (device out endpoint-3 interrupt flag   register) 
        .equ USBFS_DEVICE_DOEP3INTF_BTBSTP, 1 << 6   @ bitWidth 1 (Back-to-back SETUP packets)  
        .equ USBFS_DEVICE_DOEP3INTF_EPRXFOVR, 1 << 4   @ bitWidth 1 (Endpoint Rx FIFO overrun)  
        .equ USBFS_DEVICE_DOEP3INTF_STPF, 1 << 3   @ bitWidth 1 (Setup phase finished)  
        .equ USBFS_DEVICE_DOEP3INTF_EPDIS, 1 << 1   @ bitWidth 1 (Endpoint disabled)  
        .equ USBFS_DEVICE_DOEP3INTF_TF, 1 << 0   @ bitWidth 1 (Transfer finished)  
 
    .equ USBFS_DEVICE_DIEP0LEN, USBFS_DEVICE_BASE + 0x110 @ (device IN endpoint-0 transfer length  register) 
        .equ USBFS_DEVICE_DIEP0LEN_PCNT_Shift, 19   @ bitWidth 2 (Packet count)  
        .equ USBFS_DEVICE_DIEP0LEN_TLEN_Shift, 0   @ bitWidth 7 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP0LEN, USBFS_DEVICE_BASE + 0x310 @ (device OUT endpoint-0 transfer length  register) 
        .equ USBFS_DEVICE_DOEP0LEN_STPCNT_Shift, 29   @ bitWidth 2 (SETUP packet count)  
        .equ USBFS_DEVICE_DOEP0LEN_PCNT, 1 << 19   @ bitWidth 1 (Packet count)  
        .equ USBFS_DEVICE_DOEP0LEN_TLEN_Shift, 0   @ bitWidth 7 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP1LEN, USBFS_DEVICE_BASE + 0x130 @ (device IN endpoint-1 transfer length  register) 
        .equ USBFS_DEVICE_DIEP1LEN_MCPF_Shift, 29   @ bitWidth 2 (Multi packet count per frame)  
        .equ USBFS_DEVICE_DIEP1LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_DIEP1LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP2LEN, USBFS_DEVICE_BASE + 0x150 @ (device IN endpoint-2 transfer length  register) 
        .equ USBFS_DEVICE_DIEP2LEN_MCPF_Shift, 29   @ bitWidth 2 (Multi packet count per frame)  
        .equ USBFS_DEVICE_DIEP2LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_DIEP2LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP3LEN, USBFS_DEVICE_BASE + 0x170 @ (device IN endpoint-3 transfer length  register) 
        .equ USBFS_DEVICE_DIEP3LEN_MCPF_Shift, 29   @ bitWidth 2 (Multi packet count per frame)  
        .equ USBFS_DEVICE_DIEP3LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_DIEP3LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP1LEN, USBFS_DEVICE_BASE + 0x330 @ (device OUT endpoint-1 transfer length  register) 
        .equ USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID_Shift, 29   @ bitWidth 2 (SETUP packet count/Received data PID)  
        .equ USBFS_DEVICE_DOEP1LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_DOEP1LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP2LEN, USBFS_DEVICE_BASE + 0x350 @ (device OUT endpoint-2 transfer length  register) 
        .equ USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID_Shift, 29   @ bitWidth 2 (SETUP packet count/Received data PID)  
        .equ USBFS_DEVICE_DOEP2LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_DOEP2LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DOEP3LEN, USBFS_DEVICE_BASE + 0x370 @ (device OUT endpoint-3 transfer length  register) 
        .equ USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID_Shift, 29   @ bitWidth 2 (SETUP packet count/Received data PID)  
        .equ USBFS_DEVICE_DOEP3LEN_PCNT_Shift, 19   @ bitWidth 10 (Packet count)  
        .equ USBFS_DEVICE_DOEP3LEN_TLEN_Shift, 0   @ bitWidth 19 (Transfer length)  
 
    .equ USBFS_DEVICE_DIEP0TFSTAT, USBFS_DEVICE_BASE + 0x118 @ (device IN endpoint 0 transmit FIFO  status register) 
        .equ USBFS_DEVICE_DIEP0TFSTAT_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 
    .equ USBFS_DEVICE_DIEP1TFSTAT, USBFS_DEVICE_BASE + 0x138 @ (device IN endpoint 1 transmit FIFO  status register) 
        .equ USBFS_DEVICE_DIEP1TFSTAT_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 
    .equ USBFS_DEVICE_DIEP2TFSTAT, USBFS_DEVICE_BASE + 0x158 @ (device IN endpoint 2 transmit FIFO  status register) 
        .equ USBFS_DEVICE_DIEP2TFSTAT_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 
    .equ USBFS_DEVICE_DIEP3TFSTAT, USBFS_DEVICE_BASE + 0x178 @ (device IN endpoint 3 transmit FIFO  status register) 
        .equ USBFS_DEVICE_DIEP3TFSTAT_IEPTFS_Shift, 0   @ bitWidth 16 (IN endpoint TxFIFO space  remaining)  
 

@=========================== USBFS_PWRCLK ===========================@
.equ USBFS_PWRCLK_BASE, 0x50000E00 @ (USB on the go full speed) 
    .equ USBFS_PWRCLK_PWRCLKCTL, USBFS_PWRCLK_BASE + 0x00 @ (power and clock gating control  register PWRCLKCTL) 
        .equ USBFS_PWRCLK_PWRCLKCTL_SUCLK, 1 << 0   @ bitWidth 1 (Stop the USB clock)  
        .equ USBFS_PWRCLK_PWRCLKCTL_SHCLK, 1 << 1   @ bitWidth 1 (Stop HCLK)  
 

@=========================== WWDGT ===========================@
.equ WWDGT_BASE, 0x40002C00 @ (Window watchdog timer) 
    .equ WWDGT_CTL, WWDGT_BASE + 0x0 @ (Control register) 
        .equ WWDGT_CTL_WDGTEN, 1 << 7   @ bitWidth 1 (Activation bit)  
        .equ WWDGT_CTL_CNT_Shift, 0   @ bitWidth 7 (7-bit counter)  
 
    .equ WWDGT_CFG, WWDGT_BASE + 0x04 @ (Configuration register) 
        .equ WWDGT_CFG_EWIE, 1 << 9   @ bitWidth 1 (Early wakeup interrupt)  
        .equ WWDGT_CFG_PSC_Shift, 7   @ bitWidth 2 (Prescaler)  
        .equ WWDGT_CFG_WIN_Shift, 0   @ bitWidth 7 (7-bit window value)  
 
    .equ WWDGT_STAT, WWDGT_BASE + 0x08 @ (Status register) 
        .equ WWDGT_STAT_EWIF, 1 << 0   @ bitWidth 1 (Early wakeup interrupt  flag)  
 
