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Mecrisp-Quintus for UP5K Icebreaker, containing FemtoRV32-Gracilis (RV32IMC).
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The included bitstream contains a FemtoRV32-Gracilis core which is synthesised
with 128 kb RAM, hardware multiply & divide and compressed instruction support.

See https://github.com/BrunoLevy/learn-fpga
and https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV/RTL/PROCESSOR

How to flash:

iceprog icebreaker.bin
iceprog -o 128k mecrisp-quintus-icebreaker-with-tools.bin

How to communicate:

picocom -b 115200 /dev/ttyUSB1 --imap lfcrlf,crcrlf --omap delbs,crlf --send-cmd "ascii-xfr -s -l 400 -n"
  or
./terminal

The board has a dedicated Reset button.

Processor runs at 12 MHz and everything is copied to RAM for fast execution.

You can also run the binary in emulator:

./quintusemu-icebreaker mecrisp-quintus-icebreaker-with-tools.bin

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Memory map:

$00000000 - $0000FFFF: 64 kb RAM
$00010000 - $0001FFFF: 64 kb RAM, containing mirrored Flash contents
$00800000 - $008FFFFF: SPI Flash memory, slow.

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IO Registers:

$400010 constant port-in    [24] Random bit [23:16] PMOD2 [15:8] PMOD1B [7:0] PMOD1A
$400020 constant port-out                   [23:16] PMOD2 [15:8] PMOD1B [7:0] PMOD1A
$400040 constant port-dir                   [23:16] PMOD2 [15:8] PMOD1B [7:0] PMOD1A
$400080 constant port-leds                                              [1:0] Two LEDs

$410000 constant uart-data   [9] serial_busy [8] serial_valid [7:0] serial_data, transmit/clear side effects
$420000 constant uart-status [9] serial_busy [8] serial_valid [7:0] serial_data,             no side effects
$440000 constant ticks       Timer ticks, generates interrupt on overflow from $FFFFFFFF
$480000 constant reload      Timer reload value on overflow

The IO registers have atomic clear/set/toggle capability:

  Address +  0 : Normal write
  Address +  4 : Clear bits
  Address +  8 : Set bits
  Address + 12 : Toggle bits

The ticks counter counts up, triggers an interrupt on overflow and
loads the value from the reload register, which defaults to 0.

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