@ arm-none-eabi-as equates file for STM32WBxx_CM4
@ SVD2GAS Equates Generator, Copyright Terry Porter 2017 "terry@tjporter.com.au" for arm-none-eabi-as 
@ Matthias Koch Complimentary Edition 2017
@ Takes a CMSIS-SVD file plus a hand edited config.xml file as input 
@ Licensed under the GPL, see http://www.gnu.org/licenses/


@=========================== DMA1 ===========================@
.equ DMA1_BASE, 0x40020000 @ (Direct memory access controller) 
    .equ DMA1_ISR, DMA1_BASE + 0x0 @ (interrupt status register) 
        .equ DMA1_TEIF7_Shift, 27   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF7_Shift, 26   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF7_Shift, 25   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF7_Shift, 24   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA1_TEIF6_Shift, 23   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF6_Shift, 22   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF6_Shift, 21   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF6_Shift, 20   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA1_TEIF5_Shift, 19   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF5_Shift, 18   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF5_Shift, 17   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF5_Shift, 16   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA1_TEIF4_Shift, 15   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF4_Shift, 14   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF4_Shift, 13   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF4_Shift, 12   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA1_TEIF3_Shift, 11   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF3_Shift, 10   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF3_Shift, 9   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF3_Shift, 8   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA1_TEIF2_Shift, 7   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF2_Shift, 6   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF2_Shift, 5   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF2_Shift, 4   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA1_TEIF1_Shift, 3   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA1_HTIF1_Shift, 2   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA1_TCIF1_Shift, 1   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA1_GIF1_Shift, 0   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
 
    .equ DMA1_IFCR, DMA1_BASE + 0x4 @ (interrupt flag clear register) 
        .equ DMA1_CTEIF7_Shift, 27   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF7_Shift, 26   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF7_Shift, 25   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF7_Shift, 24   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA1_CTEIF6_Shift, 23   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF6_Shift, 22   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF6_Shift, 21   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF6_Shift, 20   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA1_CTEIF5_Shift, 19   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF5_Shift, 18   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF5_Shift, 17   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF5_Shift, 16   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA1_CTEIF4_Shift, 15   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF4_Shift, 14   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF4_Shift, 13   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF4_Shift, 12   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA1_CTEIF3_Shift, 11   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF3_Shift, 10   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF3_Shift, 9   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF3_Shift, 8   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA1_CTEIF2_Shift, 7   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF2_Shift, 6   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF2_Shift, 5   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF2_Shift, 4   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA1_CTEIF1_Shift, 3   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA1_CHTIF1_Shift, 2   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA1_CTCIF1_Shift, 1   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA1_CGIF1_Shift, 0   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
 
    .equ DMA1_CCR1, DMA1_BASE + 0x8 @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR1, DMA1_BASE + 0xC @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR1, DMA1_BASE + 0x10 @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR1, DMA1_BASE + 0x14 @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA1_CCR2, DMA1_BASE + 0x1C @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR2, DMA1_BASE + 0x20 @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR2, DMA1_BASE + 0x24 @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR2, DMA1_BASE + 0x28 @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA1_CCR3, DMA1_BASE + 0x30 @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR3, DMA1_BASE + 0x34 @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR3, DMA1_BASE + 0x38 @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR3, DMA1_BASE + 0x3C @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA1_CCR4, DMA1_BASE + 0x44 @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR4, DMA1_BASE + 0x48 @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR4, DMA1_BASE + 0x4C @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR4, DMA1_BASE + 0x50 @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA1_CCR5, DMA1_BASE + 0x58 @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR5, DMA1_BASE + 0x5C @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR5, DMA1_BASE + 0x60 @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR5, DMA1_BASE + 0x64 @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA1_CCR6, DMA1_BASE + 0x6C @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR6, DMA1_BASE + 0x70 @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR6, DMA1_BASE + 0x74 @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR6, DMA1_BASE + 0x78 @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA1_CCR7, DMA1_BASE + 0x80 @ (channel x configuration register) 
        .equ DMA1_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA1_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA1_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA1_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA1_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA1_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA1_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA1_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA1_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA1_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA1_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA1_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA1_CNDTR7, DMA1_BASE + 0x84 @ (channel x number of data register) 
        .equ DMA1_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA1_CPAR7, DMA1_BASE + 0x88 @ (channel x peripheral address register) 
        .equ DMA1_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA1_CMAR7, DMA1_BASE + 0x8C @ (channel x memory address register) 
        .equ DMA1_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 

@=========================== DMA2 ===========================@
.equ DMA2_BASE, 0x40020400 @ (Direct memory access controller) 
    .equ DMA2_ISR, DMA2_BASE + 0x0 @ (interrupt status register) 
        .equ DMA2_TEIF7_Shift, 27   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF7_Shift, 26   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF7_Shift, 25   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF7_Shift, 24   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA2_TEIF6_Shift, 23   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF6_Shift, 22   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF6_Shift, 21   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF6_Shift, 20   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA2_TEIF5_Shift, 19   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF5_Shift, 18   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF5_Shift, 17   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF5_Shift, 16   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA2_TEIF4_Shift, 15   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF4_Shift, 14   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF4_Shift, 13   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF4_Shift, 12   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA2_TEIF3_Shift, 11   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF3_Shift, 10   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF3_Shift, 9   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF3_Shift, 8   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA2_TEIF2_Shift, 7   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF2_Shift, 6   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF2_Shift, 5   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF2_Shift, 4   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
        .equ DMA2_TEIF1_Shift, 3   @ bitWidth 1 (Channel x transfer error flag x = 1 ..7)  
        .equ DMA2_HTIF1_Shift, 2   @ bitWidth 1 (Channel x half transfer flag x = 1 ..7)  
        .equ DMA2_TCIF1_Shift, 1   @ bitWidth 1 (Channel x transfer complete flag x = 1 ..7)  
        .equ DMA2_GIF1_Shift, 0   @ bitWidth 1 (Channel x global interrupt flag x = 1 ..7)  
 
    .equ DMA2_IFCR, DMA2_BASE + 0x4 @ (interrupt flag clear register) 
        .equ DMA2_CTEIF7_Shift, 27   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF7_Shift, 26   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF7_Shift, 25   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF7_Shift, 24   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA2_CTEIF6_Shift, 23   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF6_Shift, 22   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF6_Shift, 21   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF6_Shift, 20   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA2_CTEIF5_Shift, 19   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF5_Shift, 18   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF5_Shift, 17   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF5_Shift, 16   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA2_CTEIF4_Shift, 15   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF4_Shift, 14   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF4_Shift, 13   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF4_Shift, 12   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA2_CTEIF3_Shift, 11   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF3_Shift, 10   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF3_Shift, 9   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF3_Shift, 8   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA2_CTEIF2_Shift, 7   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF2_Shift, 6   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF2_Shift, 5   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF2_Shift, 4   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
        .equ DMA2_CTEIF1_Shift, 3   @ bitWidth 1 (Channel x transfer error clear x = 1 ..7)  
        .equ DMA2_CHTIF1_Shift, 2   @ bitWidth 1 (Channel x half transfer clear x = 1 ..7)  
        .equ DMA2_CTCIF1_Shift, 1   @ bitWidth 1 (Channel x transfer complete clear x = 1 ..7)  
        .equ DMA2_CGIF1_Shift, 0   @ bitWidth 1 (Channel x global interrupt clear x = 1 ..7)  
 
    .equ DMA2_CCR1, DMA2_BASE + 0x8 @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR1, DMA2_BASE + 0xC @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR1, DMA2_BASE + 0x10 @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR1, DMA2_BASE + 0x14 @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CCR2, DMA2_BASE + 0x1C @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR2, DMA2_BASE + 0x20 @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR2, DMA2_BASE + 0x24 @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR2, DMA2_BASE + 0x28 @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CCR3, DMA2_BASE + 0x30 @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR3, DMA2_BASE + 0x34 @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR3, DMA2_BASE + 0x38 @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR3, DMA2_BASE + 0x3C @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CCR4, DMA2_BASE + 0x44 @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR4, DMA2_BASE + 0x48 @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR4, DMA2_BASE + 0x4C @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR4, DMA2_BASE + 0x50 @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CCR5, DMA2_BASE + 0x58 @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR5, DMA2_BASE + 0x5C @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR5, DMA2_BASE + 0x60 @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR5, DMA2_BASE + 0x64 @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CCR6, DMA2_BASE + 0x6C @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR6, DMA2_BASE + 0x70 @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR6, DMA2_BASE + 0x74 @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR6, DMA2_BASE + 0x78 @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CCR7, DMA2_BASE + 0x80 @ (channel x configuration register) 
        .equ DMA2_MEM2MEM_Shift, 14   @ bitWidth 1 (Memory to memory mode)  
        .equ DMA2_PL_Shift, 12   @ bitWidth 2 (Channel priority level)  
        .equ DMA2_MSIZE_Shift, 10   @ bitWidth 2 (Memory size)  
        .equ DMA2_PSIZE_Shift, 8   @ bitWidth 2 (Peripheral size)  
        .equ DMA2_MINC_Shift, 7   @ bitWidth 1 (Memory increment mode)  
        .equ DMA2_PINC_Shift, 6   @ bitWidth 1 (Peripheral increment mode)  
        .equ DMA2_CIRC_Shift, 5   @ bitWidth 1 (Circular mode)  
        .equ DMA2_DIR_Shift, 4   @ bitWidth 1 (Data transfer direction)  
        .equ DMA2_TEIE_Shift, 3   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ DMA2_HTIE_Shift, 2   @ bitWidth 1 (Half transfer interrupt enable)  
        .equ DMA2_TCIE_Shift, 1   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ DMA2_EN_Shift, 0   @ bitWidth 1 (Channel enable)  
 
    .equ DMA2_CNDTR7, DMA2_BASE + 0x84 @ (channel x number of data register) 
        .equ DMA2_NDT_Shift, 0   @ bitWidth 16 (Number of data to transfer)  
 
    .equ DMA2_CPAR7, DMA2_BASE + 0x88 @ (channel x peripheral address register) 
        .equ DMA2_PA_Shift, 0   @ bitWidth 32 (Peripheral address)  
 
    .equ DMA2_CMAR7, DMA2_BASE + 0x8C @ (channel x memory address register) 
        .equ DMA2_MA_Shift, 0   @ bitWidth 32 (Memory address)  
 
    .equ DMA2_CSELR, DMA2_BASE + 0xA8 @ (channel selection register) 
        .equ DMA2_C7S_Shift, 24   @ bitWidth 4 (DMA channel 7 selection)  
        .equ DMA2_C6S_Shift, 20   @ bitWidth 4 (DMA channel 6 selection)  
        .equ DMA2_C5S_Shift, 16   @ bitWidth 4 (DMA channel 5 selection)  
        .equ DMA2_C4S_Shift, 12   @ bitWidth 4 (DMA channel 4 selection)  
        .equ DMA2_C3S_Shift, 8   @ bitWidth 4 (DMA channel 3 selection)  
        .equ DMA2_C2S_Shift, 4   @ bitWidth 4 (DMA channel 2 selection)  
        .equ DMA2_C1S_Shift, 0   @ bitWidth 4 (DMA channel 1 selection)  
 

@=========================== DMAMUX1 ===========================@
.equ DMAMUX1_BASE, 0x40020800 @ (Direct memory access Multiplexer) 
    .equ DMAMUX1_C0CR, DMAMUX1_BASE + 0x0 @ (DMA Multiplexer Channel 0 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C1CR, DMAMUX1_BASE + 0x4 @ (DMA Multiplexer Channel 1 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C2CR, DMAMUX1_BASE + 0x8 @ (DMA Multiplexer Channel 2 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C3CR, DMAMUX1_BASE + 0xC @ (DMA Multiplexer Channel 3 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C4CR, DMAMUX1_BASE + 0x10 @ (DMA Multiplexer Channel 4 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C5CR, DMAMUX1_BASE + 0x14 @ (DMA Multiplexer Channel 5 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C6CR, DMAMUX1_BASE + 0x18 @ (DMA Multiplexer Channel 6 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C7CR, DMAMUX1_BASE + 0x1C @ (DMA Multiplexer Channel 7 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C8CR, DMAMUX1_BASE + 0x20 @ (DMA Multiplexer Channel 8 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C9CR, DMAMUX1_BASE + 0x24 @ (DMA Multiplexer Channel 9 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C10CR, DMAMUX1_BASE + 0x28 @ (DMA Multiplexer Channel 10 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C11CR, DMAMUX1_BASE + 0x2C @ (DMA Multiplexer Channel 11 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C12CR, DMAMUX1_BASE + 0x30 @ (DMA Multiplexer Channel 12 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_C13CR, DMAMUX1_BASE + 0x34 @ (DMA Multiplexer Channel 13 Control register) 
        .equ DMAMUX1_SYNC_ID_Shift, 24   @ bitWidth 5 (SYNC_ID)  
        .equ DMAMUX1_NBREQ_Shift, 19   @ bitWidth 5 (Nb request)  
        .equ DMAMUX1_SPOL_Shift, 17   @ bitWidth 2 (Sync polarity)  
        .equ DMAMUX1_SE_Shift, 16   @ bitWidth 1 (Synchronization enable)  
        .equ DMAMUX1_EGE_Shift, 9   @ bitWidth 1 (Event Generation Enable)  
        .equ DMAMUX1_SOIE_Shift, 8   @ bitWidth 1 (Synchronization Overrun Interrupt Enable)  
        .equ DMAMUX1_DMAREQ_ID_Shift, 0   @ bitWidth 8 (DMA Request ID)  
 
    .equ DMAMUX1_CSR, DMAMUX1_BASE + 0x80 @ (DMA Multiplexer Channel Status register) 
        .equ DMAMUX1_SOF0_Shift, 0   @ bitWidth 1 (Synchronization Overrun Flag 0)  
        .equ DMAMUX1_SOF1_Shift, 1   @ bitWidth 1 (Synchronization Overrun Flag 1)  
        .equ DMAMUX1_SOF2_Shift, 2   @ bitWidth 1 (Synchronization Overrun Flag 2)  
        .equ DMAMUX1_SOF3_Shift, 3   @ bitWidth 1 (Synchronization Overrun Flag 3)  
        .equ DMAMUX1_SOF4_Shift, 4   @ bitWidth 1 (Synchronization Overrun Flag 4)  
        .equ DMAMUX1_SOF5_Shift, 5   @ bitWidth 1 (Synchronization Overrun Flag 5)  
        .equ DMAMUX1_SOF6_Shift, 6   @ bitWidth 1 (Synchronization Overrun Flag 6)  
        .equ DMAMUX1_SOF7_Shift, 7   @ bitWidth 1 (Synchronization Overrun Flag 7)  
        .equ DMAMUX1_SOF8_Shift, 8   @ bitWidth 1 (Synchronization Overrun Flag 8)  
        .equ DMAMUX1_SOF9_Shift, 9   @ bitWidth 1 (Synchronization Overrun Flag 9)  
        .equ DMAMUX1_SOF10_Shift, 10   @ bitWidth 1 (Synchronization Overrun Flag 10)  
        .equ DMAMUX1_SOF11_Shift, 11   @ bitWidth 1 (Synchronization Overrun Flag 11)  
        .equ DMAMUX1_SOF12_Shift, 12   @ bitWidth 1 (Synchronization Overrun Flag 12)  
        .equ DMAMUX1_SOF13_Shift, 13   @ bitWidth 1 (Synchronization Overrun Flag 13)  
 
    .equ DMAMUX1_CFR, DMAMUX1_BASE + 0x84 @ (DMA Channel Clear Flag Register) 
        .equ DMAMUX1_CSOF0_Shift, 0   @ bitWidth 1 (Synchronization Clear Overrun Flag 0)  
        .equ DMAMUX1_CSOF1_Shift, 1   @ bitWidth 1 (Synchronization Clear Overrun Flag 1)  
        .equ DMAMUX1_CSOF2_Shift, 2   @ bitWidth 1 (Synchronization Clear Overrun Flag 2)  
        .equ DMAMUX1_CSOF3_Shift, 3   @ bitWidth 1 (Synchronization Clear Overrun Flag 3)  
        .equ DMAMUX1_CSOF4_Shift, 4   @ bitWidth 1 (Synchronization Clear Overrun Flag 4)  
        .equ DMAMUX1_CSOF5_Shift, 5   @ bitWidth 1 (Synchronization Clear Overrun Flag 5)  
        .equ DMAMUX1_CSOF6_Shift, 6   @ bitWidth 1 (Synchronization Clear Overrun Flag 6)  
        .equ DMAMUX1_CSOF7_Shift, 7   @ bitWidth 1 (Synchronization Clear Overrun Flag 7)  
        .equ DMAMUX1_CSOF8_Shift, 8   @ bitWidth 1 (Synchronization Clear Overrun Flag 8)  
        .equ DMAMUX1_CSOF9_Shift, 9   @ bitWidth 1 (Synchronization Clear Overrun Flag 9)  
        .equ DMAMUX1_CSOF10_Shift, 10   @ bitWidth 1 (Synchronization Clear Overrun Flag 10)  
        .equ DMAMUX1_CSOF11_Shift, 11   @ bitWidth 1 (Synchronization Clear Overrun Flag 11)  
        .equ DMAMUX1_CSOF12_Shift, 12   @ bitWidth 1 (Synchronization Clear Overrun Flag 12)  
        .equ DMAMUX1_CSOF13_Shift, 13   @ bitWidth 1 (Synchronization Clear Overrun Flag 13)  
 
    .equ DMAMUX1_RG0CR, DMAMUX1_BASE + 0x100 @ (DMA Request Generator 0 Control Register) 
        .equ DMAMUX1_GNBREQ_Shift, 19   @ bitWidth 5 (Number of Request)  
        .equ DMAMUX1_GPOL_Shift, 17   @ bitWidth 2 (Generation Polarity)  
        .equ DMAMUX1_GE_Shift, 16   @ bitWidth 1 (Generation Enable)  
        .equ DMAMUX1_OIE_Shift, 8   @ bitWidth 1 (Overrun Interrupt Enable)  
        .equ DMAMUX1_SIG_ID_Shift, 0   @ bitWidth 5 (Signal ID)  
 
    .equ DMAMUX1_RG1CR, DMAMUX1_BASE + 0x104 @ (DMA Request Generator 1 Control Register) 
        .equ DMAMUX1_GNBREQ_Shift, 19   @ bitWidth 5 (Number of Request)  
        .equ DMAMUX1_GPOL_Shift, 17   @ bitWidth 2 (Generation Polarity)  
        .equ DMAMUX1_GE_Shift, 16   @ bitWidth 1 (Generation Enable)  
        .equ DMAMUX1_OIE_Shift, 8   @ bitWidth 1 (Overrun Interrupt Enable)  
        .equ DMAMUX1_SIG_ID_Shift, 0   @ bitWidth 5 (Signal ID)  
 
    .equ DMAMUX1_RG2CR, DMAMUX1_BASE + 0x108 @ (DMA Request Generator 2 Control Register) 
        .equ DMAMUX1_GNBREQ_Shift, 19   @ bitWidth 5 (Number of Request)  
        .equ DMAMUX1_GPOL_Shift, 17   @ bitWidth 2 (Generation Polarity)  
        .equ DMAMUX1_GE_Shift, 16   @ bitWidth 1 (Generation Enable)  
        .equ DMAMUX1_OIE_Shift, 8   @ bitWidth 1 (Overrun Interrupt Enable)  
        .equ DMAMUX1_SIG_ID_Shift, 0   @ bitWidth 5 (Signal ID)  
 
    .equ DMAMUX1_RG3CR, DMAMUX1_BASE + 0x10C @ (DMA Request Generator 3 Control Register) 
        .equ DMAMUX1_GNBREQ_Shift, 19   @ bitWidth 5 (Number of Request)  
        .equ DMAMUX1_GPOL_Shift, 17   @ bitWidth 2 (Generation Polarity)  
        .equ DMAMUX1_GE_Shift, 16   @ bitWidth 1 (Generation Enable)  
        .equ DMAMUX1_OIE_Shift, 8   @ bitWidth 1 (Overrun Interrupt Enable)  
        .equ DMAMUX1_SIG_ID_Shift, 0   @ bitWidth 5 (Signal ID)  
 
    .equ DMAMUX1_RGSR, DMAMUX1_BASE + 0x140 @ (DMA Request Generator Status Register) 
        .equ DMAMUX1_OF0_Shift, 0   @ bitWidth 1 (Generator Overrun Flag 0)  
        .equ DMAMUX1_OF1_Shift, 1   @ bitWidth 1 (Generator Overrun Flag 1)  
        .equ DMAMUX1_OF2_Shift, 2   @ bitWidth 1 (Generator Overrun Flag 2)  
        .equ DMAMUX1_OF3_Shift, 3   @ bitWidth 1 (Generator Overrun Flag 3)  
 
    .equ DMAMUX1_RGCFR, DMAMUX1_BASE + 0x144 @ (DMA Request Generator Clear Flag Register) 
        .equ DMAMUX1_CSOF0_Shift, 0   @ bitWidth 1 (Generator Clear Overrun Flag 0)  
        .equ DMAMUX1_CSOF1_Shift, 1   @ bitWidth 1 (Generator Clear Overrun Flag 1)  
        .equ DMAMUX1_CSOF2_Shift, 2   @ bitWidth 1 (Generator Clear Overrun Flag 2)  
        .equ DMAMUX1_CSOF3_Shift, 3   @ bitWidth 1 (Generator Clear Overrun Flag 3)  
 

@=========================== CRC ===========================@
.equ CRC_BASE, 0x40023000 @ (Cyclic redundancy check calculation unit) 
    .equ CRC_DR, CRC_BASE + 0x0 @ (Data register) 
        .equ CRC_DR_Shift, 0   @ bitWidth 32 (Data register bits)  
 
    .equ CRC_IDR, CRC_BASE + 0x4 @ (Independent data register) 
        .equ CRC_IDR_Shift, 0   @ bitWidth 32 (General-purpose 32-bit data register bits)  
 
    .equ CRC_CR, CRC_BASE + 0x8 @ (Control register) 
        .equ CRC_REV_OUT_Shift, 7   @ bitWidth 1 (Reverse output data)  
        .equ CRC_REV_IN_Shift, 5   @ bitWidth 2 (Reverse input data)  
        .equ CRC_POLYSIZE_Shift, 3   @ bitWidth 2 (Polynomial size)  
        .equ CRC_RESET_Shift, 0   @ bitWidth 1 (RESET bit)  
 
    .equ CRC_INIT, CRC_BASE + 0x10 @ (Initial CRC value) 
        .equ CRC_CRC_INIT_Shift, 0   @ bitWidth 32 (Programmable initial CRC value)  
 
    .equ CRC_POL, CRC_BASE + 0x14 @ (polynomial) 
        .equ CRC_POL_Shift, 0   @ bitWidth 32 (Programmable polynomial)  
 

@=========================== LCD ===========================@
.equ LCD_BASE, 0x40002400 @ (Liquid crystal display controller) 
    .equ LCD_CR, LCD_BASE + 0x0 @ (control register) 
        .equ LCD_BIAS_Shift, 5   @ bitWidth 2 (Bias selector)  
        .equ LCD_DUTY_Shift, 2   @ bitWidth 3 (Duty selection)  
        .equ LCD_VSEL_Shift, 1   @ bitWidth 1 (Voltage source selection)  
        .equ LCD_LCDEN_Shift, 0   @ bitWidth 1 (LCD controller enable)  
        .equ LCD_MUX_SEG_Shift, 7   @ bitWidth 1 (Mux segment enable)  
        .equ LCD_BUFEN_Shift, 8   @ bitWidth 1 (Voltage output buffer enable)  
 
    .equ LCD_FCR, LCD_BASE + 0x4 @ (frame control register) 
        .equ LCD_PS_Shift, 22   @ bitWidth 4 (PS 16-bit prescaler)  
        .equ LCD_DIV_Shift, 18   @ bitWidth 4 (DIV clock divider)  
        .equ LCD_BLINK_Shift, 16   @ bitWidth 2 (Blink mode selection)  
        .equ LCD_BLINKF_Shift, 13   @ bitWidth 3 (Blink frequency selection)  
        .equ LCD_CC_Shift, 10   @ bitWidth 3 (Contrast control)  
        .equ LCD_DEAD_Shift, 7   @ bitWidth 3 (Dead time duration)  
        .equ LCD_PON_Shift, 4   @ bitWidth 3 (Pulse ON duration)  
        .equ LCD_UDDIE_Shift, 3   @ bitWidth 1 (Update display done interrupt enable)  
        .equ LCD_SOFIE_Shift, 1   @ bitWidth 1 (Start of frame interrupt enable)  
        .equ LCD_HD_Shift, 0   @ bitWidth 1 (High drive enable)  
 
    .equ LCD_SR, LCD_BASE + 0x8 @ (status register) 
        .equ LCD_FCRSF_Shift, 5   @ bitWidth 1 (LCD Frame Control Register Synchronization flag)  
        .equ LCD_RDY_Shift, 4   @ bitWidth 1 (Ready flag)  
        .equ LCD_UDD_Shift, 3   @ bitWidth 1 (Update Display Done)  
        .equ LCD_UDR_Shift, 2   @ bitWidth 1 (Update display request)  
        .equ LCD_SOF_Shift, 1   @ bitWidth 1 (Start of frame flag)  
        .equ LCD_ENS_Shift, 0   @ bitWidth 1 (ENS)  
 
    .equ LCD_CLR, LCD_BASE + 0xC @ (clear register) 
        .equ LCD_UDDC_Shift, 3   @ bitWidth 1 (Update display done clear)  
        .equ LCD_SOFC_Shift, 1   @ bitWidth 1 (Start of frame flag clear)  
 
    .equ LCD_RAM_COM0, LCD_BASE + 0x14 @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM1, LCD_BASE + 0x1C @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM2, LCD_BASE + 0x24 @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM3, LCD_BASE + 0x2C @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM4, LCD_BASE + 0x34 @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM5, LCD_BASE + 0x3C @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM6, LCD_BASE + 0x44 @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 
    .equ LCD_RAM_COM7, LCD_BASE + 0x4C @ (display memory) 
        .equ LCD_S31_Shift, 31   @ bitWidth 1 (S31)  
        .equ LCD_S30_Shift, 30   @ bitWidth 1 (S30)  
        .equ LCD_S29_Shift, 29   @ bitWidth 1 (S29)  
        .equ LCD_S28_Shift, 28   @ bitWidth 1 (S28)  
        .equ LCD_S27_Shift, 27   @ bitWidth 1 (S27)  
        .equ LCD_S26_Shift, 26   @ bitWidth 1 (S26)  
        .equ LCD_S25_Shift, 25   @ bitWidth 1 (S25)  
        .equ LCD_S24_Shift, 24   @ bitWidth 1 (S24)  
        .equ LCD_S23_Shift, 23   @ bitWidth 1 (S23)  
        .equ LCD_S22_Shift, 22   @ bitWidth 1 (S22)  
        .equ LCD_S21_Shift, 21   @ bitWidth 1 (S21)  
        .equ LCD_S20_Shift, 20   @ bitWidth 1 (S20)  
        .equ LCD_S19_Shift, 19   @ bitWidth 1 (S19)  
        .equ LCD_S18_Shift, 18   @ bitWidth 1 (S18)  
        .equ LCD_S17_Shift, 17   @ bitWidth 1 (S17)  
        .equ LCD_S16_Shift, 16   @ bitWidth 1 (S16)  
        .equ LCD_S15_Shift, 15   @ bitWidth 1 (S15)  
        .equ LCD_S14_Shift, 14   @ bitWidth 1 (S14)  
        .equ LCD_S13_Shift, 13   @ bitWidth 1 (S13)  
        .equ LCD_S12_Shift, 12   @ bitWidth 1 (S12)  
        .equ LCD_S11_Shift, 11   @ bitWidth 1 (S11)  
        .equ LCD_S10_Shift, 10   @ bitWidth 1 (S10)  
        .equ LCD_S09_Shift, 9   @ bitWidth 1 (S09)  
        .equ LCD_S08_Shift, 8   @ bitWidth 1 (S08)  
        .equ LCD_S07_Shift, 7   @ bitWidth 1 (S07)  
        .equ LCD_S06_Shift, 6   @ bitWidth 1 (S06)  
        .equ LCD_S05_Shift, 5   @ bitWidth 1 (S05)  
        .equ LCD_S04_Shift, 4   @ bitWidth 1 (S04)  
        .equ LCD_S03_Shift, 3   @ bitWidth 1 (S03)  
        .equ LCD_S02_Shift, 2   @ bitWidth 1 (S02)  
        .equ LCD_S01_Shift, 1   @ bitWidth 1 (S01)  
        .equ LCD_S00_Shift, 0   @ bitWidth 1 (S00)  
 

@=========================== TSC ===========================@
.equ TSC_BASE, 0x40024000 @ (Touch sensing controller) 
    .equ TSC_CR, TSC_BASE + 0x0 @ (control register) 
        .equ TSC_CTPH_Shift, 28   @ bitWidth 4 (Charge transfer pulse high)  
        .equ TSC_CTPL_Shift, 24   @ bitWidth 4 (Charge transfer pulse low)  
        .equ TSC_SSD_Shift, 17   @ bitWidth 7 (Spread spectrum deviation)  
        .equ TSC_SSE_Shift, 16   @ bitWidth 1 (Spread spectrum enable)  
        .equ TSC_SSPSC_Shift, 15   @ bitWidth 1 (Spread spectrum prescaler)  
        .equ TSC_PGPSC_Shift, 12   @ bitWidth 3 (pulse generator prescaler)  
        .equ TSC_MCV_Shift, 5   @ bitWidth 3 (Max count value)  
        .equ TSC_IODEF_Shift, 4   @ bitWidth 1 (I/O Default mode)  
        .equ TSC_SYNCPOL_Shift, 3   @ bitWidth 1 (Synchronization pin polarity)  
        .equ TSC_AM_Shift, 2   @ bitWidth 1 (Acquisition mode)  
        .equ TSC_START_Shift, 1   @ bitWidth 1 (Start a new acquisition)  
        .equ TSC_TSCE_Shift, 0   @ bitWidth 1 (Touch sensing controller enable)  
 
    .equ TSC_IER, TSC_BASE + 0x4 @ (interrupt enable register) 
        .equ TSC_MCEIE_Shift, 1   @ bitWidth 1 (Max count error interrupt enable)  
        .equ TSC_EOAIE_Shift, 0   @ bitWidth 1 (End of acquisition interrupt enable)  
 
    .equ TSC_ICR, TSC_BASE + 0x8 @ (interrupt clear register) 
        .equ TSC_MCEIC_Shift, 1   @ bitWidth 1 (Max count error interrupt clear)  
        .equ TSC_EOAIC_Shift, 0   @ bitWidth 1 (End of acquisition interrupt clear)  
 
    .equ TSC_ISR, TSC_BASE + 0xC @ (interrupt status register) 
        .equ TSC_MCEF_Shift, 1   @ bitWidth 1 (Max count error flag)  
        .equ TSC_EOAF_Shift, 0   @ bitWidth 1 (End of acquisition flag)  
 
    .equ TSC_IOHCR, TSC_BASE + 0x10 @ (I/O hysteresis control register) 
        .equ TSC_G7_IO4_Shift, 27   @ bitWidth 1 (G7_IO4)  
        .equ TSC_G7_IO3_Shift, 26   @ bitWidth 1 (G7_IO3)  
        .equ TSC_G7_IO2_Shift, 25   @ bitWidth 1 (G7_IO2)  
        .equ TSC_G7_IO1_Shift, 24   @ bitWidth 1 (G7_IO1)  
        .equ TSC_G6_IO4_Shift, 23   @ bitWidth 1 (G6_IO4)  
        .equ TSC_G6_IO3_Shift, 22   @ bitWidth 1 (G6_IO3)  
        .equ TSC_G6_IO2_Shift, 21   @ bitWidth 1 (G6_IO2)  
        .equ TSC_G6_IO1_Shift, 20   @ bitWidth 1 (G6_IO1)  
        .equ TSC_G5_IO4_Shift, 19   @ bitWidth 1 (G5_IO4)  
        .equ TSC_G5_IO3_Shift, 18   @ bitWidth 1 (G5_IO3)  
        .equ TSC_G5_IO2_Shift, 17   @ bitWidth 1 (G5_IO2)  
        .equ TSC_G5_IO1_Shift, 16   @ bitWidth 1 (G5_IO1)  
        .equ TSC_G4_IO4_Shift, 15   @ bitWidth 1 (G4_IO4)  
        .equ TSC_G4_IO3_Shift, 14   @ bitWidth 1 (G4_IO3)  
        .equ TSC_G4_IO2_Shift, 13   @ bitWidth 1 (G4_IO2)  
        .equ TSC_G4_IO1_Shift, 12   @ bitWidth 1 (G4_IO1)  
        .equ TSC_G3_IO4_Shift, 11   @ bitWidth 1 (G3_IO4)  
        .equ TSC_G3_IO3_Shift, 10   @ bitWidth 1 (G3_IO3)  
        .equ TSC_G3_IO2_Shift, 9   @ bitWidth 1 (G3_IO2)  
        .equ TSC_G3_IO1_Shift, 8   @ bitWidth 1 (G3_IO1)  
        .equ TSC_G2_IO4_Shift, 7   @ bitWidth 1 (G2_IO4)  
        .equ TSC_G2_IO3_Shift, 6   @ bitWidth 1 (G2_IO3)  
        .equ TSC_G2_IO2_Shift, 5   @ bitWidth 1 (G2_IO2)  
        .equ TSC_G2_IO1_Shift, 4   @ bitWidth 1 (G2_IO1)  
        .equ TSC_G1_IO4_Shift, 3   @ bitWidth 1 (G1_IO4)  
        .equ TSC_G1_IO3_Shift, 2   @ bitWidth 1 (G1_IO3)  
        .equ TSC_G1_IO2_Shift, 1   @ bitWidth 1 (G1_IO2)  
        .equ TSC_G1_IO1_Shift, 0   @ bitWidth 1 (G1_IO1)  
 
    .equ TSC_IOASCR, TSC_BASE + 0x18 @ (I/O analog switch control register) 
        .equ TSC_G7_IO4_Shift, 27   @ bitWidth 1 (G7_IO4)  
        .equ TSC_G7_IO3_Shift, 26   @ bitWidth 1 (G7_IO3)  
        .equ TSC_G7_IO2_Shift, 25   @ bitWidth 1 (G7_IO2)  
        .equ TSC_G7_IO1_Shift, 24   @ bitWidth 1 (G7_IO1)  
        .equ TSC_G6_IO4_Shift, 23   @ bitWidth 1 (G6_IO4)  
        .equ TSC_G6_IO3_Shift, 22   @ bitWidth 1 (G6_IO3)  
        .equ TSC_G6_IO2_Shift, 21   @ bitWidth 1 (G6_IO2)  
        .equ TSC_G6_IO1_Shift, 20   @ bitWidth 1 (G6_IO1)  
        .equ TSC_G5_IO4_Shift, 19   @ bitWidth 1 (G5_IO4)  
        .equ TSC_G5_IO3_Shift, 18   @ bitWidth 1 (G5_IO3)  
        .equ TSC_G5_IO2_Shift, 17   @ bitWidth 1 (G5_IO2)  
        .equ TSC_G5_IO1_Shift, 16   @ bitWidth 1 (G5_IO1)  
        .equ TSC_G4_IO4_Shift, 15   @ bitWidth 1 (G4_IO4)  
        .equ TSC_G4_IO3_Shift, 14   @ bitWidth 1 (G4_IO3)  
        .equ TSC_G4_IO2_Shift, 13   @ bitWidth 1 (G4_IO2)  
        .equ TSC_G4_IO1_Shift, 12   @ bitWidth 1 (G4_IO1)  
        .equ TSC_G3_IO4_Shift, 11   @ bitWidth 1 (G3_IO4)  
        .equ TSC_G3_IO3_Shift, 10   @ bitWidth 1 (G3_IO3)  
        .equ TSC_G3_IO2_Shift, 9   @ bitWidth 1 (G3_IO2)  
        .equ TSC_G3_IO1_Shift, 8   @ bitWidth 1 (G3_IO1)  
        .equ TSC_G2_IO4_Shift, 7   @ bitWidth 1 (G2_IO4)  
        .equ TSC_G2_IO3_Shift, 6   @ bitWidth 1 (G2_IO3)  
        .equ TSC_G2_IO2_Shift, 5   @ bitWidth 1 (G2_IO2)  
        .equ TSC_G2_IO1_Shift, 4   @ bitWidth 1 (G2_IO1)  
        .equ TSC_G1_IO4_Shift, 3   @ bitWidth 1 (G1_IO4)  
        .equ TSC_G1_IO3_Shift, 2   @ bitWidth 1 (G1_IO3)  
        .equ TSC_G1_IO2_Shift, 1   @ bitWidth 1 (G1_IO2)  
        .equ TSC_G1_IO1_Shift, 0   @ bitWidth 1 (G1_IO1)  
 
    .equ TSC_IOSCR, TSC_BASE + 0x20 @ (I/O sampling control register) 
        .equ TSC_G7_IO4_Shift, 27   @ bitWidth 1 (G7_IO4)  
        .equ TSC_G7_IO3_Shift, 26   @ bitWidth 1 (G7_IO3)  
        .equ TSC_G7_IO2_Shift, 25   @ bitWidth 1 (G7_IO2)  
        .equ TSC_G7_IO1_Shift, 24   @ bitWidth 1 (G7_IO1)  
        .equ TSC_G6_IO4_Shift, 23   @ bitWidth 1 (G6_IO4)  
        .equ TSC_G6_IO3_Shift, 22   @ bitWidth 1 (G6_IO3)  
        .equ TSC_G6_IO2_Shift, 21   @ bitWidth 1 (G6_IO2)  
        .equ TSC_G6_IO1_Shift, 20   @ bitWidth 1 (G6_IO1)  
        .equ TSC_G5_IO4_Shift, 19   @ bitWidth 1 (G5_IO4)  
        .equ TSC_G5_IO3_Shift, 18   @ bitWidth 1 (G5_IO3)  
        .equ TSC_G5_IO2_Shift, 17   @ bitWidth 1 (G5_IO2)  
        .equ TSC_G5_IO1_Shift, 16   @ bitWidth 1 (G5_IO1)  
        .equ TSC_G4_IO4_Shift, 15   @ bitWidth 1 (G4_IO4)  
        .equ TSC_G4_IO3_Shift, 14   @ bitWidth 1 (G4_IO3)  
        .equ TSC_G4_IO2_Shift, 13   @ bitWidth 1 (G4_IO2)  
        .equ TSC_G4_IO1_Shift, 12   @ bitWidth 1 (G4_IO1)  
        .equ TSC_G3_IO4_Shift, 11   @ bitWidth 1 (G3_IO4)  
        .equ TSC_G3_IO3_Shift, 10   @ bitWidth 1 (G3_IO3)  
        .equ TSC_G3_IO2_Shift, 9   @ bitWidth 1 (G3_IO2)  
        .equ TSC_G3_IO1_Shift, 8   @ bitWidth 1 (G3_IO1)  
        .equ TSC_G2_IO4_Shift, 7   @ bitWidth 1 (G2_IO4)  
        .equ TSC_G2_IO3_Shift, 6   @ bitWidth 1 (G2_IO3)  
        .equ TSC_G2_IO2_Shift, 5   @ bitWidth 1 (G2_IO2)  
        .equ TSC_G2_IO1_Shift, 4   @ bitWidth 1 (G2_IO1)  
        .equ TSC_G1_IO4_Shift, 3   @ bitWidth 1 (G1_IO4)  
        .equ TSC_G1_IO3_Shift, 2   @ bitWidth 1 (G1_IO3)  
        .equ TSC_G1_IO2_Shift, 1   @ bitWidth 1 (G1_IO2)  
        .equ TSC_G1_IO1_Shift, 0   @ bitWidth 1 (G1_IO1)  
 
    .equ TSC_IOCCR, TSC_BASE + 0x28 @ (I/O channel control register) 
        .equ TSC_G7_IO4_Shift, 27   @ bitWidth 1 (G7_IO4)  
        .equ TSC_G7_IO3_Shift, 26   @ bitWidth 1 (G7_IO3)  
        .equ TSC_G7_IO2_Shift, 25   @ bitWidth 1 (G7_IO2)  
        .equ TSC_G7_IO1_Shift, 24   @ bitWidth 1 (G7_IO1)  
        .equ TSC_G6_IO4_Shift, 23   @ bitWidth 1 (G6_IO4)  
        .equ TSC_G6_IO3_Shift, 22   @ bitWidth 1 (G6_IO3)  
        .equ TSC_G6_IO2_Shift, 21   @ bitWidth 1 (G6_IO2)  
        .equ TSC_G6_IO1_Shift, 20   @ bitWidth 1 (G6_IO1)  
        .equ TSC_G5_IO4_Shift, 19   @ bitWidth 1 (G5_IO4)  
        .equ TSC_G5_IO3_Shift, 18   @ bitWidth 1 (G5_IO3)  
        .equ TSC_G5_IO2_Shift, 17   @ bitWidth 1 (G5_IO2)  
        .equ TSC_G5_IO1_Shift, 16   @ bitWidth 1 (G5_IO1)  
        .equ TSC_G4_IO4_Shift, 15   @ bitWidth 1 (G4_IO4)  
        .equ TSC_G4_IO3_Shift, 14   @ bitWidth 1 (G4_IO3)  
        .equ TSC_G4_IO2_Shift, 13   @ bitWidth 1 (G4_IO2)  
        .equ TSC_G4_IO1_Shift, 12   @ bitWidth 1 (G4_IO1)  
        .equ TSC_G3_IO4_Shift, 11   @ bitWidth 1 (G3_IO4)  
        .equ TSC_G3_IO3_Shift, 10   @ bitWidth 1 (G3_IO3)  
        .equ TSC_G3_IO2_Shift, 9   @ bitWidth 1 (G3_IO2)  
        .equ TSC_G3_IO1_Shift, 8   @ bitWidth 1 (G3_IO1)  
        .equ TSC_G2_IO4_Shift, 7   @ bitWidth 1 (G2_IO4)  
        .equ TSC_G2_IO3_Shift, 6   @ bitWidth 1 (G2_IO3)  
        .equ TSC_G2_IO2_Shift, 5   @ bitWidth 1 (G2_IO2)  
        .equ TSC_G2_IO1_Shift, 4   @ bitWidth 1 (G2_IO1)  
        .equ TSC_G1_IO4_Shift, 3   @ bitWidth 1 (G1_IO4)  
        .equ TSC_G1_IO3_Shift, 2   @ bitWidth 1 (G1_IO3)  
        .equ TSC_G1_IO2_Shift, 1   @ bitWidth 1 (G1_IO2)  
        .equ TSC_G1_IO1_Shift, 0   @ bitWidth 1 (G1_IO1)  
 
    .equ TSC_IOGCSR, TSC_BASE + 0x30 @ (I/O group control status register) 
        .equ TSC_G7S_Shift, 22   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G6S_Shift, 21   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G5S_Shift, 20   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G4S_Shift, 19   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G3S_Shift, 18   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G2S_Shift, 17   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G1S_Shift, 16   @ bitWidth 1 (Analog I/O group x status)  
        .equ TSC_G7E_Shift, 6   @ bitWidth 1 (Analog I/O group x enable)  
        .equ TSC_G6E_Shift, 5   @ bitWidth 1 (Analog I/O group x enable)  
        .equ TSC_G5E_Shift, 4   @ bitWidth 1 (Analog I/O group x enable)  
        .equ TSC_G4E_Shift, 3   @ bitWidth 1 (Analog I/O group x enable)  
        .equ TSC_G3E_Shift, 2   @ bitWidth 1 (Analog I/O group x enable)  
        .equ TSC_G2E_Shift, 1   @ bitWidth 1 (Analog I/O group x enable)  
        .equ TSC_G1E_Shift, 0   @ bitWidth 1 (Analog I/O group x enable)  
 
    .equ TSC_IOG1CR, TSC_BASE + 0x34 @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 
    .equ TSC_IOG2CR, TSC_BASE + 0x38 @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 
    .equ TSC_IOG3CR, TSC_BASE + 0x3C @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 
    .equ TSC_IOG4CR, TSC_BASE + 0x40 @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 
    .equ TSC_IOG5CR, TSC_BASE + 0x44 @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 
    .equ TSC_IOG6CR, TSC_BASE + 0x48 @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 
    .equ TSC_IOG7CR, TSC_BASE + 0x4C @ (I/O group x counter register) 
        .equ TSC_CNT_Shift, 0   @ bitWidth 14 (Counter value)  
 

@=========================== IWDG ===========================@
.equ IWDG_BASE, 0x40003000 @ (Independent watchdog) 
    .equ IWDG_KR, IWDG_BASE + 0x0 @ (Key register) 
        .equ IWDG_KEY_Shift, 0   @ bitWidth 16 (Key value write only, read 0x0000)  
 
    .equ IWDG_PR, IWDG_BASE + 0x4 @ (Prescaler register) 
        .equ IWDG_PR_Shift, 0   @ bitWidth 3 (Prescaler divider)  
 
    .equ IWDG_RLR, IWDG_BASE + 0x8 @ (Reload register) 
        .equ IWDG_RL_Shift, 0   @ bitWidth 12 (Watchdog counter reload value)  
 
    .equ IWDG_SR, IWDG_BASE + 0xC @ (Status register) 
        .equ IWDG_WVU_Shift, 2   @ bitWidth 1 (Watchdog counter window value update)  
        .equ IWDG_RVU_Shift, 1   @ bitWidth 1 (Watchdog counter reload value update)  
        .equ IWDG_PVU_Shift, 0   @ bitWidth 1 (Watchdog prescaler value update)  
 
    .equ IWDG_WINR, IWDG_BASE + 0x10 @ (Window register) 
        .equ IWDG_WIN_Shift, 0   @ bitWidth 12 (Watchdog counter window value)  
 

@=========================== WWDG ===========================@
.equ WWDG_BASE, 0x40002C00 @ (System window watchdog) 
    .equ WWDG_CR, WWDG_BASE + 0x0 @ (Control register) 
        .equ WWDG_WDGA_Shift, 7   @ bitWidth 1 (Activation bit)  
        .equ WWDG_T_Shift, 0   @ bitWidth 7 (7-bit counter MSB to LSB)  
 
    .equ WWDG_CFR, WWDG_BASE + 0x4 @ (Configuration register) 
        .equ WWDG_WDGTB_Shift, 11   @ bitWidth 3 (Timer base)  
        .equ WWDG_EWI_Shift, 9   @ bitWidth 1 (Early wakeup interrupt)  
        .equ WWDG_W_Shift, 0   @ bitWidth 7 (7-bit window value)  
 
    .equ WWDG_SR, WWDG_BASE + 0x8 @ (Status register) 
        .equ WWDG_EWIF_Shift, 0   @ bitWidth 1 (Early wakeup interrupt flag)  
 

@=========================== COMP ===========================@
.equ COMP_BASE, 0x40010200 @ (Comparator instance 1) 
    .equ COMP_COMP1_CSR, COMP_BASE + 0x0 @ (Comparator control and status register) 
        .equ COMP_COMP1_EN_Shift, 0   @ bitWidth 1 (Comparator enable)  
        .equ COMP_COMP1_PWRMODE_Shift, 2   @ bitWidth 2 (Comparator power mode)  
        .equ COMP_COMP1_INMSEL_Shift, 4   @ bitWidth 3 (Comparator input minus selection)  
        .equ COMP_COMP1_INPSEL_Shift, 7   @ bitWidth 2 (Comparator input plus selection)  
        .equ COMP_COMP1_POLARITY_Shift, 15   @ bitWidth 1 (Comparator output polarity)  
        .equ COMP_COMP1_HYST_Shift, 16   @ bitWidth 2 (Comparator hysteresis)  
        .equ COMP_COMP1_BLANKING_Shift, 18   @ bitWidth 3 (Comparator blanking source)  
        .equ COMP_COMP1_BRGEN_Shift, 22   @ bitWidth 1 (Comparator voltage scaler enable)  
        .equ COMP_COMP1_SCALEN_Shift, 23   @ bitWidth 1 (Comparator scaler bridge enable)  
        .equ COMP_COMP1_INMESEL_Shift, 25   @ bitWidth 2 (Comparator input minus extended selection)  
        .equ COMP_COMP1_VALUE_Shift, 30   @ bitWidth 1 (Comparator output level)  
        .equ COMP_COMP1_LOCK_Shift, 31   @ bitWidth 1 (Comparator lock)  
 
    .equ COMP_COMP2_CSR, COMP_BASE + 0x4 @ (Comparator 2 control and status register) 
        .equ COMP_COMP2_EN_Shift, 0   @ bitWidth 1 (Comparator 2 enable bit)  
        .equ COMP_COMP2_PWRMODE_Shift, 2   @ bitWidth 2 (Power Mode of the comparator 2)  
        .equ COMP_COMP2_INMSEL_Shift, 4   @ bitWidth 2 (Comparator 2 input minus selection bits)  
        .equ COMP_COMP2_INPSEL_Shift, 7   @ bitWidth 2 (Comparator 1 input plus selection bit)  
        .equ COMP_COMP2_WINMODE_Shift, 9   @ bitWidth 1 (Windows mode selection bit)  
        .equ COMP_COMP2_POLARITY_Shift, 15   @ bitWidth 1 (Comparator 2 polarity selection bit)  
        .equ COMP_COMP2_HYST_Shift, 16   @ bitWidth 2 (Comparator 2 hysteresis selection bits)  
        .equ COMP_COMP2_BLANKING_Shift, 18   @ bitWidth 3 (Comparator 2 blanking source selection bits)  
        .equ COMP_COMP2_BRGEN_Shift, 22   @ bitWidth 1 (Scaler bridge enable)  
        .equ COMP_COMP2_SCALEN_Shift, 23   @ bitWidth 1 (Voltage scaler enable bit)  
        .equ COMP_COMP2_INMESEL_Shift, 25   @ bitWidth 2 (comparator 2 input minus extended selection bits.)  
        .equ COMP_COMP2_VALUE_Shift, 30   @ bitWidth 1 (Comparator 2 output status bit)  
        .equ COMP_COMP2_LOCK_Shift, 31   @ bitWidth 1 (CSR register lock bit)  
 

@=========================== I2C1 ===========================@
.equ I2C1_BASE, 0x40005400 @ (Inter-integrated circuit) 
    .equ I2C1_CR1, I2C1_BASE + 0x0 @ (Control register 1) 
        .equ I2C1_PE_Shift, 0   @ bitWidth 1 (Peripheral enable)  
        .equ I2C1_TXIE_Shift, 1   @ bitWidth 1 (TX Interrupt enable)  
        .equ I2C1_RXIE_Shift, 2   @ bitWidth 1 (RX Interrupt enable)  
        .equ I2C1_ADDRIE_Shift, 3   @ bitWidth 1 (Address match interrupt enable slave only)  
        .equ I2C1_NACKIE_Shift, 4   @ bitWidth 1 (Not acknowledge received interrupt enable)  
        .equ I2C1_STOPIE_Shift, 5   @ bitWidth 1 (STOP detection Interrupt enable)  
        .equ I2C1_TCIE_Shift, 6   @ bitWidth 1 (Transfer Complete interrupt enable)  
        .equ I2C1_ERRIE_Shift, 7   @ bitWidth 1 (Error interrupts enable)  
        .equ I2C1_DNF_Shift, 8   @ bitWidth 4 (Digital noise filter)  
        .equ I2C1_ANFOFF_Shift, 12   @ bitWidth 1 (Analog noise filter OFF)  
        .equ I2C1_TXDMAEN_Shift, 14   @ bitWidth 1 (DMA transmission requests enable)  
        .equ I2C1_RXDMAEN_Shift, 15   @ bitWidth 1 (DMA reception requests enable)  
        .equ I2C1_SBC_Shift, 16   @ bitWidth 1 (Slave byte control)  
        .equ I2C1_NOSTRETCH_Shift, 17   @ bitWidth 1 (Clock stretching disable)  
        .equ I2C1_WUPEN_Shift, 18   @ bitWidth 1 (Wakeup from STOP enable)  
        .equ I2C1_GCEN_Shift, 19   @ bitWidth 1 (General call enable)  
        .equ I2C1_SMBHEN_Shift, 20   @ bitWidth 1 (SMBus Host address enable)  
        .equ I2C1_SMBDEN_Shift, 21   @ bitWidth 1 (SMBus Device Default address enable)  
        .equ I2C1_ALERTEN_Shift, 22   @ bitWidth 1 (SMBUS alert enable)  
        .equ I2C1_PECEN_Shift, 23   @ bitWidth 1 (PEC enable)  
 
    .equ I2C1_CR2, I2C1_BASE + 0x4 @ (Control register 2) 
        .equ I2C1_PECBYTE_Shift, 26   @ bitWidth 1 (Packet error checking byte)  
        .equ I2C1_AUTOEND_Shift, 25   @ bitWidth 1 (Automatic end mode master mode)  
        .equ I2C1_RELOAD_Shift, 24   @ bitWidth 1 (NBYTES reload mode)  
        .equ I2C1_NBYTES_Shift, 16   @ bitWidth 8 (Number of bytes)  
        .equ I2C1_NACK_Shift, 15   @ bitWidth 1 (NACK generation slave mode)  
        .equ I2C1_STOP_Shift, 14   @ bitWidth 1 (Stop generation master mode)  
        .equ I2C1_START_Shift, 13   @ bitWidth 1 (Start generation)  
        .equ I2C1_HEAD10R_Shift, 12   @ bitWidth 1 (10-bit address header only read direction master receiver mode)  
        .equ I2C1_ADD10_Shift, 11   @ bitWidth 1 (10-bit addressing mode master mode)  
        .equ I2C1_RD_WRN_Shift, 10   @ bitWidth 1 (Transfer direction master mode)  
        .equ I2C1_SADD_Shift, 0   @ bitWidth 10 (Slave address bit master mode)  
 
    .equ I2C1_OAR1, I2C1_BASE + 0x8 @ (Own address register 1) 
        .equ I2C1_OA1_Shift, 0   @ bitWidth 10 (Interface address)  
        .equ I2C1_OA1MODE_Shift, 10   @ bitWidth 1 (Own Address 1 10-bit mode)  
        .equ I2C1_OA1EN_Shift, 15   @ bitWidth 1 (Own Address 1 enable)  
 
    .equ I2C1_OAR2, I2C1_BASE + 0xC @ (Own address register 2) 
        .equ I2C1_OA2_Shift, 1   @ bitWidth 7 (Interface address)  
        .equ I2C1_OA2MSK_Shift, 8   @ bitWidth 3 (Own Address 2 masks)  
        .equ I2C1_OA2EN_Shift, 15   @ bitWidth 1 (Own Address 2 enable)  
 
    .equ I2C1_TIMINGR, I2C1_BASE + 0x10 @ (Timing register) 
        .equ I2C1_SCLL_Shift, 0   @ bitWidth 8 (SCL low period master mode)  
        .equ I2C1_SCLH_Shift, 8   @ bitWidth 8 (SCL high period master mode)  
        .equ I2C1_SDADEL_Shift, 16   @ bitWidth 4 (Data hold time)  
        .equ I2C1_SCLDEL_Shift, 20   @ bitWidth 4 (Data setup time)  
        .equ I2C1_PRESC_Shift, 28   @ bitWidth 4 (Timing prescaler)  
 
    .equ I2C1_TIMEOUTR, I2C1_BASE + 0x14 @ (Status register 1) 
        .equ I2C1_TIMEOUTA_Shift, 0   @ bitWidth 12 (Bus timeout A)  
        .equ I2C1_TIDLE_Shift, 12   @ bitWidth 1 (Idle clock timeout detection)  
        .equ I2C1_TIMOUTEN_Shift, 15   @ bitWidth 1 (Clock timeout enable)  
        .equ I2C1_TIMEOUTB_Shift, 16   @ bitWidth 12 (Bus timeout B)  
        .equ I2C1_TEXTEN_Shift, 31   @ bitWidth 1 (Extended clock timeout enable)  
 
    .equ I2C1_ISR, I2C1_BASE + 0x18 @ (Interrupt and Status register) 
        .equ I2C1_ADDCODE_Shift, 17   @ bitWidth 7 (Address match code Slave mode)  
        .equ I2C1_DIR_Shift, 16   @ bitWidth 1 (Transfer direction Slave mode)  
        .equ I2C1_BUSY_Shift, 15   @ bitWidth 1 (Bus busy)  
        .equ I2C1_ALERT_Shift, 13   @ bitWidth 1 (SMBus alert)  
        .equ I2C1_TIMEOUT_Shift, 12   @ bitWidth 1 (Timeout or t_low detection flag)  
        .equ I2C1_PECERR_Shift, 11   @ bitWidth 1 (PEC Error in reception)  
        .equ I2C1_OVR_Shift, 10   @ bitWidth 1 (Overrun/Underrun slave mode)  
        .equ I2C1_ARLO_Shift, 9   @ bitWidth 1 (Arbitration lost)  
        .equ I2C1_BERR_Shift, 8   @ bitWidth 1 (Bus error)  
        .equ I2C1_TCR_Shift, 7   @ bitWidth 1 (Transfer Complete Reload)  
        .equ I2C1_TC_Shift, 6   @ bitWidth 1 (Transfer Complete master mode)  
        .equ I2C1_STOPF_Shift, 5   @ bitWidth 1 (Stop detection flag)  
        .equ I2C1_NACKF_Shift, 4   @ bitWidth 1 (Not acknowledge received flag)  
        .equ I2C1_ADDR_Shift, 3   @ bitWidth 1 (Address matched slave mode)  
        .equ I2C1_RXNE_Shift, 2   @ bitWidth 1 (Receive data register not empty receivers)  
        .equ I2C1_TXIS_Shift, 1   @ bitWidth 1 (Transmit interrupt status transmitters)  
        .equ I2C1_TXE_Shift, 0   @ bitWidth 1 (Transmit data register empty transmitters)  
 
    .equ I2C1_ICR, I2C1_BASE + 0x1C @ (Interrupt clear register) 
        .equ I2C1_ALERTCF_Shift, 13   @ bitWidth 1 (Alert flag clear)  
        .equ I2C1_TIMOUTCF_Shift, 12   @ bitWidth 1 (Timeout detection flag clear)  
        .equ I2C1_PECCF_Shift, 11   @ bitWidth 1 (PEC Error flag clear)  
        .equ I2C1_OVRCF_Shift, 10   @ bitWidth 1 (Overrun/Underrun flag clear)  
        .equ I2C1_ARLOCF_Shift, 9   @ bitWidth 1 (Arbitration lost flag clear)  
        .equ I2C1_BERRCF_Shift, 8   @ bitWidth 1 (Bus error flag clear)  
        .equ I2C1_STOPCF_Shift, 5   @ bitWidth 1 (Stop detection flag clear)  
        .equ I2C1_NACKCF_Shift, 4   @ bitWidth 1 (Not Acknowledge flag clear)  
        .equ I2C1_ADDRCF_Shift, 3   @ bitWidth 1 (Address Matched flag clear)  
 
    .equ I2C1_PECR, I2C1_BASE + 0x20 @ (PEC register) 
        .equ I2C1_PEC_Shift, 0   @ bitWidth 8 (Packet error checking register)  
 
    .equ I2C1_RXDR, I2C1_BASE + 0x24 @ (Receive data register) 
        .equ I2C1_RXDATA_Shift, 0   @ bitWidth 8 (8-bit receive data)  
 
    .equ I2C1_TXDR, I2C1_BASE + 0x28 @ (Transmit data register) 
        .equ I2C1_TXDATA_Shift, 0   @ bitWidth 8 (8-bit transmit data)  
 

@=========================== I2C3 ===========================@
.equ I2C3_BASE, 0x40005C00 @ (Inter-integrated circuit) 
    .equ I2C3_CR1, I2C3_BASE + 0x0 @ (Control register 1) 
        .equ I2C3_PE_Shift, 0   @ bitWidth 1 (Peripheral enable)  
        .equ I2C3_TXIE_Shift, 1   @ bitWidth 1 (TX Interrupt enable)  
        .equ I2C3_RXIE_Shift, 2   @ bitWidth 1 (RX Interrupt enable)  
        .equ I2C3_ADDRIE_Shift, 3   @ bitWidth 1 (Address match interrupt enable slave only)  
        .equ I2C3_NACKIE_Shift, 4   @ bitWidth 1 (Not acknowledge received interrupt enable)  
        .equ I2C3_STOPIE_Shift, 5   @ bitWidth 1 (STOP detection Interrupt enable)  
        .equ I2C3_TCIE_Shift, 6   @ bitWidth 1 (Transfer Complete interrupt enable)  
        .equ I2C3_ERRIE_Shift, 7   @ bitWidth 1 (Error interrupts enable)  
        .equ I2C3_DNF_Shift, 8   @ bitWidth 4 (Digital noise filter)  
        .equ I2C3_ANFOFF_Shift, 12   @ bitWidth 1 (Analog noise filter OFF)  
        .equ I2C3_TXDMAEN_Shift, 14   @ bitWidth 1 (DMA transmission requests enable)  
        .equ I2C3_RXDMAEN_Shift, 15   @ bitWidth 1 (DMA reception requests enable)  
        .equ I2C3_SBC_Shift, 16   @ bitWidth 1 (Slave byte control)  
        .equ I2C3_NOSTRETCH_Shift, 17   @ bitWidth 1 (Clock stretching disable)  
        .equ I2C3_WUPEN_Shift, 18   @ bitWidth 1 (Wakeup from STOP enable)  
        .equ I2C3_GCEN_Shift, 19   @ bitWidth 1 (General call enable)  
        .equ I2C3_SMBHEN_Shift, 20   @ bitWidth 1 (SMBus Host address enable)  
        .equ I2C3_SMBDEN_Shift, 21   @ bitWidth 1 (SMBus Device Default address enable)  
        .equ I2C3_ALERTEN_Shift, 22   @ bitWidth 1 (SMBUS alert enable)  
        .equ I2C3_PECEN_Shift, 23   @ bitWidth 1 (PEC enable)  
 
    .equ I2C3_CR2, I2C3_BASE + 0x4 @ (Control register 2) 
        .equ I2C3_PECBYTE_Shift, 26   @ bitWidth 1 (Packet error checking byte)  
        .equ I2C3_AUTOEND_Shift, 25   @ bitWidth 1 (Automatic end mode master mode)  
        .equ I2C3_RELOAD_Shift, 24   @ bitWidth 1 (NBYTES reload mode)  
        .equ I2C3_NBYTES_Shift, 16   @ bitWidth 8 (Number of bytes)  
        .equ I2C3_NACK_Shift, 15   @ bitWidth 1 (NACK generation slave mode)  
        .equ I2C3_STOP_Shift, 14   @ bitWidth 1 (Stop generation master mode)  
        .equ I2C3_START_Shift, 13   @ bitWidth 1 (Start generation)  
        .equ I2C3_HEAD10R_Shift, 12   @ bitWidth 1 (10-bit address header only read direction master receiver mode)  
        .equ I2C3_ADD10_Shift, 11   @ bitWidth 1 (10-bit addressing mode master mode)  
        .equ I2C3_RD_WRN_Shift, 10   @ bitWidth 1 (Transfer direction master mode)  
        .equ I2C3_SADD_Shift, 0   @ bitWidth 10 (Slave address bit master mode)  
 
    .equ I2C3_OAR1, I2C3_BASE + 0x8 @ (Own address register 1) 
        .equ I2C3_OA1_Shift, 0   @ bitWidth 10 (Interface address)  
        .equ I2C3_OA1MODE_Shift, 10   @ bitWidth 1 (Own Address 1 10-bit mode)  
        .equ I2C3_OA1EN_Shift, 15   @ bitWidth 1 (Own Address 1 enable)  
 
    .equ I2C3_OAR2, I2C3_BASE + 0xC @ (Own address register 2) 
        .equ I2C3_OA2_Shift, 1   @ bitWidth 7 (Interface address)  
        .equ I2C3_OA2MSK_Shift, 8   @ bitWidth 3 (Own Address 2 masks)  
        .equ I2C3_OA2EN_Shift, 15   @ bitWidth 1 (Own Address 2 enable)  
 
    .equ I2C3_TIMINGR, I2C3_BASE + 0x10 @ (Timing register) 
        .equ I2C3_SCLL_Shift, 0   @ bitWidth 8 (SCL low period master mode)  
        .equ I2C3_SCLH_Shift, 8   @ bitWidth 8 (SCL high period master mode)  
        .equ I2C3_SDADEL_Shift, 16   @ bitWidth 4 (Data hold time)  
        .equ I2C3_SCLDEL_Shift, 20   @ bitWidth 4 (Data setup time)  
        .equ I2C3_PRESC_Shift, 28   @ bitWidth 4 (Timing prescaler)  
 
    .equ I2C3_TIMEOUTR, I2C3_BASE + 0x14 @ (Status register 1) 
        .equ I2C3_TIMEOUTA_Shift, 0   @ bitWidth 12 (Bus timeout A)  
        .equ I2C3_TIDLE_Shift, 12   @ bitWidth 1 (Idle clock timeout detection)  
        .equ I2C3_TIMOUTEN_Shift, 15   @ bitWidth 1 (Clock timeout enable)  
        .equ I2C3_TIMEOUTB_Shift, 16   @ bitWidth 12 (Bus timeout B)  
        .equ I2C3_TEXTEN_Shift, 31   @ bitWidth 1 (Extended clock timeout enable)  
 
    .equ I2C3_ISR, I2C3_BASE + 0x18 @ (Interrupt and Status register) 
        .equ I2C3_ADDCODE_Shift, 17   @ bitWidth 7 (Address match code Slave mode)  
        .equ I2C3_DIR_Shift, 16   @ bitWidth 1 (Transfer direction Slave mode)  
        .equ I2C3_BUSY_Shift, 15   @ bitWidth 1 (Bus busy)  
        .equ I2C3_ALERT_Shift, 13   @ bitWidth 1 (SMBus alert)  
        .equ I2C3_TIMEOUT_Shift, 12   @ bitWidth 1 (Timeout or t_low detection flag)  
        .equ I2C3_PECERR_Shift, 11   @ bitWidth 1 (PEC Error in reception)  
        .equ I2C3_OVR_Shift, 10   @ bitWidth 1 (Overrun/Underrun slave mode)  
        .equ I2C3_ARLO_Shift, 9   @ bitWidth 1 (Arbitration lost)  
        .equ I2C3_BERR_Shift, 8   @ bitWidth 1 (Bus error)  
        .equ I2C3_TCR_Shift, 7   @ bitWidth 1 (Transfer Complete Reload)  
        .equ I2C3_TC_Shift, 6   @ bitWidth 1 (Transfer Complete master mode)  
        .equ I2C3_STOPF_Shift, 5   @ bitWidth 1 (Stop detection flag)  
        .equ I2C3_NACKF_Shift, 4   @ bitWidth 1 (Not acknowledge received flag)  
        .equ I2C3_ADDR_Shift, 3   @ bitWidth 1 (Address matched slave mode)  
        .equ I2C3_RXNE_Shift, 2   @ bitWidth 1 (Receive data register not empty receivers)  
        .equ I2C3_TXIS_Shift, 1   @ bitWidth 1 (Transmit interrupt status transmitters)  
        .equ I2C3_TXE_Shift, 0   @ bitWidth 1 (Transmit data register empty transmitters)  
 
    .equ I2C3_ICR, I2C3_BASE + 0x1C @ (Interrupt clear register) 
        .equ I2C3_ALERTCF_Shift, 13   @ bitWidth 1 (Alert flag clear)  
        .equ I2C3_TIMOUTCF_Shift, 12   @ bitWidth 1 (Timeout detection flag clear)  
        .equ I2C3_PECCF_Shift, 11   @ bitWidth 1 (PEC Error flag clear)  
        .equ I2C3_OVRCF_Shift, 10   @ bitWidth 1 (Overrun/Underrun flag clear)  
        .equ I2C3_ARLOCF_Shift, 9   @ bitWidth 1 (Arbitration lost flag clear)  
        .equ I2C3_BERRCF_Shift, 8   @ bitWidth 1 (Bus error flag clear)  
        .equ I2C3_STOPCF_Shift, 5   @ bitWidth 1 (Stop detection flag clear)  
        .equ I2C3_NACKCF_Shift, 4   @ bitWidth 1 (Not Acknowledge flag clear)  
        .equ I2C3_ADDRCF_Shift, 3   @ bitWidth 1 (Address Matched flag clear)  
 
    .equ I2C3_PECR, I2C3_BASE + 0x20 @ (PEC register) 
        .equ I2C3_PEC_Shift, 0   @ bitWidth 8 (Packet error checking register)  
 
    .equ I2C3_RXDR, I2C3_BASE + 0x24 @ (Receive data register) 
        .equ I2C3_RXDATA_Shift, 0   @ bitWidth 8 (8-bit receive data)  
 
    .equ I2C3_TXDR, I2C3_BASE + 0x28 @ (Transmit data register) 
        .equ I2C3_TXDATA_Shift, 0   @ bitWidth 8 (8-bit transmit data)  
 

@=========================== Flash ===========================@
.equ Flash_BASE, 0x58004000 @ (Flash) 
    .equ Flash_ACR, Flash_BASE + 0x0 @ (Access control register) 
        .equ Flash_LATENCY_Shift, 0   @ bitWidth 3 (Latency)  
        .equ Flash_PRFTEN_Shift, 8   @ bitWidth 1 (Prefetch enable)  
        .equ Flash_ICEN_Shift, 9   @ bitWidth 1 (Instruction cache enable)  
        .equ Flash_DCEN_Shift, 10   @ bitWidth 1 (Data cache enable)  
        .equ Flash_ICRST_Shift, 11   @ bitWidth 1 (Instruction cache reset)  
        .equ Flash_DCRST_Shift, 12   @ bitWidth 1 (Data cache reset)  
        .equ Flash_PES_Shift, 15   @ bitWidth 1 (CPU1 CortexM4 program erase suspend request)  
        .equ Flash_EMPTY_Shift, 16   @ bitWidth 1 (Flash User area empty)  
 
    .equ Flash_KEYR, Flash_BASE + 0x8 @ (Flash key register) 
        .equ Flash_KEYR_Shift, 0   @ bitWidth 32 (KEYR)  
 
    .equ Flash_OPTKEYR, Flash_BASE + 0xC @ (Option byte key register) 
        .equ Flash_OPTKEYR_Shift, 0   @ bitWidth 32 (Option byte key)  
 
    .equ Flash_SR, Flash_BASE + 0x10 @ (Status register) 
        .equ Flash_EOP_Shift, 0   @ bitWidth 1 (End of operation)  
        .equ Flash_OPERR_Shift, 1   @ bitWidth 1 (Operation error)  
        .equ Flash_PROGERR_Shift, 3   @ bitWidth 1 (Programming error)  
        .equ Flash_WRPERR_Shift, 4   @ bitWidth 1 (Write protected error)  
        .equ Flash_PGAERR_Shift, 5   @ bitWidth 1 (Programming alignment error)  
        .equ Flash_SIZERR_Shift, 6   @ bitWidth 1 (Size error)  
        .equ Flash_PGSERR_Shift, 7   @ bitWidth 1 (Programming sequence error)  
        .equ Flash_MISERR_Shift, 8   @ bitWidth 1 (Fast programming data miss error)  
        .equ Flash_FASTERR_Shift, 9   @ bitWidth 1 (Fast programming error)  
        .equ Flash_OPTNV_Shift, 13   @ bitWidth 1 (User Option OPTVAL indication)  
        .equ Flash_RDERR_Shift, 14   @ bitWidth 1 (PCROP read error)  
        .equ Flash_OPTVERR_Shift, 15   @ bitWidth 1 (Option validity error)  
        .equ Flash_BSY_Shift, 16   @ bitWidth 1 (Busy)  
        .equ Flash_CFGBSY_Shift, 18   @ bitWidth 1 (Programming or erase configuration busy)  
        .equ Flash_PESD_Shift, 19   @ bitWidth 1 (Programming or erase operation suspended)  
 
    .equ Flash_CR, Flash_BASE + 0x14 @ (Flash control register) 
        .equ Flash_PG_Shift, 0   @ bitWidth 1 (Programming)  
        .equ Flash_PER_Shift, 1   @ bitWidth 1 (Page erase)  
        .equ Flash_MER_Shift, 2   @ bitWidth 1 (This bit triggers the mass erase all user pages when set)  
        .equ Flash_PNB_Shift, 3   @ bitWidth 8 (Page number selection)  
        .equ Flash_STRT_Shift, 16   @ bitWidth 1 (Start)  
        .equ Flash_OPTSTRT_Shift, 17   @ bitWidth 1 (Options modification start)  
        .equ Flash_FSTPG_Shift, 18   @ bitWidth 1 (Fast programming)  
        .equ Flash_EOPIE_Shift, 24   @ bitWidth 1 (End of operation interrupt enable)  
        .equ Flash_ERRIE_Shift, 25   @ bitWidth 1 (Error interrupt enable)  
        .equ Flash_RDERRIE_Shift, 26   @ bitWidth 1 (PCROP read error interrupt enable)  
        .equ Flash_OBL_LAUNCH_Shift, 27   @ bitWidth 1 (Force the option byte loading)  
        .equ Flash_OPTLOCK_Shift, 30   @ bitWidth 1 (Options Lock)  
        .equ Flash_LOCK_Shift, 31   @ bitWidth 1 (FLASH_CR Lock)  
 
    .equ Flash_ECCR, Flash_BASE + 0x18 @ (Flash ECC register) 
        .equ Flash_ADDR_ECC_Shift, 0   @ bitWidth 17 (ECC fail address)  
        .equ Flash_SYSF_ECC_Shift, 20   @ bitWidth 1 (System Flash ECC fail)  
        .equ Flash_ECCCIE_Shift, 24   @ bitWidth 1 (ECC correction interrupt enable)  
        .equ Flash_CPUID_Shift, 26   @ bitWidth 3 (CPU identification)  
        .equ Flash_ECCC_Shift, 30   @ bitWidth 1 (ECC correction)  
        .equ Flash_ECCD_Shift, 31   @ bitWidth 1 (ECC detection)  
 
    .equ Flash_OPTR, Flash_BASE + 0x20 @ (Flash option register) 
        .equ Flash_RDP_Shift, 0   @ bitWidth 8 (Read protection level)  
        .equ Flash_ESE_Shift, 8   @ bitWidth 1 (Security enabled)  
        .equ Flash_BOR_LEV_Shift, 9   @ bitWidth 3 (BOR reset Level)  
        .equ Flash_nRST_STOP_Shift, 12   @ bitWidth 1 (nRST_STOP)  
        .equ Flash_nRST_STDBY_Shift, 13   @ bitWidth 1 (nRST_STDBY)  
        .equ Flash_nRST_SHDW_Shift, 14   @ bitWidth 1 (nRST_SHDW)  
        .equ Flash_IDWG_SW_Shift, 16   @ bitWidth 1 (Independent watchdog selection)  
        .equ Flash_IWDG_STOP_Shift, 17   @ bitWidth 1 (Independent watchdog counter freeze in Stop mode)  
        .equ Flash_IWDG_STDBY_Shift, 18   @ bitWidth 1 (Independent watchdog counter freeze in Standby mode)  
        .equ Flash_WWDG_SW_Shift, 19   @ bitWidth 1 (Window watchdog selection)  
        .equ Flash_nBOOT1_Shift, 23   @ bitWidth 1 (Boot configuration)  
        .equ Flash_SRAM2_PE_Shift, 24   @ bitWidth 1 (SRAM2 parity check enable)  
        .equ Flash_SRAM2_RST_Shift, 25   @ bitWidth 1 (SRAM2 Erase when system reset)  
        .equ Flash_nSWBOOT0_Shift, 26   @ bitWidth 1 (Software Boot0)  
        .equ Flash_nBOOT0_Shift, 27   @ bitWidth 1 (nBoot0 option bit)  
        .equ Flash_AGC_TRIM_Shift, 29   @ bitWidth 3 (Radio Automatic Gain Control Trimming)  
 
    .equ Flash_PCROP1ASR, Flash_BASE + 0x24 @ (Flash Bank 1 PCROP Start address zone A register) 
        .equ Flash_PCROP1A_STRT_Shift, 0   @ bitWidth 9 (Bank 1 PCROPQ area start offset)  
 
    .equ Flash_PCROP1AER, Flash_BASE + 0x28 @ (Flash Bank 1 PCROP End address zone A register) 
        .equ Flash_PCROP1A_END_Shift, 0   @ bitWidth 9 (Bank 1 PCROP area end offset)  
        .equ Flash_PCROP_RDP_Shift, 31   @ bitWidth 1 (PCROP area preserved when RDP level decreased)  
 
    .equ Flash_WRP1AR, Flash_BASE + 0x2C @ (Flash Bank 1 WRP area A address register) 
        .equ Flash_WRP1A_STRT_Shift, 0   @ bitWidth 8 (Bank 1 WRP first area A start offset)  
        .equ Flash_WRP1A_END_Shift, 16   @ bitWidth 8 (Bank 1 WRP first area A end offset)  
 
    .equ Flash_WRP1BR, Flash_BASE + 0x30 @ (Flash Bank 1 WRP area B address register) 
        .equ Flash_WRP1B_STRT_Shift, 16   @ bitWidth 8 (Bank 1 WRP second area B end offset)  
        .equ Flash_WRP1B_END_Shift, 0   @ bitWidth 8 (Bank 1 WRP second area B start offset)  
 
    .equ Flash_PCROP1BSR, Flash_BASE + 0x34 @ (Flash Bank 1 PCROP Start address area B register) 
        .equ Flash_PCROP1B_STRT_Shift, 0   @ bitWidth 9 (Bank 1 PCROP area B start offset)  
 
    .equ Flash_PCROP1BER, Flash_BASE + 0x38 @ (Flash Bank 1 PCROP End address area B register) 
        .equ Flash_PCROP1B_END_Shift, 0   @ bitWidth 9 (Bank 1 PCROP area end area B offset)  
 
    .equ Flash_IPCCBR, Flash_BASE + 0x3C @ (IPCC mailbox data buffer address register) 
        .equ Flash_IPCCDBA_Shift, 0   @ bitWidth 14 (PCC mailbox data buffer base address)  
 
    .equ Flash_C2ACR, Flash_BASE + 0x5C @ (CPU2 cortex M0 access control register) 
        .equ Flash_PRFTEN_Shift, 8   @ bitWidth 1 (CPU2 cortex M0 prefetch enable)  
        .equ Flash_ICEN_Shift, 9   @ bitWidth 1 (CPU2 cortex M0 instruction cache enable)  
        .equ Flash_ICRST_Shift, 11   @ bitWidth 1 (CPU2 cortex M0 instruction cache reset)  
        .equ Flash_PES_Shift, 15   @ bitWidth 1 (CPU2 cortex M0 program erase suspend request)  
 
    .equ Flash_C2SR, Flash_BASE + 0x60 @ (CPU2 cortex M0 status register) 
        .equ Flash_EOP_Shift, 0   @ bitWidth 1 (End of operation)  
        .equ Flash_OPERR_Shift, 1   @ bitWidth 1 (Operation error)  
        .equ Flash_PROGERR_Shift, 3   @ bitWidth 1 (Programming error)  
        .equ Flash_WRPERR_Shift, 4   @ bitWidth 1 (write protection error)  
        .equ Flash_PGAERR_Shift, 5   @ bitWidth 1 (Programming alignment error)  
        .equ Flash_SIZERR_Shift, 6   @ bitWidth 1 (Size error)  
        .equ Flash_PGSERR_Shift, 7   @ bitWidth 1 (Programming sequence error)  
        .equ Flash_MISSERR_Shift, 8   @ bitWidth 1 (Fast programming data miss error)  
        .equ Flash_FASTERR_Shift, 9   @ bitWidth 1 (Fast programming error)  
        .equ Flash_RDERR_Shift, 14   @ bitWidth 1 (PCROP read error)  
        .equ Flash_BSY_Shift, 16   @ bitWidth 1 (Busy)  
        .equ Flash_CFGBSY_Shift, 18   @ bitWidth 1 (Programming or erase configuration busy)  
        .equ Flash_PESD_Shift, 19   @ bitWidth 1 (Programming or erase operation suspended)  
 
    .equ Flash_C2CR, Flash_BASE + 0x64 @ (CPU2 cortex M0 control register) 
        .equ Flash_PG_Shift, 0   @ bitWidth 1 (Programming)  
        .equ Flash_PER_Shift, 1   @ bitWidth 1 (Page erase)  
        .equ Flash_MER_Shift, 2   @ bitWidth 1 (Masse erase)  
        .equ Flash_PNB_Shift, 3   @ bitWidth 8 (Page Number selection)  
        .equ Flash_STRT_Shift, 16   @ bitWidth 1 (Start)  
        .equ Flash_FSTPG_Shift, 18   @ bitWidth 1 (Fast programming)  
        .equ Flash_EOPIE_Shift, 24   @ bitWidth 1 (End of operation interrupt enable)  
        .equ Flash_ERRIE_Shift, 25   @ bitWidth 1 (Error interrupt enable)  
        .equ Flash_RDERRIE_Shift, 26   @ bitWidth 1 (PCROP read error interrupt enable)  
 
    .equ Flash_SFR, Flash_BASE + 0x80 @ (Secure flash start address register) 
        .equ Flash_SFSA_Shift, 0   @ bitWidth 8 (Secure flash start address)  
        .equ Flash_DDS_Shift, 12   @ bitWidth 1 (Disable Cortex M0 debug access)  
        .equ Flash_FSD_Shift, 8   @ bitWidth 1 (Flash security disable)  
 
    .equ Flash_SRRVR, Flash_BASE + 0x84 @ (Secure SRAM2 start address and cortex M0 reset vector register) 
        .equ Flash_SBRV_Shift, 0   @ bitWidth 18 (cortex M0 access control register)  
        .equ Flash_SBRSA_Shift, 18   @ bitWidth 5 (Secure backup SRAM2a start address)  
        .equ Flash_BRSD_Shift, 23   @ bitWidth 1 (backup SRAM2a security disable)  
        .equ Flash_SNBRSA_Shift, 25   @ bitWidth 5 (Secure non backup SRAM2a start address)  
        .equ Flash_C2OPT_Shift, 31   @ bitWidth 1 (CPU2 cortex M0 boot reset vector memory selection)  
        .equ Flash_NBRSD_Shift, 30   @ bitWidth 1 (non-backup SRAM2b security disable)  
 

@=========================== QUADSPI ===========================@
.equ QUADSPI_BASE, 0xA0001000 @ (QuadSPI interface) 
    .equ QUADSPI_CR, QUADSPI_BASE + 0x0 @ (control register) 
        .equ QUADSPI_PRESCALER_Shift, 24   @ bitWidth 8 (Clock prescaler)  
        .equ QUADSPI_PMM_Shift, 23   @ bitWidth 1 (Polling match mode)  
        .equ QUADSPI_APMS_Shift, 22   @ bitWidth 1 (Automatic poll mode stop)  
        .equ QUADSPI_TOIE_Shift, 20   @ bitWidth 1 (TimeOut interrupt enable)  
        .equ QUADSPI_SMIE_Shift, 19   @ bitWidth 1 (Status match interrupt enable)  
        .equ QUADSPI_FTIE_Shift, 18   @ bitWidth 1 (FIFO threshold interrupt enable)  
        .equ QUADSPI_TCIE_Shift, 17   @ bitWidth 1 (Transfer complete interrupt enable)  
        .equ QUADSPI_TEIE_Shift, 16   @ bitWidth 1 (Transfer error interrupt enable)  
        .equ QUADSPI_FTHRES_Shift, 8   @ bitWidth 4 (FIFO threshold level)  
        .equ QUADSPI_SSHIFT_Shift, 4   @ bitWidth 1 (Sample shift)  
        .equ QUADSPI_TCEN_Shift, 3   @ bitWidth 1 (Timeout counter enable)  
        .equ QUADSPI_DMAEN_Shift, 2   @ bitWidth 1 (DMA enable)  
        .equ QUADSPI_ABORT_Shift, 1   @ bitWidth 1 (Abort request)  
        .equ QUADSPI_EN_Shift, 0   @ bitWidth 1 (Enable)  
 
    .equ QUADSPI_DCR, QUADSPI_BASE + 0x4 @ (device configuration register) 
        .equ QUADSPI_FSIZE_Shift, 16   @ bitWidth 5 (FLASH memory size)  
        .equ QUADSPI_CSHT_Shift, 8   @ bitWidth 3 (Chip select high time)  
        .equ QUADSPI_CKMODE_Shift, 0   @ bitWidth 1 (Mode 0 / mode 3)  
 
    .equ QUADSPI_SR, QUADSPI_BASE + 0x8 @ (status register) 
        .equ QUADSPI_FLEVEL_Shift, 8   @ bitWidth 5 (FIFO level)  
        .equ QUADSPI_BUSY_Shift, 5   @ bitWidth 1 (Busy)  
        .equ QUADSPI_TOF_Shift, 4   @ bitWidth 1 (Timeout flag)  
        .equ QUADSPI_SMF_Shift, 3   @ bitWidth 1 (Status match flag)  
        .equ QUADSPI_FTF_Shift, 2   @ bitWidth 1 (FIFO threshold flag)  
        .equ QUADSPI_TCF_Shift, 1   @ bitWidth 1 (Transfer complete flag)  
        .equ QUADSPI_TEF_Shift, 0   @ bitWidth 1 (Transfer error flag)  
 
    .equ QUADSPI_FCR, QUADSPI_BASE + 0xC @ (flag clear register) 
        .equ QUADSPI_CTOF_Shift, 4   @ bitWidth 1 (Clear timeout flag)  
        .equ QUADSPI_CSMF_Shift, 3   @ bitWidth 1 (Clear status match flag)  
        .equ QUADSPI_CTCF_Shift, 1   @ bitWidth 1 (Clear transfer complete flag)  
        .equ QUADSPI_CTEF_Shift, 0   @ bitWidth 1 (Clear transfer error flag)  
 
    .equ QUADSPI_DLR, QUADSPI_BASE + 0x10 @ (data length register) 
        .equ QUADSPI_DL_Shift, 0   @ bitWidth 32 (Data length)  
 
    .equ QUADSPI_CCR, QUADSPI_BASE + 0x14 @ (communication configuration register) 
        .equ QUADSPI_DDRM_Shift, 31   @ bitWidth 1 (Double data rate mode)  
        .equ QUADSPI_SIOO_Shift, 28   @ bitWidth 1 (Send instruction only once mode)  
        .equ QUADSPI_FMODE_Shift, 26   @ bitWidth 2 (Functional mode)  
        .equ QUADSPI_DMODE_Shift, 24   @ bitWidth 2 (Data mode)  
        .equ QUADSPI_DCYC_Shift, 18   @ bitWidth 5 (Number of dummy cycles)  
        .equ QUADSPI_ABSIZE_Shift, 16   @ bitWidth 2 (Alternate bytes size)  
        .equ QUADSPI_ABMODE_Shift, 14   @ bitWidth 2 (Alternate bytes mode)  
        .equ QUADSPI_ADSIZE_Shift, 12   @ bitWidth 2 (Address size)  
        .equ QUADSPI_ADMODE_Shift, 10   @ bitWidth 2 (Address mode)  
        .equ QUADSPI_IMODE_Shift, 8   @ bitWidth 2 (Instruction mode)  
        .equ QUADSPI_INSTRUCTION_Shift, 0   @ bitWidth 8 (Instruction)  
 
    .equ QUADSPI_AR, QUADSPI_BASE + 0x18 @ (address register) 
        .equ QUADSPI_ADDRESS_Shift, 0   @ bitWidth 32 (Address)  
 
    .equ QUADSPI_ABR, QUADSPI_BASE + 0x1C @ (ABR) 
        .equ QUADSPI_ALTERNATE_Shift, 0   @ bitWidth 32 (ALTERNATE)  
 
    .equ QUADSPI_DR, QUADSPI_BASE + 0x20 @ (data register) 
        .equ QUADSPI_DATA_Shift, 0   @ bitWidth 32 (Data)  
 
    .equ QUADSPI_PSMKR, QUADSPI_BASE + 0x24 @ (polling status mask register) 
        .equ QUADSPI_MASK_Shift, 0   @ bitWidth 32 (Status mask)  
 
    .equ QUADSPI_PSMAR, QUADSPI_BASE + 0x28 @ (polling status match register) 
        .equ QUADSPI_MATCH_Shift, 0   @ bitWidth 32 (Status match)  
 
    .equ QUADSPI_PIR, QUADSPI_BASE + 0x2C @ (polling interval register) 
        .equ QUADSPI_INTERVAL_Shift, 0   @ bitWidth 16 (Polling interval)  
 
    .equ QUADSPI_LPTR, QUADSPI_BASE + 0x30 @ (low-power timeout register) 
        .equ QUADSPI_TIMEOUT_Shift, 0   @ bitWidth 16 (Timeout period)  
 

@=========================== RCC ===========================@
.equ RCC_BASE, 0x58000000 @ (Reset and clock control) 
    .equ RCC_CR, RCC_BASE + 0x0 @ (Clock control register) 
        .equ RCC_PLLSAI1RDY_Shift, 27   @ bitWidth 1 (SAI1 PLL clock ready flag)  
        .equ RCC_PLLSAI1ON_Shift, 26   @ bitWidth 1 (SAI1 PLL enable)  
        .equ RCC_PLLRDY_Shift, 25   @ bitWidth 1 (Main PLL clock ready flag)  
        .equ RCC_PLLON_Shift, 24   @ bitWidth 1 (Main PLL enable)  
        .equ RCC_HSEPRE_Shift, 20   @ bitWidth 1 (HSE sysclk and PLL M divider prescaler)  
        .equ RCC_CSSON_Shift, 19   @ bitWidth 1 (HSE Clock security system enable)  
        .equ RCC_HSEBYP_Shift, 18   @ bitWidth 1 (HSE crystal oscillator bypass)  
        .equ RCC_HSERDY_Shift, 17   @ bitWidth 1 (HSE clock ready flag)  
        .equ RCC_HSEON_Shift, 16   @ bitWidth 1 (HSE clock enabled)  
        .equ RCC_HSIKERDY_Shift, 12   @ bitWidth 1 (HSI kernel clock ready flag for peripherals requests)  
        .equ RCC_HSIASFS_Shift, 11   @ bitWidth 1 (HSI automatic start from Stop)  
        .equ RCC_HSIRDY_Shift, 10   @ bitWidth 1 (HSI clock ready flag)  
        .equ RCC_HSIKERON_Shift, 9   @ bitWidth 1 (HSI always enable for peripheral kernels)  
        .equ RCC_HSION_Shift, 8   @ bitWidth 1 (HSI clock enabled)  
        .equ RCC_MSIRANGE_Shift, 4   @ bitWidth 4 (MSI clock ranges)  
        .equ RCC_MSIPLLEN_Shift, 2   @ bitWidth 1 (MSI clock PLL enable)  
        .equ RCC_MSIRDY_Shift, 1   @ bitWidth 1 (MSI clock ready flag)  
        .equ RCC_MSION_Shift, 0   @ bitWidth 1 (MSI clock enable)  
 
    .equ RCC_ICSCR, RCC_BASE + 0x4 @ (Internal clock sources calibration register) 
        .equ RCC_HSITRIM_Shift, 24   @ bitWidth 7 (HSI clock trimming)  
        .equ RCC_HSICAL_Shift, 16   @ bitWidth 8 (HSI clock calibration)  
        .equ RCC_MSITRIM_Shift, 8   @ bitWidth 8 (MSI clock trimming)  
        .equ RCC_MSICAL_Shift, 0   @ bitWidth 8 (MSI clock calibration)  
 
    .equ RCC_CFGR, RCC_BASE + 0x8 @ (Clock configuration register) 
        .equ RCC_MCOPRE_Shift, 28   @ bitWidth 3 (Microcontroller clock output prescaler)  
        .equ RCC_MCOSEL_Shift, 24   @ bitWidth 4 (Microcontroller clock output)  
        .equ RCC_PPRE2F_Shift, 18   @ bitWidth 1 (APB2 prescaler flag)  
        .equ RCC_PPRE1F_Shift, 17   @ bitWidth 1 (APB1 prescaler flag)  
        .equ RCC_HPREF_Shift, 16   @ bitWidth 1 (AHB prescaler flag)  
        .equ RCC_STOPWUCK_Shift, 15   @ bitWidth 1 (Wakeup from Stop and CSS backup clock selection)  
        .equ RCC_PPRE2_Shift, 11   @ bitWidth 3 (APB high-speed prescaler APB2)  
        .equ RCC_PPRE1_Shift, 8   @ bitWidth 3 (PB low-speed prescaler APB1)  
        .equ RCC_HPRE_Shift, 4   @ bitWidth 4 (AHB prescaler)  
        .equ RCC_SWS_Shift, 2   @ bitWidth 2 (System clock switch status)  
        .equ RCC_SW_Shift, 0   @ bitWidth 2 (System clock switch)  
 
    .equ RCC_PLLCFGR, RCC_BASE + 0xC @ (PLLSYS configuration register) 
        .equ RCC_PLLR_Shift, 29   @ bitWidth 3 (Main PLLSYS division factor R for SYSCLK system clock)  
        .equ RCC_PLLREN_Shift, 28   @ bitWidth 1 (Main PLLSYSR PLLCLK output enable)  
        .equ RCC_PLLQ_Shift, 25   @ bitWidth 3 (Main PLLSYS division factor Q for PLLSYSUSBCLK)  
        .equ RCC_PLLQEN_Shift, 24   @ bitWidth 1 (Main PLLSYSQ output enable)  
        .equ RCC_PLLP_Shift, 17   @ bitWidth 5 (Main PLL division factor P for PPLSYSSAICLK)  
        .equ RCC_PLLPEN_Shift, 16   @ bitWidth 1 (Main PLLSYSP output enable)  
        .equ RCC_PLLN_Shift, 8   @ bitWidth 7 (Main PLLSYS multiplication factor N)  
        .equ RCC_PLLM_Shift, 4   @ bitWidth 3 (Division factor M for the main PLL and audio PLL PLLSAI1 and PLLSAI2 input clock)  
        .equ RCC_PLLSRC_Shift, 0   @ bitWidth 2 (Main PLL, PLLSAI1 and PLLSAI2 entry clock source)  
 
    .equ RCC_PLLSAI1CFGR, RCC_BASE + 0x10 @ (PLLSAI1 configuration register) 
        .equ RCC_PLLR_Shift, 29   @ bitWidth 3 (PLLSAI division factor R for PLLADC1CLK ADC clock)  
        .equ RCC_PLLREN_Shift, 28   @ bitWidth 1 (PLLSAI PLLADC1CLK output enable)  
        .equ RCC_PLLQ_Shift, 25   @ bitWidth 3 (SAIPLL division factor Q for PLLSAIUSBCLK 48 MHz clock)  
        .equ RCC_PLLQEN_Shift, 24   @ bitWidth 1 (SAIPLL PLLSAIUSBCLK output enable)  
        .equ RCC_PLLP_Shift, 17   @ bitWidth 5 (SAI1PLL division factor P for PLLSAICLK SAI1clock)  
        .equ RCC_PLLPEN_Shift, 16   @ bitWidth 1 (SAIPLL PLLSAI1CLK output enable)  
        .equ RCC_PLLN_Shift, 8   @ bitWidth 7 (SAIPLL multiplication factor for VCO)  
 
    .equ RCC_CIER, RCC_BASE + 0x18 @ (Clock interrupt enable register) 
        .equ RCC_LSI2RDYIE_Shift, 11   @ bitWidth 1 (LSI2 ready interrupt enable)  
        .equ RCC_HSI48RDYIE_Shift, 10   @ bitWidth 1 (HSI48 ready interrupt enable)  
        .equ RCC_LSECSSIE_Shift, 9   @ bitWidth 1 (LSE clock security system interrupt enable)  
        .equ RCC_PLLSAI1RDYIE_Shift, 6   @ bitWidth 1 (PLLSAI1 ready interrupt enable)  
        .equ RCC_PLLRDYIE_Shift, 5   @ bitWidth 1 (PLLSYS ready interrupt enable)  
        .equ RCC_HSERDYIE_Shift, 4   @ bitWidth 1 (HSE ready interrupt enable)  
        .equ RCC_HSIRDYIE_Shift, 3   @ bitWidth 1 (HSI ready interrupt enable)  
        .equ RCC_MSIRDYIE_Shift, 2   @ bitWidth 1 (MSI ready interrupt enable)  
        .equ RCC_LSERDYIE_Shift, 1   @ bitWidth 1 (LSE ready interrupt enable)  
        .equ RCC_LSI1RDYIE_Shift, 0   @ bitWidth 1 (LSI1 ready interrupt enable)  
 
    .equ RCC_CIFR, RCC_BASE + 0x1C @ (Clock interrupt flag register) 
        .equ RCC_LSI2RDYF_Shift, 11   @ bitWidth 1 (LSI2 ready interrupt flag)  
        .equ RCC_HSI48RDYF_Shift, 10   @ bitWidth 1 (HSI48 ready interrupt flag)  
        .equ RCC_LSECSSF_Shift, 9   @ bitWidth 1 (LSE Clock security system interrupt flag)  
        .equ RCC_HSECSSF_Shift, 8   @ bitWidth 1 (HSE Clock security system interrupt flag)  
        .equ RCC_PLLSAI1RDYF_Shift, 6   @ bitWidth 1 (PLLSAI1 ready interrupt flag)  
        .equ RCC_PLLRDYF_Shift, 5   @ bitWidth 1 (PLL ready interrupt flag)  
        .equ RCC_HSERDYF_Shift, 4   @ bitWidth 1 (HSE ready interrupt flag)  
        .equ RCC_HSIRDYF_Shift, 3   @ bitWidth 1 (HSI ready interrupt flag)  
        .equ RCC_MSIRDYF_Shift, 2   @ bitWidth 1 (MSI ready interrupt flag)  
        .equ RCC_LSERDYF_Shift, 1   @ bitWidth 1 (LSE ready interrupt flag)  
        .equ RCC_LSI1RDYF_Shift, 0   @ bitWidth 1 (LSI1 ready interrupt flag)  
 
    .equ RCC_CICR, RCC_BASE + 0x20 @ (Clock interrupt clear register) 
        .equ RCC_LSI2RDYC_Shift, 11   @ bitWidth 1 (LSI2 ready interrupt clear)  
        .equ RCC_HSI48RDYC_Shift, 10   @ bitWidth 1 (HSI48 ready interrupt clear)  
        .equ RCC_LSECSSC_Shift, 9   @ bitWidth 1 (LSE Clock security system interrupt clear)  
        .equ RCC_HSECSSC_Shift, 8   @ bitWidth 1 (HSE Clock security system interrupt clear)  
        .equ RCC_PLLSAI1RDYC_Shift, 6   @ bitWidth 1 (PLLSAI1 ready interrupt clear)  
        .equ RCC_PLLRDYC_Shift, 5   @ bitWidth 1 (PLL ready interrupt clear)  
        .equ RCC_HSERDYC_Shift, 4   @ bitWidth 1 (HSE ready interrupt clear)  
        .equ RCC_HSIRDYC_Shift, 3   @ bitWidth 1 (HSI ready interrupt clear)  
        .equ RCC_MSIRDYC_Shift, 2   @ bitWidth 1 (MSI ready interrupt clear)  
        .equ RCC_LSERDYC_Shift, 1   @ bitWidth 1 (LSE ready interrupt clear)  
        .equ RCC_LSI1RDYC_Shift, 0   @ bitWidth 1 (LSI1 ready interrupt clear)  
 
    .equ RCC_SMPSCR, RCC_BASE + 0x24 @ (Step Down converter control register) 
        .equ RCC_SMPSSWS_Shift, 8   @ bitWidth 2 (Step Down converter clock switch status)  
        .equ RCC_SMPSDIV_Shift, 4   @ bitWidth 2 (Step Down converter clock prescaler)  
        .equ RCC_SMPSSEL_Shift, 0   @ bitWidth 2 (Step Down converter clock selection)  
 
    .equ RCC_AHB1RSTR, RCC_BASE + 0x28 @ (AHB1 peripheral reset register) 
        .equ RCC_TSCRST_Shift, 16   @ bitWidth 1 (Touch Sensing Controller reset)  
        .equ RCC_CRCRST_Shift, 12   @ bitWidth 1 (CRC reset)  
        .equ RCC_DMAMUXRST_Shift, 2   @ bitWidth 1 (DMAMUX reset)  
        .equ RCC_DMA2RST_Shift, 1   @ bitWidth 1 (DMA2 reset)  
        .equ RCC_DMA1RST_Shift, 0   @ bitWidth 1 (DMA1 reset)  
 
    .equ RCC_AHB2RSTR, RCC_BASE + 0x2C @ (AHB2 peripheral reset register) 
        .equ RCC_AES1RST_Shift, 16   @ bitWidth 1 (AES1 hardware accelerator reset)  
        .equ RCC_ADCRST_Shift, 13   @ bitWidth 1 (ADC reset)  
        .equ RCC_GPIOHRST_Shift, 7   @ bitWidth 1 (IO port H reset)  
        .equ RCC_GPIOERST_Shift, 4   @ bitWidth 1 (IO port E reset)  
        .equ RCC_GPIODRST_Shift, 3   @ bitWidth 1 (IO port D reset)  
        .equ RCC_GPIOCRST_Shift, 2   @ bitWidth 1 (IO port C reset)  
        .equ RCC_GPIOBRST_Shift, 1   @ bitWidth 1 (IO port B reset)  
        .equ RCC_GPIOARST_Shift, 0   @ bitWidth 1 (IO port A reset)  
 
    .equ RCC_AHB3RSTR, RCC_BASE + 0x30 @ (AHB3 peripheral reset register) 
        .equ RCC_FLASHRST_Shift, 25   @ bitWidth 1 (Flash interface reset)  
        .equ RCC_IPCCRST_Shift, 20   @ bitWidth 1 (IPCC interface reset)  
        .equ RCC_HSEMRST_Shift, 19   @ bitWidth 1 (HSEM interface reset)  
        .equ RCC_RNGRST_Shift, 18   @ bitWidth 1 (RNG interface reset)  
        .equ RCC_AES2RST_Shift, 17   @ bitWidth 1 (AES2 interface reset)  
        .equ RCC_PKARST_Shift, 16   @ bitWidth 1 (PKA interface reset)  
        .equ RCC_QSPIRST_Shift, 8   @ bitWidth 1 (Quad SPI memory interface reset)  
 
    .equ RCC_APB1RSTR1, RCC_BASE + 0x38 @ (APB1 peripheral reset register 1) 
        .equ RCC_LPTIM1RST_Shift, 31   @ bitWidth 1 (Low Power Timer 1 reset)  
        .equ RCC_USBFSRST_Shift, 26   @ bitWidth 1 (USB FS reset)  
        .equ RCC_CRSRST_Shift, 24   @ bitWidth 1 (CRS reset)  
        .equ RCC_I2C3RST_Shift, 23   @ bitWidth 1 (I2C3 reset)  
        .equ RCC_I2C1RST_Shift, 21   @ bitWidth 1 (I2C1 reset)  
        .equ RCC_SPI2RST_Shift, 14   @ bitWidth 1 (SPI2 reset)  
        .equ RCC_LCDRST_Shift, 9   @ bitWidth 1 (LCD interface reset)  
        .equ RCC_TIM2RST_Shift, 0   @ bitWidth 1 (TIM2 timer reset)  
 
    .equ RCC_APB1RSTR2, RCC_BASE + 0x3C @ (APB1 peripheral reset register 2) 
        .equ RCC_LPTIM2RST_Shift, 5   @ bitWidth 1 (Low-power timer 2 reset)  
        .equ RCC_LPUART1RST_Shift, 0   @ bitWidth 1 (Low-power UART 1 reset)  
 
    .equ RCC_APB2RSTR, RCC_BASE + 0x40 @ (APB2 peripheral reset register) 
        .equ RCC_SAI1RST_Shift, 21   @ bitWidth 1 (Serial audio interface 1 SAI1 reset)  
        .equ RCC_TIM17RST_Shift, 18   @ bitWidth 1 (TIM17 timer reset)  
        .equ RCC_TIM16RST_Shift, 17   @ bitWidth 1 (TIM16 timer reset)  
        .equ RCC_USART1RST_Shift, 14   @ bitWidth 1 (USART1 reset)  
        .equ RCC_SPI1RST_Shift, 12   @ bitWidth 1 (SPI1 reset)  
        .equ RCC_TIM1RST_Shift, 11   @ bitWidth 1 (TIM1 timer reset)  
 
    .equ RCC_APB3RSTR, RCC_BASE + 0x44 @ (APB3 peripheral reset register) 
        .equ RCC_RFRST_Shift, 0   @ bitWidth 1 (Radio system BLE reset)  
 
    .equ RCC_AHB1ENR, RCC_BASE + 0x48 @ (AHB1 peripheral clock enable register) 
        .equ RCC_TSCEN_Shift, 16   @ bitWidth 1 (Touch Sensing Controller clock enable)  
        .equ RCC_CRCEN_Shift, 12   @ bitWidth 1 (CPU1 CRC clock enable)  
        .equ RCC_DMAMUXEN_Shift, 2   @ bitWidth 1 (DMAMUX clock enable)  
        .equ RCC_DMA2EN_Shift, 1   @ bitWidth 1 (DMA2 clock enable)  
        .equ RCC_DMA1EN_Shift, 0   @ bitWidth 1 (DMA1 clock enable)  
 
    .equ RCC_AHB2ENR, RCC_BASE + 0x4C @ (AHB2 peripheral clock enable register) 
        .equ RCC_AES1EN_Shift, 16   @ bitWidth 1 (AES1 accelerator clock enable)  
        .equ RCC_ADCEN_Shift, 13   @ bitWidth 1 (ADC clock enable)  
        .equ RCC_GPIOHEN_Shift, 7   @ bitWidth 1 (IO port H clock enable)  
        .equ RCC_GPIOEEN_Shift, 4   @ bitWidth 1 (IO port E clock enable)  
        .equ RCC_GPIODEN_Shift, 3   @ bitWidth 1 (IO port D clock enable)  
        .equ RCC_GPIOCEN_Shift, 2   @ bitWidth 1 (IO port C clock enable)  
        .equ RCC_GPIOBEN_Shift, 1   @ bitWidth 1 (IO port B clock enable)  
        .equ RCC_GPIOAEN_Shift, 0   @ bitWidth 1 (IO port A clock enable)  
 
    .equ RCC_AHB3ENR, RCC_BASE + 0x50 @ (AHB3 peripheral clock enable register) 
        .equ RCC_FLASHEN_Shift, 25   @ bitWidth 1 (FLASHEN)  
        .equ RCC_IPCCEN_Shift, 20   @ bitWidth 1 (IPCCEN)  
        .equ RCC_HSEMEN_Shift, 19   @ bitWidth 1 (HSEMEN)  
        .equ RCC_RNGEN_Shift, 18   @ bitWidth 1 (RNGEN)  
        .equ RCC_AES2EN_Shift, 17   @ bitWidth 1 (AES2EN)  
        .equ RCC_PKAEN_Shift, 16   @ bitWidth 1 (PKAEN)  
        .equ RCC_QSPIEN_Shift, 8   @ bitWidth 1 (QSPIEN)  
 
    .equ RCC_APB1ENR1, RCC_BASE + 0x58 @ (APB1ENR1) 
        .equ RCC_LPTIM1EN_Shift, 31   @ bitWidth 1 (CPU1 Low power timer 1 clock enable)  
        .equ RCC_USBEN_Shift, 26   @ bitWidth 1 (CPU1 USB clock enable)  
        .equ RCC_CRSEN_Shift, 24   @ bitWidth 1 (CPU1 CRS clock enable)  
        .equ RCC_I2C3EN_Shift, 23   @ bitWidth 1 (CPU1 I2C3 clock enable)  
        .equ RCC_I2C1EN_Shift, 21   @ bitWidth 1 (CPU1 I2C1 clock enable)  
        .equ RCC_SPI2EN_Shift, 14   @ bitWidth 1 (CPU1 SPI2 clock enable)  
        .equ RCC_WWDGEN_Shift, 11   @ bitWidth 1 (CPU1 Window watchdog clock enable)  
        .equ RCC_RTCAPBEN_Shift, 10   @ bitWidth 1 (CPU1 RTC APB clock enable)  
        .equ RCC_LCDEN_Shift, 9   @ bitWidth 1 (CPU1 LCD clock enable)  
        .equ RCC_TIM2EN_Shift, 0   @ bitWidth 1 (CPU1 TIM2 timer clock enable)  
 
    .equ RCC_APB1ENR2, RCC_BASE + 0x5C @ (APB1 peripheral clock enable register 2) 
        .equ RCC_LPTIM2EN_Shift, 5   @ bitWidth 1 (CPU1 LPTIM2EN)  
        .equ RCC_LPUART1EN_Shift, 0   @ bitWidth 1 (CPU1 Low power UART 1 clock enable)  
 
    .equ RCC_APB2ENR, RCC_BASE + 0x60 @ (APB2ENR) 
        .equ RCC_SAI1EN_Shift, 21   @ bitWidth 1 (CPU1 SAI1 clock enable)  
        .equ RCC_TIM17EN_Shift, 18   @ bitWidth 1 (CPU1 TIM17 timer clock enable)  
        .equ RCC_TIM16EN_Shift, 17   @ bitWidth 1 (CPU1 TIM16 timer clock enable)  
        .equ RCC_USART1EN_Shift, 14   @ bitWidth 1 (CPU1 USART1clock enable)  
        .equ RCC_SPI1EN_Shift, 12   @ bitWidth 1 (CPU1 SPI1 clock enable)  
        .equ RCC_TIM1EN_Shift, 11   @ bitWidth 1 (CPU1 TIM1 timer clock enable)  
 
    .equ RCC_AHB1SMENR, RCC_BASE + 0x68 @ (AHB1 peripheral clocks enable in Sleep and Stop modes register) 
        .equ RCC_TSCSMEN_Shift, 16   @ bitWidth 1 (CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes)  
        .equ RCC_CRCSMEN_Shift, 12   @ bitWidth 1 (CPU1 CRCSMEN)  
        .equ RCC_SRAM1SMEN_Shift, 9   @ bitWidth 1 (CPU1 SRAM1 interface clocks enable during Sleep and Stop modes)  
        .equ RCC_DMAMUXSMEN_Shift, 2   @ bitWidth 1 (CPU1 DMAMUX clocks enable during Sleep and Stop modes)  
        .equ RCC_DMA2SMEN_Shift, 1   @ bitWidth 1 (CPU1 DMA2 clocks enable during Sleep and Stop modes)  
        .equ RCC_DMA1SMEN_Shift, 0   @ bitWidth 1 (CPU1 DMA1 clocks enable during Sleep and Stop modes)  
 
    .equ RCC_AHB2SMENR, RCC_BASE + 0x6C @ (AHB2 peripheral clocks enable in Sleep and Stop modes register) 
        .equ RCC_AES1SMEN_Shift, 16   @ bitWidth 1 (CPU1 AES1 accelerator clocks enable during Sleep and Stop modes)  
        .equ RCC_ADCFSSMEN_Shift, 13   @ bitWidth 1 (CPU1 ADC clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOHSMEN_Shift, 7   @ bitWidth 1 (CPU1 IO port H clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOESMEN_Shift, 4   @ bitWidth 1 (CPU1 IO port E clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIODSMEN_Shift, 3   @ bitWidth 1 (CPU1 IO port D clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOCSMEN_Shift, 2   @ bitWidth 1 (CPU1 IO port C clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOBSMEN_Shift, 1   @ bitWidth 1 (CPU1 IO port B clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOASMEN_Shift, 0   @ bitWidth 1 (CPU1 IO port A clocks enable during Sleep and Stop modes)  
 
    .equ RCC_AHB3SMENR, RCC_BASE + 0x70 @ (AHB3 peripheral clocks enable in Sleep and Stop modes register) 
        .equ RCC_FLASHSMEN_Shift, 25   @ bitWidth 1 (Flash interface clocks enable during CPU1 sleep mode)  
        .equ RCC_SRAM2SMEN_Shift, 24   @ bitWidth 1 (SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode)  
        .equ RCC_RNGSMEN_Shift, 18   @ bitWidth 1 (True RNG clocks enable during CPU1 sleep mode)  
        .equ RCC_AES2SMEN_Shift, 17   @ bitWidth 1 (AES2 accelerator clocks enable during CPU1 sleep mode)  
        .equ RCC_PKASMEN_Shift, 16   @ bitWidth 1 (PKA accelerator clocks enable during CPU1 sleep mode)  
        .equ RCC_QSPISMEN_Shift, 8   @ bitWidth 1 (QSPISMEN)  
 
    .equ RCC_APB1SMENR1, RCC_BASE + 0x78 @ (APB1SMENR1) 
        .equ RCC_LPTIM1SMEN_Shift, 31   @ bitWidth 1 (Low power timer 1 clocks enable during CPU1 Sleep mode)  
        .equ RCC_USBSMEN_Shift, 26   @ bitWidth 1 (USB FS clocks enable during CPU1 Sleep mode)  
        .equ RCC_CRSMEN_Shift, 24   @ bitWidth 1 (CRS clocks enable during CPU1 Sleep mode)  
        .equ RCC_I2C3SMEN_Shift, 23   @ bitWidth 1 (I2C3 clocks enable during CPU1 Sleep mode)  
        .equ RCC_I2C1SMEN_Shift, 21   @ bitWidth 1 (I2C1 clocks enable during CPU1 Sleep mode)  
        .equ RCC_SPI2SMEN_Shift, 14   @ bitWidth 1 (SPI2 clocks enable during CPU1 Sleep mode)  
        .equ RCC_WWDGSMEN_Shift, 11   @ bitWidth 1 (Window watchdog clocks enable during CPU1 Sleep mode)  
        .equ RCC_RTCAPBSMEN_Shift, 10   @ bitWidth 1 (RTC APB clocks enable during CPU1 Sleep mode)  
        .equ RCC_LCDSMEN_Shift, 9   @ bitWidth 1 (LCD clocks enable during CPU1 Sleep mode)  
        .equ RCC_TIM2SMEN_Shift, 0   @ bitWidth 1 (TIM2 timer clocks enable during CPU1 Sleep mode)  
 
    .equ RCC_APB1SMENR2, RCC_BASE + 0x7C @ (APB1 peripheral clocks enable in Sleep and Stop modes register 2) 
        .equ RCC_LPTIM2SMEN_Shift, 5   @ bitWidth 1 (Low power timer 2 clocks enable during CPU1 Sleep mode)  
        .equ RCC_LPUART1SMEN_Shift, 0   @ bitWidth 1 (Low power UART 1 clocks enable during CPU1 Sleep mode)  
 
    .equ RCC_APB2SMENR, RCC_BASE + 0x80 @ (APB2SMENR) 
        .equ RCC_SAI1SMEN_Shift, 21   @ bitWidth 1 (SAI1 clocks enable during CPU1 Sleep mode)  
        .equ RCC_TIM17SMEN_Shift, 18   @ bitWidth 1 (TIM17 timer clocks enable during CPU1 Sleep mode)  
        .equ RCC_TIM16SMEN_Shift, 17   @ bitWidth 1 (TIM16 timer clocks enable during CPU1 Sleep mode)  
        .equ RCC_USART1SMEN_Shift, 14   @ bitWidth 1 (USART1clocks enable during CPU1 Sleep mode)  
        .equ RCC_SPI1SMEN_Shift, 12   @ bitWidth 1 (SPI1 clocks enable during CPU1 Sleep mode)  
        .equ RCC_TIM1SMEN_Shift, 11   @ bitWidth 1 (TIM1 timer clocks enable during CPU1 Sleep mode)  
 
    .equ RCC_CCIPR, RCC_BASE + 0x88 @ (CCIPR) 
        .equ RCC_RNGSEL_Shift, 30   @ bitWidth 2 (RNG clock source selection)  
        .equ RCC_ADCSEL_Shift, 28   @ bitWidth 2 (ADCs clock source selection)  
        .equ RCC_CLK48SEL_Shift, 26   @ bitWidth 2 (48 MHz clock source selection)  
        .equ RCC_SAI1SEL_Shift, 22   @ bitWidth 2 (SAI1 clock source selection)  
        .equ RCC_LPTIM2SEL_Shift, 20   @ bitWidth 2 (Low power timer 2 clock source selection)  
        .equ RCC_LPTIM1SEL_Shift, 18   @ bitWidth 2 (Low power timer 1 clock source selection)  
        .equ RCC_I2C3SEL_Shift, 16   @ bitWidth 2 (I2C3 clock source selection)  
        .equ RCC_I2C1SEL_Shift, 12   @ bitWidth 2 (I2C1 clock source selection)  
        .equ RCC_LPUART1SEL_Shift, 10   @ bitWidth 2 (LPUART1 clock source selection)  
        .equ RCC_USART1SEL_Shift, 0   @ bitWidth 2 (USART1 clock source selection)  
 
    .equ RCC_BDCR, RCC_BASE + 0x90 @ (BDCR) 
        .equ RCC_LSCOSEL_Shift, 25   @ bitWidth 2 (Low speed clock output selection)  
        .equ RCC_LSCOEN_Shift, 24   @ bitWidth 1 (Low speed clock output enable)  
        .equ RCC_BDRST_Shift, 16   @ bitWidth 1 (Backup domain software reset)  
        .equ RCC_RTCEN_Shift, 15   @ bitWidth 1 (RTC clock enable)  
        .equ RCC_RTCSEL_Shift, 8   @ bitWidth 2 (RTC clock source selection)  
        .equ RCC_LSECSSD__Shift, 6   @ bitWidth 1 (CSS on LSE failure detection)  
        .equ RCC_LSECSSON_Shift, 5   @ bitWidth 1 (LSECSSON)  
        .equ RCC_LSEDRV_Shift, 3   @ bitWidth 2 (SE oscillator drive capability)  
        .equ RCC_LSEBYP_Shift, 2   @ bitWidth 1 (LSE oscillator bypass)  
        .equ RCC_LSERDY_Shift, 1   @ bitWidth 1 (LSE oscillator ready)  
        .equ RCC_LSEON_Shift, 0   @ bitWidth 1 (LSE oscillator enable)  
 
    .equ RCC_CSR, RCC_BASE + 0x94 @ (CSR) 
        .equ RCC_LPWRRSTF_Shift, 31   @ bitWidth 1 (Low-power reset flag)  
        .equ RCC_WWDGRSTF_Shift, 30   @ bitWidth 1 (Window watchdog reset flag)  
        .equ RCC_IWDGRSTF_Shift, 29   @ bitWidth 1 (Independent window watchdog reset flag)  
        .equ RCC_SFTRSTF_Shift, 28   @ bitWidth 1 (Software reset flag)  
        .equ RCC_BORRSTF_Shift, 27   @ bitWidth 1 (BOR flag)  
        .equ RCC_PINRSTF_Shift, 26   @ bitWidth 1 (Pin reset flag)  
        .equ RCC_OBLRSTF_Shift, 25   @ bitWidth 1 (Option byte loader reset flag)  
        .equ RCC_RMVF_Shift, 23   @ bitWidth 1 (Remove reset flag)  
        .equ RCC_RFWKPSEL_Shift, 14   @ bitWidth 2 (RF system wakeup clock source selection)  
        .equ RCC_LSI2BW_Shift, 8   @ bitWidth 4 (LSI2 oscillator bias configuration)  
        .equ RCC_LSI2TRIMOK_Shift, 5   @ bitWidth 1 (LSI2 oscillator trim OK)  
        .equ RCC_LSI2TRIMEN_Shift, 4   @ bitWidth 1 (LSI2 oscillator trimming enable)  
        .equ RCC_LSI2RDY_Shift, 3   @ bitWidth 1 (LSI2 oscillator ready)  
        .equ RCC_LSI2ON_Shift, 2   @ bitWidth 1 (LSI2 oscillator enabled)  
        .equ RCC_LSI1RDY_Shift, 1   @ bitWidth 1 (LSI1 oscillator ready)  
        .equ RCC_LSI1ON_Shift, 0   @ bitWidth 1 (LSI1 oscillator enabled)  
        .equ RCC_RFRSTS_Shift, 16   @ bitWidth 1 (Radio system BLE and 802.15.4 reset status)  
 
    .equ RCC_CRRCR, RCC_BASE + 0x98 @ (Clock recovery RC register) 
        .equ RCC_HSI48CAL_Shift, 7   @ bitWidth 9 (HSI48 clock calibration)  
        .equ RCC_HSI48RDY_Shift, 1   @ bitWidth 1 (HSI48 clock ready)  
        .equ RCC_HSI48ON_Shift, 0   @ bitWidth 1 (HSI48 oscillator enabled)  
 
    .equ RCC_HSECR, RCC_BASE + 0x9C @ (Clock HSE register) 
        .equ RCC_HSETUNE_Shift, 8   @ bitWidth 6 (HSE capacitor tuning)  
        .equ RCC_HSEGMC_Shift, 4   @ bitWidth 3 (HSE current control)  
        .equ RCC_HSES_Shift, 3   @ bitWidth 1 (HSE Sense amplifier threshold)  
        .equ RCC_UNLOCKED_Shift, 0   @ bitWidth 1 (Register lock system)  
 
    .equ RCC_EXTCFGR, RCC_BASE + 0x108 @ (Extended clock recovery register) 
        .equ RCC_RFCSS_Shift, 20   @ bitWidth 1 (RF clock source selected)  
        .equ RCC_C2HPREF_Shift, 17   @ bitWidth 1 (CPU2 AHB prescaler flag)  
        .equ RCC_SHDHPREF_Shift, 16   @ bitWidth 1 (Shared AHB prescaler flag)  
        .equ RCC_C2HPRE_Shift, 4   @ bitWidth 4 (CPU2 AHB prescaler)  
        .equ RCC_SHDHPRE_Shift, 0   @ bitWidth 4 (Shared AHB prescaler)  
 
    .equ RCC_C2AHB1ENR, RCC_BASE + 0x148 @ (CPU2 AHB1 peripheral clock enable register) 
        .equ RCC_TSCEN_Shift, 16   @ bitWidth 1 (CPU2 Touch Sensing Controller clock enable)  
        .equ RCC_CRCEN_Shift, 12   @ bitWidth 1 (CPU2 CRC clock enable)  
        .equ RCC_SRAM1EN_Shift, 9   @ bitWidth 1 (CPU2 SRAM1 clock enable)  
        .equ RCC_DMAMUXEN_Shift, 2   @ bitWidth 1 (CPU2 DMAMUX clock enable)  
        .equ RCC_DMA2EN_Shift, 1   @ bitWidth 1 (CPU2 DMA2 clock enable)  
        .equ RCC_DMA1EN_Shift, 0   @ bitWidth 1 (CPU2 DMA1 clock enable)  
 
    .equ RCC_C2AHB2ENR, RCC_BASE + 0x14C @ (CPU2 AHB2 peripheral clock enable register) 
        .equ RCC_AES1EN_Shift, 16   @ bitWidth 1 (CPU2 AES1 accelerator clock enable)  
        .equ RCC_ADCEN_Shift, 13   @ bitWidth 1 (CPU2 ADC clock enable)  
        .equ RCC_GPIOHEN_Shift, 7   @ bitWidth 1 (CPU2 IO port H clock enable)  
        .equ RCC_GPIOEEN_Shift, 4   @ bitWidth 1 (CPU2 IO port E clock enable)  
        .equ RCC_GPIODEN_Shift, 3   @ bitWidth 1 (CPU2 IO port D clock enable)  
        .equ RCC_GPIOCEN_Shift, 2   @ bitWidth 1 (CPU2 IO port C clock enable)  
        .equ RCC_GPIOBEN_Shift, 1   @ bitWidth 1 (CPU2 IO port B clock enable)  
        .equ RCC_GPIOAEN_Shift, 0   @ bitWidth 1 (CPU2 IO port A clock enable)  
 
    .equ RCC_C2AHB3ENR, RCC_BASE + 0x150 @ (CPU2 AHB3 peripheral clock enable register) 
        .equ RCC_FLASHEN_Shift, 25   @ bitWidth 1 (CPU2 FLASHEN)  
        .equ RCC_IPCCEN_Shift, 20   @ bitWidth 1 (CPU2 IPCCEN)  
        .equ RCC_HSEMEN_Shift, 19   @ bitWidth 1 (CPU2 HSEMEN)  
        .equ RCC_RNGEN_Shift, 18   @ bitWidth 1 (CPU2 RNGEN)  
        .equ RCC_AES2EN_Shift, 17   @ bitWidth 1 (CPU2 AES2EN)  
        .equ RCC_PKAEN_Shift, 16   @ bitWidth 1 (CPU2 PKAEN)  
 
    .equ RCC_C2APB1ENR1, RCC_BASE + 0x158 @ (CPU2 APB1ENR1) 
        .equ RCC_LPTIM1EN_Shift, 31   @ bitWidth 1 (CPU2 Low power timer 1 clock enable)  
        .equ RCC_USBEN_Shift, 26   @ bitWidth 1 (CPU2 USB clock enable)  
        .equ RCC_CRSEN_Shift, 24   @ bitWidth 1 (CPU2 CRS clock enable)  
        .equ RCC_I2C3EN_Shift, 23   @ bitWidth 1 (CPU2 I2C3 clock enable)  
        .equ RCC_I2C1EN_Shift, 21   @ bitWidth 1 (CPU2 I2C1 clock enable)  
        .equ RCC_SPI2EN_Shift, 14   @ bitWidth 1 (CPU2 SPI2 clock enable)  
        .equ RCC_RTCAPBEN_Shift, 10   @ bitWidth 1 (CPU2 RTC APB clock enable)  
        .equ RCC_LCDEN_Shift, 9   @ bitWidth 1 (CPU2 LCD clock enable)  
        .equ RCC_TIM2EN_Shift, 0   @ bitWidth 1 (CPU2 TIM2 timer clock enable)  
 
    .equ RCC_C2APB1ENR2, RCC_BASE + 0x15C @ (CPU2 APB1 peripheral clock enable register 2) 
        .equ RCC_LPTIM2EN_Shift, 5   @ bitWidth 1 (CPU2 LPTIM2EN)  
        .equ RCC_LPUART1EN_Shift, 0   @ bitWidth 1 (CPU2 Low power UART 1 clock enable)  
 
    .equ RCC_C2APB2ENR, RCC_BASE + 0x160 @ (CPU2 APB2ENR) 
        .equ RCC_SAI1EN_Shift, 21   @ bitWidth 1 (CPU2 SAI1 clock enable)  
        .equ RCC_TIM17EN_Shift, 18   @ bitWidth 1 (CPU2 TIM17 timer clock enable)  
        .equ RCC_TIM16EN_Shift, 17   @ bitWidth 1 (CPU2 TIM16 timer clock enable)  
        .equ RCC_USART1EN_Shift, 14   @ bitWidth 1 (CPU2 USART1clock enable)  
        .equ RCC_SPI1EN_Shift, 12   @ bitWidth 1 (CPU2 SPI1 clock enable)  
        .equ RCC_TIM1EN_Shift, 11   @ bitWidth 1 (CPU2 TIM1 timer clock enable)  
 
    .equ RCC_C2APB3ENR, RCC_BASE + 0x164 @ (CPU2 APB3ENR) 
        .equ RCC_EN802_Shift, 1   @ bitWidth 1 (CPU2 802.15.4 interface clock enable)  
        .equ RCC_BLEEN_Shift, 0   @ bitWidth 1 (CPU2 BLE interface clock enable)  
 
    .equ RCC_C2AHB1SMENR, RCC_BASE + 0x168 @ (CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register) 
        .equ RCC_TSCSMEN_Shift, 16   @ bitWidth 1 (CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes)  
        .equ RCC_CRCSMEN_Shift, 12   @ bitWidth 1 (CPU2 CRCSMEN)  
        .equ RCC_SRAM1SMEN_Shift, 9   @ bitWidth 1 (SRAM1 interface clock enable during CPU1 CSleep mode)  
        .equ RCC_DMAMUXSMEN_Shift, 2   @ bitWidth 1 (CPU2 DMAMUX clocks enable during Sleep and Stop modes)  
        .equ RCC_DMA2SMEN_Shift, 1   @ bitWidth 1 (CPU2 DMA2 clocks enable during Sleep and Stop modes)  
        .equ RCC_DMA1SMEN_Shift, 0   @ bitWidth 1 (CPU2 DMA1 clocks enable during Sleep and Stop modes)  
 
    .equ RCC_C2AHB2SMENR, RCC_BASE + 0x16C @ (CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register) 
        .equ RCC_AES1SMEN_Shift, 16   @ bitWidth 1 (CPU2 AES1 accelerator clocks enable during Sleep and Stop modes)  
        .equ RCC_ADCFSSMEN_Shift, 13   @ bitWidth 1 (CPU2 ADC clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOHSMEN_Shift, 7   @ bitWidth 1 (CPU2 IO port H clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOESMEN_Shift, 4   @ bitWidth 1 (CPU2 IO port E clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIODSMEN_Shift, 3   @ bitWidth 1 (CPU2 IO port D clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOCSMEN_Shift, 2   @ bitWidth 1 (CPU2 IO port C clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOBSMEN_Shift, 1   @ bitWidth 1 (CPU2 IO port B clocks enable during Sleep and Stop modes)  
        .equ RCC_GPIOASMEN_Shift, 0   @ bitWidth 1 (CPU2 IO port A clocks enable during Sleep and Stop modes)  
 
    .equ RCC_C2AHB3SMENR, RCC_BASE + 0x170 @ (CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register) 
        .equ RCC_FLASHSMEN_Shift, 25   @ bitWidth 1 (Flash interface clocks enable during CPU2 sleep modes)  
        .equ RCC_SRAM2SMEN_Shift, 24   @ bitWidth 1 (SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes)  
        .equ RCC_RNGSMEN_Shift, 18   @ bitWidth 1 (True RNG clocks enable during CPU2 sleep modes)  
        .equ RCC_AES2SMEN_Shift, 17   @ bitWidth 1 (AES2 accelerator clocks enable during CPU2 sleep modes)  
        .equ RCC_PKASMEN_Shift, 16   @ bitWidth 1 (PKA accelerator clocks enable during CPU2 sleep modes)  
 
    .equ RCC_C2APB1SMENR1, RCC_BASE + 0x178 @ (CPU2 APB1SMENR1) 
        .equ RCC_LPTIM1SMEN_Shift, 31   @ bitWidth 1 (Low power timer 1 clocks enable during CPU2 Sleep mode)  
        .equ RCC_USBSMEN_Shift, 26   @ bitWidth 1 (USB FS clocks enable during CPU2 Sleep mode)  
        .equ RCC_CRSMEN_Shift, 24   @ bitWidth 1 (CRS clocks enable during CPU2 Sleep mode)  
        .equ RCC_I2C3SMEN_Shift, 23   @ bitWidth 1 (I2C3 clocks enable during CPU2 Sleep mode)  
        .equ RCC_I2C1SMEN_Shift, 21   @ bitWidth 1 (I2C1 clocks enable during CPU2 Sleep mode)  
        .equ RCC_SPI2SMEN_Shift, 14   @ bitWidth 1 (SPI2 clocks enable during CPU2 Sleep mode)  
        .equ RCC_RTCAPBSMEN_Shift, 10   @ bitWidth 1 (RTC APB clocks enable during CPU2 Sleep mode)  
        .equ RCC_LCDSMEN_Shift, 9   @ bitWidth 1 (LCD clocks enable during CPU2 Sleep mode)  
        .equ RCC_TIM2SMEN_Shift, 0   @ bitWidth 1 (TIM2 timer clocks enable during CPU2 Sleep mode)  
 
    .equ RCC_C2APB1SMENR2, RCC_BASE + 0x17C @ (CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2) 
        .equ RCC_LPTIM2SMEN_Shift, 5   @ bitWidth 1 (Low power timer 2 clocks enable during CPU2 Sleep mode)  
        .equ RCC_LPUART1SMEN_Shift, 0   @ bitWidth 1 (Low power UART 1 clocks enable during CPU2 Sleep mode)  
 
    .equ RCC_C2APB2SMENR, RCC_BASE + 0x180 @ (CPU2 APB2SMENR) 
        .equ RCC_SAI1SMEN_Shift, 21   @ bitWidth 1 (SAI1 clocks enable during CPU2 Sleep mode)  
        .equ RCC_TIM17SMEN_Shift, 18   @ bitWidth 1 (TIM17 timer clocks enable during CPU2 Sleep mode)  
        .equ RCC_TIM16SMEN_Shift, 17   @ bitWidth 1 (TIM16 timer clocks enable during CPU2 Sleep mode)  
        .equ RCC_USART1SMEN_Shift, 14   @ bitWidth 1 (USART1clocks enable during CPU2 Sleep mode)  
        .equ RCC_SPI1SMEN_Shift, 12   @ bitWidth 1 (SPI1 clocks enable during CPU2 Sleep mode)  
        .equ RCC_TIM1SMEN_Shift, 11   @ bitWidth 1 (TIM1 timer clocks enable during CPU2 Sleep mode)  
 
    .equ RCC_C2APB3SMENR, RCC_BASE + 0x184 @ (CPU2 APB3SMENR) 
        .equ RCC_SMEN802_Shift, 1   @ bitWidth 1 (802.15.4 interface clocks enable during CPU2 Sleep modes)  
        .equ RCC_BLESMEN_Shift, 0   @ bitWidth 1 (BLE interface clocks enable during CPU2 Sleep mode)  
 

@=========================== PWR ===========================@
.equ PWR_BASE, 0x58000400 @ (Power control) 
    .equ PWR_CR1, PWR_BASE + 0x0 @ (Power control register 1) 
        .equ PWR_LPR_Shift, 14   @ bitWidth 1 (Low-power run)  
        .equ PWR_VOS_Shift, 9   @ bitWidth 2 (Voltage scaling range selection)  
        .equ PWR_DBP_Shift, 8   @ bitWidth 1 (Disable backup domain write protection)  
        .equ PWR_FPDS_Shift, 5   @ bitWidth 1 (Flash power down mode during LPsSleep for CPU1)  
        .equ PWR_FPDR_Shift, 4   @ bitWidth 1 (Flash power down mode during LPRun for CPU1)  
        .equ PWR_LPMS_Shift, 0   @ bitWidth 3 (Low-power mode selection for CPU1)  
 
    .equ PWR_CR2, PWR_BASE + 0x4 @ (Power control register 2) 
        .equ PWR_USV_Shift, 10   @ bitWidth 1 (VDDUSB USB supply valid)  
        .equ PWR_PVME3_Shift, 6   @ bitWidth 1 (Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V)  
        .equ PWR_PVME1_Shift, 4   @ bitWidth 1 (Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V)  
        .equ PWR_PLS_Shift, 1   @ bitWidth 3 (Power voltage detector level selection)  
        .equ PWR_PVDE_Shift, 0   @ bitWidth 1 (Power voltage detector enable)  
 
    .equ PWR_CR3, PWR_BASE + 0x8 @ (Power control register 3) 
        .equ PWR_EIWUL_Shift, 15   @ bitWidth 1 (Enable internal wakeup line for CPU1)  
        .equ PWR_EC2H_Shift, 14   @ bitWidth 1 (Enable CPU2 Hold interrupt for CPU1)  
        .equ PWR_E802A_Shift, 13   @ bitWidth 1 (Enable end of activity interrupt for CPU1)  
        .equ PWR_EBLEA_Shift, 11   @ bitWidth 1 (Enable BLE end of activity interrupt for CPU1)  
        .equ PWR_ECRPE_Shift, 12   @ bitWidth 1 (Enable critical radio phase end of activity interrupt for CPU1)  
        .equ PWR_APC_Shift, 10   @ bitWidth 1 (Apply pull-up and pull-down configuration)  
        .equ PWR_RRS_Shift, 9   @ bitWidth 1 (SRAM2a retention in Standby mode)  
        .equ PWR_EBORHSDFB_Shift, 8   @ bitWidth 1 (Enable BORH and Step Down counverter forced in Bypass interrups for CPU1)  
        .equ PWR_EWUP5_Shift, 4   @ bitWidth 1 (Enable Wakeup pin WKUP5)  
        .equ PWR_EWUP4_Shift, 3   @ bitWidth 1 (Enable Wakeup pin WKUP4)  
        .equ PWR_EWUP3_Shift, 2   @ bitWidth 1 (Enable Wakeup pin WKUP3)  
        .equ PWR_EWUP2_Shift, 1   @ bitWidth 1 (Enable Wakeup pin WKUP2)  
        .equ PWR_EWUP1_Shift, 0   @ bitWidth 1 (Enable Wakeup pin WKUP1)  
 
    .equ PWR_CR4, PWR_BASE + 0xC @ (Power control register 4) 
        .equ PWR_C2BOOT_Shift, 15   @ bitWidth 1 (BOOT CPU2 after reset or wakeup from Stop or Standby modes)  
        .equ PWR_VBRS_Shift, 9   @ bitWidth 1 (VBAT battery charging resistor selection)  
        .equ PWR_VBE_Shift, 8   @ bitWidth 1 (VBAT battery charging enable)  
        .equ PWR_WP5_Shift, 4   @ bitWidth 1 (Wakeup pin WKUP5 polarity)  
        .equ PWR_WP4_Shift, 3   @ bitWidth 1 (Wakeup pin WKUP4 polarity)  
        .equ PWR_WP3_Shift, 2   @ bitWidth 1 (Wakeup pin WKUP3 polarity)  
        .equ PWR_WP2_Shift, 1   @ bitWidth 1 (Wakeup pin WKUP2 polarity)  
        .equ PWR_WP1_Shift, 0   @ bitWidth 1 (Wakeup pin WKUP1 polarity)  
 
    .equ PWR_SR1, PWR_BASE + 0x10 @ (Power status register 1) 
        .equ PWR_WUFI_Shift, 15   @ bitWidth 1 (Internal Wakeup interrupt flag)  
        .equ PWR_C2HF_Shift, 14   @ bitWidth 1 (CPU2 Hold interrupt flag)  
        .equ PWR_AF802_Shift, 13   @ bitWidth 1 (802.15.4 end of activity interrupt flag)  
        .equ PWR_BLEAF_Shift, 12   @ bitWidth 1 (BLE end of activity interrupt flag)  
        .equ PWR_CRPEF_Shift, 11   @ bitWidth 1 (Enable critical radio phase end of activity interrupt flag)  
        .equ PWR_802WUF_Shift, 10   @ bitWidth 1 (802.15.4 wakeup interrupt flag)  
        .equ PWR_BLEWUF_Shift, 9   @ bitWidth 1 (BLE wakeup interrupt flag)  
        .equ PWR_BORHF_Shift, 8   @ bitWidth 1 (BORH interrupt flag)  
        .equ PWR_SDFBF_Shift, 7   @ bitWidth 1 (Step Down converter forced in Bypass interrupt flag)  
        .equ PWR_CWUF5_Shift, 4   @ bitWidth 1 (Wakeup flag 5)  
        .equ PWR_CWUF4_Shift, 3   @ bitWidth 1 (Wakeup flag 4)  
        .equ PWR_CWUF3_Shift, 2   @ bitWidth 1 (Wakeup flag 3)  
        .equ PWR_CWUF2_Shift, 1   @ bitWidth 1 (Wakeup flag 2)  
        .equ PWR_CWUF1_Shift, 0   @ bitWidth 1 (Wakeup flag 1)  
 
    .equ PWR_SR2, PWR_BASE + 0x14 @ (Power status register 2) 
        .equ PWR_PVMO3_Shift, 14   @ bitWidth 1 (Peripheral voltage monitoring output: VDDA vs. 1.62 V)  
        .equ PWR_PVMO1_Shift, 12   @ bitWidth 1 (Peripheral voltage monitoring output: VDDUSB vs. 1.2 V)  
        .equ PWR_PVDO_Shift, 11   @ bitWidth 1 (Power voltage detector output)  
        .equ PWR_VOSF_Shift, 10   @ bitWidth 1 (Voltage scaling flag)  
        .equ PWR_REGLPF_Shift, 9   @ bitWidth 1 (Low-power regulator flag)  
        .equ PWR_REGLPS_Shift, 8   @ bitWidth 1 (Low-power regulator started)  
        .equ PWR_SDSMPSF_Shift, 1   @ bitWidth 1 (Step Down converter SMPS mode flag)  
        .equ PWR_SDBF_Shift, 0   @ bitWidth 1 (Step Down converter Bypass mode flag)  
 
    .equ PWR_SCR, PWR_BASE + 0x18 @ (Power status clear register) 
        .equ PWR_CC2HF_Shift, 14   @ bitWidth 1 (Clear CPU2 Hold interrupt flag)  
        .equ PWR_C802AF_Shift, 13   @ bitWidth 1 (Clear 802.15.4 end of activity interrupt flag)  
        .equ PWR_CBLEAF_Shift, 12   @ bitWidth 1 (Clear BLE end of activity interrupt flag)  
        .equ PWR_CCRPEF_Shift, 11   @ bitWidth 1 (Clear critical radio phase end of activity interrupt flag)  
        .equ PWR_C802WUF_Shift, 10   @ bitWidth 1 (Clear 802.15.4 wakeup interrupt flag)  
        .equ PWR_CBLEWUF_Shift, 9   @ bitWidth 1 (Clear BLE wakeup interrupt flag)  
        .equ PWR_CBORHF_Shift, 8   @ bitWidth 1 (Clear BORH interrupt flag)  
        .equ PWR_CSMPSFBF_Shift, 7   @ bitWidth 1 (Clear SMPS Step Down converter forced in Bypass interrupt flag)  
        .equ PWR_CWUF5_Shift, 4   @ bitWidth 1 (Clear wakeup flag 5)  
        .equ PWR_CWUF4_Shift, 3   @ bitWidth 1 (Clear wakeup flag 4)  
        .equ PWR_CWUF3_Shift, 2   @ bitWidth 1 (Clear wakeup flag 3)  
        .equ PWR_CWUF2_Shift, 1   @ bitWidth 1 (Clear wakeup flag 2)  
        .equ PWR_CWUF1_Shift, 0   @ bitWidth 1 (Clear wakeup flag 1)  
 
    .equ PWR_CR5, PWR_BASE + 0x1C @ (Power control register 5) 
        .equ PWR_SDEB_Shift, 15   @ bitWidth 1 (Enable Step Down converter SMPS mode enabled)  
        .equ PWR_SDBEN_Shift, 14   @ bitWidth 1 (Enable Step Down converter Bypass mode enabled)  
        .equ PWR_SMPSCFG_Shift, 9   @ bitWidth 1 (VOS configuration selection non user)  
        .equ PWR_BORHC_Shift, 8   @ bitWidth 1 (BORH configuration selection)  
        .equ PWR_SDSC_Shift, 4   @ bitWidth 3 (Step Down converter supplt startup current selection)  
        .equ PWR_SDVOS_Shift, 0   @ bitWidth 4 (Step Down converter voltage output scaling)  
 
    .equ PWR_PUCRA, PWR_BASE + 0x20 @ (Power Port A pull-up control register) 
        .equ PWR_PU15_Shift, 15   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU13_Shift, 13   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU12_Shift, 12   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU11_Shift, 11   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU10_Shift, 10   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU9_Shift, 9   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU8_Shift, 8   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU7_Shift, 7   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU6_Shift, 6   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU5_Shift, 5   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU4_Shift, 4   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU3_Shift, 3   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU2_Shift, 2   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU1_Shift, 1   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
        .equ PWR_PU0_Shift, 0   @ bitWidth 1 (Port A pull-up bit y y=0..15)  
 
    .equ PWR_PDCRA, PWR_BASE + 0x24 @ (Power Port A pull-down control register) 
        .equ PWR_PD14_Shift, 14   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD12_Shift, 12   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD11_Shift, 11   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD10_Shift, 10   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD9_Shift, 9   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD8_Shift, 8   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD7_Shift, 7   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD6_Shift, 6   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD5_Shift, 5   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD4_Shift, 4   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD3_Shift, 3   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD2_Shift, 2   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD1_Shift, 1   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
        .equ PWR_PD0_Shift, 0   @ bitWidth 1 (Port A pull-down bit y y=0..15)  
 
    .equ PWR_PUCRB, PWR_BASE + 0x28 @ (Power Port B pull-up control register) 
        .equ PWR_PU15_Shift, 15   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU14_Shift, 14   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU13_Shift, 13   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU12_Shift, 12   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU11_Shift, 11   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU10_Shift, 10   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU9_Shift, 9   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU8_Shift, 8   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU7_Shift, 7   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU6_Shift, 6   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU5_Shift, 5   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU4_Shift, 4   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU3_Shift, 3   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU2_Shift, 2   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU1_Shift, 1   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
        .equ PWR_PU0_Shift, 0   @ bitWidth 1 (Port B pull-up bit y y=0..15)  
 
    .equ PWR_PDCRB, PWR_BASE + 0x2C @ (Power Port B pull-down control register) 
        .equ PWR_PD15_Shift, 15   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD14_Shift, 14   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD13_Shift, 13   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD12_Shift, 12   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD11_Shift, 11   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD10_Shift, 10   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD9_Shift, 9   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD8_Shift, 8   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD7_Shift, 7   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD6_Shift, 6   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD5_Shift, 5   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD3_Shift, 3   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD2_Shift, 2   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD1_Shift, 1   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
        .equ PWR_PD0_Shift, 0   @ bitWidth 1 (Port B pull-down bit y y=0..15)  
 
    .equ PWR_PUCRC, PWR_BASE + 0x30 @ (Power Port C pull-up control register) 
        .equ PWR_PU15_Shift, 15   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU14_Shift, 14   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU13_Shift, 13   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU12_Shift, 12   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU11_Shift, 11   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU10_Shift, 10   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU9_Shift, 9   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU8_Shift, 8   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU7_Shift, 7   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU6_Shift, 6   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU5_Shift, 5   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU4_Shift, 4   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU3_Shift, 3   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU2_Shift, 2   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU1_Shift, 1   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
        .equ PWR_PU0_Shift, 0   @ bitWidth 1 (Port C pull-up bit y y=0..15)  
 
    .equ PWR_PDCRC, PWR_BASE + 0x34 @ (Power Port C pull-down control register) 
        .equ PWR_PD15_Shift, 15   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD14_Shift, 14   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD13_Shift, 13   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD12_Shift, 12   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD11_Shift, 11   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD10_Shift, 10   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD9_Shift, 9   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD8_Shift, 8   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD7_Shift, 7   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD6_Shift, 6   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD5_Shift, 5   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD4_Shift, 4   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD3_Shift, 3   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD2_Shift, 2   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD1_Shift, 1   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
        .equ PWR_PD0_Shift, 0   @ bitWidth 1 (Port C pull-down bit y y=0..15)  
 
    .equ PWR_PUCRD, PWR_BASE + 0x38 @ (Power Port D pull-up control register) 
        .equ PWR_PU15_Shift, 15   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU14_Shift, 14   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU13_Shift, 13   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU12_Shift, 12   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU11_Shift, 11   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU10_Shift, 10   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU9_Shift, 9   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU8_Shift, 8   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU7_Shift, 7   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU6_Shift, 6   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU5_Shift, 5   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU4_Shift, 4   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU3_Shift, 3   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU2_Shift, 2   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU1_Shift, 1   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
        .equ PWR_PU0_Shift, 0   @ bitWidth 1 (Port D pull-up bit y y=0..15)  
 
    .equ PWR_PDCRD, PWR_BASE + 0x3C @ (Power Port D pull-down control register) 
        .equ PWR_PD15_Shift, 15   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD14_Shift, 14   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD13_Shift, 13   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD12_Shift, 12   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD11_Shift, 11   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD10_Shift, 10   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD9_Shift, 9   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD8_Shift, 8   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD7_Shift, 7   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD6_Shift, 6   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD5_Shift, 5   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD4_Shift, 4   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD3_Shift, 3   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD2_Shift, 2   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD1_Shift, 1   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
        .equ PWR_PD0_Shift, 0   @ bitWidth 1 (Port D pull-down bit y y=0..15)  
 
    .equ PWR_PUCRE, PWR_BASE + 0x40 @ (Power Port E pull-up control register) 
        .equ PWR_PU4_Shift, 4   @ bitWidth 1 (Port E pull-up bit y y=0..15)  
        .equ PWR_PU3_Shift, 3   @ bitWidth 1 (Port E pull-up bit y y=0..15)  
        .equ PWR_PU2_Shift, 2   @ bitWidth 1 (Port E pull-up bit y y=0..15)  
        .equ PWR_PU1_Shift, 1   @ bitWidth 1 (Port E pull-up bit y y=0..15)  
        .equ PWR_PU0_Shift, 0   @ bitWidth 1 (Port E pull-up bit y y=0..15)  
 
    .equ PWR_PDCRE, PWR_BASE + 0x44 @ (Power Port E pull-down control register) 
        .equ PWR_PD4_Shift, 4   @ bitWidth 1 (Port E pull-down bit y y=0..15)  
        .equ PWR_PD3_Shift, 3   @ bitWidth 1 (Port E pull-down bit y y=0..15)  
        .equ PWR_PD2_Shift, 2   @ bitWidth 1 (Port E pull-down bit y y=0..15)  
        .equ PWR_PD1_Shift, 1   @ bitWidth 1 (Port E pull-down bit y y=0..15)  
        .equ PWR_PD0_Shift, 0   @ bitWidth 1 (Port E pull-down bit y y=0..15)  
 
    .equ PWR_PUCRH, PWR_BASE + 0x58 @ (Power Port H pull-up control register) 
        .equ PWR_PU3_Shift, 3   @ bitWidth 1 (Port H pull-up bit y y=0..1)  
        .equ PWR_PU1_Shift, 1   @ bitWidth 1 (Port H pull-up bit y y=0..1)  
        .equ PWR_PU0_Shift, 0   @ bitWidth 1 (Port H pull-up bit y y=0..1)  
 
    .equ PWR_PDCRH, PWR_BASE + 0x5C @ (Power Port H pull-down control register) 
        .equ PWR_PD3_Shift, 3   @ bitWidth 1 (Port H pull-down bit y y=0..1)  
        .equ PWR_PD1_Shift, 1   @ bitWidth 1 (Port H pull-down bit y y=0..1)  
        .equ PWR_PD0_Shift, 0   @ bitWidth 1 (Port H pull-down bit y y=0..1)  
 
    .equ PWR_C2CR1, PWR_BASE + 0x80 @ (CPU2 Power control register 1) 
        .equ PWR_802EWKUP_Shift, 15   @ bitWidth 1 (802.15.4 external wakeup signal)  
        .equ PWR_BLEEWKUP_Shift, 14   @ bitWidth 1 (BLE external wakeup signal)  
        .equ PWR_FPDS_Shift, 5   @ bitWidth 1 (Flash power down mode during LPSleep for CPU2)  
        .equ PWR_FPDR_Shift, 4   @ bitWidth 1 (Flash power down mode during LPRun for CPU2)  
        .equ PWR_LPMS_Shift, 0   @ bitWidth 3 (Low-power mode selection for CPU2)  
 
    .equ PWR_C2CR3, PWR_BASE + 0x84 @ (CPU2 Power control register 3) 
        .equ PWR_EIWUL_Shift, 15   @ bitWidth 1 (Enable internal wakeup line for CPU2)  
        .equ PWR_APC_Shift, 12   @ bitWidth 1 (Apply pull-up and pull-down configuration for CPU2)  
        .equ PWR_E802WUP_Shift, 10   @ bitWidth 1 (Enable 802.15.4 host wakeup interrupt for CPU2)  
        .equ PWR_EBLEWUP_Shift, 9   @ bitWidth 1 (Enable BLE host wakeup interrupt for CPU2)  
        .equ PWR_EWUP5_Shift, 4   @ bitWidth 1 (Enable Wakeup pin WKUP5 for CPU2)  
        .equ PWR_EWUP4_Shift, 3   @ bitWidth 1 (Enable Wakeup pin WKUP4 for CPU2)  
        .equ PWR_EWUP3_Shift, 2   @ bitWidth 1 (Enable Wakeup pin WKUP3 for CPU2)  
        .equ PWR_EWUP2_Shift, 1   @ bitWidth 1 (Enable Wakeup pin WKUP2 for CPU2)  
        .equ PWR_EWUP1_Shift, 0   @ bitWidth 1 (Enable Wakeup pin WKUP1 for CPU2)  
 
    .equ PWR_EXTSCR, PWR_BASE + 0x88 @ (Power status clear register) 
        .equ PWR_C2DS_Shift, 15   @ bitWidth 1 (CPU2 deepsleep mode)  
        .equ PWR_C1DS_Shift, 14   @ bitWidth 1 (CPU1 deepsleep mode)  
        .equ PWR_CRPF_Shift, 13   @ bitWidth 1 (Critical Radio system phase)  
        .equ PWR_C2STOPF_Shift, 11   @ bitWidth 1 (System Stop flag for CPU2)  
        .equ PWR_C2SBF_Shift, 10   @ bitWidth 1 (System Standby flag for CPU2)  
        .equ PWR_C1STOPF_Shift, 9   @ bitWidth 1 (System Stop flag for CPU1)  
        .equ PWR_C1SBF_Shift, 8   @ bitWidth 1 (System Standby flag for CPU1)  
        .equ PWR_CCRPF_Shift, 2   @ bitWidth 1 (Clear Critical Radio system phase)  
        .equ PWR_C2CSSF_Shift, 1   @ bitWidth 1 (Clear CPU2 Stop Standby flags)  
        .equ PWR_C1CSSF_Shift, 0   @ bitWidth 1 (Clear CPU1 Stop Standby flags)  
 

@=========================== SYSCFG ===========================@
.equ SYSCFG_BASE, 0x40010100 @ (System configuration controller) 
    .equ SYSCFG_MEMRMP, SYSCFG_BASE + 0x0 @ (memory remap register) 
        .equ SYSCFG_MEM_MODE_Shift, 0   @ bitWidth 3 (Memory mapping selection)  
 
    .equ SYSCFG_CFGR1, SYSCFG_BASE + 0x4 @ (configuration register 1) 
        .equ SYSCFG_FPU_IE_Shift, 26   @ bitWidth 6 (Floating Point Unit interrupts enable bits)  
        .equ SYSCFG_I2C3_FMP_Shift, 22   @ bitWidth 1 (I2C3 Fast-mode Plus driving capability activation)  
        .equ SYSCFG_I2C1_FMP_Shift, 20   @ bitWidth 1 (I2C1 Fast-mode Plus driving capability activation)  
        .equ SYSCFG_I2C_PB9_FMP_Shift, 19   @ bitWidth 1 (Fast-mode Plus Fm+ driving capability activation on PB9)  
        .equ SYSCFG_I2C_PB8_FMP_Shift, 18   @ bitWidth 1 (Fast-mode Plus Fm+ driving capability activation on PB8)  
        .equ SYSCFG_I2C_PB7_FMP_Shift, 17   @ bitWidth 1 (Fast-mode Plus Fm+ driving capability activation on PB7)  
        .equ SYSCFG_I2C_PB6_FMP_Shift, 16   @ bitWidth 1 (Fast-mode Plus Fm+ driving capability activation on PB6)  
        .equ SYSCFG_BOOSTEN_Shift, 8   @ bitWidth 1 (I/O analog switch voltage booster enable)  
 
    .equ SYSCFG_EXTICR1, SYSCFG_BASE + 0x8 @ (external interrupt configuration register 1) 
        .equ SYSCFG_EXTI3_Shift, 12   @ bitWidth 3 (EXTI 3 configuration bits)  
        .equ SYSCFG_EXTI2_Shift, 8   @ bitWidth 3 (EXTI 2 configuration bits)  
        .equ SYSCFG_EXTI1_Shift, 4   @ bitWidth 3 (EXTI 1 configuration bits)  
        .equ SYSCFG_EXTI0_Shift, 0   @ bitWidth 3 (EXTI 0 configuration bits)  
 
    .equ SYSCFG_EXTICR2, SYSCFG_BASE + 0xC @ (external interrupt configuration register 2) 
        .equ SYSCFG_EXTI7_Shift, 12   @ bitWidth 3 (EXTI 7 configuration bits)  
        .equ SYSCFG_EXTI6_Shift, 8   @ bitWidth 3 (EXTI 6 configuration bits)  
        .equ SYSCFG_EXTI5_Shift, 4   @ bitWidth 3 (EXTI 5 configuration bits)  
        .equ SYSCFG_EXTI4_Shift, 0   @ bitWidth 3 (EXTI 4 configuration bits)  
 
    .equ SYSCFG_EXTICR3, SYSCFG_BASE + 0x10 @ (external interrupt configuration register 3) 
        .equ SYSCFG_EXTI11_Shift, 12   @ bitWidth 3 (EXTI 11 configuration bits)  
        .equ SYSCFG_EXTI10_Shift, 8   @ bitWidth 3 (EXTI 10 configuration bits)  
        .equ SYSCFG_EXTI9_Shift, 4   @ bitWidth 3 (EXTI 9 configuration bits)  
        .equ SYSCFG_EXTI8_Shift, 0   @ bitWidth 3 (EXTI 8 configuration bits)  
 
    .equ SYSCFG_EXTICR4, SYSCFG_BASE + 0x14 @ (external interrupt configuration register 4) 
        .equ SYSCFG_EXTI15_Shift, 12   @ bitWidth 3 (EXTI15 configuration bits)  
        .equ SYSCFG_EXTI14_Shift, 8   @ bitWidth 3 (EXTI14 configuration bits)  
        .equ SYSCFG_EXTI13_Shift, 4   @ bitWidth 3 (EXTI13 configuration bits)  
        .equ SYSCFG_EXTI12_Shift, 0   @ bitWidth 3 (EXTI12 configuration bits)  
 
    .equ SYSCFG_SCSR, SYSCFG_BASE + 0x18 @ (SCSR) 
        .equ SYSCFG_SRAM2BSY_Shift, 1   @ bitWidth 1 (SRAM2 busy by erase operation)  
        .equ SYSCFG_SRAM2ER_Shift, 0   @ bitWidth 1 (SRAM2 Erase)  
        .equ SYSCFG_C2RFD_Shift, 31   @ bitWidth 1 (CPU2 SRAM fetch execution disable.)  
 
    .equ SYSCFG_CFGR2, SYSCFG_BASE + 0x1C @ (CFGR2) 
        .equ SYSCFG_SPF_Shift, 8   @ bitWidth 1 (SRAM2 parity error flag)  
        .equ SYSCFG_ECCL_Shift, 3   @ bitWidth 1 (ECC Lock)  
        .equ SYSCFG_PVDL_Shift, 2   @ bitWidth 1 (PVD lock enable bit)  
        .equ SYSCFG_SPL_Shift, 1   @ bitWidth 1 (SRAM2 parity lock bit)  
        .equ SYSCFG_CLL_Shift, 0   @ bitWidth 1 (Cortex-M4 LOCKUP Hardfault output enable bit)  
 
    .equ SYSCFG_SWPR, SYSCFG_BASE + 0x20 @ (SRAM2 write protection register) 
        .equ SYSCFG_P31WP_Shift, 31   @ bitWidth 1 (SRAM2 page 31 write protection)  
        .equ SYSCFG_P30WP_Shift, 30   @ bitWidth 1 (P30WP)  
        .equ SYSCFG_P29WP_Shift, 29   @ bitWidth 1 (P29WP)  
        .equ SYSCFG_P28WP_Shift, 28   @ bitWidth 1 (P28WP)  
        .equ SYSCFG_P27WP_Shift, 27   @ bitWidth 1 (P27WP)  
        .equ SYSCFG_P26WP_Shift, 26   @ bitWidth 1 (P26WP)  
        .equ SYSCFG_P25WP_Shift, 25   @ bitWidth 1 (P25WP)  
        .equ SYSCFG_P24WP_Shift, 24   @ bitWidth 1 (P24WP)  
        .equ SYSCFG_P23WP_Shift, 23   @ bitWidth 1 (P23WP)  
        .equ SYSCFG_P22WP_Shift, 22   @ bitWidth 1 (P22WP)  
        .equ SYSCFG_P21WP_Shift, 21   @ bitWidth 1 (P21WP)  
        .equ SYSCFG_P20WP_Shift, 20   @ bitWidth 1 (P20WP)  
        .equ SYSCFG_P19WP_Shift, 19   @ bitWidth 1 (P19WP)  
        .equ SYSCFG_P18WP_Shift, 18   @ bitWidth 1 (P18WP)  
        .equ SYSCFG_P17WP_Shift, 17   @ bitWidth 1 (P17WP)  
        .equ SYSCFG_P16WP_Shift, 16   @ bitWidth 1 (P16WP)  
        .equ SYSCFG_P15WP_Shift, 15   @ bitWidth 1 (P15WP)  
        .equ SYSCFG_P14WP_Shift, 14   @ bitWidth 1 (P14WP)  
        .equ SYSCFG_P13WP_Shift, 13   @ bitWidth 1 (P13WP)  
        .equ SYSCFG_P12WP_Shift, 12   @ bitWidth 1 (P12WP)  
        .equ SYSCFG_P11WP_Shift, 11   @ bitWidth 1 (P11WP)  
        .equ SYSCFG_P10WP_Shift, 10   @ bitWidth 1 (P10WP)  
        .equ SYSCFG_P9WP_Shift, 9   @ bitWidth 1 (P9WP)  
        .equ SYSCFG_P8WP_Shift, 8   @ bitWidth 1 (P8WP)  
        .equ SYSCFG_P7WP_Shift, 7   @ bitWidth 1 (P7WP)  
        .equ SYSCFG_P6WP_Shift, 6   @ bitWidth 1 (P6WP)  
        .equ SYSCFG_P5WP_Shift, 5   @ bitWidth 1 (P5WP)  
        .equ SYSCFG_P4WP_Shift, 4   @ bitWidth 1 (P4WP)  
        .equ SYSCFG_P3WP_Shift, 3   @ bitWidth 1 (P3WP)  
        .equ SYSCFG_P2WP_Shift, 2   @ bitWidth 1 (P2WP)  
        .equ SYSCFG_P1WP_Shift, 1   @ bitWidth 1 (P1WP)  
        .equ SYSCFG_P0WP_Shift, 0   @ bitWidth 1 (P0WP)  
 
    .equ SYSCFG_SKR, SYSCFG_BASE + 0x24 @ (SKR) 
        .equ SYSCFG_KEY_Shift, 0   @ bitWidth 8 (SRAM2 write protection key for software erase)  
 
    .equ SYSCFG_SWPR2, SYSCFG_BASE + 0x28 @ (SRAM2 write protection register 2) 
        .equ SYSCFG_P63WP_Shift, 31   @ bitWidth 1 (SRAM2 page 63 write protection)  
        .equ SYSCFG_P62WP_Shift, 30   @ bitWidth 1 (P62WP)  
        .equ SYSCFG_P61WP_Shift, 29   @ bitWidth 1 (P61WP)  
        .equ SYSCFG_P60WP_Shift, 28   @ bitWidth 1 (P60WP)  
        .equ SYSCFG_P59WP_Shift, 27   @ bitWidth 1 (P59WP)  
        .equ SYSCFG_P58WP_Shift, 26   @ bitWidth 1 (P58WP)  
        .equ SYSCFG_P57WP_Shift, 25   @ bitWidth 1 (P57WP)  
        .equ SYSCFG_P56WP_Shift, 24   @ bitWidth 1 (P56WP)  
        .equ SYSCFG_P55WP_Shift, 23   @ bitWidth 1 (P55WP)  
        .equ SYSCFG_P54WP_Shift, 22   @ bitWidth 1 (P54WP)  
        .equ SYSCFG_P53WP_Shift, 21   @ bitWidth 1 (P53WP)  
        .equ SYSCFG_P52WP_Shift, 20   @ bitWidth 1 (P52WP)  
        .equ SYSCFG_P51WP_Shift, 19   @ bitWidth 1 (P51WP)  
        .equ SYSCFG_P50WP_Shift, 18   @ bitWidth 1 (P50WP)  
        .equ SYSCFG_P49WP_Shift, 17   @ bitWidth 1 (P49WP)  
        .equ SYSCFG_P48WP_Shift, 16   @ bitWidth 1 (P48WP)  
        .equ SYSCFG_P47WP_Shift, 15   @ bitWidth 1 (P47WP)  
        .equ SYSCFG_P46WP_Shift, 14   @ bitWidth 1 (P46WP)  
        .equ SYSCFG_P45WP_Shift, 13   @ bitWidth 1 (P45WP)  
        .equ SYSCFG_P44WP_Shift, 12   @ bitWidth 1 (P44WP)  
        .equ SYSCFG_P43WP_Shift, 11   @ bitWidth 1 (P43WP)  
        .equ SYSCFG_P42WP_Shift, 10   @ bitWidth 1 (P42WP)  
        .equ SYSCFG_P41WP_Shift, 9   @ bitWidth 1 (P41WP)  
        .equ SYSCFG_P40WP_Shift, 8   @ bitWidth 1 (P40WP)  
        .equ SYSCFG_P39WP_Shift, 7   @ bitWidth 1 (P39WP)  
        .equ SYSCFG_P38WP_Shift, 6   @ bitWidth 1 (P38WP)  
        .equ SYSCFG_P37WP_Shift, 5   @ bitWidth 1 (P37WP)  
        .equ SYSCFG_P36WP_Shift, 4   @ bitWidth 1 (P36WP)  
        .equ SYSCFG_P35WP_Shift, 3   @ bitWidth 1 (P35WP)  
        .equ SYSCFG_P34WP_Shift, 2   @ bitWidth 1 (P34WP)  
        .equ SYSCFG_P33WP_Shift, 1   @ bitWidth 1 (P33WP)  
        .equ SYSCFG_P32WP_Shift, 0   @ bitWidth 1 (P32WP)  
 
    .equ SYSCFG_IMR1, SYSCFG_BASE + 0x2C @ (CPU1 interrupt mask register 1) 
        .equ SYSCFG_TIM1IM_Shift, 13   @ bitWidth 1 (Peripheral TIM1 interrupt mask to CPU1)  
        .equ SYSCFG_TIM16IM_Shift, 14   @ bitWidth 1 (Peripheral TIM16 interrupt mask to CPU1)  
        .equ SYSCFG_TIM17IM_Shift, 15   @ bitWidth 1 (Peripheral TIM17 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT5IM_Shift, 21   @ bitWidth 1 (Peripheral EXIT5 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT6IM_Shift, 22   @ bitWidth 1 (Peripheral EXIT6 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT7IM_Shift, 23   @ bitWidth 1 (Peripheral EXIT7 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT8IM_Shift, 24   @ bitWidth 1 (Peripheral EXIT8 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT9IM_Shift, 25   @ bitWidth 1 (Peripheral EXIT9 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT10IM_Shift, 26   @ bitWidth 1 (Peripheral EXIT10 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT11IM_Shift, 27   @ bitWidth 1 (Peripheral EXIT11 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT12IM_Shift, 28   @ bitWidth 1 (Peripheral EXIT12 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT13IM_Shift, 29   @ bitWidth 1 (Peripheral EXIT13 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT14IM_Shift, 30   @ bitWidth 1 (Peripheral EXIT14 interrupt mask to CPU1)  
        .equ SYSCFG_EXIT15IM_Shift, 31   @ bitWidth 1 (Peripheral EXIT15 interrupt mask to CPU1)  
 
    .equ SYSCFG_IMR2, SYSCFG_BASE + 0x30 @ (CPU1 interrupt mask register 2) 
        .equ SYSCFG_PVM3IM_Shift, 18   @ bitWidth 1 (Peripheral PVM3 interrupt mask to CPU1)  
        .equ SYSCFG_PVM1IM_Shift, 16   @ bitWidth 1 (Peripheral PVM1 interrupt mask to CPU1)  
        .equ SYSCFG_PVDIM_Shift, 20   @ bitWidth 1 (Peripheral PVD interrupt mask to CPU1)  
 
    .equ SYSCFG_C2IMR1, SYSCFG_BASE + 0x34 @ (CPU2 interrupt mask register 1) 
        .equ SYSCFG_RTCSTAMP_Shift, 0   @ bitWidth 1 (Peripheral RTCSTAMP interrupt mask to CPU2)  
        .equ SYSCFG_RTCWKUP_Shift, 3   @ bitWidth 1 (Peripheral RTCWKUP interrupt mask to CPU2)  
        .equ SYSCFG_RTCALARM_Shift, 4   @ bitWidth 1 (Peripheral RTCALARM interrupt mask to CPU2)  
        .equ SYSCFG_RCC_Shift, 5   @ bitWidth 1 (Peripheral RCC interrupt mask to CPU2)  
        .equ SYSCFG_FLASH_Shift, 6   @ bitWidth 1 (Peripheral FLASH interrupt mask to CPU2)  
        .equ SYSCFG_PKA_Shift, 8   @ bitWidth 1 (Peripheral PKA interrupt mask to CPU2)  
        .equ SYSCFG_RNG_Shift, 9   @ bitWidth 1 (Peripheral RNG interrupt mask to CPU2)  
        .equ SYSCFG_AES1_Shift, 10   @ bitWidth 1 (Peripheral AES1 interrupt mask to CPU2)  
        .equ SYSCFG_COMP_Shift, 11   @ bitWidth 1 (Peripheral COMP interrupt mask to CPU2)  
        .equ SYSCFG_ADC_Shift, 12   @ bitWidth 1 (Peripheral ADC interrupt mask to CPU2)  
 
    .equ SYSCFG_C2IMR2, SYSCFG_BASE + 0x38 @ (CPU2 interrupt mask register 1) 
        .equ SYSCFG_DMA1_CH1_IM_Shift, 0   @ bitWidth 1 (Peripheral DMA1 CH1 interrupt mask to CPU2)  
        .equ SYSCFG_DMA1_CH2_IM_Shift, 1   @ bitWidth 1 (Peripheral DMA1 CH2 interrupt mask to CPU2)  
        .equ SYSCFG_DMA1_CH3_IM_Shift, 2   @ bitWidth 1 (Peripheral DMA1 CH3 interrupt mask to CPU2)  
        .equ SYSCFG_DMA1_CH4_IM_Shift, 3   @ bitWidth 1 (Peripheral DMA1 CH4 interrupt mask to CPU2)  
        .equ SYSCFG_DMA1_CH5_IM_Shift, 4   @ bitWidth 1 (Peripheral DMA1 CH5 interrupt mask to CPU2)  
        .equ SYSCFG_DMA1_CH6_IM_Shift, 5   @ bitWidth 1 (Peripheral DMA1 CH6 interrupt mask to CPU2)  
        .equ SYSCFG_DMA1_CH7_IM_Shift, 6   @ bitWidth 1 (Peripheral DMA1 CH7 interrupt mask to CPU2)  
        .equ SYSCFG_DMA2_CH1_IM_Shift, 8   @ bitWidth 1 (Peripheral DMA2 CH1 interrupt mask to CPU1)  
        .equ SYSCFG_DMA2_CH2_IM_Shift, 9   @ bitWidth 1 (Peripheral DMA2 CH2 interrupt mask to CPU1)  
        .equ SYSCFG_DMA2_CH3_IM_Shift, 10   @ bitWidth 1 (Peripheral DMA2 CH3 interrupt mask to CPU1)  
        .equ SYSCFG_DMA2_CH4_IM_Shift, 11   @ bitWidth 1 (Peripheral DMA2 CH4 interrupt mask to CPU1)  
        .equ SYSCFG_DMA2_CH5_IM_Shift, 12   @ bitWidth 1 (Peripheral DMA2 CH5 interrupt mask to CPU1)  
        .equ SYSCFG_DMA2_CH6_IM_Shift, 13   @ bitWidth 1 (Peripheral DMA2 CH6 interrupt mask to CPU1)  
        .equ SYSCFG_DMA2_CH7_IM_Shift, 14   @ bitWidth 1 (Peripheral DMA2 CH7 interrupt mask to CPU1)  
        .equ SYSCFG_DMAM_UX1_IM_Shift, 15   @ bitWidth 1 (Peripheral DMAM UX1 interrupt mask to CPU1)  
        .equ SYSCFG_PVM1IM_Shift, 16   @ bitWidth 1 (Peripheral PVM1IM interrupt mask to CPU1)  
        .equ SYSCFG_PVM3IM_Shift, 18   @ bitWidth 1 (Peripheral PVM3IM interrupt mask to CPU1)  
        .equ SYSCFG_PVDIM_Shift, 20   @ bitWidth 1 (Peripheral PVDIM interrupt mask to CPU1)  
        .equ SYSCFG_TSCIM_Shift, 21   @ bitWidth 1 (Peripheral TSCIM interrupt mask to CPU1)  
        .equ SYSCFG_LCDIM_Shift, 22   @ bitWidth 1 (Peripheral LCDIM interrupt mask to CPU1)  
 
    .equ SYSCFG_SIPCR, SYSCFG_BASE + 0x3C @ (secure IP control register) 
        .equ SYSCFG_SAES1_Shift, 0   @ bitWidth 1 (Enable AES1 KEY[7:0] security.)  
        .equ SYSCFG_SAES2_Shift, 1   @ bitWidth 1 (Enable AES2 security.)  
        .equ SYSCFG_SPKA_Shift, 2   @ bitWidth 1 (Enable PKA security)  
        .equ SYSCFG_SRNG_Shift, 3   @ bitWidth 1 (Enable True RNG security)  
 

@=========================== RNG ===========================@
.equ RNG_BASE, 0x58001000 @ (Random number generator) 
    .equ RNG_CR, RNG_BASE + 0x0 @ (control register) 
        .equ RNG_RNGEN_Shift, 2   @ bitWidth 1 (Random number generator enable)  
        .equ RNG_IE_Shift, 3   @ bitWidth 1 (Interrupt enable)  
        .equ RNG_BYP_Shift, 6   @ bitWidth 1 (Bypass mode enable)  
 
    .equ RNG_SR, RNG_BASE + 0x4 @ (status register) 
        .equ RNG_SEIS_Shift, 6   @ bitWidth 1 (Seed error interrupt status)  
        .equ RNG_CEIS_Shift, 5   @ bitWidth 1 (Clock error interrupt status)  
        .equ RNG_SECS_Shift, 2   @ bitWidth 1 (Seed error current status)  
        .equ RNG_CECS_Shift, 1   @ bitWidth 1 (Clock error current status)  
        .equ RNG_DRDY_Shift, 0   @ bitWidth 1 (Data ready)  
 
    .equ RNG_DR, RNG_BASE + 0x8 @ (data register) 
        .equ RNG_RNDATA_Shift, 0   @ bitWidth 32 (Random data)  
 

@=========================== AES1 ===========================@
.equ AES1_BASE, 0x50060000 @ (Advanced encryption standard hardware accelerator 1) 
    .equ AES1_CR, AES1_BASE + 0x0 @ (control register) 
        .equ AES1_NPBLB_Shift, 20   @ bitWidth 4 (Number of padding bytes in last block of payload)  
        .equ AES1_KEYSIZE_Shift, 18   @ bitWidth 1 (Key size selection)  
        .equ AES1_CHMOD2_Shift, 16   @ bitWidth 1 (AES chaining mode Bit2)  
        .equ AES1_GCMPH_Shift, 13   @ bitWidth 2 (Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected)  
        .equ AES1_DMAOUTEN_Shift, 12   @ bitWidth 1 (Enable DMA management of data output phase)  
        .equ AES1_DMAINEN_Shift, 11   @ bitWidth 1 (Enable DMA management of data input phase)  
        .equ AES1_ERRIE_Shift, 10   @ bitWidth 1 (Error interrupt enable)  
        .equ AES1_CCFIE_Shift, 9   @ bitWidth 1 (CCF flag interrupt enable)  
        .equ AES1_ERRC_Shift, 8   @ bitWidth 1 (Error clear)  
        .equ AES1_CCFC_Shift, 7   @ bitWidth 1 (Computation Complete Flag Clear)  
        .equ AES1_CHMOD10_Shift, 5   @ bitWidth 2 (AES chaining mode Bit1 Bit0)  
        .equ AES1_MODE_Shift, 3   @ bitWidth 2 (AES operating mode)  
        .equ AES1_DATATYPE_Shift, 1   @ bitWidth 2 (Data type selection for data in and data out to/from the cryptographic block)  
        .equ AES1_EN_Shift, 0   @ bitWidth 1 (AES enable)  
 
    .equ AES1_SR, AES1_BASE + 0x4 @ (status register) 
        .equ AES1_BUSY_Shift, 3   @ bitWidth 1 (Busy flag)  
        .equ AES1_WRERR_Shift, 2   @ bitWidth 1 (Write error flag)  
        .equ AES1_RDERR_Shift, 1   @ bitWidth 1 (Read error flag)  
        .equ AES1_CCF_Shift, 0   @ bitWidth 1 (Computation complete flag)  
 
    .equ AES1_DINR, AES1_BASE + 0x8 @ (data input register) 
        .equ AES1_AES_DINR_Shift, 0   @ bitWidth 32 (Data Input Register)  
 
    .equ AES1_DOUTR, AES1_BASE + 0xC @ (data output register) 
        .equ AES1_AES_DOUTR_Shift, 0   @ bitWidth 32 (Data output register)  
 
    .equ AES1_KEYR0, AES1_BASE + 0x10 @ (key register 0) 
        .equ AES1_AES_KEYR0_Shift, 0   @ bitWidth 32 (Data Output Register LSB key [31:0])  
 
    .equ AES1_KEYR1, AES1_BASE + 0x14 @ (key register 1) 
        .equ AES1_AES_KEYR1_Shift, 0   @ bitWidth 32 (AES key register key [63:32])  
 
    .equ AES1_KEYR2, AES1_BASE + 0x18 @ (key register 2) 
        .equ AES1_AES_KEYR2_Shift, 0   @ bitWidth 32 (AES key register key [95:64])  
 
    .equ AES1_KEYR3, AES1_BASE + 0x1C @ (key register 3) 
        .equ AES1_AES_KEYR3_Shift, 0   @ bitWidth 32 (AES key register MSB key [127:96])  
 
    .equ AES1_IVR0, AES1_BASE + 0x20 @ (initialization vector register 0) 
        .equ AES1_AES_IVR0_Shift, 0   @ bitWidth 32 (initialization vector register LSB IVR [31:0])  
 
    .equ AES1_IVR1, AES1_BASE + 0x24 @ (initialization vector register 1) 
        .equ AES1_AES_IVR1_Shift, 0   @ bitWidth 32 (Initialization Vector Register IVR [63:32])  
 
    .equ AES1_IVR2, AES1_BASE + 0x28 @ (initialization vector register 2) 
        .equ AES1_AES_IVR2_Shift, 0   @ bitWidth 32 (Initialization Vector Register IVR [95:64])  
 
    .equ AES1_IVR3, AES1_BASE + 0x2C @ (initialization vector register 3) 
        .equ AES1_AES_IVR3_Shift, 0   @ bitWidth 32 (Initialization Vector Register MSB IVR [127:96])  
 
    .equ AES1_KEYR4, AES1_BASE + 0x30 @ (key register 4) 
        .equ AES1_AES_KEYR4_Shift, 0   @ bitWidth 32 (AES key register MSB key [159:128])  
 
    .equ AES1_KEYR5, AES1_BASE + 0x34 @ (key register 5) 
        .equ AES1_AES_KEYR5_Shift, 0   @ bitWidth 32 (AES key register MSB key [191:160])  
 
    .equ AES1_KEYR6, AES1_BASE + 0x38 @ (key register 6) 
        .equ AES1_AES_KEYR6_Shift, 0   @ bitWidth 32 (AES key register MSB key [223:192])  
 
    .equ AES1_KEYR7, AES1_BASE + 0x3C @ (key register 7) 
        .equ AES1_AES_KEYR7_Shift, 0   @ bitWidth 32 (AES key register MSB key [255:224])  
 
    .equ AES1_SUSP0R, AES1_BASE + 0x40 @ (AES suspend register 0) 
        .equ AES1_AES_SUSP0R_Shift, 0   @ bitWidth 32 (AES suspend register 0)  
 
    .equ AES1_SUSP1R, AES1_BASE + 0x44 @ (AES suspend register 1) 
        .equ AES1_AES_SUSP1R_Shift, 0   @ bitWidth 32 (AES suspend register 1)  
 
    .equ AES1_SUSP2R, AES1_BASE + 0x48 @ (AES suspend register 2) 
        .equ AES1_AES_SUSP2R_Shift, 0   @ bitWidth 32 (AES suspend register 2)  
 
    .equ AES1_SUSP3R, AES1_BASE + 0x4C @ (AES suspend register 3) 
        .equ AES1_AES_SUSP3R_Shift, 0   @ bitWidth 32 (AES suspend register 3)  
 
    .equ AES1_SUSP4R, AES1_BASE + 0x50 @ (AES suspend register 4) 
        .equ AES1_AES_SUSP4R_Shift, 0   @ bitWidth 32 (AES suspend register 4)  
 
    .equ AES1_SUSP5R, AES1_BASE + 0x54 @ (AES suspend register 5) 
        .equ AES1_AES_SUSP5R_Shift, 0   @ bitWidth 32 (AES suspend register 5)  
 
    .equ AES1_SUSP6R, AES1_BASE + 0x58 @ (AES suspend register 6) 
        .equ AES1_AES_SUSP6R_Shift, 0   @ bitWidth 32 (AES suspend register 6)  
 
    .equ AES1_SUSP7R, AES1_BASE + 0x5C @ (AES suspend register 7) 
        .equ AES1_AES_SUSP7R_Shift, 0   @ bitWidth 32 (AES suspend register 7)  
 
    .equ AES1_HWCFR, AES1_BASE + 0x3F0 @ (AES hardware configuration register) 
        .equ AES1_CFG4_Shift, 12   @ bitWidth 4 (HW Generic 4)  
        .equ AES1_CFG3_Shift, 8   @ bitWidth 4 (HW Generic 3)  
        .equ AES1_CFG2_Shift, 4   @ bitWidth 4 (HW Generic 2)  
        .equ AES1_CFG1_Shift, 0   @ bitWidth 4 (HW Generic 1)  
 
    .equ AES1_VERR, AES1_BASE + 0x3F4 @ (AES version register) 
        .equ AES1_MAJREV_Shift, 4   @ bitWidth 4 (Major revision)  
        .equ AES1_MINREV_Shift, 0   @ bitWidth 4 (Minor revision)  
 
    .equ AES1_IPIDR, AES1_BASE + 0x3F8 @ (AES identification register) 
        .equ AES1_ID_Shift, 0   @ bitWidth 32 (Identification code)  
 
    .equ AES1_SIDR, AES1_BASE + 0x3FC @ (AES size ID register) 
        .equ AES1_ID_Shift, 0   @ bitWidth 32 (Size Identification code)  
 

@=========================== AES2 ===========================@
.equ AES2_BASE, 0x58001800 @ (Advanced encryption standard hardware accelerator 1) 
    .equ AES2_CR, AES2_BASE + 0x0 @ (control register) 
        .equ AES2_NPBLB_Shift, 20   @ bitWidth 4 (Number of padding bytes in last block of payload)  
        .equ AES2_KEYSIZE_Shift, 18   @ bitWidth 1 (Key size selection)  
        .equ AES2_CHMOD2_Shift, 16   @ bitWidth 1 (AES chaining mode Bit2)  
        .equ AES2_GCMPH_Shift, 13   @ bitWidth 2 (Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected)  
        .equ AES2_DMAOUTEN_Shift, 12   @ bitWidth 1 (Enable DMA management of data output phase)  
        .equ AES2_DMAINEN_Shift, 11   @ bitWidth 1 (Enable DMA management of data input phase)  
        .equ AES2_ERRIE_Shift, 10   @ bitWidth 1 (Error interrupt enable)  
        .equ AES2_CCFIE_Shift, 9   @ bitWidth 1 (CCF flag interrupt enable)  
        .equ AES2_ERRC_Shift, 8   @ bitWidth 1 (Error clear)  
        .equ AES2_CCFC_Shift, 7   @ bitWidth 1 (Computation Complete Flag Clear)  
        .equ AES2_CHMOD10_Shift, 5   @ bitWidth 2 (AES chaining mode Bit1 Bit0)  
        .equ AES2_MODE_Shift, 3   @ bitWidth 2 (AES operating mode)  
        .equ AES2_DATATYPE_Shift, 1   @ bitWidth 2 (Data type selection for data in and data out to/from the cryptographic block)  
        .equ AES2_EN_Shift, 0   @ bitWidth 1 (AES enable)  
 
    .equ AES2_SR, AES2_BASE + 0x4 @ (status register) 
        .equ AES2_BUSY_Shift, 3   @ bitWidth 1 (Busy flag)  
        .equ AES2_WRERR_Shift, 2   @ bitWidth 1 (Write error flag)  
        .equ AES2_RDERR_Shift, 1   @ bitWidth 1 (Read error flag)  
        .equ AES2_CCF_Shift, 0   @ bitWidth 1 (Computation complete flag)  
 
    .equ AES2_DINR, AES2_BASE + 0x8 @ (data input register) 
        .equ AES2_AES_DINR_Shift, 0   @ bitWidth 32 (Data Input Register)  
 
    .equ AES2_DOUTR, AES2_BASE + 0xC @ (data output register) 
        .equ AES2_AES_DOUTR_Shift, 0   @ bitWidth 32 (Data output register)  
 
    .equ AES2_KEYR0, AES2_BASE + 0x10 @ (key register 0) 
        .equ AES2_AES_KEYR0_Shift, 0   @ bitWidth 32 (Data Output Register LSB key [31:0])  
 
    .equ AES2_KEYR1, AES2_BASE + 0x14 @ (key register 1) 
        .equ AES2_AES_KEYR1_Shift, 0   @ bitWidth 32 (AES key register key [63:32])  
 
    .equ AES2_KEYR2, AES2_BASE + 0x18 @ (key register 2) 
        .equ AES2_AES_KEYR2_Shift, 0   @ bitWidth 32 (AES key register key [95:64])  
 
    .equ AES2_KEYR3, AES2_BASE + 0x1C @ (key register 3) 
        .equ AES2_AES_KEYR3_Shift, 0   @ bitWidth 32 (AES key register MSB key [127:96])  
 
    .equ AES2_IVR0, AES2_BASE + 0x20 @ (initialization vector register 0) 
        .equ AES2_AES_IVR0_Shift, 0   @ bitWidth 32 (initialization vector register LSB IVR [31:0])  
 
    .equ AES2_IVR1, AES2_BASE + 0x24 @ (initialization vector register 1) 
        .equ AES2_AES_IVR1_Shift, 0   @ bitWidth 32 (Initialization Vector Register IVR [63:32])  
 
    .equ AES2_IVR2, AES2_BASE + 0x28 @ (initialization vector register 2) 
        .equ AES2_AES_IVR2_Shift, 0   @ bitWidth 32 (Initialization Vector Register IVR [95:64])  
 
    .equ AES2_IVR3, AES2_BASE + 0x2C @ (initialization vector register 3) 
        .equ AES2_AES_IVR3_Shift, 0   @ bitWidth 32 (Initialization Vector Register MSB IVR [127:96])  
 
    .equ AES2_KEYR4, AES2_BASE + 0x30 @ (key register 4) 
        .equ AES2_AES_KEYR4_Shift, 0   @ bitWidth 32 (AES key register MSB key [159:128])  
 
    .equ AES2_KEYR5, AES2_BASE + 0x34 @ (key register 5) 
        .equ AES2_AES_KEYR5_Shift, 0   @ bitWidth 32 (AES key register MSB key [191:160])  
 
    .equ AES2_KEYR6, AES2_BASE + 0x38 @ (key register 6) 
        .equ AES2_AES_KEYR6_Shift, 0   @ bitWidth 32 (AES key register MSB key [223:192])  
 
    .equ AES2_KEYR7, AES2_BASE + 0x3C @ (key register 7) 
        .equ AES2_AES_KEYR7_Shift, 0   @ bitWidth 32 (AES key register MSB key [255:224])  
 
    .equ AES2_SUSP0R, AES2_BASE + 0x40 @ (AES suspend register 0) 
        .equ AES2_AES_SUSP0R_Shift, 0   @ bitWidth 32 (AES suspend register 0)  
 
    .equ AES2_SUSP1R, AES2_BASE + 0x44 @ (AES suspend register 1) 
        .equ AES2_AES_SUSP1R_Shift, 0   @ bitWidth 32 (AES suspend register 1)  
 
    .equ AES2_SUSP2R, AES2_BASE + 0x48 @ (AES suspend register 2) 
        .equ AES2_AES_SUSP2R_Shift, 0   @ bitWidth 32 (AES suspend register 2)  
 
    .equ AES2_SUSP3R, AES2_BASE + 0x4C @ (AES suspend register 3) 
        .equ AES2_AES_SUSP3R_Shift, 0   @ bitWidth 32 (AES suspend register 3)  
 
    .equ AES2_SUSP4R, AES2_BASE + 0x50 @ (AES suspend register 4) 
        .equ AES2_AES_SUSP4R_Shift, 0   @ bitWidth 32 (AES suspend register 4)  
 
    .equ AES2_SUSP5R, AES2_BASE + 0x54 @ (AES suspend register 5) 
        .equ AES2_AES_SUSP5R_Shift, 0   @ bitWidth 32 (AES suspend register 5)  
 
    .equ AES2_SUSP6R, AES2_BASE + 0x58 @ (AES suspend register 6) 
        .equ AES2_AES_SUSP6R_Shift, 0   @ bitWidth 32 (AES suspend register 6)  
 
    .equ AES2_SUSP7R, AES2_BASE + 0x5C @ (AES suspend register 7) 
        .equ AES2_AES_SUSP7R_Shift, 0   @ bitWidth 32 (AES suspend register 7)  
 
    .equ AES2_HWCFR, AES2_BASE + 0x60 @ (AES hardware configuration register) 
        .equ AES2_CFG4_Shift, 12   @ bitWidth 4 (HW Generic 4)  
        .equ AES2_CFG3_Shift, 8   @ bitWidth 4 (HW Generic 3)  
        .equ AES2_CFG2_Shift, 4   @ bitWidth 4 (HW Generic 2)  
        .equ AES2_CFG1_Shift, 0   @ bitWidth 4 (HW Generic 1)  
 
    .equ AES2_VERR, AES2_BASE + 0x64 @ (AES version register) 
        .equ AES2_MAJREV_Shift, 4   @ bitWidth 4 (Major revision)  
        .equ AES2_MINREV_Shift, 0   @ bitWidth 4 (Minor revision)  
 
    .equ AES2_IPIDR, AES2_BASE + 0x68 @ (AES identification register) 
        .equ AES2_ID_Shift, 0   @ bitWidth 32 (Identification code)  
 
    .equ AES2_SIDR, AES2_BASE + 0x6C @ (AES size ID register) 
        .equ AES2_ID_Shift, 0   @ bitWidth 32 (Size Identification code)  
 

@=========================== HSEM ===========================@
.equ HSEM_BASE, 0x58001400 @ (HSEM) 
    .equ HSEM_R0, HSEM_BASE + 0x0 @ (Semaphore 0 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R1, HSEM_BASE + 0x4 @ (Semaphore 1 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R2, HSEM_BASE + 0x8 @ (Semaphore 2 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R3, HSEM_BASE + 0xC @ (Semaphore 3 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R4, HSEM_BASE + 0x10 @ (Semaphore 4 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R5, HSEM_BASE + 0x14 @ (Semaphore 5 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R6, HSEM_BASE + 0x18 @ (Semaphore 6 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R7, HSEM_BASE + 0x1C @ (Semaphore 7 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R8, HSEM_BASE + 0x20 @ (Semaphore 8 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R9, HSEM_BASE + 0x24 @ (Semaphore 9 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R10, HSEM_BASE + 0x28 @ (Semaphore 10 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R11, HSEM_BASE + 0x2C @ (Semaphore 11 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R12, HSEM_BASE + 0x30 @ (Semaphore 12 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R13, HSEM_BASE + 0x34 @ (Semaphore 13 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R14, HSEM_BASE + 0x38 @ (Semaphore 14 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R15, HSEM_BASE + 0x3C @ (Semaphore 15 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R16, HSEM_BASE + 0x40 @ (Semaphore 16 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R17, HSEM_BASE + 0x44 @ (Semaphore 17 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R18, HSEM_BASE + 0x48 @ (Semaphore 18 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R19, HSEM_BASE + 0x4C @ (Semaphore 19 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R20, HSEM_BASE + 0x50 @ (Semaphore 20 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R21, HSEM_BASE + 0x54 @ (Semaphore 21 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R22, HSEM_BASE + 0x58 @ (Semaphore 22 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R23, HSEM_BASE + 0x5C @ (Semaphore 23 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R24, HSEM_BASE + 0x60 @ (Semaphore 24 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R25, HSEM_BASE + 0x64 @ (Semaphore 25 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R26, HSEM_BASE + 0x68 @ (Semaphore 26 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R27, HSEM_BASE + 0x6C @ (Semaphore 27 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R28, HSEM_BASE + 0x70 @ (Semaphore 28 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R29, HSEM_BASE + 0x74 @ (Semaphore 29 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R30, HSEM_BASE + 0x78 @ (Semaphore 30 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_R31, HSEM_BASE + 0x7C @ (Semaphore 31 register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR0, HSEM_BASE + 0x80 @ (Semaphore 0 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR1, HSEM_BASE + 0x84 @ (Semaphore 1 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR2, HSEM_BASE + 0x88 @ (Semaphore 2 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR3, HSEM_BASE + 0x8C @ (Semaphore 3 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR4, HSEM_BASE + 0x90 @ (Semaphore 4 read lock read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR5, HSEM_BASE + 0x94 @ (Semaphore 5 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR6, HSEM_BASE + 0x98 @ (Semaphore 6 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR7, HSEM_BASE + 0x9C @ (Semaphore 7 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR8, HSEM_BASE + 0xA0 @ (Semaphore 8 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR9, HSEM_BASE + 0xA4 @ (Semaphore 9 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR10, HSEM_BASE + 0xA8 @ (Semaphore 10 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR11, HSEM_BASE + 0xAC @ (Semaphore 11 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR12, HSEM_BASE + 0xB0 @ (Semaphore 12 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR13, HSEM_BASE + 0xB4 @ (Semaphore 13 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR14, HSEM_BASE + 0xB8 @ (Semaphore 14 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR15, HSEM_BASE + 0xBC @ (Semaphore 15 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR16, HSEM_BASE + 0xC0 @ (Semaphore 16 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR17, HSEM_BASE + 0xC4 @ (Semaphore 17 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR18, HSEM_BASE + 0xC8 @ (Semaphore 18 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR19, HSEM_BASE + 0xCC @ (Semaphore 19 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR20, HSEM_BASE + 0xD0 @ (Semaphore 20 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR21, HSEM_BASE + 0xD4 @ (Semaphore 21 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR22, HSEM_BASE + 0xD8 @ (Semaphore 22 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR23, HSEM_BASE + 0xDC @ (Semaphore 23 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR24, HSEM_BASE + 0xE0 @ (Semaphore 24 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR25, HSEM_BASE + 0xE4 @ (Semaphore 25 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR26, HSEM_BASE + 0xE8 @ (Semaphore 26 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR27, HSEM_BASE + 0xEC @ (Semaphore 27 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR28, HSEM_BASE + 0xF0 @ (Semaphore 28 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR29, HSEM_BASE + 0xF4 @ (Semaphore 29 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR30, HSEM_BASE + 0xF8 @ (Semaphore 30 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_RLR31, HSEM_BASE + 0xFC @ (Semaphore 31 read lock register) 
        .equ HSEM_LOCK_Shift, 31   @ bitWidth 1 (lock indication)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (Semaphore CoreID)  
        .equ HSEM_PROCID_Shift, 0   @ bitWidth 8 (Semaphore ProcessID)  
 
    .equ HSEM_CR, HSEM_BASE + 0x140 @ (Semaphore Clear register) 
        .equ HSEM_KEY_Shift, 16   @ bitWidth 16 (Semaphore clear Key)  
        .equ HSEM_COREID_Shift, 8   @ bitWidth 4 (CoreID of semaphore to be cleared)  
 
    .equ HSEM_KEYR, HSEM_BASE + 0x144 @ (Interrupt clear register) 
        .equ HSEM_KEY_Shift, 16   @ bitWidth 16 (Semaphore Clear Key)  
 
    .equ HSEM_HWCFGR2, HSEM_BASE + 0x3EC @ (Semaphore hardware configuration register 2) 
        .equ HSEM_MASTERID4_Shift, 12   @ bitWidth 4 (Hardware Configuration valid bus masters ID4)  
        .equ HSEM_MASTERID3_Shift, 8   @ bitWidth 4 (Hardware Configuration valid bus masters ID3)  
        .equ HSEM_MASTERID2_Shift, 4   @ bitWidth 4 (Hardware Configuration valid bus masters ID2)  
        .equ HSEM_MASTERID1_Shift, 0   @ bitWidth 4 (Hardware Configuration valid bus masters ID1)  
 
    .equ HSEM_HWCFGR1, HSEM_BASE + 0x3F0 @ (Semaphore hardware configuration register 1) 
        .equ HSEM_NBINT_Shift, 8   @ bitWidth 4 (Hardware Configuration number of interrupts supported number of master IDs)  
        .equ HSEM_NBSEM_Shift, 0   @ bitWidth 8 (Hardware Configuration number of semaphores)  
 
    .equ HSEM_VERR, HSEM_BASE + 0x3F4 @ (HSEM version register) 
        .equ HSEM_MAJREV_Shift, 4   @ bitWidth 4 (Major Revision)  
        .equ HSEM_MINREV_Shift, 0   @ bitWidth 4 (Minor Revision)  
 
    .equ HSEM_IPIDR, HSEM_BASE + 0x3F8 @ (HSEM indentification register) 
        .equ HSEM_ID_Shift, 0   @ bitWidth 32 (Identification Code)  
 
    .equ HSEM_SIDR, HSEM_BASE + 0x3FC @ (HSEM size indentification register) 
        .equ HSEM_SID_Shift, 0   @ bitWidth 32 (Size Identification Code)  
 
    .equ HSEM_C1IER0, HSEM_BASE + 0x100 @ (HSEM Interrupt enable register) 
        .equ HSEM_ISEm_Shift, 0   @ bitWidth 32 (CPUn semaphore m enable bit)  
 
    .equ HSEM_C1ICR, HSEM_BASE + 0x104 @ (HSEM Interrupt clear register) 
        .equ HSEM_ISCm_Shift, 0   @ bitWidth 32 (CPUn semaphore m clear bit)  
 
    .equ HSEM_C1ISR, HSEM_BASE + 0x108 @ (HSEM Interrupt status register) 
        .equ HSEM_ISFm_Shift, 0   @ bitWidth 32 (CPUn semaphore m status bit before enable mask)  
 
    .equ HSEM_C1MISR, HSEM_BASE + 0x10C @ (HSEM Masked interrupt status register) 
        .equ HSEM_MISFm_Shift, 0   @ bitWidth 32 (masked CPUn semaphore m status bit after enable mask.)  
 
    .equ HSEM_C2IER0, HSEM_BASE + 0x110 @ (HSEM Interrupt enable register) 
        .equ HSEM_ISEm_Shift, 0   @ bitWidth 32 (CPU2 semaphore m enable bit.)  
 
    .equ HSEM_C2ICR, HSEM_BASE + 0x114 @ (HSEM Interrupt clear register) 
        .equ HSEM_ISCm_Shift, 0   @ bitWidth 32 (CPU2 semaphore m clear bit)  
 
    .equ HSEM_C2ISR, HSEM_BASE + 0x118 @ (HSEM Interrupt status register) 
        .equ HSEM_ISFm_Shift, 0   @ bitWidth 32 (CPU2 semaphore m status bit before enable mask.)  
 
    .equ HSEM_C2MISR, HSEM_BASE + 0x11C @ (HSEM Masked interrupt status register) 
        .equ HSEM_MISFm_Shift, 0   @ bitWidth 32 (masked CPU2 semaphore m status bit after enable mask.)  
 

@=========================== ADC ===========================@
.equ ADC_BASE, 0x50040000 @ (Analog to Digital Converter instance 1) 
    .equ ADC_ISR, ADC_BASE + 0x0 @ (ADC interrupt and status register) 
        .equ ADC_JQOVF_Shift, 10   @ bitWidth 1 (ADC group injected contexts queue overflow flag)  
        .equ ADC_AWD3_Shift, 9   @ bitWidth 1 (ADC analog watchdog 3 flag)  
        .equ ADC_AWD2_Shift, 8   @ bitWidth 1 (ADC analog watchdog 2 flag)  
        .equ ADC_AWD1_Shift, 7   @ bitWidth 1 (ADC analog watchdog 1 flag)  
        .equ ADC_JEOS_Shift, 6   @ bitWidth 1 (ADC group injected end of sequence conversions flag)  
        .equ ADC_JEOC_Shift, 5   @ bitWidth 1 (ADC group injected end of unitary conversion flag)  
        .equ ADC_OVR_Shift, 4   @ bitWidth 1 (ADC group regular overrun flag)  
        .equ ADC_EOS_Shift, 3   @ bitWidth 1 (ADC group regular end of sequence conversions flag)  
        .equ ADC_EOC_Shift, 2   @ bitWidth 1 (ADC group regular end of unitary conversion flag)  
        .equ ADC_EOSMP_Shift, 1   @ bitWidth 1 (ADC group regular end of sampling flag)  
        .equ ADC_ADRDY_Shift, 0   @ bitWidth 1 (ADC ready flag)  
 
    .equ ADC_IER, ADC_BASE + 0x4 @ (ADC interrupt enable register) 
        .equ ADC_JQOVFIE_Shift, 10   @ bitWidth 1 (ADC group injected contexts queue overflow interrupt)  
        .equ ADC_AWD3IE_Shift, 9   @ bitWidth 1 (ADC analog watchdog 3 interrupt)  
        .equ ADC_AWD2IE_Shift, 8   @ bitWidth 1 (ADC analog watchdog 2 interrupt)  
        .equ ADC_AWD1IE_Shift, 7   @ bitWidth 1 (ADC analog watchdog 1 interrupt)  
        .equ ADC_JEOSIE_Shift, 6   @ bitWidth 1 (ADC group injected end of sequence conversions interrupt)  
        .equ ADC_JEOCIE_Shift, 5   @ bitWidth 1 (ADC group injected end of unitary conversion interrupt)  
        .equ ADC_OVRIE_Shift, 4   @ bitWidth 1 (ADC group regular overrun interrupt)  
        .equ ADC_EOSIE_Shift, 3   @ bitWidth 1 (ADC group regular end of sequence conversions interrupt)  
        .equ ADC_EOCIE_Shift, 2   @ bitWidth 1 (ADC group regular end of unitary conversion interrupt)  
        .equ ADC_EOSMPIE_Shift, 1   @ bitWidth 1 (ADC group regular end of sampling interrupt)  
        .equ ADC_ADRDYIE_Shift, 0   @ bitWidth 1 (ADC ready interrupt)  
 
    .equ ADC_CR, ADC_BASE + 0x8 @ (ADC control register) 
        .equ ADC_ADCAL_Shift, 31   @ bitWidth 1 (ADC calibration)  
        .equ ADC_ADCALDIF_Shift, 30   @ bitWidth 1 (ADC differential mode for calibration)  
        .equ ADC_DEEPPWD_Shift, 29   @ bitWidth 1 (ADC deep power down enable)  
        .equ ADC_ADVREGEN_Shift, 28   @ bitWidth 1 (ADC voltage regulator enable)  
        .equ ADC_JADSTP_Shift, 5   @ bitWidth 1 (ADC group injected conversion stop)  
        .equ ADC_ADSTP_Shift, 4   @ bitWidth 1 (ADC group regular conversion stop)  
        .equ ADC_JADSTART_Shift, 3   @ bitWidth 1 (ADC group injected conversion start)  
        .equ ADC_ADSTART_Shift, 2   @ bitWidth 1 (ADC group regular conversion start)  
        .equ ADC_ADDIS_Shift, 1   @ bitWidth 1 (ADC disable)  
        .equ ADC_ADEN_Shift, 0   @ bitWidth 1 (ADC enable)  
 
    .equ ADC_CFGR, ADC_BASE + 0xC @ (ADC configuration register 1) 
        .equ ADC_JQDIS_Shift, 31   @ bitWidth 1 (ADC group injected contexts queue disable)  
        .equ ADC_AWDCH1CH_Shift, 26   @ bitWidth 5 (ADC analog watchdog 1 monitored channel selection)  
        .equ ADC_JAUTO_Shift, 25   @ bitWidth 1 (ADC group injected automatic trigger mode)  
        .equ ADC_JAWD1EN_Shift, 24   @ bitWidth 1 (ADC analog watchdog 1 enable on scope ADC group injected)  
        .equ ADC_AWD1EN_Shift, 23   @ bitWidth 1 (ADC analog watchdog 1 enable on scope ADC group regular)  
        .equ ADC_AWD1SGL_Shift, 22   @ bitWidth 1 (ADC analog watchdog 1 monitoring a single channel or all channels)  
        .equ ADC_JQM_Shift, 21   @ bitWidth 1 (ADC group injected contexts queue mode)  
        .equ ADC_JDISCEN_Shift, 20   @ bitWidth 1 (ADC group injected sequencer discontinuous mode)  
        .equ ADC_DISCNUM_Shift, 17   @ bitWidth 3 (ADC group regular sequencer discontinuous number of ranks)  
        .equ ADC_DISCEN_Shift, 16   @ bitWidth 1 (ADC group regular sequencer discontinuous mode)  
        .equ ADC_AUTDLY_Shift, 14   @ bitWidth 1 (ADC low power auto wait)  
        .equ ADC_CONT_Shift, 13   @ bitWidth 1 (ADC group regular continuous conversion mode)  
        .equ ADC_OVRMOD_Shift, 12   @ bitWidth 1 (ADC group regular overrun configuration)  
        .equ ADC_EXTEN_Shift, 10   @ bitWidth 2 (ADC group regular external trigger polarity)  
        .equ ADC_EXTSEL_Shift, 6   @ bitWidth 4 (ADC group regular external trigger source)  
        .equ ADC_ALIGN_Shift, 5   @ bitWidth 1 (ADC data alignement)  
        .equ ADC_RES_Shift, 3   @ bitWidth 2 (ADC data resolution)  
        .equ ADC_DMACFG_Shift, 1   @ bitWidth 1 (ADC DMA transfer configuration)  
        .equ ADC_DMAEN_Shift, 0   @ bitWidth 1 (ADC DMA transfer enable)  
 
    .equ ADC_CFGR2, ADC_BASE + 0x10 @ (ADC configuration register 2) 
        .equ ADC_ROVSM_Shift, 10   @ bitWidth 1 (ADC oversampling mode managing interlaced conversions of ADC group regular and group injected)  
        .equ ADC_TOVS_Shift, 9   @ bitWidth 1 (ADC oversampling discontinuous mode triggered mode for ADC group regular)  
        .equ ADC_OVSS_Shift, 5   @ bitWidth 4 (ADC oversampling shift)  
        .equ ADC_OVSR_Shift, 2   @ bitWidth 3 (ADC oversampling ratio)  
        .equ ADC_JOVSE_Shift, 1   @ bitWidth 1 (ADC oversampler enable on scope ADC group injected)  
        .equ ADC_ROVSE_Shift, 0   @ bitWidth 1 (ADC oversampler enable on scope ADC group regular)  
 
    .equ ADC_SMPR1, ADC_BASE + 0x14 @ (ADC sampling time register 1) 
        .equ ADC_SMP9_Shift, 27   @ bitWidth 3 (ADC channel 9 sampling time selection)  
        .equ ADC_SMP8_Shift, 24   @ bitWidth 3 (ADC channel 8 sampling time selection)  
        .equ ADC_SMP7_Shift, 21   @ bitWidth 3 (ADC channel 7 sampling time selection)  
        .equ ADC_SMP6_Shift, 18   @ bitWidth 3 (ADC channel 6 sampling time selection)  
        .equ ADC_SMP5_Shift, 15   @ bitWidth 3 (ADC channel 5 sampling time selection)  
        .equ ADC_SMP4_Shift, 12   @ bitWidth 3 (ADC channel 4 sampling time selection)  
        .equ ADC_SMP3_Shift, 9   @ bitWidth 3 (ADC channel 3 sampling time selection)  
        .equ ADC_SMP2_Shift, 6   @ bitWidth 3 (ADC channel 2 sampling time selection)  
        .equ ADC_SMP1_Shift, 3   @ bitWidth 3 (ADC channel 1 sampling time selection)  
 
    .equ ADC_SMPR2, ADC_BASE + 0x18 @ (ADC sampling time register 2) 
        .equ ADC_SMP18_Shift, 24   @ bitWidth 3 (ADC channel 18 sampling time selection)  
        .equ ADC_SMP17_Shift, 21   @ bitWidth 3 (ADC channel 17 sampling time selection)  
        .equ ADC_SMP16_Shift, 18   @ bitWidth 3 (ADC channel 16 sampling time selection)  
        .equ ADC_SMP15_Shift, 15   @ bitWidth 3 (ADC channel 15 sampling time selection)  
        .equ ADC_SMP14_Shift, 12   @ bitWidth 3 (ADC channel 14 sampling time selection)  
        .equ ADC_SMP13_Shift, 9   @ bitWidth 3 (ADC channel 13 sampling time selection)  
        .equ ADC_SMP12_Shift, 6   @ bitWidth 3 (ADC channel 12 sampling time selection)  
        .equ ADC_SMP11_Shift, 3   @ bitWidth 3 (ADC channel 11 sampling time selection)  
        .equ ADC_SMP10_Shift, 0   @ bitWidth 3 (ADC channel 10 sampling time selection)  
 
    .equ ADC_TR1, ADC_BASE + 0x20 @ (ADC analog watchdog 1 threshold register) 
        .equ ADC_HT1_Shift, 16   @ bitWidth 12 (ADC analog watchdog 1 threshold high)  
        .equ ADC_LT1_Shift, 0   @ bitWidth 12 (ADC analog watchdog 1 threshold low)  
 
    .equ ADC_TR2, ADC_BASE + 0x24 @ (ADC analog watchdog 2 threshold register) 
        .equ ADC_HT2_Shift, 16   @ bitWidth 8 (ADC analog watchdog 2 threshold high)  
        .equ ADC_LT2_Shift, 0   @ bitWidth 8 (ADC analog watchdog 2 threshold low)  
 
    .equ ADC_TR3, ADC_BASE + 0x28 @ (ADC analog watchdog 3 threshold register) 
        .equ ADC_HT3_Shift, 16   @ bitWidth 8 (ADC analog watchdog 3 threshold high)  
        .equ ADC_LT3_Shift, 0   @ bitWidth 8 (ADC analog watchdog 3 threshold low)  
 
    .equ ADC_SQR1, ADC_BASE + 0x30 @ (ADC group regular sequencer ranks register 1) 
        .equ ADC_SQ4_Shift, 24   @ bitWidth 5 (ADC group regular sequencer rank 4)  
        .equ ADC_SQ3_Shift, 18   @ bitWidth 5 (ADC group regular sequencer rank 3)  
        .equ ADC_SQ2_Shift, 12   @ bitWidth 5 (ADC group regular sequencer rank 2)  
        .equ ADC_SQ1_Shift, 6   @ bitWidth 5 (ADC group regular sequencer rank 1)  
        .equ ADC_L3_Shift, 0   @ bitWidth 4 (L3)  
 
    .equ ADC_SQR2, ADC_BASE + 0x34 @ (ADC group regular sequencer ranks register 2) 
        .equ ADC_SQ9_Shift, 24   @ bitWidth 5 (ADC group regular sequencer rank 9)  
        .equ ADC_SQ8_Shift, 18   @ bitWidth 5 (ADC group regular sequencer rank 8)  
        .equ ADC_SQ7_Shift, 12   @ bitWidth 5 (ADC group regular sequencer rank 7)  
        .equ ADC_SQ6_Shift, 6   @ bitWidth 5 (ADC group regular sequencer rank 6)  
        .equ ADC_SQ5_Shift, 0   @ bitWidth 5 (ADC group regular sequencer rank 5)  
 
    .equ ADC_SQR3, ADC_BASE + 0x38 @ (ADC group regular sequencer ranks register 3) 
        .equ ADC_SQ14_Shift, 24   @ bitWidth 5 (ADC group regular sequencer rank 14)  
        .equ ADC_SQ13_Shift, 18   @ bitWidth 5 (ADC group regular sequencer rank 13)  
        .equ ADC_SQ12_Shift, 12   @ bitWidth 5 (ADC group regular sequencer rank 12)  
        .equ ADC_SQ11_Shift, 6   @ bitWidth 5 (ADC group regular sequencer rank 11)  
        .equ ADC_SQ10_Shift, 0   @ bitWidth 5 (ADC group regular sequencer rank 10)  
 
    .equ ADC_SQR4, ADC_BASE + 0x3C @ (ADC group regular sequencer ranks register 4) 
        .equ ADC_SQ16_Shift, 6   @ bitWidth 5 (ADC group regular sequencer rank 16)  
        .equ ADC_SQ15_Shift, 0   @ bitWidth 5 (ADC group regular sequencer rank 15)  
 
    .equ ADC_DR, ADC_BASE + 0x40 @ (ADC group regular conversion data register) 
        .equ ADC_RDATA_0_6_Shift, 0   @ bitWidth 6 (Regular Data converted 0_6)  
        .equ ADC_RDATA_7_15_Shift, 7   @ bitWidth 9 (15)  
 
    .equ ADC_JSQR, ADC_BASE + 0x4C @ (ADC group injected sequencer register) 
        .equ ADC_JSQ4_Shift, 26   @ bitWidth 5 (ADC group injected sequencer rank 4)  
        .equ ADC_JSQ3_Shift, 20   @ bitWidth 5 (ADC group injected sequencer rank 3)  
        .equ ADC_JSQ2_Shift, 14   @ bitWidth 5 (ADC group injected sequencer rank 2)  
        .equ ADC_JSQ1_Shift, 8   @ bitWidth 5 (ADC group injected sequencer rank 1)  
        .equ ADC_JEXTEN_Shift, 6   @ bitWidth 2 (ADC group injected external trigger polarity)  
        .equ ADC_JEXTSEL_Shift, 2   @ bitWidth 4 (ADC group injected external trigger source)  
        .equ ADC_JL_Shift, 0   @ bitWidth 2 (ADC group injected sequencer scan length)  
 
    .equ ADC_OFR1, ADC_BASE + 0x60 @ (ADC offset number 1 register) 
        .equ ADC_OFFSET1_EN_Shift, 31   @ bitWidth 1 (ADC offset number 1 enable)  
        .equ ADC_OFFSET1_CH_Shift, 26   @ bitWidth 5 (ADC offset number 1 channel selection)  
        .equ ADC_OFFSET1_Shift, 0   @ bitWidth 12 (ADC offset number 1 offset level)  
 
    .equ ADC_OFR2, ADC_BASE + 0x64 @ (ADC offset number 2 register) 
        .equ ADC_OFFSET2_EN_Shift, 31   @ bitWidth 1 (ADC offset number 2 enable)  
        .equ ADC_OFFSET2_CH_Shift, 26   @ bitWidth 5 (ADC offset number 2 channel selection)  
        .equ ADC_OFFSET2_Shift, 0   @ bitWidth 12 (ADC offset number 2 offset level)  
 
    .equ ADC_OFR3, ADC_BASE + 0x68 @ (ADC offset number 3 register) 
        .equ ADC_OFFSET3_EN_Shift, 31   @ bitWidth 1 (ADC offset number 3 enable)  
        .equ ADC_OFFSET3_CH_Shift, 26   @ bitWidth 5 (ADC offset number 3 channel selection)  
        .equ ADC_OFFSET3_Shift, 0   @ bitWidth 12 (ADC offset number 3 offset level)  
 
    .equ ADC_OFR4, ADC_BASE + 0x6C @ (ADC offset number 4 register) 
        .equ ADC_OFFSET4_EN_Shift, 31   @ bitWidth 1 (ADC offset number 4 enable)  
        .equ ADC_OFFSET4_CH_Shift, 26   @ bitWidth 5 (ADC offset number 4 channel selection)  
        .equ ADC_OFFSET4_Shift, 0   @ bitWidth 12 (ADC offset number 4 offset level)  
 
    .equ ADC_JDR1, ADC_BASE + 0x80 @ (ADC group injected sequencer rank 1 register) 
        .equ ADC_JDATA1_Shift, 0   @ bitWidth 16 (ADC group injected sequencer rank 1 conversion data)  
 
    .equ ADC_JDR2, ADC_BASE + 0x84 @ (ADC group injected sequencer rank 2 register) 
        .equ ADC_JDATA2_Shift, 0   @ bitWidth 16 (ADC group injected sequencer rank 2 conversion data)  
 
    .equ ADC_JDR3, ADC_BASE + 0x88 @ (ADC group injected sequencer rank 3 register) 
        .equ ADC_JDATA3_Shift, 0   @ bitWidth 16 (ADC group injected sequencer rank 3 conversion data)  
 
    .equ ADC_JDR4, ADC_BASE + 0x8C @ (ADC group injected sequencer rank 4 register) 
        .equ ADC_JDATA4_Shift, 0   @ bitWidth 16 (ADC group injected sequencer rank 4 conversion data)  
 
    .equ ADC_AWD2CR, ADC_BASE + 0xA0 @ (ADC analog watchdog 2 configuration register) 
        .equ ADC_AWD2CH_Shift, 0   @ bitWidth 19 (ADC analog watchdog 2 monitored channel selection)  
 
    .equ ADC_AWD3CR, ADC_BASE + 0xA4 @ (ADC analog watchdog 3 configuration register) 
        .equ ADC_AWD3CH_Shift, 0   @ bitWidth 19 (ADC analog watchdog 3 monitored channel selection)  
 
    .equ ADC_DIFSEL, ADC_BASE + 0xB0 @ (ADC channel differential or single-ended mode selection register) 
        .equ ADC_DIFSEL_0_Shift, 0   @ bitWidth 1 (ADC channel differential or single-ended mode for channel 0)  
        .equ ADC_DIFSEL_1_15_Shift, 1   @ bitWidth 15 (ADC channel differential or single-ended mode for channels 1 to 15)  
        .equ ADC_DIFSEL_16_18_Shift, 16   @ bitWidth 3 (ADC channel differential or single-ended mode for channels 18 to 16)  
 
    .equ ADC_CALFACT, ADC_BASE + 0xB4 @ (ADC calibration factors register) 
        .equ ADC_CALFACT_D_Shift, 16   @ bitWidth 7 (ADC calibration factor in differential mode)  
        .equ ADC_CALFACT_S_Shift, 0   @ bitWidth 7 (ADC calibration factor in single-ended mode)  
 
    .equ ADC_CCR, ADC_BASE + 0x308 @ (ADC common control register) 
        .equ ADC_VBATEN_Shift, 24   @ bitWidth 1 (VBAT enable)  
        .equ ADC_TSEN_Shift, 23   @ bitWidth 1 (Temperature sensor enable)  
        .equ ADC_VREFEN_Shift, 22   @ bitWidth 1 (VREFEN)  
        .equ ADC_PRESC_Shift, 18   @ bitWidth 4 (ADC prescaler)  
        .equ ADC_CKMODE_Shift, 16   @ bitWidth 2 (ADC clock mode)  
 

@=========================== GPIOA ===========================@
.equ GPIOA_BASE, 0x48000000 @ (General-purpose I/Os) 
    .equ GPIOA_MODER, GPIOA_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOA_MODER15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_MODER0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOA_OTYPER, GPIOA_BASE + 0x4 @ (GPIO port output type register) 
        .equ GPIOA_OT15_Shift, 15   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT14_Shift, 14   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT13_Shift, 13   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT12_Shift, 12   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT11_Shift, 11   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT10_Shift, 10   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT9_Shift, 9   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT8_Shift, 8   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT7_Shift, 7   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT6_Shift, 6   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT5_Shift, 5   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT4_Shift, 4   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT3_Shift, 3   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT2_Shift, 2   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT1_Shift, 1   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OT0_Shift, 0   @ bitWidth 1 (Port x configuration bits y = 0..15)  
 
    .equ GPIOA_OSPEEDR, GPIOA_BASE + 0x8 @ (GPIO port output speed register) 
        .equ GPIOA_OSPEEDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_OSPEEDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOA_PUPDR, GPIOA_BASE + 0xC @ (GPIO port pull-up/pull-down register) 
        .equ GPIOA_PUPDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOA_PUPDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOA_IDR, GPIOA_BASE + 0x10 @ (GPIO port input data register) 
        .equ GPIOA_IDR15_Shift, 15   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR14_Shift, 14   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR13_Shift, 13   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR12_Shift, 12   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR11_Shift, 11   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR10_Shift, 10   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR9_Shift, 9   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR8_Shift, 8   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR7_Shift, 7   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR6_Shift, 6   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR5_Shift, 5   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR4_Shift, 4   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR3_Shift, 3   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR2_Shift, 2   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR1_Shift, 1   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOA_IDR0_Shift, 0   @ bitWidth 1 (Port input data y = 0..15)  
 
    .equ GPIOA_ODR, GPIOA_BASE + 0x14 @ (GPIO port output data register) 
        .equ GPIOA_ODR15_Shift, 15   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR14_Shift, 14   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR13_Shift, 13   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR12_Shift, 12   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR11_Shift, 11   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR10_Shift, 10   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR9_Shift, 9   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR8_Shift, 8   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR7_Shift, 7   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR6_Shift, 6   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR5_Shift, 5   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR4_Shift, 4   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR3_Shift, 3   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR2_Shift, 2   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR1_Shift, 1   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOA_ODR0_Shift, 0   @ bitWidth 1 (Port output data y = 0..15)  
 
    .equ GPIOA_BSRR, GPIOA_BASE + 0x18 @ (GPIO port bit set/reset register) 
        .equ GPIOA_BR15_Shift, 31   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR14_Shift, 30   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR13_Shift, 29   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR12_Shift, 28   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR11_Shift, 27   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR10_Shift, 26   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR9_Shift, 25   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR8_Shift, 24   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR7_Shift, 23   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR6_Shift, 22   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR5_Shift, 21   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR4_Shift, 20   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR3_Shift, 19   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR2_Shift, 18   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR1_Shift, 17   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOA_BR0_Shift, 16   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS15_Shift, 15   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS14_Shift, 14   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS13_Shift, 13   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS12_Shift, 12   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS11_Shift, 11   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS10_Shift, 10   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS9_Shift, 9   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS8_Shift, 8   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS7_Shift, 7   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS6_Shift, 6   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS5_Shift, 5   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS4_Shift, 4   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS3_Shift, 3   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS2_Shift, 2   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS1_Shift, 1   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOA_BS0_Shift, 0   @ bitWidth 1 (Port x set bit y y= 0..15)  
 
    .equ GPIOA_LCKR, GPIOA_BASE + 0x1C @ (GPIO port configuration lock register) 
        .equ GPIOA_LCKK_Shift, 16   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK15_Shift, 15   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK14_Shift, 14   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK13_Shift, 13   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK12_Shift, 12   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK11_Shift, 11   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK10_Shift, 10   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK9_Shift, 9   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK8_Shift, 8   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK7_Shift, 7   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK6_Shift, 6   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK5_Shift, 5   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK4_Shift, 4   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK3_Shift, 3   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK2_Shift, 2   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK1_Shift, 1   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOA_LCK0_Shift, 0   @ bitWidth 1 (Port x lock bit y y= 0..15)  
 
    .equ GPIOA_AFRL, GPIOA_BASE + 0x20 @ (GPIO alternate function low register) 
        .equ GPIOA_AFSEL7_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL6_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL5_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL4_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL3_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL2_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL1_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOA_AFSEL0_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
 
    .equ GPIOA_AFRH, GPIOA_BASE + 0x24 @ (GPIO alternate function high register) 
        .equ GPIOA_AFSEL15_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL14_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL13_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL12_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL11_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL10_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL9_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOA_AFSEL8_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
 
    .equ GPIOA_BRR, GPIOA_BASE + 0x28 @ (port bit reset register) 
        .equ GPIOA_BR0_Shift, 0   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR1_Shift, 1   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR2_Shift, 2   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR3_Shift, 3   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR4_Shift, 4   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR5_Shift, 5   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR6_Shift, 6   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR7_Shift, 7   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR8_Shift, 8   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR9_Shift, 9   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR10_Shift, 10   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR11_Shift, 11   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR12_Shift, 12   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR13_Shift, 13   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR14_Shift, 14   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOA_BR15_Shift, 15   @ bitWidth 1 (Port Reset bit)  
 

@=========================== GPIOB ===========================@
.equ GPIOB_BASE, 0x48000400 @ (General-purpose I/Os) 
    .equ GPIOB_MODER, GPIOB_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOB_MODER15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_MODER0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOB_OTYPER, GPIOB_BASE + 0x4 @ (GPIO port output type register) 
        .equ GPIOB_OT15_Shift, 15   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT14_Shift, 14   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT13_Shift, 13   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT12_Shift, 12   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT11_Shift, 11   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT10_Shift, 10   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT9_Shift, 9   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT8_Shift, 8   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT7_Shift, 7   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT6_Shift, 6   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT5_Shift, 5   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT4_Shift, 4   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT3_Shift, 3   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT2_Shift, 2   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT1_Shift, 1   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OT0_Shift, 0   @ bitWidth 1 (Port x configuration bits y = 0..15)  
 
    .equ GPIOB_OSPEEDR, GPIOB_BASE + 0x8 @ (GPIO port output speed register) 
        .equ GPIOB_OSPEEDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_OSPEEDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOB_PUPDR, GPIOB_BASE + 0xC @ (GPIO port pull-up/pull-down register) 
        .equ GPIOB_PUPDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOB_PUPDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOB_IDR, GPIOB_BASE + 0x10 @ (GPIO port input data register) 
        .equ GPIOB_IDR15_Shift, 15   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR14_Shift, 14   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR13_Shift, 13   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR12_Shift, 12   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR11_Shift, 11   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR10_Shift, 10   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR9_Shift, 9   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR8_Shift, 8   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR7_Shift, 7   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR6_Shift, 6   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR5_Shift, 5   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR4_Shift, 4   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR3_Shift, 3   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR2_Shift, 2   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR1_Shift, 1   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOB_IDR0_Shift, 0   @ bitWidth 1 (Port input data y = 0..15)  
 
    .equ GPIOB_ODR, GPIOB_BASE + 0x14 @ (GPIO port output data register) 
        .equ GPIOB_ODR15_Shift, 15   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR14_Shift, 14   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR13_Shift, 13   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR12_Shift, 12   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR11_Shift, 11   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR10_Shift, 10   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR9_Shift, 9   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR8_Shift, 8   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR7_Shift, 7   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR6_Shift, 6   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR5_Shift, 5   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR4_Shift, 4   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR3_Shift, 3   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR2_Shift, 2   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR1_Shift, 1   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOB_ODR0_Shift, 0   @ bitWidth 1 (Port output data y = 0..15)  
 
    .equ GPIOB_BSRR, GPIOB_BASE + 0x18 @ (GPIO port bit set/reset register) 
        .equ GPIOB_BR15_Shift, 31   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR14_Shift, 30   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR13_Shift, 29   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR12_Shift, 28   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR11_Shift, 27   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR10_Shift, 26   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR9_Shift, 25   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR8_Shift, 24   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR7_Shift, 23   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR6_Shift, 22   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR5_Shift, 21   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR4_Shift, 20   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR3_Shift, 19   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR2_Shift, 18   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR1_Shift, 17   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOB_BR0_Shift, 16   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS15_Shift, 15   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS14_Shift, 14   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS13_Shift, 13   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS12_Shift, 12   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS11_Shift, 11   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS10_Shift, 10   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS9_Shift, 9   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS8_Shift, 8   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS7_Shift, 7   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS6_Shift, 6   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS5_Shift, 5   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS4_Shift, 4   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS3_Shift, 3   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS2_Shift, 2   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS1_Shift, 1   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOB_BS0_Shift, 0   @ bitWidth 1 (Port x set bit y y= 0..15)  
 
    .equ GPIOB_LCKR, GPIOB_BASE + 0x1C @ (GPIO port configuration lock register) 
        .equ GPIOB_LCKK_Shift, 16   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK15_Shift, 15   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK14_Shift, 14   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK13_Shift, 13   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK12_Shift, 12   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK11_Shift, 11   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK10_Shift, 10   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK9_Shift, 9   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK8_Shift, 8   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK7_Shift, 7   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK6_Shift, 6   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK5_Shift, 5   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK4_Shift, 4   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK3_Shift, 3   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK2_Shift, 2   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK1_Shift, 1   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOB_LCK0_Shift, 0   @ bitWidth 1 (Port x lock bit y y= 0..15)  
 
    .equ GPIOB_AFRL, GPIOB_BASE + 0x20 @ (GPIO alternate function low register) 
        .equ GPIOB_AFSEL7_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL6_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL5_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL4_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL3_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL2_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL1_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOB_AFSEL0_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
 
    .equ GPIOB_AFRH, GPIOB_BASE + 0x24 @ (GPIO alternate function high register) 
        .equ GPIOB_AFSEL15_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL14_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL13_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL12_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL11_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL10_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL9_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOB_AFSEL8_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
 
    .equ GPIOB_BRR, GPIOB_BASE + 0x28 @ (port bit reset register) 
        .equ GPIOB_BR0_Shift, 0   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR1_Shift, 1   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR2_Shift, 2   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR3_Shift, 3   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR4_Shift, 4   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR5_Shift, 5   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR6_Shift, 6   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR7_Shift, 7   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR8_Shift, 8   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR9_Shift, 9   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR10_Shift, 10   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR11_Shift, 11   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR12_Shift, 12   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR13_Shift, 13   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR14_Shift, 14   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOB_BR15_Shift, 15   @ bitWidth 1 (Port Reset bit)  
 

@=========================== GPIOC ===========================@
.equ GPIOC_BASE, 0x48000800 @ (General-purpose I/Os) 
    .equ GPIOC_MODER, GPIOC_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOC_MODER15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_MODER0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOC_OTYPER, GPIOC_BASE + 0x4 @ (GPIO port output type register) 
        .equ GPIOC_OT15_Shift, 15   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT14_Shift, 14   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT13_Shift, 13   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT12_Shift, 12   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT11_Shift, 11   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT10_Shift, 10   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT9_Shift, 9   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT8_Shift, 8   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT7_Shift, 7   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT6_Shift, 6   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT5_Shift, 5   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT4_Shift, 4   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT3_Shift, 3   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT2_Shift, 2   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT1_Shift, 1   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OT0_Shift, 0   @ bitWidth 1 (Port x configuration bits y = 0..15)  
 
    .equ GPIOC_OSPEEDR, GPIOC_BASE + 0x8 @ (GPIO port output speed register) 
        .equ GPIOC_OSPEEDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_OSPEEDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOC_PUPDR, GPIOC_BASE + 0xC @ (GPIO port pull-up/pull-down register) 
        .equ GPIOC_PUPDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOC_PUPDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOC_IDR, GPIOC_BASE + 0x10 @ (GPIO port input data register) 
        .equ GPIOC_IDR15_Shift, 15   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR14_Shift, 14   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR13_Shift, 13   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR12_Shift, 12   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR11_Shift, 11   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR10_Shift, 10   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR9_Shift, 9   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR8_Shift, 8   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR7_Shift, 7   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR6_Shift, 6   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR5_Shift, 5   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR4_Shift, 4   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR3_Shift, 3   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR2_Shift, 2   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR1_Shift, 1   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOC_IDR0_Shift, 0   @ bitWidth 1 (Port input data y = 0..15)  
 
    .equ GPIOC_ODR, GPIOC_BASE + 0x14 @ (GPIO port output data register) 
        .equ GPIOC_ODR15_Shift, 15   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR14_Shift, 14   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR13_Shift, 13   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR12_Shift, 12   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR11_Shift, 11   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR10_Shift, 10   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR9_Shift, 9   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR8_Shift, 8   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR7_Shift, 7   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR6_Shift, 6   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR5_Shift, 5   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR4_Shift, 4   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR3_Shift, 3   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR2_Shift, 2   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR1_Shift, 1   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOC_ODR0_Shift, 0   @ bitWidth 1 (Port output data y = 0..15)  
 
    .equ GPIOC_BSRR, GPIOC_BASE + 0x18 @ (GPIO port bit set/reset register) 
        .equ GPIOC_BR15_Shift, 31   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR14_Shift, 30   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR13_Shift, 29   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR12_Shift, 28   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR11_Shift, 27   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR10_Shift, 26   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR9_Shift, 25   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR8_Shift, 24   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR7_Shift, 23   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR6_Shift, 22   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR5_Shift, 21   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR4_Shift, 20   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR3_Shift, 19   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR2_Shift, 18   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR1_Shift, 17   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOC_BR0_Shift, 16   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS15_Shift, 15   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS14_Shift, 14   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS13_Shift, 13   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS12_Shift, 12   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS11_Shift, 11   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS10_Shift, 10   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS9_Shift, 9   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS8_Shift, 8   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS7_Shift, 7   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS6_Shift, 6   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS5_Shift, 5   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS4_Shift, 4   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS3_Shift, 3   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS2_Shift, 2   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS1_Shift, 1   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOC_BS0_Shift, 0   @ bitWidth 1 (Port x set bit y y= 0..15)  
 
    .equ GPIOC_LCKR, GPIOC_BASE + 0x1C @ (GPIO port configuration lock register) 
        .equ GPIOC_LCKK_Shift, 16   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK15_Shift, 15   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK14_Shift, 14   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK13_Shift, 13   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK12_Shift, 12   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK11_Shift, 11   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK10_Shift, 10   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK9_Shift, 9   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK8_Shift, 8   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK7_Shift, 7   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK6_Shift, 6   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK5_Shift, 5   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK4_Shift, 4   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK3_Shift, 3   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK2_Shift, 2   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK1_Shift, 1   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOC_LCK0_Shift, 0   @ bitWidth 1 (Port x lock bit y y= 0..15)  
 
    .equ GPIOC_AFRL, GPIOC_BASE + 0x20 @ (GPIO alternate function low register) 
        .equ GPIOC_AFSEL7_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL6_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL5_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL4_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL3_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL2_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL1_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOC_AFSEL0_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
 
    .equ GPIOC_AFRH, GPIOC_BASE + 0x24 @ (GPIO alternate function high register) 
        .equ GPIOC_AFSEL15_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL14_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL13_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL12_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL11_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL10_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL9_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOC_AFSEL8_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
 
    .equ GPIOC_BRR, GPIOC_BASE + 0x28 @ (port bit reset register) 
        .equ GPIOC_BR0_Shift, 0   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR1_Shift, 1   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR2_Shift, 2   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR3_Shift, 3   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR4_Shift, 4   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR5_Shift, 5   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR6_Shift, 6   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR7_Shift, 7   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR8_Shift, 8   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR9_Shift, 9   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR10_Shift, 10   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR11_Shift, 11   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR12_Shift, 12   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR13_Shift, 13   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR14_Shift, 14   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOC_BR15_Shift, 15   @ bitWidth 1 (Port Reset bit)  
 

@=========================== GPIOD ===========================@
.equ GPIOD_BASE, 0x48000C00 @ (General-purpose I/Os) 
    .equ GPIOD_MODER, GPIOD_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOD_MODER15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_MODER0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOD_OTYPER, GPIOD_BASE + 0x4 @ (GPIO port output type register) 
        .equ GPIOD_OT15_Shift, 15   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT14_Shift, 14   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT13_Shift, 13   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT12_Shift, 12   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT11_Shift, 11   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT10_Shift, 10   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT9_Shift, 9   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT8_Shift, 8   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT7_Shift, 7   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT6_Shift, 6   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT5_Shift, 5   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT4_Shift, 4   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT3_Shift, 3   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT2_Shift, 2   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT1_Shift, 1   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OT0_Shift, 0   @ bitWidth 1 (Port x configuration bits y = 0..15)  
 
    .equ GPIOD_OSPEEDR, GPIOD_BASE + 0x8 @ (GPIO port output speed register) 
        .equ GPIOD_OSPEEDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_OSPEEDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOD_PUPDR, GPIOD_BASE + 0xC @ (GPIO port pull-up/pull-down register) 
        .equ GPIOD_PUPDR15_Shift, 30   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR14_Shift, 28   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR13_Shift, 26   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR12_Shift, 24   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR11_Shift, 22   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR10_Shift, 20   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR9_Shift, 18   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR8_Shift, 16   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR7_Shift, 14   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR6_Shift, 12   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR5_Shift, 10   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOD_PUPDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOD_IDR, GPIOD_BASE + 0x10 @ (GPIO port input data register) 
        .equ GPIOD_IDR15_Shift, 15   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR14_Shift, 14   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR13_Shift, 13   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR12_Shift, 12   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR11_Shift, 11   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR10_Shift, 10   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR9_Shift, 9   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR8_Shift, 8   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR7_Shift, 7   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR6_Shift, 6   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR5_Shift, 5   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR4_Shift, 4   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR3_Shift, 3   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR2_Shift, 2   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR1_Shift, 1   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOD_IDR0_Shift, 0   @ bitWidth 1 (Port input data y = 0..15)  
 
    .equ GPIOD_ODR, GPIOD_BASE + 0x14 @ (GPIO port output data register) 
        .equ GPIOD_ODR15_Shift, 15   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR14_Shift, 14   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR13_Shift, 13   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR12_Shift, 12   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR11_Shift, 11   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR10_Shift, 10   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR9_Shift, 9   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR8_Shift, 8   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR7_Shift, 7   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR6_Shift, 6   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR5_Shift, 5   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR4_Shift, 4   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR3_Shift, 3   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR2_Shift, 2   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR1_Shift, 1   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOD_ODR0_Shift, 0   @ bitWidth 1 (Port output data y = 0..15)  
 
    .equ GPIOD_BSRR, GPIOD_BASE + 0x18 @ (GPIO port bit set/reset register) 
        .equ GPIOD_BR15_Shift, 31   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR14_Shift, 30   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR13_Shift, 29   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR12_Shift, 28   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR11_Shift, 27   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR10_Shift, 26   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR9_Shift, 25   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR8_Shift, 24   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR7_Shift, 23   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR6_Shift, 22   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR5_Shift, 21   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR4_Shift, 20   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR3_Shift, 19   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR2_Shift, 18   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR1_Shift, 17   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOD_BR0_Shift, 16   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS15_Shift, 15   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS14_Shift, 14   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS13_Shift, 13   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS12_Shift, 12   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS11_Shift, 11   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS10_Shift, 10   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS9_Shift, 9   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS8_Shift, 8   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS7_Shift, 7   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS6_Shift, 6   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS5_Shift, 5   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS4_Shift, 4   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS3_Shift, 3   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS2_Shift, 2   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS1_Shift, 1   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOD_BS0_Shift, 0   @ bitWidth 1 (Port x set bit y y= 0..15)  
 
    .equ GPIOD_LCKR, GPIOD_BASE + 0x1C @ (GPIO port configuration lock register) 
        .equ GPIOD_LCKK_Shift, 16   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK15_Shift, 15   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK14_Shift, 14   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK13_Shift, 13   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK12_Shift, 12   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK11_Shift, 11   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK10_Shift, 10   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK9_Shift, 9   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK8_Shift, 8   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK7_Shift, 7   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK6_Shift, 6   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK5_Shift, 5   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK4_Shift, 4   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK3_Shift, 3   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK2_Shift, 2   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK1_Shift, 1   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOD_LCK0_Shift, 0   @ bitWidth 1 (Port x lock bit y y= 0..15)  
 
    .equ GPIOD_AFRL, GPIOD_BASE + 0x20 @ (GPIO alternate function low register) 
        .equ GPIOD_AFSEL7_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL6_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL5_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL4_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL3_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL2_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL1_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOD_AFSEL0_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
 
    .equ GPIOD_AFRH, GPIOD_BASE + 0x24 @ (GPIO alternate function high register) 
        .equ GPIOD_AFSEL15_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL14_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL13_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL12_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL11_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL10_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL9_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOD_AFSEL8_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
 
    .equ GPIOD_BRR, GPIOD_BASE + 0x28 @ (port bit reset register) 
        .equ GPIOD_BR0_Shift, 0   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR1_Shift, 1   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR2_Shift, 2   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR3_Shift, 3   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR4_Shift, 4   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR5_Shift, 5   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR6_Shift, 6   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR7_Shift, 7   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR8_Shift, 8   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR9_Shift, 9   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR10_Shift, 10   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR11_Shift, 11   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR12_Shift, 12   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR13_Shift, 13   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR14_Shift, 14   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOD_BR15_Shift, 15   @ bitWidth 1 (Port Reset bit)  
 

@=========================== GPIOE ===========================@
.equ GPIOE_BASE, 0x48001000 @ (General-purpose I/Os) 
    .equ GPIOE_MODER, GPIOE_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOE_MODER4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_MODER3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_MODER2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_MODER1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_MODER0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOE_OTYPER, GPIOE_BASE + 0x4 @ (GPIO port output type register) 
        .equ GPIOE_OT4_Shift, 4   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OT3_Shift, 3   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OT2_Shift, 2   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OT1_Shift, 1   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OT0_Shift, 0   @ bitWidth 1 (Port x configuration bits y = 0..15)  
 
    .equ GPIOE_OSPEEDR, GPIOE_BASE + 0x8 @ (GPIO port output speed register) 
        .equ GPIOE_OSPEEDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OSPEEDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OSPEEDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OSPEEDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_OSPEEDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOE_PUPDR, GPIOE_BASE + 0xC @ (GPIO port pull-up/pull-down register) 
        .equ GPIOE_PUPDR4_Shift, 8   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_PUPDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_PUPDR2_Shift, 4   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_PUPDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOE_PUPDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOE_IDR, GPIOE_BASE + 0x10 @ (GPIO port input data register) 
        .equ GPIOE_IDR4_Shift, 4   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOE_IDR3_Shift, 3   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOE_IDR2_Shift, 2   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOE_IDR1_Shift, 1   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOE_IDR0_Shift, 0   @ bitWidth 1 (Port input data y = 0..15)  
 
    .equ GPIOE_ODR, GPIOE_BASE + 0x14 @ (GPIO port output data register) 
        .equ GPIOE_ODR4_Shift, 4   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOE_ODR3_Shift, 3   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOE_ODR2_Shift, 2   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOE_ODR1_Shift, 1   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOE_ODR0_Shift, 0   @ bitWidth 1 (Port output data y = 0..15)  
 
    .equ GPIOE_BSRR, GPIOE_BASE + 0x18 @ (GPIO port bit set/reset register) 
        .equ GPIOE_BR4_Shift, 20   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOE_BR3_Shift, 19   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOE_BR2_Shift, 18   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOE_BR1_Shift, 17   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOE_BR0_Shift, 16   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOE_BS4_Shift, 4   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOE_BS3_Shift, 3   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOE_BS2_Shift, 2   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOE_BS1_Shift, 1   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOE_BS0_Shift, 0   @ bitWidth 1 (Port x set bit y y= 0..15)  
 
    .equ GPIOE_LCKR, GPIOE_BASE + 0x1C @ (GPIO port configuration lock register) 
        .equ GPIOE_LCKK_Shift, 16   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOE_LCK4_Shift, 4   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOE_LCK3_Shift, 3   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOE_LCK2_Shift, 2   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOE_LCK1_Shift, 1   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOE_LCK0_Shift, 0   @ bitWidth 1 (Port x lock bit y y= 0..15)  
 
    .equ GPIOE_AFRL, GPIOE_BASE + 0x20 @ (GPIO alternate function low register) 
        .equ GPIOE_AFSEL4_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOE_AFSEL3_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOE_AFSEL2_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOE_AFSEL1_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOE_AFSEL0_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
 
    .equ GPIOE_AFRH, GPIOE_BASE + 0x24 @ (GPIO alternate function high register) 
        .equ GPIOE_AFSEL15_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL14_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL13_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL12_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL11_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL10_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL9_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOE_AFSEL8_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
 
    .equ GPIOE_BRR, GPIOE_BASE + 0x28 @ (port bit reset register) 
        .equ GPIOE_BR0_Shift, 0   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOE_BR1_Shift, 1   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOE_BR2_Shift, 2   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOE_BR3_Shift, 3   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOE_BR4_Shift, 4   @ bitWidth 1 (Port Reset bit)  
 

@=========================== GPIOH ===========================@
.equ GPIOH_BASE, 0x48001C00 @ (General-purpose I/Os) 
    .equ GPIOH_MODER, GPIOH_BASE + 0x0 @ (GPIO port mode register) 
        .equ GPIOH_MODER3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOH_MODER1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOH_MODER0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOH_OTYPER, GPIOH_BASE + 0x4 @ (GPIO port output type register) 
        .equ GPIOH_OT3_Shift, 3   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOH_OT1_Shift, 1   @ bitWidth 1 (Port x configuration bits y = 0..15)  
        .equ GPIOH_OT0_Shift, 0   @ bitWidth 1 (Port x configuration bits y = 0..15)  
 
    .equ GPIOH_OSPEEDR, GPIOH_BASE + 0x8 @ (GPIO port output speed register) 
        .equ GPIOH_OSPEEDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOH_OSPEEDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOH_OSPEEDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOH_PUPDR, GPIOH_BASE + 0xC @ (GPIO port pull-up/pull-down register) 
        .equ GPIOH_PUPDR3_Shift, 6   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOH_PUPDR1_Shift, 2   @ bitWidth 2 (Port x configuration bits y = 0..15)  
        .equ GPIOH_PUPDR0_Shift, 0   @ bitWidth 2 (Port x configuration bits y = 0..15)  
 
    .equ GPIOH_IDR, GPIOH_BASE + 0x10 @ (GPIO port input data register) 
        .equ GPIOH_IDR3_Shift, 3   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOH_IDR1_Shift, 1   @ bitWidth 1 (Port input data y = 0..15)  
        .equ GPIOH_IDR0_Shift, 0   @ bitWidth 1 (Port input data y = 0..15)  
 
    .equ GPIOH_ODR, GPIOH_BASE + 0x14 @ (GPIO port output data register) 
        .equ GPIOH_ODR3_Shift, 3   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOH_ODR1_Shift, 1   @ bitWidth 1 (Port output data y = 0..15)  
        .equ GPIOH_ODR0_Shift, 0   @ bitWidth 1 (Port output data y = 0..15)  
 
    .equ GPIOH_BSRR, GPIOH_BASE + 0x18 @ (GPIO port bit set/reset register) 
        .equ GPIOH_BR3_Shift, 19   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOH_BR1_Shift, 17   @ bitWidth 1 (Port x reset bit y y = 0..15)  
        .equ GPIOH_BR0_Shift, 16   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOH_BS3_Shift, 3   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOH_BS1_Shift, 1   @ bitWidth 1 (Port x set bit y y= 0..15)  
        .equ GPIOH_BS0_Shift, 0   @ bitWidth 1 (Port x set bit y y= 0..15)  
 
    .equ GPIOH_LCKR, GPIOH_BASE + 0x1C @ (GPIO port configuration lock register) 
        .equ GPIOH_LCKK_Shift, 16   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOH_LCK3_Shift, 3   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOH_LCK1_Shift, 1   @ bitWidth 1 (Port x lock bit y y= 0..15)  
        .equ GPIOH_LCK0_Shift, 0   @ bitWidth 1 (Port x lock bit y y= 0..15)  
 
    .equ GPIOH_AFRL, GPIOH_BASE + 0x20 @ (GPIO alternate function low register) 
        .equ GPIOH_AFSEL3_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOH_AFSEL1_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
        .equ GPIOH_AFSEL0_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 0..7)  
 
    .equ GPIOH_AFRH, GPIOH_BASE + 0x24 @ (GPIO alternate function high register) 
        .equ GPIOH_AFSEL15_Shift, 28   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL14_Shift, 24   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL13_Shift, 20   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL12_Shift, 16   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL11_Shift, 12   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL10_Shift, 8   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL9_Shift, 4   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
        .equ GPIOH_AFSEL8_Shift, 0   @ bitWidth 4 (Alternate function selection for port x bit y y = 8..15)  
 
    .equ GPIOH_BRR, GPIOH_BASE + 0x28 @ (port bit reset register) 
        .equ GPIOH_BR0_Shift, 0   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOH_BR1_Shift, 1   @ bitWidth 1 (Port Reset bit)  
        .equ GPIOH_BR3_Shift, 3   @ bitWidth 1 (Port Reset bit)  
 

@=========================== SAI1 ===========================@
.equ SAI1_BASE, 0x40015400 @ (Serial audio interface) 
    .equ SAI1_GCR, SAI1_BASE + 0x0 @ (Global configuration register) 
        .equ SAI1_SYNCOUT_Shift, 4   @ bitWidth 2 (Synchronization outputs)  
        .equ SAI1_SYNCIN_Shift, 0   @ bitWidth 2 (Synchronization inputs)  
 
    .equ SAI1_BCR1, SAI1_BASE + 0x24 @ (BConfiguration register 1) 
        .equ SAI1_MCKEN_Shift, 27   @ bitWidth 1 (Master clock generation enable)  
        .equ SAI1_OSR_Shift, 26   @ bitWidth 1 (Oversampling ratio for master clock)  
        .equ SAI1_MCJDIV_Shift, 20   @ bitWidth 6 (Master clock divider)  
        .equ SAI1_NODIV_Shift, 19   @ bitWidth 1 (No divider)  
        .equ SAI1_DMAEN_Shift, 17   @ bitWidth 1 (DMA enable)  
        .equ SAI1_SAIBEN_Shift, 16   @ bitWidth 1 (Audio block B enable)  
        .equ SAI1_OutDri_Shift, 13   @ bitWidth 1 (Output drive)  
        .equ SAI1_MONO_Shift, 12   @ bitWidth 1 (Mono mode)  
        .equ SAI1_SYNCEN_Shift, 10   @ bitWidth 2 (Synchronization enable)  
        .equ SAI1_CKSTR_Shift, 9   @ bitWidth 1 (Clock strobing edge)  
        .equ SAI1_LSBFIRST_Shift, 8   @ bitWidth 1 (Least significant bit first)  
        .equ SAI1_DS_Shift, 5   @ bitWidth 3 (Data size)  
        .equ SAI1_PRTCFG_Shift, 2   @ bitWidth 2 (Protocol configuration)  
        .equ SAI1_MODE_Shift, 0   @ bitWidth 2 (Audio block mode)  
 
    .equ SAI1_BCR2, SAI1_BASE + 0x28 @ (BConfiguration register 2) 
        .equ SAI1_COMP_Shift, 14   @ bitWidth 2 (Companding mode)  
        .equ SAI1_CPL_Shift, 13   @ bitWidth 1 (Complement bit)  
        .equ SAI1_MUTECN_Shift, 7   @ bitWidth 6 (Mute counter)  
        .equ SAI1_MUTEVAL_Shift, 6   @ bitWidth 1 (Mute value)  
        .equ SAI1_MUTE_Shift, 5   @ bitWidth 1 (Mute)  
        .equ SAI1_TRIS_Shift, 4   @ bitWidth 1 (Tristate management on data line)  
        .equ SAI1_FFLUS_Shift, 3   @ bitWidth 1 (FIFO flush)  
        .equ SAI1_FTH_Shift, 0   @ bitWidth 3 (FIFO threshold)  
 
    .equ SAI1_BFRCR, SAI1_BASE + 0x2C @ (BFRCR) 
        .equ SAI1_FSOFF_Shift, 18   @ bitWidth 1 (Frame synchronization offset)  
        .equ SAI1_FSPOL_Shift, 17   @ bitWidth 1 (Frame synchronization polarity)  
        .equ SAI1_FSDEF_Shift, 16   @ bitWidth 1 (Frame synchronization definition)  
        .equ SAI1_FSALL_Shift, 8   @ bitWidth 7 (Frame synchronization active level length)  
        .equ SAI1_FRL_Shift, 0   @ bitWidth 8 (Frame length)  
 
    .equ SAI1_BSLOTR, SAI1_BASE + 0x30 @ (BSlot register) 
        .equ SAI1_SLOTEN_Shift, 16   @ bitWidth 16 (Slot enable)  
        .equ SAI1_NBSLOT_Shift, 8   @ bitWidth 4 (Number of slots in an audio frame)  
        .equ SAI1_SLOTSZ_Shift, 6   @ bitWidth 2 (Slot size)  
        .equ SAI1_FBOFF_Shift, 0   @ bitWidth 5 (First bit offset)  
 
    .equ SAI1_BIM, SAI1_BASE + 0x34 @ (BInterrupt mask register2) 
        .equ SAI1_LFSDETIE_Shift, 6   @ bitWidth 1 (Late frame synchronization detection interrupt enable)  
        .equ SAI1_AFSDETIE_Shift, 5   @ bitWidth 1 (Anticipated frame synchronization detection interrupt enable)  
        .equ SAI1_CNRDYIE_Shift, 4   @ bitWidth 1 (Codec not ready interrupt enable)  
        .equ SAI1_FREQIE_Shift, 3   @ bitWidth 1 (FIFO request interrupt enable)  
        .equ SAI1_WCKCFG_Shift, 2   @ bitWidth 1 (Wrong clock configuration interrupt enable)  
        .equ SAI1_MUTEDET_Shift, 1   @ bitWidth 1 (Mute detection interrupt enable)  
        .equ SAI1_OVRUDRIE_Shift, 0   @ bitWidth 1 (Overrun/underrun interrupt enable)  
 
    .equ SAI1_BSR, SAI1_BASE + 0x38 @ (BStatus register) 
        .equ SAI1_FLVL_Shift, 16   @ bitWidth 3 (FIFO level threshold)  
        .equ SAI1_LFSDET_Shift, 6   @ bitWidth 1 (Late frame synchronization detection)  
        .equ SAI1_AFSDET_Shift, 5   @ bitWidth 1 (Anticipated frame synchronization detection)  
        .equ SAI1_CNRDY_Shift, 4   @ bitWidth 1 (Codec not ready)  
        .equ SAI1_FREQ_Shift, 3   @ bitWidth 1 (FIFO request)  
        .equ SAI1_WCKCFG_Shift, 2   @ bitWidth 1 (Wrong clock configuration flag)  
        .equ SAI1_MUTEDET_Shift, 1   @ bitWidth 1 (Mute detection)  
        .equ SAI1_OVRUDR_Shift, 0   @ bitWidth 1 (Overrun / underrun)  
 
    .equ SAI1_BCLRFR, SAI1_BASE + 0x3C @ (BClear flag register) 
        .equ SAI1_LFSDET_Shift, 6   @ bitWidth 1 (Clear late frame synchronization detection flag)  
        .equ SAI1_CAFSDET_Shift, 5   @ bitWidth 1 (Clear anticipated frame synchronization detection flag)  
        .equ SAI1_CNRDY_Shift, 4   @ bitWidth 1 (Clear codec not ready flag)  
        .equ SAI1_WCKCFG_Shift, 2   @ bitWidth 1 (Clear wrong clock configuration flag)  
        .equ SAI1_MUTEDET_Shift, 1   @ bitWidth 1 (Mute detection flag)  
        .equ SAI1_OVRUDR_Shift, 0   @ bitWidth 1 (Clear overrun / underrun)  
 
    .equ SAI1_BDR, SAI1_BASE + 0x40 @ (BData register) 
        .equ SAI1_DATA_Shift, 0   @ bitWidth 32 (Data)  
 
    .equ SAI1_ACR1, SAI1_BASE + 0x4 @ (AConfiguration register 1) 
        .equ SAI1_MCKEN_Shift, 27   @ bitWidth 1 (Master clock generation enable)  
        .equ SAI1_OSR_Shift, 26   @ bitWidth 1 (Oversampling ratio for master clock)  
        .equ SAI1_MCJDIV_Shift, 20   @ bitWidth 6 (Master clock divider)  
        .equ SAI1_NODIV_Shift, 19   @ bitWidth 1 (No divider)  
        .equ SAI1_DMAEN_Shift, 17   @ bitWidth 1 (DMA enable)  
        .equ SAI1_SAIBEN_Shift, 16   @ bitWidth 1 (Audio block B enable)  
        .equ SAI1_OutDri_Shift, 13   @ bitWidth 1 (Output drive)  
        .equ SAI1_MONO_Shift, 12   @ bitWidth 1 (Mono mode)  
        .equ SAI1_SYNCEN_Shift, 10   @ bitWidth 2 (Synchronization enable)  
        .equ SAI1_CKSTR_Shift, 9   @ bitWidth 1 (Clock strobing edge)  
        .equ SAI1_LSBFIRST_Shift, 8   @ bitWidth 1 (Least significant bit first)  
        .equ SAI1_DS_Shift, 5   @ bitWidth 3 (Data size)  
        .equ SAI1_PRTCFG_Shift, 2   @ bitWidth 2 (Protocol configuration)  
        .equ SAI1_MODE_Shift, 0   @ bitWidth 2 (Audio block mode)  
 
    .equ SAI1_ACR2, SAI1_BASE + 0x8 @ (AConfiguration register 2) 
        .equ SAI1_COMP_Shift, 14   @ bitWidth 2 (Companding mode)  
        .equ SAI1_CPL_Shift, 13   @ bitWidth 1 (Complement bit)  
        .equ SAI1_MUTECN_Shift, 7   @ bitWidth 6 (Mute counter)  
        .equ SAI1_MUTEVAL_Shift, 6   @ bitWidth 1 (Mute value)  
        .equ SAI1_MUTE_Shift, 5   @ bitWidth 1 (Mute)  
        .equ SAI1_TRIS_Shift, 4   @ bitWidth 1 (Tristate management on data line)  
        .equ SAI1_FFLUS_Shift, 3   @ bitWidth 1 (FIFO flush)  
        .equ SAI1_FTH_Shift, 0   @ bitWidth 3 (FIFO threshold)  
 
    .equ SAI1_AFRCR, SAI1_BASE + 0xC @ (AFRCR) 
        .equ SAI1_FSOFF_Shift, 18   @ bitWidth 1 (Frame synchronization offset)  
        .equ SAI1_FSPOL_Shift, 17   @ bitWidth 1 (Frame synchronization polarity)  
        .equ SAI1_FSDEF_Shift, 16   @ bitWidth 1 (Frame synchronization definition)  
        .equ SAI1_FSALL_Shift, 8   @ bitWidth 7 (Frame synchronization active level length)  
        .equ SAI1_FRL_Shift, 0   @ bitWidth 8 (Frame length)  
 
    .equ SAI1_ASLOTR, SAI1_BASE + 0x10 @ (ASlot register) 
        .equ SAI1_SLOTEN_Shift, 16   @ bitWidth 16 (Slot enable)  
        .equ SAI1_NBSLOT_Shift, 8   @ bitWidth 4 (Number of slots in an audio frame)  
        .equ SAI1_SLOTSZ_Shift, 6   @ bitWidth 2 (Slot size)  
        .equ SAI1_FBOFF_Shift, 0   @ bitWidth 5 (First bit offset)  
 
    .equ SAI1_AIM, SAI1_BASE + 0x14 @ (AInterrupt mask register2) 
        .equ SAI1_LFSDET_Shift, 6   @ bitWidth 1 (Late frame synchronization detection interrupt enable)  
        .equ SAI1_AFSDETIE_Shift, 5   @ bitWidth 1 (Anticipated frame synchronization detection interrupt enable)  
        .equ SAI1_CNRDYIE_Shift, 4   @ bitWidth 1 (Codec not ready interrupt enable)  
        .equ SAI1_FREQIE_Shift, 3   @ bitWidth 1 (FIFO request interrupt enable)  
        .equ SAI1_WCKCFG_Shift, 2   @ bitWidth 1 (Wrong clock configuration interrupt enable)  
        .equ SAI1_MUTEDET_Shift, 1   @ bitWidth 1 (Mute detection interrupt enable)  
        .equ SAI1_OVRUDRIE_Shift, 0   @ bitWidth 1 (Overrun/underrun interrupt enable)  
 
    .equ SAI1_ASR, SAI1_BASE + 0x18 @ (AStatus register) 
        .equ SAI1_FLVL_Shift, 16   @ bitWidth 3 (FIFO level threshold)  
        .equ SAI1_LFSDET_Shift, 6   @ bitWidth 1 (Late frame synchronization detection)  
        .equ SAI1_AFSDET_Shift, 5   @ bitWidth 1 (Anticipated frame synchronization detection)  
        .equ SAI1_CNRDY_Shift, 4   @ bitWidth 1 (Codec not ready)  
        .equ SAI1_FREQ_Shift, 3   @ bitWidth 1 (FIFO request)  
        .equ SAI1_WCKCFG_Shift, 2   @ bitWidth 1 (Wrong clock configuration flag. This bit is read only)  
        .equ SAI1_MUTEDET_Shift, 1   @ bitWidth 1 (Mute detection)  
        .equ SAI1_OVRUDR_Shift, 0   @ bitWidth 1 (Overrun / underrun)  
 
    .equ SAI1_ACLRFR, SAI1_BASE + 0x1C @ (AClear flag register) 
        .equ SAI1_LFSDET_Shift, 6   @ bitWidth 1 (Clear late frame synchronization detection flag)  
        .equ SAI1_CAFSDET_Shift, 5   @ bitWidth 1 (Clear anticipated frame synchronization detection flag)  
        .equ SAI1_CNRDY_Shift, 4   @ bitWidth 1 (Clear codec not ready flag)  
        .equ SAI1_WCKCFG_Shift, 2   @ bitWidth 1 (Clear wrong clock configuration flag)  
        .equ SAI1_MUTEDET_Shift, 1   @ bitWidth 1 (Mute detection flag)  
        .equ SAI1_OVRUDR_Shift, 0   @ bitWidth 1 (Clear overrun / underrun)  
 
    .equ SAI1_ADR, SAI1_BASE + 0x20 @ (AData register) 
        .equ SAI1_DATA_Shift, 0   @ bitWidth 32 (Data)  
 
    .equ SAI1_PDMCR, SAI1_BASE + 0x44 @ (PDM control register) 
        .equ SAI1_CKEN4_Shift, 11   @ bitWidth 1 (Clock enable of bitstream clock number 4)  
        .equ SAI1_CKEN3_Shift, 10   @ bitWidth 1 (Clock enable of bitstream clock number 3)  
        .equ SAI1_CKEN2_Shift, 9   @ bitWidth 1 (Clock enable of bitstream clock number 2)  
        .equ SAI1_CKEN1_Shift, 8   @ bitWidth 1 (Clock enable of bitstream clock number 1)  
        .equ SAI1_MICNBR_Shift, 4   @ bitWidth 2 (Number of microphones)  
        .equ SAI1_PDMEN_Shift, 0   @ bitWidth 1 (PDM enable)  
 
    .equ SAI1_PDMDLY, SAI1_BASE + 0x48 @ (PDM delay register) 
        .equ SAI1_DLYM4R_Shift, 28   @ bitWidth 3 (Delay line for second microphone of pair 4)  
        .equ SAI1_DLYM4L_Shift, 24   @ bitWidth 3 (Delay line for first microphone of pair 4)  
        .equ SAI1_DLYM3R_Shift, 20   @ bitWidth 3 (Delay line for second microphone of pair 3)  
        .equ SAI1_DLYM3L_Shift, 16   @ bitWidth 3 (Delay line for first microphone of pair 3)  
        .equ SAI1_DLYM2R_Shift, 12   @ bitWidth 3 (Delay line for second microphone of pair 2)  
        .equ SAI1_DLYM2L_Shift, 8   @ bitWidth 3 (Delay line for first microphone of pair 2)  
        .equ SAI1_DLYM1R_Shift, 4   @ bitWidth 3 (Delay line for second microphone of pair 1)  
        .equ SAI1_DLYM1L_Shift, 0   @ bitWidth 3 (Delay line for first microphone of pair 1)  
 

@=========================== TIM2 ===========================@
.equ TIM2_BASE, 0x40000000 @ (General-purpose-timers) 
    .equ TIM2_CR1, TIM2_BASE + 0x0 @ (control register 1) 
        .equ TIM2_UIFREMAP_Shift, 11   @ bitWidth 1 (UIF status bit remapping)  
        .equ TIM2_CKD_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIM2_ARPE_Shift, 7   @ bitWidth 1 (Auto-reload preload enable)  
        .equ TIM2_CMS_Shift, 5   @ bitWidth 2 (Center-aligned mode selection)  
        .equ TIM2_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIM2_OPM_Shift, 3   @ bitWidth 1 (One-pulse mode)  
        .equ TIM2_URS_Shift, 2   @ bitWidth 1 (Update request source)  
        .equ TIM2_UDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIM2_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
 
    .equ TIM2_CR2, TIM2_BASE + 0x4 @ (control register 2) 
        .equ TIM2_TI1S_Shift, 7   @ bitWidth 1 (TI1 selection)  
        .equ TIM2_MMS_Shift, 4   @ bitWidth 3 (Master mode selection)  
        .equ TIM2_CCDS_Shift, 3   @ bitWidth 1 (Capture/compare DMA selection)  
 
    .equ TIM2_SMCR, TIM2_BASE + 0x8 @ (slave mode control register) 
        .equ TIM2_SMS_3_Shift, 16   @ bitWidth 1 (Slave mode selection - bit 3)  
        .equ TIM2_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIM2_ECE_Shift, 14   @ bitWidth 1 (External clock enable)  
        .equ TIM2_ETPS_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIM2_ETF_Shift, 8   @ bitWidth 4 (External trigger filter)  
        .equ TIM2_MSM_Shift, 7   @ bitWidth 1 (Master/Slave mode)  
        .equ TIM2_TS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIM2_OCCS_Shift, 3   @ bitWidth 1 (OCREF clear selection)  
        .equ TIM2_SMS_Shift, 0   @ bitWidth 3 (Slave mode selection)  
 
    .equ TIM2_DIER, TIM2_BASE + 0xC @ (DMA/Interrupt enable register) 
        .equ TIM2_CC4DE_Shift, 12   @ bitWidth 1 (Capture/Compare 4 DMA request enable)  
        .equ TIM2_CC3DE_Shift, 11   @ bitWidth 1 (Capture/Compare 3 DMA request enable)  
        .equ TIM2_CC2DE_Shift, 10   @ bitWidth 1 (Capture/Compare 2 DMA request enable)  
        .equ TIM2_CC1DE_Shift, 9   @ bitWidth 1 (Capture/Compare 1 DMA request enable)  
        .equ TIM2_UDE_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIM2_TIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIM2_CC4IE_Shift, 4   @ bitWidth 1 (Capture/Compare 4 interrupt enable)  
        .equ TIM2_CC3IE_Shift, 3   @ bitWidth 1 (Capture/Compare 3 interrupt enable)  
        .equ TIM2_CC2IE_Shift, 2   @ bitWidth 1 (Capture/Compare 2 interrupt enable)  
        .equ TIM2_CC1IE_Shift, 1   @ bitWidth 1 (Capture/Compare 1 interrupt enable)  
        .equ TIM2_UIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
 
    .equ TIM2_SR, TIM2_BASE + 0x10 @ (status register) 
        .equ TIM2_CC4OF_Shift, 12   @ bitWidth 1 (Capture/Compare 4 overcapture flag)  
        .equ TIM2_CC3OF_Shift, 11   @ bitWidth 1 (Capture/Compare 3 overcapture flag)  
        .equ TIM2_CC2OF_Shift, 10   @ bitWidth 1 (Capture/compare 2 overcapture flag)  
        .equ TIM2_CC1OF_Shift, 9   @ bitWidth 1 (Capture/Compare 1 overcapture flag)  
        .equ TIM2_TIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIM2_CC4IF_Shift, 4   @ bitWidth 1 (Capture/Compare 4 interrupt flag)  
        .equ TIM2_CC3IF_Shift, 3   @ bitWidth 1 (Capture/Compare 3 interrupt flag)  
        .equ TIM2_CC2IF_Shift, 2   @ bitWidth 1 (Capture/Compare 2 interrupt flag)  
        .equ TIM2_CC1IF_Shift, 1   @ bitWidth 1 (Capture/compare 1 interrupt flag)  
        .equ TIM2_UIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIM2_EGR, TIM2_BASE + 0x14 @ (event generation register) 
        .equ TIM2_TG_Shift, 6   @ bitWidth 1 (Trigger generation)  
        .equ TIM2_CC4G_Shift, 4   @ bitWidth 1 (Capture/compare 4 generation)  
        .equ TIM2_CC3G_Shift, 3   @ bitWidth 1 (Capture/compare 3 generation)  
        .equ TIM2_CC2G_Shift, 2   @ bitWidth 1 (Capture/compare 2 generation)  
        .equ TIM2_CC1G_Shift, 1   @ bitWidth 1 (Capture/compare 1 generation)  
        .equ TIM2_UG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIM2_CCMR1_Output, TIM2_BASE + 0x18 @ (capture/compare mode register 1 output mode) 
        .equ TIM2_OC2M_3_Shift, 24   @ bitWidth 1 (Output Compare 2 mode - bit 3)  
        .equ TIM2_OC1M_3_Shift, 16   @ bitWidth 1 (Output Compare 1 mode - bit 3)  
        .equ TIM2_OC2CE_Shift, 15   @ bitWidth 1 (Output compare 2 clear enable)  
        .equ TIM2_OC2M_Shift, 12   @ bitWidth 3 (Output compare 2 mode)  
        .equ TIM2_OC2PE_Shift, 11   @ bitWidth 1 (Output compare 2 preload enable)  
        .equ TIM2_OC2FE_Shift, 10   @ bitWidth 1 (Output compare 2 fast enable)  
        .equ TIM2_CC2S_Shift, 8   @ bitWidth 2 (Capture/Compare 2 selection)  
        .equ TIM2_OC1CE_Shift, 7   @ bitWidth 1 (Output compare 1 clear enable)  
        .equ TIM2_OC1M_Shift, 4   @ bitWidth 3 (Output compare 1 mode)  
        .equ TIM2_OC1PE_Shift, 3   @ bitWidth 1 (Output compare 1 preload enable)  
        .equ TIM2_OC1FE_Shift, 2   @ bitWidth 1 (Output compare 1 fast enable)  
        .equ TIM2_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
 
    .equ TIM2_CCMR1_Input, TIM2_BASE + 0x18 @ (capture/compare mode register 1 input mode) 
        .equ TIM2_IC2F_Shift, 12   @ bitWidth 4 (Input capture 2 filter)  
        .equ TIM2_IC2PSC_Shift, 10   @ bitWidth 2 (Input capture 2 prescaler)  
        .equ TIM2_CC2S_Shift, 8   @ bitWidth 2 (Capture/compare 2 selection)  
        .equ TIM2_IC1F_Shift, 4   @ bitWidth 4 (Input capture 1 filter)  
        .equ TIM2_IC1PSC_Shift, 2   @ bitWidth 2 (Input capture 1 prescaler)  
        .equ TIM2_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
 
    .equ TIM2_CCMR2_Output, TIM2_BASE + 0x1C @ (capture/compare mode register 2 output mode) 
        .equ TIM2_OC4M_3_Shift, 24   @ bitWidth 1 (Output Compare 4 mode - bit 3)  
        .equ TIM2_OC3M_3_Shift, 16   @ bitWidth 1 (Output Compare 3 mode - bit 3)  
        .equ TIM2_OC4CE_Shift, 15   @ bitWidth 1 (Output compare 4 clear enable)  
        .equ TIM2_OC4M_Shift, 12   @ bitWidth 3 (Output compare 4 mode)  
        .equ TIM2_OC4PE_Shift, 11   @ bitWidth 1 (Output compare 4 preload enable)  
        .equ TIM2_OC4FE_Shift, 10   @ bitWidth 1 (Output compare 4 fast enable)  
        .equ TIM2_CC4S_Shift, 8   @ bitWidth 2 (Capture/Compare 4 selection)  
        .equ TIM2_OC3CE_Shift, 7   @ bitWidth 1 (Output compare 3 clear enable)  
        .equ TIM2_OC3M_Shift, 4   @ bitWidth 3 (Output compare 3 mode)  
        .equ TIM2_OC3PE_Shift, 3   @ bitWidth 1 (Output compare 3 preload enable)  
        .equ TIM2_OC3FE_Shift, 2   @ bitWidth 1 (Output compare 3 fast enable)  
        .equ TIM2_CC3S_Shift, 0   @ bitWidth 2 (Capture/Compare 3 selection)  
 
    .equ TIM2_CCMR2_Input, TIM2_BASE + 0x1C @ (capture/compare mode register 2 input mode) 
        .equ TIM2_IC4F_Shift, 12   @ bitWidth 4 (Input capture 4 filter)  
        .equ TIM2_IC4PSC_Shift, 10   @ bitWidth 2 (Input capture 4 prescaler)  
        .equ TIM2_CC4S_Shift, 8   @ bitWidth 2 (Capture/Compare 4 selection)  
        .equ TIM2_IC3F_Shift, 4   @ bitWidth 4 (Input capture 3 filter)  
        .equ TIM2_IC3PSC_Shift, 2   @ bitWidth 2 (Input capture 3 prescaler)  
        .equ TIM2_CC3S_Shift, 0   @ bitWidth 2 (Capture/Compare 3 selection)  
 
    .equ TIM2_CCER, TIM2_BASE + 0x20 @ (capture/compare enable register) 
        .equ TIM2_CC4NP_Shift, 15   @ bitWidth 1 (Capture/Compare 4 output Polarity)  
        .equ TIM2_CC4P_Shift, 13   @ bitWidth 1 (Capture/Compare 3 output Polarity)  
        .equ TIM2_CC4E_Shift, 12   @ bitWidth 1 (Capture/Compare 4 output enable)  
        .equ TIM2_CC3NP_Shift, 11   @ bitWidth 1 (Capture/Compare 3 output Polarity)  
        .equ TIM2_CC3P_Shift, 9   @ bitWidth 1 (Capture/Compare 3 output Polarity)  
        .equ TIM2_CC3E_Shift, 8   @ bitWidth 1 (Capture/Compare 3 output enable)  
        .equ TIM2_CC2NP_Shift, 7   @ bitWidth 1 (Capture/Compare 2 output Polarity)  
        .equ TIM2_CC2P_Shift, 5   @ bitWidth 1 (Capture/Compare 2 output Polarity)  
        .equ TIM2_CC2E_Shift, 4   @ bitWidth 1 (Capture/Compare 2 output enable)  
        .equ TIM2_CC1NP_Shift, 3   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM2_CC1P_Shift, 1   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM2_CC1E_Shift, 0   @ bitWidth 1 (Capture/Compare 1 output enable)  
 
    .equ TIM2_CNT, TIM2_BASE + 0x24 @ (counter) 
        .equ TIM2_CNT_H_Shift, 16   @ bitWidth 15 (High counter value TIM2 only)  
        .equ TIM2_CNT_L_Shift, 0   @ bitWidth 16 (Low counter value)  
        .equ TIM2_UIFCPY_Shift, 31   @ bitWidth 1 (Value depends on IUFREMAP in TIM2_CR1.)  
 
    .equ TIM2_PSC, TIM2_BASE + 0x28 @ (prescaler) 
        .equ TIM2_PSC_Shift, 0   @ bitWidth 16 (Prescaler value)  
 
    .equ TIM2_ARR, TIM2_BASE + 0x2C @ (auto-reload register) 
        .equ TIM2_ARR_H_Shift, 16   @ bitWidth 16 (High Auto-reload value TIM2 only)  
        .equ TIM2_ARR_L_Shift, 0   @ bitWidth 16 (Low Auto-reload value)  
 
    .equ TIM2_CCR1, TIM2_BASE + 0x34 @ (capture/compare register 1) 
        .equ TIM2_CCR1_H_Shift, 16   @ bitWidth 16 (High Capture/Compare 1 value TIM2 only)  
        .equ TIM2_CCR1_L_Shift, 0   @ bitWidth 16 (Low Capture/Compare 1 value)  
 
    .equ TIM2_CCR2, TIM2_BASE + 0x38 @ (capture/compare register 2) 
        .equ TIM2_CCR2_H_Shift, 16   @ bitWidth 16 (High Capture/Compare 2 value TIM2 only)  
        .equ TIM2_CCR2_L_Shift, 0   @ bitWidth 16 (Low Capture/Compare 2 value)  
 
    .equ TIM2_CCR3, TIM2_BASE + 0x3C @ (capture/compare register 3) 
        .equ TIM2_CCR3_H_Shift, 16   @ bitWidth 16 (High Capture/Compare value TIM2 only)  
        .equ TIM2_CCR3_L_Shift, 0   @ bitWidth 16 (Low Capture/Compare value)  
 
    .equ TIM2_CCR4, TIM2_BASE + 0x40 @ (capture/compare register 4) 
        .equ TIM2_CCR4_H_Shift, 16   @ bitWidth 16 (High Capture/Compare value TIM2 only)  
        .equ TIM2_CCR4_L_Shift, 0   @ bitWidth 16 (Low Capture/Compare value)  
 
    .equ TIM2_DCR, TIM2_BASE + 0x48 @ (DMA control register) 
        .equ TIM2_DBL_Shift, 8   @ bitWidth 5 (DMA burst length)  
        .equ TIM2_DBA_Shift, 0   @ bitWidth 5 (DMA base address)  
 
    .equ TIM2_DMAR, TIM2_BASE + 0x4C @ (DMA address for full transfer) 
        .equ TIM2_DMAB_Shift, 0   @ bitWidth 16 (DMA register for burst accesses)  
 
    .equ TIM2_OR, TIM2_BASE + 0x50 @ (TIM2 option register) 
        .equ TIM2_TI4_RMP_Shift, 2   @ bitWidth 2 (Input capture 4 remap)  
        .equ TIM2_ETR_RMP_Shift, 1   @ bitWidth 1 (External trigger remap)  
        .equ TIM2_ITR_RMP_Shift, 0   @ bitWidth 1 (Internal trigger remap)  
 
    .equ TIM2_AF, TIM2_BASE + 0x60 @ (TIM2 alternate function option register 1) 
        .equ TIM2_ETRSEL_Shift, 14   @ bitWidth 3 (External trigger source selection)  
 

@=========================== TIM16 ===========================@
.equ TIM16_BASE, 0x40014400 @ (General purpose timers) 
    .equ TIM16_CR1, TIM16_BASE + 0x0 @ (control register 1) 
        .equ TIM16_BKINE_Shift, 0   @ bitWidth 1 (BRK BKIN input enable)  
        .equ TIM16_BKCMP1E_Shift, 1   @ bitWidth 1 (BRK COMP1 enable)  
        .equ TIM16_BKCMP2E_Shift, 2   @ bitWidth 1 (BRK COMP2 enable)  
        .equ TIM16_BKINP_Shift, 9   @ bitWidth 1 (BRK BKIN input polarity)  
        .equ TIM16_BKCMP1P_Shift, 10   @ bitWidth 1 (BRK COMP1 input polarity)  
        .equ TIM16_BKCMP2P_Shift, 11   @ bitWidth 1 (BRK COMP2 input polarit)  
 
    .equ TIM16_CR2, TIM16_BASE + 0x4 @ (control register 2) 
        .equ TIM16_OIS1N_Shift, 9   @ bitWidth 1 (Output Idle state 1)  
        .equ TIM16_OIS1_Shift, 8   @ bitWidth 1 (Output Idle state 1)  
        .equ TIM16_CCDS_Shift, 3   @ bitWidth 1 (Capture/compare DMA selection)  
        .equ TIM16_CCUS_Shift, 2   @ bitWidth 1 (Capture/compare control update selection)  
        .equ TIM16_CCPC_Shift, 0   @ bitWidth 1 (Capture/compare preloaded control)  
 
    .equ TIM16_DIER, TIM16_BASE + 0xC @ (DMA/Interrupt enable register) 
        .equ TIM16_BKINE_Shift, 0   @ bitWidth 1 (BRK BKIN input enable)  
        .equ TIM16_BKCMP1E_Shift, 1   @ bitWidth 1 (BRK COMP1 enable)  
        .equ TIM16_BKCMP2E_Shift, 2   @ bitWidth 1 (BRK COMP2 enable)  
        .equ TIM16_BKINP_Shift, 9   @ bitWidth 1 (BRK BKIN input polarity)  
        .equ TIM16_BKCMP1P_Shift, 10   @ bitWidth 1 (BRK COMP1 input polarity)  
        .equ TIM16_BKCMP2P_Shift, 11   @ bitWidth 1 (BRK COMP2 input polarit)  
 
    .equ TIM16_SR, TIM16_BASE + 0x10 @ (status register) 
        .equ TIM16_CC1OF_Shift, 9   @ bitWidth 1 (Capture/Compare 1 overcapture flag)  
        .equ TIM16_BIF_Shift, 7   @ bitWidth 1 (Break interrupt flag)  
        .equ TIM16_TIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIM16_COMIF_Shift, 5   @ bitWidth 1 (COM interrupt flag)  
        .equ TIM16_CC1IF_Shift, 1   @ bitWidth 1 (Capture/compare 1 interrupt flag)  
        .equ TIM16_UIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIM16_EGR, TIM16_BASE + 0x14 @ (event generation register) 
        .equ TIM16_BG_Shift, 7   @ bitWidth 1 (Break generation)  
        .equ TIM16_TG_Shift, 6   @ bitWidth 1 (Trigger generation)  
        .equ TIM16_COMG_Shift, 5   @ bitWidth 1 (Capture/Compare control update generation)  
        .equ TIM16_CC1G_Shift, 1   @ bitWidth 1 (Capture/compare 1 generation)  
        .equ TIM16_UG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIM16_CCMR1_Output, TIM16_BASE + 0x18 @ (capture/compare mode register output mode) 
        .equ TIM16_OC1M_2_Shift, 16   @ bitWidth 1 (Output Compare 1 mode)  
        .equ TIM16_OC1M_Shift, 4   @ bitWidth 3 (Output Compare 1 mode)  
        .equ TIM16_OC1PE_Shift, 3   @ bitWidth 1 (Output Compare 1 preload enable)  
        .equ TIM16_OC1FE_Shift, 2   @ bitWidth 1 (Output Compare 1 fast enable)  
        .equ TIM16_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
 
    .equ TIM16_CCMR1_Input, TIM16_BASE + 0x18 @ (capture/compare mode register 1 input mode) 
        .equ TIM16_IC1F_Shift, 4   @ bitWidth 4 (Input capture 1 filter)  
        .equ TIM16_IC1PSC_Shift, 2   @ bitWidth 2 (Input capture 1 prescaler)  
        .equ TIM16_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
 
    .equ TIM16_CCER, TIM16_BASE + 0x20 @ (capture/compare enable register) 
        .equ TIM16_CC1NP_Shift, 3   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM16_CC1NE_Shift, 2   @ bitWidth 1 (Capture/Compare 1 complementary output enable)  
        .equ TIM16_CC1P_Shift, 1   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM16_CC1E_Shift, 0   @ bitWidth 1 (Capture/Compare 1 output enable)  
 
    .equ TIM16_CNT, TIM16_BASE + 0x24 @ (counter) 
        .equ TIM16_CNT_Shift, 0   @ bitWidth 16 (counter value)  
        .equ TIM16_UIFCPY_Shift, 31   @ bitWidth 1 (UIF Copy)  
 
    .equ TIM16_PSC, TIM16_BASE + 0x28 @ (prescaler) 
        .equ TIM16_PSC_Shift, 0   @ bitWidth 16 (Prescaler value)  
 
    .equ TIM16_ARR, TIM16_BASE + 0x2C @ (auto-reload register) 
        .equ TIM16_ARR_Shift, 0   @ bitWidth 16 (Auto-reload value)  
 
    .equ TIM16_RCR, TIM16_BASE + 0x30 @ (repetition counter register) 
        .equ TIM16_REP_Shift, 0   @ bitWidth 8 (Repetition counter value)  
 
    .equ TIM16_CCR1, TIM16_BASE + 0x34 @ (capture/compare register 1) 
        .equ TIM16_CCR1_Shift, 0   @ bitWidth 16 (Capture/Compare 1 value)  
 
    .equ TIM16_BDTR, TIM16_BASE + 0x44 @ (break and dead-time register) 
        .equ TIM16_DTG_Shift, 0   @ bitWidth 8 (Dead-time generator setup)  
        .equ TIM16_LOCK_Shift, 8   @ bitWidth 2 (Lock configuration)  
        .equ TIM16_OSSI_Shift, 10   @ bitWidth 1 (Off-state selection for Idle mode)  
        .equ TIM16_OSSR_Shift, 11   @ bitWidth 1 (Off-state selection for Run mode)  
        .equ TIM16_BKE_Shift, 12   @ bitWidth 1 (Break enable)  
        .equ TIM16_BKP_Shift, 13   @ bitWidth 1 (Break polarity)  
        .equ TIM16_AOE_Shift, 14   @ bitWidth 1 (Automatic output enable)  
        .equ TIM16_MOE_Shift, 15   @ bitWidth 1 (Main output enable)  
        .equ TIM16_BKF_Shift, 16   @ bitWidth 4 (Break filter)  
 
    .equ TIM16_DCR, TIM16_BASE + 0x48 @ (DMA control register) 
        .equ TIM16_DBL_Shift, 8   @ bitWidth 5 (DMA burst length)  
        .equ TIM16_DBA_Shift, 0   @ bitWidth 5 (DMA base address)  
 
    .equ TIM16_DMAR, TIM16_BASE + 0x4C @ (DMA address for full transfer) 
        .equ TIM16_DMAB_Shift, 0   @ bitWidth 16 (DMA register for burst accesses)  
 
    .equ TIM16_OR, TIM16_BASE + 0x50 @ (TIM16 option register 1) 
        .equ TIM16_TI1_RMP_Shift, 0   @ bitWidth 2 (Input capture 1 remap)  
 
    .equ TIM16_AF1, TIM16_BASE + 0x60 @ (TIM17 option register 1) 
        .equ TIM16_BKINE_Shift, 0   @ bitWidth 1 (BRK BKIN input enable)  
        .equ TIM16_BKCMP1E_Shift, 1   @ bitWidth 1 (BRK COMP1 enable)  
        .equ TIM16_BKCMP2E_Shift, 2   @ bitWidth 1 (BRK COMP2 enable)  
        .equ TIM16_BKINP_Shift, 9   @ bitWidth 1 (BRK BKIN input polarity)  
        .equ TIM16_BKCMP1P_Shift, 10   @ bitWidth 1 (BRK COMP1 input polarity)  
        .equ TIM16_BKCMP2P_Shift, 11   @ bitWidth 1 (BRK COMP2 input polarit)  
 

@=========================== TIM17 ===========================@
.equ TIM17_BASE, 0x40014800 @ (General purpose timers) 
    .equ TIM17_CR1, TIM17_BASE + 0x0 @ (control register 1) 
        .equ TIM17_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
        .equ TIM17_UDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIM17_URS_Shift, 2   @ bitWidth 1 (Update request source)  
        .equ TIM17_OPM_Shift, 3   @ bitWidth 1 (One-pulse mode)  
        .equ TIM17_ARPE_Shift, 7   @ bitWidth 1 (Auto-reload preload enable)  
        .equ TIM17_CKD_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIM17_UIFREMAP_Shift, 11   @ bitWidth 1 (UIF status bit remapping)  
 
    .equ TIM17_CR2, TIM17_BASE + 0x4 @ (control register 2) 
        .equ TIM17_OIS1N_Shift, 9   @ bitWidth 1 (Output Idle state 1)  
        .equ TIM17_OIS1_Shift, 8   @ bitWidth 1 (Output Idle state 1)  
        .equ TIM17_CCDS_Shift, 3   @ bitWidth 1 (Capture/compare DMA selection)  
        .equ TIM17_CCUS_Shift, 2   @ bitWidth 1 (Capture/compare control update selection)  
        .equ TIM17_CCPC_Shift, 0   @ bitWidth 1 (Capture/compare preloaded control)  
 
    .equ TIM17_DIER, TIM17_BASE + 0x8 @ (DMA/Interrupt enable register) 
        .equ TIM17_BKINE_Shift, 0   @ bitWidth 1 (BRK BKIN input enable)  
        .equ TIM17_BKCMP1E_Shift, 1   @ bitWidth 1 (BRK COMP1 enable)  
        .equ TIM17_BKCMP2E_Shift, 2   @ bitWidth 1 (BRK COMP2 enable)  
        .equ TIM17_BKINP_Shift, 9   @ bitWidth 1 (BRK BKIN input polarity)  
        .equ TIM17_BKCMP1P_Shift, 10   @ bitWidth 1 (BRK COMP1 input polarity)  
        .equ TIM17_BKCMP2P_Shift, 11   @ bitWidth 1 (BRK COMP2 input polarit)  
 
    .equ TIM17_SR, TIM17_BASE + 0xC @ (status register) 
        .equ TIM17_CC1OF_Shift, 9   @ bitWidth 1 (Capture/Compare 1 overcapture flag)  
        .equ TIM17_BIF_Shift, 7   @ bitWidth 1 (Break interrupt flag)  
        .equ TIM17_TIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIM17_COMIF_Shift, 5   @ bitWidth 1 (COM interrupt flag)  
        .equ TIM17_CC1IF_Shift, 1   @ bitWidth 1 (Capture/compare 1 interrupt flag)  
        .equ TIM17_UIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
 
    .equ TIM17_EGR, TIM17_BASE + 0x10 @ (event generation register) 
        .equ TIM17_BG_Shift, 7   @ bitWidth 1 (Break generation)  
        .equ TIM17_TG_Shift, 6   @ bitWidth 1 (Trigger generation)  
        .equ TIM17_COMG_Shift, 5   @ bitWidth 1 (Capture/Compare control update generation)  
        .equ TIM17_CC1G_Shift, 1   @ bitWidth 1 (Capture/compare 1 generation)  
        .equ TIM17_UG_Shift, 0   @ bitWidth 1 (Update generation)  
 
    .equ TIM17_CCMR1_Output, TIM17_BASE + 0x14 @ (capture/compare mode register output mode) 
        .equ TIM17_OC1M_2_Shift, 16   @ bitWidth 1 (Output Compare 1 mode)  
        .equ TIM17_OC1M_Shift, 4   @ bitWidth 3 (Output Compare 1 mode)  
        .equ TIM17_OC1PE_Shift, 3   @ bitWidth 1 (Output Compare 1 preload enable)  
        .equ TIM17_OC1FE_Shift, 2   @ bitWidth 1 (Output Compare 1 fast enable)  
        .equ TIM17_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
 
    .equ TIM17_CCMR1_Input, TIM17_BASE + 0x18 @ (capture/compare mode register 1 input mode) 
        .equ TIM17_IC1F_Shift, 4   @ bitWidth 4 (Input capture 1 filter)  
        .equ TIM17_IC1PSC_Shift, 2   @ bitWidth 2 (Input capture 1 prescaler)  
        .equ TIM17_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
 
    .equ TIM17_CCER, TIM17_BASE + 0x1C @ (capture/compare enable register) 
        .equ TIM17_CC1NP_Shift, 3   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM17_CC1NE_Shift, 2   @ bitWidth 1 (Capture/Compare 1 complementary output enable)  
        .equ TIM17_CC1P_Shift, 1   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM17_CC1E_Shift, 0   @ bitWidth 1 (Capture/Compare 1 output enable)  
 
    .equ TIM17_CNT, TIM17_BASE + 0x20 @ (counter) 
        .equ TIM17_CNT_Shift, 0   @ bitWidth 16 (counter value)  
        .equ TIM17_UIFCPY_Shift, 31   @ bitWidth 1 (UIF Copy)  
 
    .equ TIM17_PSC, TIM17_BASE + 0x24 @ (prescaler) 
        .equ TIM17_PSC_Shift, 0   @ bitWidth 16 (Prescaler value)  
 
    .equ TIM17_ARR, TIM17_BASE + 0x28 @ (auto-reload register) 
        .equ TIM17_ARR_Shift, 0   @ bitWidth 16 (Auto-reload value)  
 
    .equ TIM17_RCR, TIM17_BASE + 0x2C @ (repetition counter register) 
        .equ TIM17_REP_Shift, 0   @ bitWidth 8 (Repetition counter value)  
 
    .equ TIM17_CCR1, TIM17_BASE + 0x30 @ (capture/compare register 1) 
        .equ TIM17_CCR1_Shift, 0   @ bitWidth 16 (Capture/Compare 1 value)  
 
    .equ TIM17_BDTR, TIM17_BASE + 0x34 @ (break and dead-time register) 
        .equ TIM17_DTG_Shift, 0   @ bitWidth 8 (Dead-time generator setup)  
        .equ TIM17_LOCK_Shift, 8   @ bitWidth 2 (Lock configuration)  
        .equ TIM17_OSSI_Shift, 10   @ bitWidth 1 (Off-state selection for Idle mode)  
        .equ TIM17_OSSR_Shift, 11   @ bitWidth 1 (Off-state selection for Run mode)  
        .equ TIM17_BKE_Shift, 12   @ bitWidth 1 (Break enable)  
        .equ TIM17_BKP_Shift, 13   @ bitWidth 1 (Break polarity)  
        .equ TIM17_AOE_Shift, 14   @ bitWidth 1 (Automatic output enable)  
        .equ TIM17_MOE_Shift, 15   @ bitWidth 1 (Main output enable)  
        .equ TIM17_BKF_Shift, 16   @ bitWidth 4 (Break filter)  
 
    .equ TIM17_DCR, TIM17_BASE + 0x38 @ (DMA control register) 
        .equ TIM17_DBL_Shift, 8   @ bitWidth 5 (DMA burst length)  
        .equ TIM17_DBA_Shift, 0   @ bitWidth 5 (DMA base address)  
 
    .equ TIM17_DMAR, TIM17_BASE + 0x3C @ (DMA address for full transfer) 
        .equ TIM17_DMAB_Shift, 0   @ bitWidth 16 (DMA register for burst accesses)  
 
    .equ TIM17_OR, TIM17_BASE + 0x40 @ (TIM16 option register 1) 
        .equ TIM17_TI1_RMP_Shift, 0   @ bitWidth 2 (Input capture 1 remap)  
 
    .equ TIM17_AF1, TIM17_BASE + 0x44 @ (TIM17 option register 1) 
        .equ TIM17_BKINE_Shift, 0   @ bitWidth 1 (BRK BKIN input enable)  
        .equ TIM17_BKCMP1E_Shift, 1   @ bitWidth 1 (BRK COMP1 enable)  
        .equ TIM17_BKCMP2E_Shift, 2   @ bitWidth 1 (BRK COMP2 enable)  
        .equ TIM17_BKINP_Shift, 9   @ bitWidth 1 (BRK BKIN input polarity)  
        .equ TIM17_BKCMP1P_Shift, 10   @ bitWidth 1 (BRK COMP1 input polarity)  
        .equ TIM17_BKCMP2P_Shift, 11   @ bitWidth 1 (BRK COMP2 input polarit)  
 

@=========================== TIM1 ===========================@
.equ TIM1_BASE, 0x40012C00 @ (Advanced-timers) 
    .equ TIM1_CR1, TIM1_BASE + 0x0 @ (control register 1) 
        .equ TIM1_CEN_Shift, 0   @ bitWidth 1 (Counter enable)  
        .equ TIM1_OPM_Shift, 3   @ bitWidth 1 (One-pulse mode)  
        .equ TIM1_UDIS_Shift, 1   @ bitWidth 1 (Update disable)  
        .equ TIM1_URS_Shift, 2   @ bitWidth 1 (Update request source)  
        .equ TIM1_DIR_Shift, 4   @ bitWidth 1 (Direction)  
        .equ TIM1_CMS_Shift, 5   @ bitWidth 2 (Center-aligned mode selection)  
        .equ TIM1_ARPE_Shift, 7   @ bitWidth 1 (Auto-reload preload enable)  
        .equ TIM1_CKD_Shift, 8   @ bitWidth 2 (Clock division)  
        .equ TIM1_UIFREMAP_Shift, 11   @ bitWidth 1 (UIF status bit remapping)  
 
    .equ TIM1_CR2, TIM1_BASE + 0x4 @ (control register 2) 
        .equ TIM1_MMS2_Shift, 20   @ bitWidth 4 (Master mode selection 2)  
        .equ TIM1_OIS6_Shift, 18   @ bitWidth 1 (Output Idle state 6 OC6 output)  
        .equ TIM1_OIS5_Shift, 16   @ bitWidth 1 (Output Idle state 5 OC5 output)  
        .equ TIM1_OIS4_Shift, 14   @ bitWidth 1 (Output Idle state 4)  
        .equ TIM1_OIS3N_Shift, 13   @ bitWidth 1 (Output Idle state 3)  
        .equ TIM1_OIS3_Shift, 12   @ bitWidth 1 (Output Idle state 3)  
        .equ TIM1_OIS2N_Shift, 11   @ bitWidth 1 (Output Idle state 2)  
        .equ TIM1_OIS2_Shift, 10   @ bitWidth 1 (Output Idle state 2)  
        .equ TIM1_OIS1N_Shift, 9   @ bitWidth 1 (Output Idle state 1)  
        .equ TIM1_OIS1_Shift, 8   @ bitWidth 1 (Output Idle state 1)  
        .equ TIM1_TI1S_Shift, 7   @ bitWidth 1 (TI1 selection)  
        .equ TIM1_MMS_Shift, 4   @ bitWidth 3 (Master mode selection)  
        .equ TIM1_CCDS_Shift, 3   @ bitWidth 1 (Capture/compare DMA selection)  
        .equ TIM1_CCUS_Shift, 2   @ bitWidth 1 (Capture/compare control update selection)  
        .equ TIM1_CCPC_Shift, 0   @ bitWidth 1 (Capture/compare preloaded control)  
 
    .equ TIM1_SMCR, TIM1_BASE + 0x8 @ (slave mode control register) 
        .equ TIM1_SMS_Shift, 0   @ bitWidth 3 (Slave mode selection)  
        .equ TIM1_OCCS_Shift, 3   @ bitWidth 1 (OCREF clear selection)  
        .equ TIM1_TS_Shift, 4   @ bitWidth 3 (Trigger selection)  
        .equ TIM1_MSM_Shift, 7   @ bitWidth 1 (Master/Slave mode)  
        .equ TIM1_ETF_Shift, 8   @ bitWidth 4 (External trigger filter)  
        .equ TIM1_ETPS_Shift, 12   @ bitWidth 2 (External trigger prescaler)  
        .equ TIM1_ECE_Shift, 14   @ bitWidth 1 (External clock enable)  
        .equ TIM1_ETP_Shift, 15   @ bitWidth 1 (External trigger polarity)  
        .equ TIM1_SMS_3_Shift, 16   @ bitWidth 1 (Slave mode selection - bit 3)  
 
    .equ TIM1_DIER, TIM1_BASE + 0xC @ (DMA/Interrupt enable register) 
        .equ TIM1_UIE_Shift, 0   @ bitWidth 1 (Update interrupt enable)  
        .equ TIM1_CC1IE_Shift, 1   @ bitWidth 1 (Capture/Compare 1 interrupt enable)  
        .equ TIM1_CC2IE_Shift, 2   @ bitWidth 1 (Capture/Compare 2 interrupt enable)  
        .equ TIM1_CC3IE_Shift, 3   @ bitWidth 1 (Capture/Compare 3 interrupt enable)  
        .equ TIM1_CC4IE_Shift, 4   @ bitWidth 1 (Capture/Compare 4 interrupt enable)  
        .equ TIM1_COMIE_Shift, 5   @ bitWidth 1 (COM interrupt enable)  
        .equ TIM1_TIE_Shift, 6   @ bitWidth 1 (Trigger interrupt enable)  
        .equ TIM1_BIE_Shift, 7   @ bitWidth 1 (Break interrupt enable)  
        .equ TIM1_UDE_Shift, 8   @ bitWidth 1 (Update DMA request enable)  
        .equ TIM1_CC1DE_Shift, 9   @ bitWidth 1 (Capture/Compare 1 DMA request enable)  
        .equ TIM1_CC2DE_Shift, 10   @ bitWidth 1 (Capture/Compare 2 DMA request enable)  
        .equ TIM1_CC3DE_Shift, 11   @ bitWidth 1 (Capture/Compare 3 DMA request enable)  
        .equ TIM1_CC4DE_Shift, 12   @ bitWidth 1 (Capture/Compare 4 DMA request enable)  
        .equ TIM1_COMDE_Shift, 13   @ bitWidth 1 (COM DMA request enable)  
        .equ TIM1_TDE_Shift, 14   @ bitWidth 1 (Trigger DMA request enable)  
 
    .equ TIM1_SR, TIM1_BASE + 0x10 @ (status register) 
        .equ TIM1_UIF_Shift, 0   @ bitWidth 1 (Update interrupt flag)  
        .equ TIM1_CC1IF_Shift, 1   @ bitWidth 1 (Capture/compare 1 interrupt flag)  
        .equ TIM1_CC2IF_Shift, 2   @ bitWidth 1 (Capture/Compare 2 interrupt flag)  
        .equ TIM1_CC3IF_Shift, 3   @ bitWidth 1 (Capture/Compare 3 interrupt flag)  
        .equ TIM1_CC4IF_Shift, 4   @ bitWidth 1 (Capture/Compare 4 interrupt flag)  
        .equ TIM1_COMIF_Shift, 5   @ bitWidth 1 (COM interrupt flag)  
        .equ TIM1_TIF_Shift, 6   @ bitWidth 1 (Trigger interrupt flag)  
        .equ TIM1_BIF_Shift, 7   @ bitWidth 1 (Break interrupt flag)  
        .equ TIM1_B2IF_Shift, 8   @ bitWidth 1 (Break 2 interrupt flag)  
        .equ TIM1_CC1OF_Shift, 9   @ bitWidth 1 (Capture/Compare 1 overcapture flag)  
        .equ TIM1_CC2OF_Shift, 10   @ bitWidth 1 (Capture/compare 2 overcapture flag)  
        .equ TIM1_CC3OF_Shift, 11   @ bitWidth 1 (Capture/Compare 3 overcapture flag)  
        .equ TIM1_CC4OF_Shift, 12   @ bitWidth 1 (Capture/Compare 4 overcapture flag)  
        .equ TIM1_SBIF_Shift, 13   @ bitWidth 1 (System Break interrupt flag)  
        .equ TIM1_CC5IF_Shift, 16   @ bitWidth 1 (Compare 5 interrupt flag)  
        .equ TIM1_CC6IF_Shift, 17   @ bitWidth 1 (Compare 6 interrupt flag)  
 
    .equ TIM1_EGR, TIM1_BASE + 0x14 @ (event generation register) 
        .equ TIM1_UG_Shift, 0   @ bitWidth 1 (Update generation)  
        .equ TIM1_CC1G_Shift, 1   @ bitWidth 1 (Capture/compare 1 generation)  
        .equ TIM1_CC2G_Shift, 2   @ bitWidth 1 (Capture/compare 2 generation)  
        .equ TIM1_CC3G_Shift, 3   @ bitWidth 1 (Capture/compare 3 generation)  
        .equ TIM1_CC4G_Shift, 4   @ bitWidth 1 (Capture/compare 4 generation)  
        .equ TIM1_COMG_Shift, 5   @ bitWidth 1 (Capture/Compare control update generation)  
        .equ TIM1_TG_Shift, 6   @ bitWidth 1 (Trigger generation)  
        .equ TIM1_BG_Shift, 7   @ bitWidth 1 (Break generation)  
        .equ TIM1_B2G_Shift, 8   @ bitWidth 1 (Break 2 generation)  
 
    .equ TIM1_CCMR1_Input, TIM1_BASE + 0x18 @ (capture/compare mode register 1 output mode) 
        .equ TIM1_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
        .equ TIM1_IC1PSC_Shift, 2   @ bitWidth 2 (Input capture 1 prescaler)  
        .equ TIM1_C1F_Shift, 4   @ bitWidth 4 (Input capture 1 filter)  
        .equ TIM1_CC2S_Shift, 8   @ bitWidth 2 (capture/Compare 2 selection)  
        .equ TIM1_IC2PSC_Shift, 10   @ bitWidth 2 (Input capture 2 prescaler)  
        .equ TIM1_IC2F_Shift, 12   @ bitWidth 4 (Input capture 2 filter)  
 
    .equ TIM1_CCMR1_Output, TIM1_BASE + 0x18 @ (capture/compare mode register 1 output mode) 
        .equ TIM1_CC1S_Shift, 0   @ bitWidth 2 (Capture/Compare 1 selection)  
        .equ TIM1_OC1FE_Shift, 2   @ bitWidth 1 (Output Compare 1 fast enable)  
        .equ TIM1_OC1PE_Shift, 3   @ bitWidth 1 (Output Compare 1 preload enable)  
        .equ TIM1_OC1M_Shift, 4   @ bitWidth 3 (Output Compare 1 mode)  
        .equ TIM1_OC1CE_Shift, 7   @ bitWidth 1 (Output Compare 1 clear enable)  
        .equ TIM1_CC2S_Shift, 8   @ bitWidth 2 (Capture/Compare 2 selection)  
        .equ TIM1_OC2FE_Shift, 10   @ bitWidth 1 (Output Compare 2 fast enable)  
        .equ TIM1_OC2PE_Shift, 11   @ bitWidth 1 (Output Compare 2 preload enable)  
        .equ TIM1_OC2M_Shift, 12   @ bitWidth 3 (Output Compare 2 mode)  
        .equ TIM1_OC2CE_Shift, 15   @ bitWidth 1 (Output Compare 2 clear enable)  
        .equ TIM1_OC1M_3_Shift, 16   @ bitWidth 1 (Output Compare 1 mode - bit 3)  
        .equ TIM1_OC2M_3_Shift, 24   @ bitWidth 1 (Output Compare 2 mode - bit 3)  
 
    .equ TIM1_CCMR2_Output, TIM1_BASE + 0x1C @ (capture/compare mode register 2 output mode) 
        .equ TIM1_CC3S_Shift, 0   @ bitWidth 2 (Capture/Compare 3 selection)  
        .equ TIM1_OC3FE_Shift, 2   @ bitWidth 1 (Output compare 3 fast enable)  
        .equ TIM1_OC3PE_Shift, 3   @ bitWidth 1 (Output compare 3 preload enable)  
        .equ TIM1_OC3M_Shift, 4   @ bitWidth 3 (Output compare 3 mode)  
        .equ TIM1_OC3CE_Shift, 7   @ bitWidth 1 (Output compare 3 clear enable)  
        .equ TIM1_CC4S_Shift, 8   @ bitWidth 2 (Capture/Compare 4 selection)  
        .equ TIM1_OC4FE_Shift, 10   @ bitWidth 1 (Output compare 4 fast enable)  
        .equ TIM1_OC4PE_Shift, 11   @ bitWidth 1 (Output compare 4 preload enable)  
        .equ TIM1_OC4M_Shift, 12   @ bitWidth 3 (Output compare 4 mode)  
        .equ TIM1_OC4CE_Shift, 15   @ bitWidth 1 (Output compare 4 clear enable)  
        .equ TIM1_OC3M_3_Shift, 16   @ bitWidth 1 (Output Compare 3 mode - bit 3)  
        .equ TIM1_OC4M_3_Shift, 24   @ bitWidth 1 (Output Compare 4 mode - bit 3)  
 
    .equ TIM1_CCMR2_Input, TIM1_BASE + 0x1C @ (capture/compare mode register 2 output mode) 
        .equ TIM1_CC3S_Shift, 0   @ bitWidth 2 (Capture/Compare 3 selection)  
        .equ TIM1_C3PSC_Shift, 2   @ bitWidth 2 (Input capture 3 prescaler)  
        .equ TIM1_IC3F_Shift, 4   @ bitWidth 4 (Input capture 3 filter)  
        .equ TIM1_CC4S_Shift, 8   @ bitWidth 2 (Capture/Compare 4 selection)  
        .equ TIM1_IC4PSC_Shift, 10   @ bitWidth 2 (Input capture 4 prescaler)  
        .equ TIM1_IC4F_Shift, 12   @ bitWidth 4 (Input capture 4 filter)  
 
    .equ TIM1_CCER, TIM1_BASE + 0x20 @ (capture/compare enable register) 
        .equ TIM1_CC1E_Shift, 0   @ bitWidth 1 (Capture/Compare 1 output enable)  
        .equ TIM1_CC1P_Shift, 1   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM1_CC1NE_Shift, 2   @ bitWidth 1 (Capture/Compare 1 complementary output enable)  
        .equ TIM1_CC1NP_Shift, 3   @ bitWidth 1 (Capture/Compare 1 output Polarity)  
        .equ TIM1_CC2E_Shift, 4   @ bitWidth 1 (Capture/Compare 2 output enable)  
        .equ TIM1_CC2P_Shift, 5   @ bitWidth 1 (Capture/Compare 2 output Polarity)  
        .equ TIM1_CC2NE_Shift, 6   @ bitWidth 1 (Capture/Compare 2 complementary output enable)  
        .equ TIM1_CC2NP_Shift, 7   @ bitWidth 1 (Capture/Compare 2 output Polarity)  
        .equ TIM1_CC3E_Shift, 8   @ bitWidth 1 (Capture/Compare 3 output enable)  
        .equ TIM1_CC3P_Shift, 9   @ bitWidth 1 (Capture/Compare 3 output Polarity)  
        .equ TIM1_CC3NE_Shift, 10   @ bitWidth 1 (Capture/Compare 3 complementary output enable)  
        .equ TIM1_CC3NP_Shift, 11   @ bitWidth 1 (Capture/Compare 3 output Polarity)  
        .equ TIM1_CC4E_Shift, 12   @ bitWidth 1 (Capture/Compare 4 output enable)  
        .equ TIM1_CC4P_Shift, 13   @ bitWidth 1 (Capture/Compare 3 output Polarity)  
        .equ TIM1_CC4NP_Shift, 15   @ bitWidth 1 (Capture/Compare 4 complementary output polarity)  
        .equ TIM1_CC5E_Shift, 16   @ bitWidth 1 (Capture/Compare 5 output enable)  
        .equ TIM1_CC5P_Shift, 17   @ bitWidth 1 (Capture/Compare 5 output polarity)  
        .equ TIM1_CC6E_Shift, 20   @ bitWidth 1 (Capture/Compare 6 output enable)  
        .equ TIM1_CC6P_Shift, 21   @ bitWidth 1 (Capture/Compare 6 output polarity)  
 
    .equ TIM1_CNT, TIM1_BASE + 0x24 @ (counter) 
        .equ TIM1_CNT_Shift, 0   @ bitWidth 16 (counter value)  
        .equ TIM1_UIFCPY_Shift, 31   @ bitWidth 1 (UIF copy)  
 
    .equ TIM1_PSC, TIM1_BASE + 0x28 @ (prescaler) 
        .equ TIM1_PSC_Shift, 0   @ bitWidth 16 (Prescaler value)  
 
    .equ TIM1_ARR, TIM1_BASE + 0x2C @ (auto-reload register) 
        .equ TIM1_ARR_Shift, 0   @ bitWidth 16 (Auto-reload value)  
 
    .equ TIM1_RCR, TIM1_BASE + 0x30 @ (repetition counter register) 
        .equ TIM1_REP_Shift, 0   @ bitWidth 16 (Repetition counter value)  
 
    .equ TIM1_CCR1, TIM1_BASE + 0x34 @ (capture/compare register 1) 
        .equ TIM1_CCR1_Shift, 0   @ bitWidth 16 (Capture/Compare 1 value)  
 
    .equ TIM1_CCR2, TIM1_BASE + 0x38 @ (capture/compare register 2) 
        .equ TIM1_CCR2_Shift, 0   @ bitWidth 16 (Capture/Compare 2 value)  
 
    .equ TIM1_CCR3, TIM1_BASE + 0x3C @ (capture/compare register 3) 
        .equ TIM1_CCR3_Shift, 0   @ bitWidth 16 (Capture/Compare value)  
 
    .equ TIM1_CCR4, TIM1_BASE + 0x40 @ (capture/compare register 4) 
        .equ TIM1_CCR4_Shift, 0   @ bitWidth 16 (Capture/Compare value)  
 
    .equ TIM1_BDTR, TIM1_BASE + 0x44 @ (break and dead-time register) 
        .equ TIM1_DTG_Shift, 0   @ bitWidth 8 (Dead-time generator setup)  
        .equ TIM1_LOCK_Shift, 8   @ bitWidth 2 (Lock configuration)  
        .equ TIM1_OSSI_Shift, 10   @ bitWidth 1 (Off-state selection for Idle mode)  
        .equ TIM1_OSSR_Shift, 11   @ bitWidth 1 (Off-state selection for Run mode)  
        .equ TIM1_BKE_Shift, 12   @ bitWidth 1 (Break enable)  
        .equ TIM1_BKP_Shift, 13   @ bitWidth 1 (Break polarity)  
        .equ TIM1_AOE_Shift, 14   @ bitWidth 1 (Automatic output enable)  
        .equ TIM1_MOE_Shift, 15   @ bitWidth 1 (Main output enable)  
        .equ TIM1_BKF_Shift, 16   @ bitWidth 4 (Break filter)  
        .equ TIM1_BK2F_Shift, 20   @ bitWidth 4 (Break 2 filter)  
        .equ TIM1_BK2E_Shift, 24   @ bitWidth 1 (Break 2 enable)  
        .equ TIM1_BK2P_Shift, 25   @ bitWidth 1 (Break 2 polarity)  
 
    .equ TIM1_DCR, TIM1_BASE + 0x48 @ (DMA control register) 
        .equ TIM1_DBL_Shift, 8   @ bitWidth 5 (DMA burst length)  
        .equ TIM1_DBA_Shift, 0   @ bitWidth 5 (DMA base address)  
 
    .equ TIM1_DMAR, TIM1_BASE + 0x4C @ (DMA address for full transfer) 
        .equ TIM1_DMAB_Shift, 0   @ bitWidth 16 (DMA register for burst accesses)  
 
    .equ TIM1_OR, TIM1_BASE + 0x50 @ (DMA address for full transfer) 
        .equ TIM1_TIM1_ETR_ADC1_RMP_Shift, 0   @ bitWidth 2 (TIM1_ETR_ADC1 remapping capability)  
        .equ TIM1_TI1_RMP_Shift, 4   @ bitWidth 1 (Input Capture 1 remap)  
 
    .equ TIM1_CCMR3_Output, TIM1_BASE + 0x54 @ (capture/compare mode register 2 output mode) 
        .equ TIM1_OC6M_bit3_Shift, 24   @ bitWidth 1 (Output Compare 6 mode bit 3)  
        .equ TIM1_OC5M_bit3_Shift, 16   @ bitWidth 1 (Output Compare 5 mode bit 3)  
        .equ TIM1_OC6CE_Shift, 15   @ bitWidth 1 (Output compare 6 clear enable)  
        .equ TIM1_OC6M_Shift, 12   @ bitWidth 3 (Output compare 6 mode)  
        .equ TIM1_OC6PE_Shift, 11   @ bitWidth 1 (Output compare 6 preload enable)  
        .equ TIM1_OC6FE_Shift, 10   @ bitWidth 1 (Output compare 6 fast enable)  
        .equ TIM1_OC5CE_Shift, 7   @ bitWidth 1 (Output compare 5 clear enable)  
        .equ TIM1_OC5M_Shift, 4   @ bitWidth 3 (Output compare 5 mode)  
        .equ TIM1_OC5PE_Shift, 3   @ bitWidth 1 (Output compare 5 preload enable)  
        .equ TIM1_OC5FE_Shift, 2   @ bitWidth 1 (Output compare 5 fast enable)  
 
    .equ TIM1_CCR5, TIM1_BASE + 0x58 @ (capture/compare register 4) 
        .equ TIM1_CCR5_Shift, 0   @ bitWidth 16 (Capture/Compare value)  
        .equ TIM1_GC5C1_Shift, 29   @ bitWidth 1 (Group Channel 5 and Channel 1)  
        .equ TIM1_GC5C2_Shift, 30   @ bitWidth 1 (Group Channel 5 and Channel 2)  
        .equ TIM1_GC5C3_Shift, 31   @ bitWidth 1 (Group Channel 5 and Channel 3)  
 
    .equ TIM1_CCR6, TIM1_BASE + 0x5C @ (capture/compare register 4) 
        .equ TIM1_CCR6_Shift, 0   @ bitWidth 16 (Capture/Compare value)  
 
    .equ TIM1_AF1, TIM1_BASE + 0x60 @ (DMA address for full transfer) 
        .equ TIM1_BKINE_Shift, 0   @ bitWidth 1 (BRK BKIN input enable)  
        .equ TIM1_BKCMP1E_Shift, 1   @ bitWidth 1 (BRK COMP1 enable)  
        .equ TIM1_BKCMP2E_Shift, 2   @ bitWidth 1 (BRK COMP2 enable)  
        .equ TIM1_BKINP_Shift, 9   @ bitWidth 1 (BRK BKIN input polarity)  
        .equ TIM1_BKCMP1P_Shift, 10   @ bitWidth 1 (BRK COMP1 input polarity)  
        .equ TIM1_BKCMP2P_Shift, 11   @ bitWidth 1 (BRK COMP2 input polarity)  
        .equ TIM1_ETRSEL_Shift, 14   @ bitWidth 3 (ETR source selection)  
 
    .equ TIM1_AF2, TIM1_BASE + 0x64 @ (DMA address for full transfer) 
        .equ TIM1_BK2INE_Shift, 0   @ bitWidth 1 (BRK2 BKIN input enable)  
        .equ TIM1_BK2CMP1E_Shift, 1   @ bitWidth 1 (BRK2 COMP1 enable)  
        .equ TIM1_BK2CMP2E_Shift, 2   @ bitWidth 1 (BRK2 COMP2 enable)  
        .equ TIM1_BK2DFBK0E_Shift, 8   @ bitWidth 1 (BRK2 DFSDM_BREAK0 enable)  
        .equ TIM1_BK2INP_Shift, 9   @ bitWidth 1 (BRK2 BKIN input polarity)  
        .equ TIM1_BK2CMP1P_Shift, 10   @ bitWidth 1 (BRK2 COMP1 input polarity)  
        .equ TIM1_BK2CMP2P_Shift, 11   @ bitWidth 1 (BRK2 COMP2 input polarity)  
 

@=========================== LPTIM1 ===========================@
.equ LPTIM1_BASE, 0x40007C00 @ (Low power timer) 
    .equ LPTIM1_ISR, LPTIM1_BASE + 0x0 @ (Interrupt and Status Register) 
        .equ LPTIM1_DOWN_Shift, 6   @ bitWidth 1 (Counter direction change up to down)  
        .equ LPTIM1_UP_Shift, 5   @ bitWidth 1 (Counter direction change down to up)  
        .equ LPTIM1_ARROK_Shift, 4   @ bitWidth 1 (Autoreload register update OK)  
        .equ LPTIM1_CMPOK_Shift, 3   @ bitWidth 1 (Compare register update OK)  
        .equ LPTIM1_EXTTRIG_Shift, 2   @ bitWidth 1 (External trigger edge event)  
        .equ LPTIM1_ARRM_Shift, 1   @ bitWidth 1 (Autoreload match)  
        .equ LPTIM1_CMPM_Shift, 0   @ bitWidth 1 (Compare match)  
 
    .equ LPTIM1_ICR, LPTIM1_BASE + 0x4 @ (Interrupt Clear Register) 
        .equ LPTIM1_DOWNCF_Shift, 6   @ bitWidth 1 (Direction change to down Clear Flag)  
        .equ LPTIM1_UPCF_Shift, 5   @ bitWidth 1 (Direction change to UP Clear Flag)  
        .equ LPTIM1_ARROKCF_Shift, 4   @ bitWidth 1 (Autoreload register update OK Clear Flag)  
        .equ LPTIM1_CMPOKCF_Shift, 3   @ bitWidth 1 (Compare register update OK Clear Flag)  
        .equ LPTIM1_EXTTRIGCF_Shift, 2   @ bitWidth 1 (External trigger valid edge Clear Flag)  
        .equ LPTIM1_ARRMCF_Shift, 1   @ bitWidth 1 (Autoreload match Clear Flag)  
        .equ LPTIM1_CMPMCF_Shift, 0   @ bitWidth 1 (compare match Clear Flag)  
 
    .equ LPTIM1_IER, LPTIM1_BASE + 0x8 @ (Interrupt Enable Register) 
        .equ LPTIM1_DOWNIE_Shift, 6   @ bitWidth 1 (Direction change to down Interrupt Enable)  
        .equ LPTIM1_UPIE_Shift, 5   @ bitWidth 1 (Direction change to UP Interrupt Enable)  
        .equ LPTIM1_ARROKIE_Shift, 4   @ bitWidth 1 (Autoreload register update OK Interrupt Enable)  
        .equ LPTIM1_CMPOKIE_Shift, 3   @ bitWidth 1 (Compare register update OK Interrupt Enable)  
        .equ LPTIM1_EXTTRIGIE_Shift, 2   @ bitWidth 1 (External trigger valid edge Interrupt Enable)  
        .equ LPTIM1_ARRMIE_Shift, 1   @ bitWidth 1 (Autoreload match Interrupt Enable)  
        .equ LPTIM1_CMPMIE_Shift, 0   @ bitWidth 1 (Compare match Interrupt Enable)  
 
    .equ LPTIM1_CFGR, LPTIM1_BASE + 0xC @ (Configuration Register) 
        .equ LPTIM1_ENC_Shift, 24   @ bitWidth 1 (Encoder mode enable)  
        .equ LPTIM1_COUNTMODE_Shift, 23   @ bitWidth 1 (counter mode enabled)  
        .equ LPTIM1_PRELOAD_Shift, 22   @ bitWidth 1 (Registers update mode)  
        .equ LPTIM1_WAVPOL_Shift, 21   @ bitWidth 1 (Waveform shape polarity)  
        .equ LPTIM1_WAVE_Shift, 20   @ bitWidth 1 (Waveform shape)  
        .equ LPTIM1_TIMOUT_Shift, 19   @ bitWidth 1 (Timeout enable)  
        .equ LPTIM1_TRIGEN_Shift, 17   @ bitWidth 2 (Trigger enable and polarity)  
        .equ LPTIM1_TRIGSEL_Shift, 13   @ bitWidth 3 (Trigger selector)  
        .equ LPTIM1_PRESC_Shift, 9   @ bitWidth 3 (Clock prescaler)  
        .equ LPTIM1_TRGFLT_Shift, 6   @ bitWidth 2 (Configurable digital filter for trigger)  
        .equ LPTIM1_CKFLT_Shift, 3   @ bitWidth 2 (Configurable digital filter for external clock)  
        .equ LPTIM1_CKPOL_Shift, 1   @ bitWidth 2 (Clock Polarity)  
        .equ LPTIM1_CKSEL_Shift, 0   @ bitWidth 1 (Clock selector)  
 
    .equ LPTIM1_CR, LPTIM1_BASE + 0x10 @ (Control Register) 
        .equ LPTIM1_RSTARE_Shift, 4   @ bitWidth 1 (Reset after read enable)  
        .equ LPTIM1_COUNTRST_Shift, 3   @ bitWidth 1 (Counter reset)  
        .equ LPTIM1_CNTSTRT_Shift, 2   @ bitWidth 1 (Timer start in continuous mode)  
        .equ LPTIM1_SNGSTRT_Shift, 1   @ bitWidth 1 (LPTIM start in single mode)  
        .equ LPTIM1_ENABLE_Shift, 0   @ bitWidth 1 (LPTIM Enable)  
 
    .equ LPTIM1_CMP, LPTIM1_BASE + 0x14 @ (Compare Register) 
        .equ LPTIM1_CMP_Shift, 0   @ bitWidth 16 (Compare value)  
 
    .equ LPTIM1_ARR, LPTIM1_BASE + 0x18 @ (Autoreload Register) 
        .equ LPTIM1_ARR_Shift, 0   @ bitWidth 16 (Auto reload value)  
 
    .equ LPTIM1_CNT, LPTIM1_BASE + 0x1C @ (Counter Register) 
        .equ LPTIM1_CNT_Shift, 0   @ bitWidth 16 (Counter value)  
 
    .equ LPTIM1_OR, LPTIM1_BASE + 0x20 @ (Option Register) 
        .equ LPTIM1_OR1_Shift, 0   @ bitWidth 1 (Option register bit 1)  
        .equ LPTIM1_OR2_Shift, 1   @ bitWidth 1 (Option register bit 2)  
 

@=========================== LPTIM2 ===========================@
.equ LPTIM2_BASE, 0x40009400 @ (Low power timer) 
    .equ LPTIM2_ISR, LPTIM2_BASE + 0x0 @ (Interrupt and Status Register) 
        .equ LPTIM2_DOWN_Shift, 6   @ bitWidth 1 (Counter direction change up to down)  
        .equ LPTIM2_UP_Shift, 5   @ bitWidth 1 (Counter direction change down to up)  
        .equ LPTIM2_ARROK_Shift, 4   @ bitWidth 1 (Autoreload register update OK)  
        .equ LPTIM2_CMPOK_Shift, 3   @ bitWidth 1 (Compare register update OK)  
        .equ LPTIM2_EXTTRIG_Shift, 2   @ bitWidth 1 (External trigger edge event)  
        .equ LPTIM2_ARRM_Shift, 1   @ bitWidth 1 (Autoreload match)  
        .equ LPTIM2_CMPM_Shift, 0   @ bitWidth 1 (Compare match)  
 
    .equ LPTIM2_ICR, LPTIM2_BASE + 0x4 @ (Interrupt Clear Register) 
        .equ LPTIM2_DOWNCF_Shift, 6   @ bitWidth 1 (Direction change to down Clear Flag)  
        .equ LPTIM2_UPCF_Shift, 5   @ bitWidth 1 (Direction change to UP Clear Flag)  
        .equ LPTIM2_ARROKCF_Shift, 4   @ bitWidth 1 (Autoreload register update OK Clear Flag)  
        .equ LPTIM2_CMPOKCF_Shift, 3   @ bitWidth 1 (Compare register update OK Clear Flag)  
        .equ LPTIM2_EXTTRIGCF_Shift, 2   @ bitWidth 1 (External trigger valid edge Clear Flag)  
        .equ LPTIM2_ARRMCF_Shift, 1   @ bitWidth 1 (Autoreload match Clear Flag)  
        .equ LPTIM2_CMPMCF_Shift, 0   @ bitWidth 1 (compare match Clear Flag)  
 
    .equ LPTIM2_IER, LPTIM2_BASE + 0x8 @ (Interrupt Enable Register) 
        .equ LPTIM2_DOWNIE_Shift, 6   @ bitWidth 1 (Direction change to down Interrupt Enable)  
        .equ LPTIM2_UPIE_Shift, 5   @ bitWidth 1 (Direction change to UP Interrupt Enable)  
        .equ LPTIM2_ARROKIE_Shift, 4   @ bitWidth 1 (Autoreload register update OK Interrupt Enable)  
        .equ LPTIM2_CMPOKIE_Shift, 3   @ bitWidth 1 (Compare register update OK Interrupt Enable)  
        .equ LPTIM2_EXTTRIGIE_Shift, 2   @ bitWidth 1 (External trigger valid edge Interrupt Enable)  
        .equ LPTIM2_ARRMIE_Shift, 1   @ bitWidth 1 (Autoreload match Interrupt Enable)  
        .equ LPTIM2_CMPMIE_Shift, 0   @ bitWidth 1 (Compare match Interrupt Enable)  
 
    .equ LPTIM2_CFGR, LPTIM2_BASE + 0xC @ (Configuration Register) 
        .equ LPTIM2_ENC_Shift, 24   @ bitWidth 1 (Encoder mode enable)  
        .equ LPTIM2_COUNTMODE_Shift, 23   @ bitWidth 1 (counter mode enabled)  
        .equ LPTIM2_PRELOAD_Shift, 22   @ bitWidth 1 (Registers update mode)  
        .equ LPTIM2_WAVPOL_Shift, 21   @ bitWidth 1 (Waveform shape polarity)  
        .equ LPTIM2_WAVE_Shift, 20   @ bitWidth 1 (Waveform shape)  
        .equ LPTIM2_TIMOUT_Shift, 19   @ bitWidth 1 (Timeout enable)  
        .equ LPTIM2_TRIGEN_Shift, 17   @ bitWidth 2 (Trigger enable and polarity)  
        .equ LPTIM2_TRIGSEL_Shift, 13   @ bitWidth 3 (Trigger selector)  
        .equ LPTIM2_PRESC_Shift, 9   @ bitWidth 3 (Clock prescaler)  
        .equ LPTIM2_TRGFLT_Shift, 6   @ bitWidth 2 (Configurable digital filter for trigger)  
        .equ LPTIM2_CKFLT_Shift, 3   @ bitWidth 2 (Configurable digital filter for external clock)  
        .equ LPTIM2_CKPOL_Shift, 1   @ bitWidth 2 (Clock Polarity)  
        .equ LPTIM2_CKSEL_Shift, 0   @ bitWidth 1 (Clock selector)  
 
    .equ LPTIM2_CR, LPTIM2_BASE + 0x10 @ (Control Register) 
        .equ LPTIM2_RSTARE_Shift, 4   @ bitWidth 1 (Reset after read enable)  
        .equ LPTIM2_COUNTRST_Shift, 3   @ bitWidth 1 (Counter reset)  
        .equ LPTIM2_CNTSTRT_Shift, 2   @ bitWidth 1 (Timer start in continuous mode)  
        .equ LPTIM2_SNGSTRT_Shift, 1   @ bitWidth 1 (LPTIM start in single mode)  
        .equ LPTIM2_ENABLE_Shift, 0   @ bitWidth 1 (LPTIM Enable)  
 
    .equ LPTIM2_CMP, LPTIM2_BASE + 0x14 @ (Compare Register) 
        .equ LPTIM2_CMP_Shift, 0   @ bitWidth 16 (Compare value)  
 
    .equ LPTIM2_ARR, LPTIM2_BASE + 0x18 @ (Autoreload Register) 
        .equ LPTIM2_ARR_Shift, 0   @ bitWidth 16 (Auto reload value)  
 
    .equ LPTIM2_CNT, LPTIM2_BASE + 0x1C @ (Counter Register) 
        .equ LPTIM2_CNT_Shift, 0   @ bitWidth 16 (Counter value)  
 
    .equ LPTIM2_OR, LPTIM2_BASE + 0x20 @ (Option Register) 
        .equ LPTIM2_OR1_Shift, 0   @ bitWidth 1 (Option register bit 1)  
        .equ LPTIM2_OR2_Shift, 1   @ bitWidth 1 (Option register bit 2)  
 

@=========================== USART1 ===========================@
.equ USART1_BASE, 0x40013800 @ (Universal synchronous asynchronous receiver transmitter) 
    .equ USART1_CR1, USART1_BASE + 0x0 @ (Control register 1) 
        .equ USART1_RXFFIE_Shift, 31   @ bitWidth 1 (RXFIFO Full interrupt enable)  
        .equ USART1_TXFEIE_Shift, 30   @ bitWidth 1 (TXFIFO empty interrupt enable)  
        .equ USART1_FIFOEN_Shift, 29   @ bitWidth 1 (FIFO mode enable)  
        .equ USART1_M1_Shift, 28   @ bitWidth 1 (Word length)  
        .equ USART1_EOBIE_Shift, 27   @ bitWidth 1 (End of Block interrupt enable)  
        .equ USART1_RTOIE_Shift, 26   @ bitWidth 1 (Receiver timeout interrupt enable)  
        .equ USART1_DEAT4_Shift, 25   @ bitWidth 1 (Driver Enable assertion time)  
        .equ USART1_DEAT3_Shift, 24   @ bitWidth 1 (DEAT3)  
        .equ USART1_DEAT2_Shift, 23   @ bitWidth 1 (DEAT2)  
        .equ USART1_DEAT1_Shift, 22   @ bitWidth 1 (DEAT1)  
        .equ USART1_DEAT0_Shift, 21   @ bitWidth 1 (DEAT0)  
        .equ USART1_DEDT4_Shift, 20   @ bitWidth 1 (Driver Enable de-assertion time)  
        .equ USART1_DEDT3_Shift, 19   @ bitWidth 1 (DEDT3)  
        .equ USART1_DEDT2_Shift, 18   @ bitWidth 1 (DEDT2)  
        .equ USART1_DEDT1_Shift, 17   @ bitWidth 1 (DEDT1)  
        .equ USART1_DEDT0_Shift, 16   @ bitWidth 1 (DEDT0)  
        .equ USART1_OVER8_Shift, 15   @ bitWidth 1 (Oversampling mode)  
        .equ USART1_CMIE_Shift, 14   @ bitWidth 1 (Character match interrupt enable)  
        .equ USART1_MME_Shift, 13   @ bitWidth 1 (Mute mode enable)  
        .equ USART1_M0_Shift, 12   @ bitWidth 1 (Word length)  
        .equ USART1_WAKE_Shift, 11   @ bitWidth 1 (Receiver wakeup method)  
        .equ USART1_PCE_Shift, 10   @ bitWidth 1 (Parity control enable)  
        .equ USART1_PS_Shift, 9   @ bitWidth 1 (Parity selection)  
        .equ USART1_PEIE_Shift, 8   @ bitWidth 1 (PE interrupt enable)  
        .equ USART1_TXEIE_Shift, 7   @ bitWidth 1 (interrupt enable)  
        .equ USART1_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ USART1_RXNEIE_Shift, 5   @ bitWidth 1 (RXNE interrupt enable)  
        .equ USART1_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE interrupt enable)  
        .equ USART1_TE_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ USART1_RE_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ USART1_UESM_Shift, 1   @ bitWidth 1 (USART enable in Stop mode)  
        .equ USART1_UE_Shift, 0   @ bitWidth 1 (USART enable)  
 
    .equ USART1_CR2, USART1_BASE + 0x4 @ (Control register 2) 
        .equ USART1_ADD4_7_Shift, 28   @ bitWidth 4 (Address of the USART node)  
        .equ USART1_ADD0_3_Shift, 24   @ bitWidth 4 (Address of the USART node)  
        .equ USART1_RTOEN_Shift, 23   @ bitWidth 1 (Receiver timeout enable)  
        .equ USART1_ABRMOD1_Shift, 22   @ bitWidth 1 (Auto baud rate mode)  
        .equ USART1_ABRMOD0_Shift, 21   @ bitWidth 1 (ABRMOD0)  
        .equ USART1_ABREN_Shift, 20   @ bitWidth 1 (Auto baud rate enable)  
        .equ USART1_MSBFIRST_Shift, 19   @ bitWidth 1 (Most significant bit first)  
        .equ USART1_TAINV_Shift, 18   @ bitWidth 1 (Binary data inversion)  
        .equ USART1_TXINV_Shift, 17   @ bitWidth 1 (TX pin active level inversion)  
        .equ USART1_RXINV_Shift, 16   @ bitWidth 1 (RX pin active level inversion)  
        .equ USART1_SWAP_Shift, 15   @ bitWidth 1 (Swap TX/RX pins)  
        .equ USART1_LINEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ USART1_STOP_Shift, 12   @ bitWidth 2 (STOP bits)  
        .equ USART1_CLKEN_Shift, 11   @ bitWidth 1 (Clock enable)  
        .equ USART1_CPOL_Shift, 10   @ bitWidth 1 (Clock polarity)  
        .equ USART1_CPHA_Shift, 9   @ bitWidth 1 (Clock phase)  
        .equ USART1_LBCL_Shift, 8   @ bitWidth 1 (Last bit clock pulse)  
        .equ USART1_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt enable)  
        .equ USART1_LBDL_Shift, 5   @ bitWidth 1 (LIN break detection length)  
        .equ USART1_ADDM7_Shift, 4   @ bitWidth 1 (7-bit Address Detection/4-bit Address Detection)  
        .equ USART1_DIS_NSS_Shift, 3   @ bitWidth 1 (When the DSI_NSS bit is set, the NSS pin input will be ignored)  
        .equ USART1_SLVEN_Shift, 0   @ bitWidth 1 (Synchronous Slave mode enable)  
 
    .equ USART1_CR3, USART1_BASE + 0x8 @ (Control register 3) 
        .equ USART1_TXFTCFG_Shift, 29   @ bitWidth 3 (TXFIFO threshold configuration)  
        .equ USART1_RXFTIE_Shift, 28   @ bitWidth 1 (RXFIFO threshold interrupt enable)  
        .equ USART1_RXFTCFG_Shift, 25   @ bitWidth 3 (Receive FIFO threshold configuration)  
        .equ USART1_TCBGTIE_Shift, 24   @ bitWidth 1 (Tr Complete before guard time, interrupt enable)  
        .equ USART1_TXFTIE_Shift, 23   @ bitWidth 1 (threshold interrupt enable)  
        .equ USART1_WUFIE_Shift, 22   @ bitWidth 1 (Wakeup from Stop mode interrupt enable)  
        .equ USART1_WUS_Shift, 20   @ bitWidth 2 (Wakeup from Stop mode interrupt flag selection)  
        .equ USART1_SCARCNT_Shift, 17   @ bitWidth 3 (Smartcard auto-retry count)  
        .equ USART1_DEP_Shift, 15   @ bitWidth 1 (Driver enable polarity selection)  
        .equ USART1_DEM_Shift, 14   @ bitWidth 1 (Driver enable mode)  
        .equ USART1_DDRE_Shift, 13   @ bitWidth 1 (DMA Disable on Reception Error)  
        .equ USART1_OVRDIS_Shift, 12   @ bitWidth 1 (Overrun Disable)  
        .equ USART1_ONEBIT_Shift, 11   @ bitWidth 1 (One sample bit method enable)  
        .equ USART1_CTSIE_Shift, 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ USART1_CTSE_Shift, 9   @ bitWidth 1 (CTS enable)  
        .equ USART1_RTSE_Shift, 8   @ bitWidth 1 (RTS enable)  
        .equ USART1_DMAT_Shift, 7   @ bitWidth 1 (DMA enable transmitter)  
        .equ USART1_DMAR_Shift, 6   @ bitWidth 1 (DMA enable receiver)  
        .equ USART1_SCEN_Shift, 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ USART1_NACK_Shift, 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ USART1_HDSEL_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ USART1_IRLP_Shift, 2   @ bitWidth 1 (Ir low-power)  
        .equ USART1_IREN_Shift, 1   @ bitWidth 1 (Ir mode enable)  
        .equ USART1_EIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ USART1_BRR, USART1_BASE + 0xC @ (Baud rate register) 
        .equ USART1_BRR_Shift, 0   @ bitWidth 16 (BRR_4_15)  
 
    .equ USART1_GTPR, USART1_BASE + 0x10 @ (Guard time and prescaler register) 
        .equ USART1_GT_Shift, 8   @ bitWidth 8 (Guard time value)  
        .equ USART1_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 
    .equ USART1_RTOR, USART1_BASE + 0x14 @ (Receiver timeout register) 
        .equ USART1_BLEN_Shift, 24   @ bitWidth 8 (Block Length)  
        .equ USART1_RTO_Shift, 0   @ bitWidth 24 (Receiver timeout value)  
 
    .equ USART1_RQR, USART1_BASE + 0x18 @ (Request register) 
        .equ USART1_TXFRQ_Shift, 4   @ bitWidth 1 (Transmit data flush request)  
        .equ USART1_RXFRQ_Shift, 3   @ bitWidth 1 (Receive data flush request)  
        .equ USART1_MMRQ_Shift, 2   @ bitWidth 1 (Mute mode request)  
        .equ USART1_SBKRQ_Shift, 1   @ bitWidth 1 (Send break request)  
        .equ USART1_ABRRQ_Shift, 0   @ bitWidth 1 (Auto baud rate request)  
 
    .equ USART1_ISR, USART1_BASE + 0x1C @ (Interrupt & status register) 
        .equ USART1_TXFT_Shift, 27   @ bitWidth 1 (TXFIFO threshold flag)  
        .equ USART1_RXFT_Shift, 26   @ bitWidth 1 (RXFIFO threshold flag)  
        .equ USART1_TCBGT_Shift, 25   @ bitWidth 1 (Transmission complete before guard time flag)  
        .equ USART1_RXFF_Shift, 24   @ bitWidth 1 (RXFIFO Full)  
        .equ USART1_TXFE_Shift, 23   @ bitWidth 1 (TXFIFO Empty)  
        .equ USART1_REACK_Shift, 22   @ bitWidth 1 (REACK)  
        .equ USART1_TEACK_Shift, 21   @ bitWidth 1 (TEACK)  
        .equ USART1_WUF_Shift, 20   @ bitWidth 1 (WUF)  
        .equ USART1_RWU_Shift, 19   @ bitWidth 1 (RWU)  
        .equ USART1_SBKF_Shift, 18   @ bitWidth 1 (SBKF)  
        .equ USART1_CMF_Shift, 17   @ bitWidth 1 (CMF)  
        .equ USART1_BUSY_Shift, 16   @ bitWidth 1 (BUSY)  
        .equ USART1_ABRF_Shift, 15   @ bitWidth 1 (ABRF)  
        .equ USART1_ABRE_Shift, 14   @ bitWidth 1 (ABRE)  
        .equ USART1_UDR_Shift, 13   @ bitWidth 1 (SPI slave underrun error flag)  
        .equ USART1_EOBF_Shift, 12   @ bitWidth 1 (EOBF)  
        .equ USART1_RTOF_Shift, 11   @ bitWidth 1 (RTOF)  
        .equ USART1_CTS_Shift, 10   @ bitWidth 1 (CTS)  
        .equ USART1_CTSIF_Shift, 9   @ bitWidth 1 (CTSIF)  
        .equ USART1_LBDF_Shift, 8   @ bitWidth 1 (LBDF)  
        .equ USART1_TXE_Shift, 7   @ bitWidth 1 (TXE)  
        .equ USART1_TC_Shift, 6   @ bitWidth 1 (TC)  
        .equ USART1_RXNE_Shift, 5   @ bitWidth 1 (RXNE)  
        .equ USART1_IDLE_Shift, 4   @ bitWidth 1 (IDLE)  
        .equ USART1_ORE_Shift, 3   @ bitWidth 1 (ORE)  
        .equ USART1_NF_Shift, 2   @ bitWidth 1 (NF)  
        .equ USART1_FE_Shift, 1   @ bitWidth 1 (FE)  
        .equ USART1_PE_Shift, 0   @ bitWidth 1 (PE)  
 
    .equ USART1_ICR, USART1_BASE + 0x20 @ (Interrupt flag clear register) 
        .equ USART1_WUCF_Shift, 20   @ bitWidth 1 (Wakeup from Stop mode clear flag)  
        .equ USART1_CMCF_Shift, 17   @ bitWidth 1 (Character match clear flag)  
        .equ USART1_UDRCF_Shift, 13   @ bitWidth 1 (SPI slave underrun clear flag)  
        .equ USART1_EOBCF_Shift, 12   @ bitWidth 1 (End of block clear flag)  
        .equ USART1_RTOCF_Shift, 11   @ bitWidth 1 (Receiver timeout clear flag)  
        .equ USART1_CTSCF_Shift, 9   @ bitWidth 1 (CTS clear flag)  
        .equ USART1_LBDCF_Shift, 8   @ bitWidth 1 (LIN break detection clear flag)  
        .equ USART1_TCBGTCF_Shift, 7   @ bitWidth 1 (Transmission complete before Guard time clear flag)  
        .equ USART1_TCCF_Shift, 6   @ bitWidth 1 (Transmission complete clear flag)  
        .equ USART1_TXFECF_Shift, 5   @ bitWidth 1 (TXFIFO empty clear flag)  
        .equ USART1_IDLECF_Shift, 4   @ bitWidth 1 (Idle line detected clear flag)  
        .equ USART1_ORECF_Shift, 3   @ bitWidth 1 (Overrun error clear flag)  
        .equ USART1_NCF_Shift, 2   @ bitWidth 1 (Noise detected clear flag)  
        .equ USART1_FECF_Shift, 1   @ bitWidth 1 (Framing error clear flag)  
        .equ USART1_PECF_Shift, 0   @ bitWidth 1 (Parity error clear flag)  
 
    .equ USART1_RDR, USART1_BASE + 0x24 @ (Receive data register) 
        .equ USART1_RDR_Shift, 0   @ bitWidth 9 (Receive data value)  
 
    .equ USART1_TDR, USART1_BASE + 0x28 @ (Transmit data register) 
        .equ USART1_TDR_Shift, 0   @ bitWidth 9 (Transmit data value)  
 
    .equ USART1_PRESC, USART1_BASE + 0x2C @ (Prescaler register) 
        .equ USART1_PRESCALER_Shift, 0   @ bitWidth 4 (Clock prescaler)  
 

@=========================== LPUART1 ===========================@
.equ LPUART1_BASE, 0x40008000 @ (Universal synchronous asynchronous receiver transmitter) 
    .equ LPUART1_CR1, LPUART1_BASE + 0x0 @ (Control register 1) 
        .equ LPUART1_RXFFIE_Shift, 31   @ bitWidth 1 (RXFIFO Full interrupt enable)  
        .equ LPUART1_TXFEIE_Shift, 30   @ bitWidth 1 (TXFIFO empty interrupt enable)  
        .equ LPUART1_FIFOEN_Shift, 29   @ bitWidth 1 (FIFO mode enable)  
        .equ LPUART1_M1_Shift, 28   @ bitWidth 1 (Word length)  
        .equ LPUART1_EOBIE_Shift, 27   @ bitWidth 1 (End of Block interrupt enable)  
        .equ LPUART1_RTOIE_Shift, 26   @ bitWidth 1 (Receiver timeout interrupt enable)  
        .equ LPUART1_DEAT4_Shift, 25   @ bitWidth 1 (Driver Enable assertion time)  
        .equ LPUART1_DEAT3_Shift, 24   @ bitWidth 1 (DEAT3)  
        .equ LPUART1_DEAT2_Shift, 23   @ bitWidth 1 (DEAT2)  
        .equ LPUART1_DEAT1_Shift, 22   @ bitWidth 1 (DEAT1)  
        .equ LPUART1_DEAT0_Shift, 21   @ bitWidth 1 (DEAT0)  
        .equ LPUART1_DEDT4_Shift, 20   @ bitWidth 1 (Driver Enable de-assertion time)  
        .equ LPUART1_DEDT3_Shift, 19   @ bitWidth 1 (DEDT3)  
        .equ LPUART1_DEDT2_Shift, 18   @ bitWidth 1 (DEDT2)  
        .equ LPUART1_DEDT1_Shift, 17   @ bitWidth 1 (DEDT1)  
        .equ LPUART1_DEDT0_Shift, 16   @ bitWidth 1 (DEDT0)  
        .equ LPUART1_OVER8_Shift, 15   @ bitWidth 1 (Oversampling mode)  
        .equ LPUART1_CMIE_Shift, 14   @ bitWidth 1 (Character match interrupt enable)  
        .equ LPUART1_MME_Shift, 13   @ bitWidth 1 (Mute mode enable)  
        .equ LPUART1_M0_Shift, 12   @ bitWidth 1 (Word length)  
        .equ LPUART1_WAKE_Shift, 11   @ bitWidth 1 (Receiver wakeup method)  
        .equ LPUART1_PCE_Shift, 10   @ bitWidth 1 (Parity control enable)  
        .equ LPUART1_PS_Shift, 9   @ bitWidth 1 (Parity selection)  
        .equ LPUART1_PEIE_Shift, 8   @ bitWidth 1 (PE interrupt enable)  
        .equ LPUART1_TXEIE_Shift, 7   @ bitWidth 1 (interrupt enable)  
        .equ LPUART1_TCIE_Shift, 6   @ bitWidth 1 (Transmission complete interrupt enable)  
        .equ LPUART1_RXNEIE_Shift, 5   @ bitWidth 1 (RXNE interrupt enable)  
        .equ LPUART1_IDLEIE_Shift, 4   @ bitWidth 1 (IDLE interrupt enable)  
        .equ LPUART1_TE_Shift, 3   @ bitWidth 1 (Transmitter enable)  
        .equ LPUART1_RE_Shift, 2   @ bitWidth 1 (Receiver enable)  
        .equ LPUART1_UESM_Shift, 1   @ bitWidth 1 (USART enable in Stop mode)  
        .equ LPUART1_UE_Shift, 0   @ bitWidth 1 (USART enable)  
 
    .equ LPUART1_CR2, LPUART1_BASE + 0x4 @ (Control register 2) 
        .equ LPUART1_ADD4_7_Shift, 28   @ bitWidth 4 (Address of the USART node)  
        .equ LPUART1_ADD0_3_Shift, 24   @ bitWidth 4 (Address of the USART node)  
        .equ LPUART1_RTOEN_Shift, 23   @ bitWidth 1 (Receiver timeout enable)  
        .equ LPUART1_ABRMOD1_Shift, 22   @ bitWidth 1 (Auto baud rate mode)  
        .equ LPUART1_ABRMOD0_Shift, 21   @ bitWidth 1 (ABRMOD0)  
        .equ LPUART1_ABREN_Shift, 20   @ bitWidth 1 (Auto baud rate enable)  
        .equ LPUART1_MSBFIRST_Shift, 19   @ bitWidth 1 (Most significant bit first)  
        .equ LPUART1_TAINV_Shift, 18   @ bitWidth 1 (Binary data inversion)  
        .equ LPUART1_TXINV_Shift, 17   @ bitWidth 1 (TX pin active level inversion)  
        .equ LPUART1_RXINV_Shift, 16   @ bitWidth 1 (RX pin active level inversion)  
        .equ LPUART1_SWAP_Shift, 15   @ bitWidth 1 (Swap TX/RX pins)  
        .equ LPUART1_LINEN_Shift, 14   @ bitWidth 1 (LIN mode enable)  
        .equ LPUART1_STOP_Shift, 12   @ bitWidth 2 (STOP bits)  
        .equ LPUART1_CLKEN_Shift, 11   @ bitWidth 1 (Clock enable)  
        .equ LPUART1_CPOL_Shift, 10   @ bitWidth 1 (Clock polarity)  
        .equ LPUART1_CPHA_Shift, 9   @ bitWidth 1 (Clock phase)  
        .equ LPUART1_LBCL_Shift, 8   @ bitWidth 1 (Last bit clock pulse)  
        .equ LPUART1_LBDIE_Shift, 6   @ bitWidth 1 (LIN break detection interrupt enable)  
        .equ LPUART1_LBDL_Shift, 5   @ bitWidth 1 (LIN break detection length)  
        .equ LPUART1_ADDM7_Shift, 4   @ bitWidth 1 (7-bit Address Detection/4-bit Address Detection)  
        .equ LPUART1_DIS_NSS_Shift, 3   @ bitWidth 1 (When the DSI_NSS bit is set, the NSS pin input will be ignored)  
        .equ LPUART1_SLVEN_Shift, 0   @ bitWidth 1 (Synchronous Slave mode enable)  
 
    .equ LPUART1_CR3, LPUART1_BASE + 0x8 @ (Control register 3) 
        .equ LPUART1_TXFTCFG_Shift, 29   @ bitWidth 3 (TXFIFO threshold configuration)  
        .equ LPUART1_RXFTIE_Shift, 28   @ bitWidth 1 (RXFIFO threshold interrupt enable)  
        .equ LPUART1_RXFTCFG_Shift, 25   @ bitWidth 3 (Receive FIFO threshold configuration)  
        .equ LPUART1_TCBGTIE_Shift, 24   @ bitWidth 1 (Tr Complete before guard time, interrupt enable)  
        .equ LPUART1_TXFTIE_Shift, 23   @ bitWidth 1 (threshold interrupt enable)  
        .equ LPUART1_WUFIE_Shift, 22   @ bitWidth 1 (Wakeup from Stop mode interrupt enable)  
        .equ LPUART1_WUS_Shift, 20   @ bitWidth 2 (Wakeup from Stop mode interrupt flag selection)  
        .equ LPUART1_SCARCNT_Shift, 17   @ bitWidth 3 (Smartcard auto-retry count)  
        .equ LPUART1_DEP_Shift, 15   @ bitWidth 1 (Driver enable polarity selection)  
        .equ LPUART1_DEM_Shift, 14   @ bitWidth 1 (Driver enable mode)  
        .equ LPUART1_DDRE_Shift, 13   @ bitWidth 1 (DMA Disable on Reception Error)  
        .equ LPUART1_OVRDIS_Shift, 12   @ bitWidth 1 (Overrun Disable)  
        .equ LPUART1_ONEBIT_Shift, 11   @ bitWidth 1 (One sample bit method enable)  
        .equ LPUART1_CTSIE_Shift, 10   @ bitWidth 1 (CTS interrupt enable)  
        .equ LPUART1_CTSE_Shift, 9   @ bitWidth 1 (CTS enable)  
        .equ LPUART1_RTSE_Shift, 8   @ bitWidth 1 (RTS enable)  
        .equ LPUART1_DMAT_Shift, 7   @ bitWidth 1 (DMA enable transmitter)  
        .equ LPUART1_DMAR_Shift, 6   @ bitWidth 1 (DMA enable receiver)  
        .equ LPUART1_SCEN_Shift, 5   @ bitWidth 1 (Smartcard mode enable)  
        .equ LPUART1_NACK_Shift, 4   @ bitWidth 1 (Smartcard NACK enable)  
        .equ LPUART1_HDSEL_Shift, 3   @ bitWidth 1 (Half-duplex selection)  
        .equ LPUART1_IRLP_Shift, 2   @ bitWidth 1 (Ir low-power)  
        .equ LPUART1_IREN_Shift, 1   @ bitWidth 1 (Ir mode enable)  
        .equ LPUART1_EIE_Shift, 0   @ bitWidth 1 (Error interrupt enable)  
 
    .equ LPUART1_BRR, LPUART1_BASE + 0xC @ (Baud rate register) 
        .equ LPUART1_BRR_Shift, 0   @ bitWidth 16 (BRR_4_15)  
 
    .equ LPUART1_GTPR, LPUART1_BASE + 0x10 @ (Guard time and prescaler register) 
        .equ LPUART1_GT_Shift, 8   @ bitWidth 8 (Guard time value)  
        .equ LPUART1_PSC_Shift, 0   @ bitWidth 8 (Prescaler value)  
 
    .equ LPUART1_RTOR, LPUART1_BASE + 0x14 @ (Receiver timeout register) 
        .equ LPUART1_BLEN_Shift, 24   @ bitWidth 8 (Block Length)  
        .equ LPUART1_RTO_Shift, 0   @ bitWidth 24 (Receiver timeout value)  
 
    .equ LPUART1_RQR, LPUART1_BASE + 0x18 @ (Request register) 
        .equ LPUART1_TXFRQ_Shift, 4   @ bitWidth 1 (Transmit data flush request)  
        .equ LPUART1_RXFRQ_Shift, 3   @ bitWidth 1 (Receive data flush request)  
        .equ LPUART1_MMRQ_Shift, 2   @ bitWidth 1 (Mute mode request)  
        .equ LPUART1_SBKRQ_Shift, 1   @ bitWidth 1 (Send break request)  
        .equ LPUART1_ABRRQ_Shift, 0   @ bitWidth 1 (Auto baud rate request)  
 
    .equ LPUART1_ISR, LPUART1_BASE + 0x1C @ (Interrupt & status register) 
        .equ LPUART1_TXFT_Shift, 27   @ bitWidth 1 (TXFIFO threshold flag)  
        .equ LPUART1_RXFT_Shift, 26   @ bitWidth 1 (RXFIFO threshold flag)  
        .equ LPUART1_TCBGT_Shift, 25   @ bitWidth 1 (Transmission complete before guard time flag)  
        .equ LPUART1_RXFF_Shift, 24   @ bitWidth 1 (RXFIFO Full)  
        .equ LPUART1_TXFE_Shift, 23   @ bitWidth 1 (TXFIFO Empty)  
        .equ LPUART1_REACK_Shift, 22   @ bitWidth 1 (REACK)  
        .equ LPUART1_TEACK_Shift, 21   @ bitWidth 1 (TEACK)  
        .equ LPUART1_WUF_Shift, 20   @ bitWidth 1 (WUF)  
        .equ LPUART1_RWU_Shift, 19   @ bitWidth 1 (RWU)  
        .equ LPUART1_SBKF_Shift, 18   @ bitWidth 1 (SBKF)  
        .equ LPUART1_CMF_Shift, 17   @ bitWidth 1 (CMF)  
        .equ LPUART1_BUSY_Shift, 16   @ bitWidth 1 (BUSY)  
        .equ LPUART1_ABRF_Shift, 15   @ bitWidth 1 (ABRF)  
        .equ LPUART1_ABRE_Shift, 14   @ bitWidth 1 (ABRE)  
        .equ LPUART1_UDR_Shift, 13   @ bitWidth 1 (SPI slave underrun error flag)  
        .equ LPUART1_EOBF_Shift, 12   @ bitWidth 1 (EOBF)  
        .equ LPUART1_RTOF_Shift, 11   @ bitWidth 1 (RTOF)  
        .equ LPUART1_CTS_Shift, 10   @ bitWidth 1 (CTS)  
        .equ LPUART1_CTSIF_Shift, 9   @ bitWidth 1 (CTSIF)  
        .equ LPUART1_LBDF_Shift, 8   @ bitWidth 1 (LBDF)  
        .equ LPUART1_TXE_Shift, 7   @ bitWidth 1 (TXE)  
        .equ LPUART1_TC_Shift, 6   @ bitWidth 1 (TC)  
        .equ LPUART1_RXNE_Shift, 5   @ bitWidth 1 (RXNE)  
        .equ LPUART1_IDLE_Shift, 4   @ bitWidth 1 (IDLE)  
        .equ LPUART1_ORE_Shift, 3   @ bitWidth 1 (ORE)  
        .equ LPUART1_NF_Shift, 2   @ bitWidth 1 (NF)  
        .equ LPUART1_FE_Shift, 1   @ bitWidth 1 (FE)  
        .equ LPUART1_PE_Shift, 0   @ bitWidth 1 (PE)  
 
    .equ LPUART1_ICR, LPUART1_BASE + 0x20 @ (Interrupt flag clear register) 
        .equ LPUART1_WUCF_Shift, 20   @ bitWidth 1 (Wakeup from Stop mode clear flag)  
        .equ LPUART1_CMCF_Shift, 17   @ bitWidth 1 (Character match clear flag)  
        .equ LPUART1_UDRCF_Shift, 13   @ bitWidth 1 (SPI slave underrun clear flag)  
        .equ LPUART1_EOBCF_Shift, 12   @ bitWidth 1 (End of block clear flag)  
        .equ LPUART1_RTOCF_Shift, 11   @ bitWidth 1 (Receiver timeout clear flag)  
        .equ LPUART1_CTSCF_Shift, 9   @ bitWidth 1 (CTS clear flag)  
        .equ LPUART1_LBDCF_Shift, 8   @ bitWidth 1 (LIN break detection clear flag)  
        .equ LPUART1_TCBGTCF_Shift, 7   @ bitWidth 1 (Transmission complete before Guard time clear flag)  
        .equ LPUART1_TCCF_Shift, 6   @ bitWidth 1 (Transmission complete clear flag)  
        .equ LPUART1_TXFECF_Shift, 5   @ bitWidth 1 (TXFIFO empty clear flag)  
        .equ LPUART1_IDLECF_Shift, 4   @ bitWidth 1 (Idle line detected clear flag)  
        .equ LPUART1_ORECF_Shift, 3   @ bitWidth 1 (Overrun error clear flag)  
        .equ LPUART1_NCF_Shift, 2   @ bitWidth 1 (Noise detected clear flag)  
        .equ LPUART1_FECF_Shift, 1   @ bitWidth 1 (Framing error clear flag)  
        .equ LPUART1_PECF_Shift, 0   @ bitWidth 1 (Parity error clear flag)  
 
    .equ LPUART1_RDR, LPUART1_BASE + 0x24 @ (Receive data register) 
        .equ LPUART1_RDR_Shift, 0   @ bitWidth 9 (Receive data value)  
 
    .equ LPUART1_TDR, LPUART1_BASE + 0x28 @ (Transmit data register) 
        .equ LPUART1_TDR_Shift, 0   @ bitWidth 9 (Transmit data value)  
 
    .equ LPUART1_PRESC, LPUART1_BASE + 0x2C @ (Prescaler register) 
        .equ LPUART1_PRESCALER_Shift, 0   @ bitWidth 4 (Clock prescaler)  
 

@=========================== SPI1 ===========================@
.equ SPI1_BASE, 0x40013000 @ (Serial peripheral interface/Inter-IC sound) 
    .equ SPI1_CR1, SPI1_BASE + 0x0 @ (control register 1) 
        .equ SPI1_BIDIMODE_Shift, 15   @ bitWidth 1 (Bidirectional data mode enable)  
        .equ SPI1_BIDIOE_Shift, 14   @ bitWidth 1 (Output enable in bidirectional mode)  
        .equ SPI1_CRCEN_Shift, 13   @ bitWidth 1 (Hardware CRC calculation enable)  
        .equ SPI1_CRCNEXT_Shift, 12   @ bitWidth 1 (CRC transfer next)  
        .equ SPI1_DFF_Shift, 11   @ bitWidth 1 (Data frame format)  
        .equ SPI1_RXONLY_Shift, 10   @ bitWidth 1 (Receive only)  
        .equ SPI1_SSM_Shift, 9   @ bitWidth 1 (Software slave management)  
        .equ SPI1_SSI_Shift, 8   @ bitWidth 1 (Internal slave select)  
        .equ SPI1_LSBFIRST_Shift, 7   @ bitWidth 1 (Frame format)  
        .equ SPI1_SPE_Shift, 6   @ bitWidth 1 (SPI enable)  
        .equ SPI1_BR_Shift, 3   @ bitWidth 3 (Baud rate control)  
        .equ SPI1_MSTR_Shift, 2   @ bitWidth 1 (Master selection)  
        .equ SPI1_CPOL_Shift, 1   @ bitWidth 1 (Clock polarity)  
        .equ SPI1_CPHA_Shift, 0   @ bitWidth 1 (Clock phase)  
 
    .equ SPI1_CR2, SPI1_BASE + 0x4 @ (control register 2) 
        .equ SPI1_RXDMAEN_Shift, 0   @ bitWidth 1 (Rx buffer DMA enable)  
        .equ SPI1_TXDMAEN_Shift, 1   @ bitWidth 1 (Tx buffer DMA enable)  
        .equ SPI1_SSOE_Shift, 2   @ bitWidth 1 (SS output enable)  
        .equ SPI1_NSSP_Shift, 3   @ bitWidth 1 (NSS pulse management)  
        .equ SPI1_FRF_Shift, 4   @ bitWidth 1 (Frame format)  
        .equ SPI1_ERRIE_Shift, 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI1_RXNEIE_Shift, 6   @ bitWidth 1 (RX buffer not empty interrupt enable)  
        .equ SPI1_TXEIE_Shift, 7   @ bitWidth 1 (Tx buffer empty interrupt enable)  
        .equ SPI1_DS_Shift, 8   @ bitWidth 4 (Data size)  
        .equ SPI1_FRXTH_Shift, 12   @ bitWidth 1 (FIFO reception threshold)  
        .equ SPI1_LDMA_RX_Shift, 13   @ bitWidth 1 (Last DMA transfer for reception)  
        .equ SPI1_LDMA_TX_Shift, 14   @ bitWidth 1 (Last DMA transfer for transmission)  
 
    .equ SPI1_SR, SPI1_BASE + 0x8 @ (status register) 
        .equ SPI1_RXNE_Shift, 0   @ bitWidth 1 (Receive buffer not empty)  
        .equ SPI1_TXE_Shift, 1   @ bitWidth 1 (Transmit buffer empty)  
        .equ SPI1_CRCERR_Shift, 4   @ bitWidth 1 (CRC error flag)  
        .equ SPI1_MODF_Shift, 5   @ bitWidth 1 (Mode fault)  
        .equ SPI1_OVR_Shift, 6   @ bitWidth 1 (Overrun flag)  
        .equ SPI1_BSY_Shift, 7   @ bitWidth 1 (Busy flag)  
        .equ SPI1_TIFRFE_Shift, 8   @ bitWidth 1 (TI frame format error)  
        .equ SPI1_FRLVL_Shift, 9   @ bitWidth 2 (FIFO reception level)  
        .equ SPI1_FTLVL_Shift, 11   @ bitWidth 2 (FIFO transmission level)  
 
    .equ SPI1_DR, SPI1_BASE + 0xC @ (data register) 
        .equ SPI1_DR_Shift, 0   @ bitWidth 16 (Data register)  
 
    .equ SPI1_CRCPR, SPI1_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI1_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial register)  
 
    .equ SPI1_RXCRCR, SPI1_BASE + 0x14 @ (RX CRC register) 
        .equ SPI1_RxCRC_Shift, 0   @ bitWidth 16 (Rx CRC register)  
 
    .equ SPI1_TXCRCR, SPI1_BASE + 0x18 @ (TX CRC register) 
        .equ SPI1_TxCRC_Shift, 0   @ bitWidth 16 (Tx CRC register)  
 

@=========================== SPI2 ===========================@
.equ SPI2_BASE, 0x40003800 @ (Serial peripheral interface/Inter-IC sound) 
    .equ SPI2_CR1, SPI2_BASE + 0x0 @ (control register 1) 
        .equ SPI2_BIDIMODE_Shift, 15   @ bitWidth 1 (Bidirectional data mode enable)  
        .equ SPI2_BIDIOE_Shift, 14   @ bitWidth 1 (Output enable in bidirectional mode)  
        .equ SPI2_CRCEN_Shift, 13   @ bitWidth 1 (Hardware CRC calculation enable)  
        .equ SPI2_CRCNEXT_Shift, 12   @ bitWidth 1 (CRC transfer next)  
        .equ SPI2_DFF_Shift, 11   @ bitWidth 1 (Data frame format)  
        .equ SPI2_RXONLY_Shift, 10   @ bitWidth 1 (Receive only)  
        .equ SPI2_SSM_Shift, 9   @ bitWidth 1 (Software slave management)  
        .equ SPI2_SSI_Shift, 8   @ bitWidth 1 (Internal slave select)  
        .equ SPI2_LSBFIRST_Shift, 7   @ bitWidth 1 (Frame format)  
        .equ SPI2_SPE_Shift, 6   @ bitWidth 1 (SPI enable)  
        .equ SPI2_BR_Shift, 3   @ bitWidth 3 (Baud rate control)  
        .equ SPI2_MSTR_Shift, 2   @ bitWidth 1 (Master selection)  
        .equ SPI2_CPOL_Shift, 1   @ bitWidth 1 (Clock polarity)  
        .equ SPI2_CPHA_Shift, 0   @ bitWidth 1 (Clock phase)  
 
    .equ SPI2_CR2, SPI2_BASE + 0x4 @ (control register 2) 
        .equ SPI2_RXDMAEN_Shift, 0   @ bitWidth 1 (Rx buffer DMA enable)  
        .equ SPI2_TXDMAEN_Shift, 1   @ bitWidth 1 (Tx buffer DMA enable)  
        .equ SPI2_SSOE_Shift, 2   @ bitWidth 1 (SS output enable)  
        .equ SPI2_NSSP_Shift, 3   @ bitWidth 1 (NSS pulse management)  
        .equ SPI2_FRF_Shift, 4   @ bitWidth 1 (Frame format)  
        .equ SPI2_ERRIE_Shift, 5   @ bitWidth 1 (Error interrupt enable)  
        .equ SPI2_RXNEIE_Shift, 6   @ bitWidth 1 (RX buffer not empty interrupt enable)  
        .equ SPI2_TXEIE_Shift, 7   @ bitWidth 1 (Tx buffer empty interrupt enable)  
        .equ SPI2_DS_Shift, 8   @ bitWidth 4 (Data size)  
        .equ SPI2_FRXTH_Shift, 12   @ bitWidth 1 (FIFO reception threshold)  
        .equ SPI2_LDMA_RX_Shift, 13   @ bitWidth 1 (Last DMA transfer for reception)  
        .equ SPI2_LDMA_TX_Shift, 14   @ bitWidth 1 (Last DMA transfer for transmission)  
 
    .equ SPI2_SR, SPI2_BASE + 0x8 @ (status register) 
        .equ SPI2_RXNE_Shift, 0   @ bitWidth 1 (Receive buffer not empty)  
        .equ SPI2_TXE_Shift, 1   @ bitWidth 1 (Transmit buffer empty)  
        .equ SPI2_CRCERR_Shift, 4   @ bitWidth 1 (CRC error flag)  
        .equ SPI2_MODF_Shift, 5   @ bitWidth 1 (Mode fault)  
        .equ SPI2_OVR_Shift, 6   @ bitWidth 1 (Overrun flag)  
        .equ SPI2_BSY_Shift, 7   @ bitWidth 1 (Busy flag)  
        .equ SPI2_TIFRFE_Shift, 8   @ bitWidth 1 (TI frame format error)  
        .equ SPI2_FRLVL_Shift, 9   @ bitWidth 2 (FIFO reception level)  
        .equ SPI2_FTLVL_Shift, 11   @ bitWidth 2 (FIFO transmission level)  
 
    .equ SPI2_DR, SPI2_BASE + 0xC @ (data register) 
        .equ SPI2_DR_Shift, 0   @ bitWidth 16 (Data register)  
 
    .equ SPI2_CRCPR, SPI2_BASE + 0x10 @ (CRC polynomial register) 
        .equ SPI2_CRCPOLY_Shift, 0   @ bitWidth 16 (CRC polynomial register)  
 
    .equ SPI2_RXCRCR, SPI2_BASE + 0x14 @ (RX CRC register) 
        .equ SPI2_RxCRC_Shift, 0   @ bitWidth 16 (Rx CRC register)  
 
    .equ SPI2_TXCRCR, SPI2_BASE + 0x18 @ (TX CRC register) 
        .equ SPI2_TxCRC_Shift, 0   @ bitWidth 16 (Tx CRC register)  
 

@=========================== VREFBUF ===========================@
.equ VREFBUF_BASE, 0x40010030 @ (Voltage reference buffer) 
    .equ VREFBUF_CSR, VREFBUF_BASE + 0x0 @ (VREF control and status register) 
        .equ VREFBUF_ENVR_Shift, 0   @ bitWidth 1 (Voltage reference buffer enable)  
        .equ VREFBUF_HIZ_Shift, 1   @ bitWidth 1 (High impedance mode)  
        .equ VREFBUF_VRS_Shift, 2   @ bitWidth 1 (Voltage reference scale)  
        .equ VREFBUF_VRR_Shift, 3   @ bitWidth 1 (Voltage reference buffer ready)  
 
    .equ VREFBUF_CCR, VREFBUF_BASE + 0x4 @ (calibration control register) 
        .equ VREFBUF_TRIM_Shift, 0   @ bitWidth 6 (Trimming code)  
 

@=========================== RTC ===========================@
.equ RTC_BASE, 0x40002800 @ (Real-time clock) 
    .equ RTC_TR, RTC_BASE + 0x0 @ (time register) 
        .equ RTC_PM_Shift, 22   @ bitWidth 1 (AM/PM notation)  
        .equ RTC_HT_Shift, 20   @ bitWidth 2 (Hour tens in BCD format)  
        .equ RTC_HU_Shift, 16   @ bitWidth 4 (Hour units in BCD format)  
        .equ RTC_MNT_Shift, 12   @ bitWidth 3 (Minute tens in BCD format)  
        .equ RTC_MNU_Shift, 8   @ bitWidth 4 (Minute units in BCD format)  
        .equ RTC_ST_Shift, 4   @ bitWidth 3 (Second tens in BCD format)  
        .equ RTC_SU_Shift, 0   @ bitWidth 4 (Second units in BCD format)  
 
    .equ RTC_DR, RTC_BASE + 0x4 @ (date register) 
        .equ RTC_YT_Shift, 20   @ bitWidth 4 (Year tens in BCD format)  
        .equ RTC_YU_Shift, 16   @ bitWidth 4 (Year units in BCD format)  
        .equ RTC_WDU_Shift, 13   @ bitWidth 3 (Week day units)  
        .equ RTC_MT_Shift, 12   @ bitWidth 1 (Month tens in BCD format)  
        .equ RTC_MU_Shift, 8   @ bitWidth 4 (Month units in BCD format)  
        .equ RTC_DT_Shift, 4   @ bitWidth 2 (Date tens in BCD format)  
        .equ RTC_DU_Shift, 0   @ bitWidth 4 (Date units in BCD format)  
 
    .equ RTC_CR, RTC_BASE + 0x8 @ (control register) 
        .equ RTC_WCKSEL_Shift, 0   @ bitWidth 3 (Wakeup clock selection)  
        .equ RTC_TSEDGE_Shift, 3   @ bitWidth 1 (Time-stamp event active edge)  
        .equ RTC_REFCKON_Shift, 4   @ bitWidth 1 (Reference clock detection enable 50 or 60 Hz)  
        .equ RTC_BYPSHAD_Shift, 5   @ bitWidth 1 (Bypass the shadow registers)  
        .equ RTC_FMT_Shift, 6   @ bitWidth 1 (Hour format)  
        .equ RTC_ALRAE_Shift, 8   @ bitWidth 1 (Alarm A enable)  
        .equ RTC_ALRBE_Shift, 9   @ bitWidth 1 (Alarm B enable)  
        .equ RTC_WUTE_Shift, 10   @ bitWidth 1 (Wakeup timer enable)  
        .equ RTC_TSE_Shift, 11   @ bitWidth 1 (Time stamp enable)  
        .equ RTC_ALRAIE_Shift, 12   @ bitWidth 1 (Alarm A interrupt enable)  
        .equ RTC_ALRBIE_Shift, 13   @ bitWidth 1 (Alarm B interrupt enable)  
        .equ RTC_WUTIE_Shift, 14   @ bitWidth 1 (Wakeup timer interrupt enable)  
        .equ RTC_TSIE_Shift, 15   @ bitWidth 1 (Time-stamp interrupt enable)  
        .equ RTC_ADD1H_Shift, 16   @ bitWidth 1 (Add 1 hour summer time change)  
        .equ RTC_SUB1H_Shift, 17   @ bitWidth 1 (Subtract 1 hour winter time change)  
        .equ RTC_BKP_Shift, 18   @ bitWidth 1 (Backup)  
        .equ RTC_COSEL_Shift, 19   @ bitWidth 1 (Calibration output selection)  
        .equ RTC_POL_Shift, 20   @ bitWidth 1 (Output polarity)  
        .equ RTC_OSEL_Shift, 21   @ bitWidth 2 (Output selection)  
        .equ RTC_COE_Shift, 23   @ bitWidth 1 (Calibration output enable)  
        .equ RTC_ITSE_Shift, 24   @ bitWidth 1 (timestamp on internal event enable)  
 
    .equ RTC_ISR, RTC_BASE + 0xC @ (initialization and status register) 
        .equ RTC_ALRAWF_Shift, 0   @ bitWidth 1 (Alarm A write flag)  
        .equ RTC_ALRBWF_Shift, 1   @ bitWidth 1 (Alarm B write flag)  
        .equ RTC_WUTWF_Shift, 2   @ bitWidth 1 (Wakeup timer write flag)  
        .equ RTC_SHPF_Shift, 3   @ bitWidth 1 (Shift operation pending)  
        .equ RTC_INITS_Shift, 4   @ bitWidth 1 (Initialization status flag)  
        .equ RTC_RSF_Shift, 5   @ bitWidth 1 (Registers synchronization flag)  
        .equ RTC_INITF_Shift, 6   @ bitWidth 1 (Initialization flag)  
        .equ RTC_INIT_Shift, 7   @ bitWidth 1 (Initialization mode)  
        .equ RTC_ALRAF_Shift, 8   @ bitWidth 1 (Alarm A flag)  
        .equ RTC_ALRBF_Shift, 9   @ bitWidth 1 (Alarm B flag)  
        .equ RTC_WUTF_Shift, 10   @ bitWidth 1 (Wakeup timer flag)  
        .equ RTC_TSF_Shift, 11   @ bitWidth 1 (Time-stamp flag)  
        .equ RTC_TSOVF_Shift, 12   @ bitWidth 1 (Time-stamp overflow flag)  
        .equ RTC_TAMP1F_Shift, 13   @ bitWidth 1 (Tamper detection flag)  
        .equ RTC_TAMP2F_Shift, 14   @ bitWidth 1 (RTC_TAMP2 detection flag)  
        .equ RTC_TAMP3F_Shift, 15   @ bitWidth 1 (RTC_TAMP3 detection flag)  
        .equ RTC_RECALPF_Shift, 16   @ bitWidth 1 (Recalibration pending Flag)  
        .equ RTC_ITSF_Shift, 17   @ bitWidth 1 (INTERNAL TIME-STAMP FLAG)  
 
    .equ RTC_PRER, RTC_BASE + 0x10 @ (prescaler register) 
        .equ RTC_PREDIV_A_Shift, 16   @ bitWidth 7 (Asynchronous prescaler factor)  
        .equ RTC_PREDIV_S_Shift, 0   @ bitWidth 15 (Synchronous prescaler factor)  
 
    .equ RTC_WUTR, RTC_BASE + 0x14 @ (wakeup timer register) 
        .equ RTC_WUT_Shift, 0   @ bitWidth 16 (Wakeup auto-reload value bits)  
 
    .equ RTC_ALRMAR, RTC_BASE + 0x1C @ (alarm A register) 
        .equ RTC_MSK4_Shift, 31   @ bitWidth 1 (Alarm A date mask)  
        .equ RTC_WDSEL_Shift, 30   @ bitWidth 1 (Week day selection)  
        .equ RTC_DT_Shift, 28   @ bitWidth 2 (Date tens in BCD format)  
        .equ RTC_DU_Shift, 24   @ bitWidth 4 (Date units or day in BCD format)  
        .equ RTC_MSK3_Shift, 23   @ bitWidth 1 (Alarm A hours mask)  
        .equ RTC_PM_Shift, 22   @ bitWidth 1 (AM/PM notation)  
        .equ RTC_HT_Shift, 20   @ bitWidth 2 (Hour tens in BCD format)  
        .equ RTC_HU_Shift, 16   @ bitWidth 4 (Hour units in BCD format)  
        .equ RTC_MSK2_Shift, 15   @ bitWidth 1 (Alarm A minutes mask)  
        .equ RTC_MNT_Shift, 12   @ bitWidth 3 (Minute tens in BCD format)  
        .equ RTC_MNU_Shift, 8   @ bitWidth 4 (Minute units in BCD format)  
        .equ RTC_MSK1_Shift, 7   @ bitWidth 1 (Alarm A seconds mask)  
        .equ RTC_ST_Shift, 4   @ bitWidth 3 (Second tens in BCD format)  
        .equ RTC_SU_Shift, 0   @ bitWidth 4 (Second units in BCD format)  
 
    .equ RTC_ALRMBR, RTC_BASE + 0x20 @ (alarm B register) 
        .equ RTC_MSK4_Shift, 31   @ bitWidth 1 (Alarm B date mask)  
        .equ RTC_WDSEL_Shift, 30   @ bitWidth 1 (Week day selection)  
        .equ RTC_DT_Shift, 28   @ bitWidth 2 (Date tens in BCD format)  
        .equ RTC_DU_Shift, 24   @ bitWidth 4 (Date units or day in BCD format)  
        .equ RTC_MSK3_Shift, 23   @ bitWidth 1 (Alarm B hours mask)  
        .equ RTC_PM_Shift, 22   @ bitWidth 1 (AM/PM notation)  
        .equ RTC_HT_Shift, 20   @ bitWidth 2 (Hour tens in BCD format)  
        .equ RTC_HU_Shift, 16   @ bitWidth 4 (Hour units in BCD format)  
        .equ RTC_MSK2_Shift, 15   @ bitWidth 1 (Alarm B minutes mask)  
        .equ RTC_MNT_Shift, 12   @ bitWidth 3 (Minute tens in BCD format)  
        .equ RTC_MNU_Shift, 8   @ bitWidth 4 (Minute units in BCD format)  
        .equ RTC_MSK1_Shift, 7   @ bitWidth 1 (Alarm B seconds mask)  
        .equ RTC_ST_Shift, 4   @ bitWidth 3 (Second tens in BCD format)  
        .equ RTC_SU_Shift, 0   @ bitWidth 4 (Second units in BCD format)  
 
    .equ RTC_WPR, RTC_BASE + 0x24 @ (write protection register) 
        .equ RTC_KEY_Shift, 0   @ bitWidth 8 (Write protection key)  
 
    .equ RTC_SSR, RTC_BASE + 0x28 @ (sub second register) 
        .equ RTC_SS_Shift, 0   @ bitWidth 16 (Sub second value)  
 
    .equ RTC_SHIFTR, RTC_BASE + 0x2C @ (shift control register) 
        .equ RTC_ADD1S_Shift, 31   @ bitWidth 1 (Add one second)  
        .equ RTC_SUBFS_Shift, 0   @ bitWidth 15 (Subtract a fraction of a second)  
 
    .equ RTC_TSTR, RTC_BASE + 0x30 @ (time stamp time register) 
        .equ RTC_SU_Shift, 0   @ bitWidth 4 (Second units in BCD format)  
        .equ RTC_ST_Shift, 4   @ bitWidth 3 (Second tens in BCD format)  
        .equ RTC_MNU_Shift, 8   @ bitWidth 4 (Minute units in BCD format)  
        .equ RTC_MNT_Shift, 12   @ bitWidth 3 (Minute tens in BCD format)  
        .equ RTC_HU_Shift, 16   @ bitWidth 4 (Hour units in BCD format)  
        .equ RTC_HT_Shift, 20   @ bitWidth 2 (Hour tens in BCD format)  
        .equ RTC_PM_Shift, 22   @ bitWidth 1 (AM/PM notation)  
 
    .equ RTC_TSDR, RTC_BASE + 0x34 @ (time stamp date register) 
        .equ RTC_WDU_Shift, 13   @ bitWidth 3 (Week day units)  
        .equ RTC_MT_Shift, 12   @ bitWidth 1 (Month tens in BCD format)  
        .equ RTC_MU_Shift, 8   @ bitWidth 4 (Month units in BCD format)  
        .equ RTC_DT_Shift, 4   @ bitWidth 2 (Date tens in BCD format)  
        .equ RTC_DU_Shift, 0   @ bitWidth 4 (Date units in BCD format)  
 
    .equ RTC_TSSSR, RTC_BASE + 0x38 @ (timestamp sub second register) 
        .equ RTC_SS_Shift, 0   @ bitWidth 16 (Sub second value)  
 
    .equ RTC_CALR, RTC_BASE + 0x3C @ (calibration register) 
        .equ RTC_CALP_Shift, 15   @ bitWidth 1 (Increase frequency of RTC by 488.5 ppm)  
        .equ RTC_CALW8_Shift, 14   @ bitWidth 1 (Use an 8-second calibration cycle period)  
        .equ RTC_CALW16_Shift, 13   @ bitWidth 1 (Use a 16-second calibration cycle period)  
        .equ RTC_CALM_Shift, 0   @ bitWidth 9 (Calibration minus)  
 
    .equ RTC_TAMPCR, RTC_BASE + 0x40 @ (tamper configuration register) 
        .equ RTC_TAMP1E_Shift, 0   @ bitWidth 1 (Tamper 1 detection enable)  
        .equ RTC_TAMP1TRG_Shift, 1   @ bitWidth 1 (Active level for tamper 1)  
        .equ RTC_TAMPIE_Shift, 2   @ bitWidth 1 (Tamper interrupt enable)  
        .equ RTC_TAMP2E_Shift, 3   @ bitWidth 1 (Tamper 2 detection enable)  
        .equ RTC_TAMP2TRG_Shift, 4   @ bitWidth 1 (Active level for tamper 2)  
        .equ RTC_TAMP3E_Shift, 5   @ bitWidth 1 (Tamper 3 detection enable)  
        .equ RTC_TAMP3TRG_Shift, 6   @ bitWidth 1 (Active level for tamper 3)  
        .equ RTC_TAMPTS_Shift, 7   @ bitWidth 1 (Activate timestamp on tamper detection event)  
        .equ RTC_TAMPFREQ_Shift, 8   @ bitWidth 3 (Tamper sampling frequency)  
        .equ RTC_TAMPFLT_Shift, 11   @ bitWidth 2 (Tamper filter count)  
        .equ RTC_TAMPPRCH_Shift, 13   @ bitWidth 2 (Tamper precharge duration)  
        .equ RTC_TAMPPUDIS_Shift, 15   @ bitWidth 1 (TAMPER pull-up disable)  
        .equ RTC_TAMP1IE_Shift, 16   @ bitWidth 1 (Tamper 1 interrupt enable)  
        .equ RTC_TAMP1NOERASE_Shift, 17   @ bitWidth 1 (Tamper 1 no erase)  
        .equ RTC_TAMP1MF_Shift, 18   @ bitWidth 1 (Tamper 1 mask flag)  
        .equ RTC_TAMP2IE_Shift, 19   @ bitWidth 1 (Tamper 2 interrupt enable)  
        .equ RTC_TAMP2NOERASE_Shift, 20   @ bitWidth 1 (Tamper 2 no erase)  
        .equ RTC_TAMP2MF_Shift, 21   @ bitWidth 1 (Tamper 2 mask flag)  
        .equ RTC_TAMP3IE_Shift, 22   @ bitWidth 1 (Tamper 3 interrupt enable)  
        .equ RTC_TAMP3NOERASE_Shift, 23   @ bitWidth 1 (Tamper 3 no erase)  
        .equ RTC_TAMP3MF_Shift, 24   @ bitWidth 1 (Tamper 3 mask flag)  
 
    .equ RTC_ALRMASSR, RTC_BASE + 0x44 @ (alarm A sub second register) 
        .equ RTC_MASKSS_Shift, 24   @ bitWidth 4 (Mask the most-significant bits starting at this bit)  
        .equ RTC_SS_Shift, 0   @ bitWidth 15 (Sub seconds value)  
 
    .equ RTC_ALRMBSSR, RTC_BASE + 0x48 @ (alarm B sub second register) 
        .equ RTC_MASKSS_Shift, 24   @ bitWidth 4 (Mask the most-significant bits starting at this bit)  
        .equ RTC_SS_Shift, 0   @ bitWidth 15 (Sub seconds value)  
 
    .equ RTC_OR, RTC_BASE + 0x4C @ (option register) 
        .equ RTC_RTC_ALARM_TYPE_Shift, 0   @ bitWidth 1 (RTC_ALARM on PC13 output type)  
        .equ RTC_RTC_OUT_RMP_Shift, 1   @ bitWidth 1 (RTC_OUT remap)  
 
    .equ RTC_BKP0R, RTC_BASE + 0x50 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP1R, RTC_BASE + 0x54 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP2R, RTC_BASE + 0x58 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP3R, RTC_BASE + 0x5C @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP4R, RTC_BASE + 0x60 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP5R, RTC_BASE + 0x64 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP6R, RTC_BASE + 0x68 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP7R, RTC_BASE + 0x6C @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP8R, RTC_BASE + 0x70 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP9R, RTC_BASE + 0x74 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP10R, RTC_BASE + 0x78 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP11R, RTC_BASE + 0x7C @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP12R, RTC_BASE + 0x80 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP13R, RTC_BASE + 0x84 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP14R, RTC_BASE + 0x88 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP15R, RTC_BASE + 0x8C @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP16R, RTC_BASE + 0x90 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP17R, RTC_BASE + 0x94 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP18R, RTC_BASE + 0x98 @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 
    .equ RTC_BKP19R, RTC_BASE + 0x9C @ (backup register) 
        .equ RTC_BKP_Shift, 0   @ bitWidth 32 (BKP)  
 

@=========================== DBGMCU ===========================@
.equ DBGMCU_BASE, 0xE0042000 @ (Debug support) 
    .equ DBGMCU_IDCODE, DBGMCU_BASE + 0x0 @ (MCU Device ID Code Register) 
        .equ DBGMCU_DEV_ID_Shift, 0   @ bitWidth 12 (Device Identifier)  
        .equ DBGMCU_REV_ID_Shift, 16   @ bitWidth 16 (Revision Identifier)  
 
    .equ DBGMCU_CR, DBGMCU_BASE + 0x4 @ (Debug MCU Configuration Register) 
        .equ DBGMCU_DBG_SLEEP_Shift, 0   @ bitWidth 1 (Debug Sleep Mode)  
        .equ DBGMCU_DBG_STOP_Shift, 1   @ bitWidth 1 (Debug Stop Mode)  
        .equ DBGMCU_DBG_STANDBY_Shift, 2   @ bitWidth 1 (Debug Standby Mode)  
        .equ DBGMCU_TRACE_IOEN_Shift, 5   @ bitWidth 1 (Trace port and clock enable)  
        .equ DBGMCU_TRGOEN_Shift, 28   @ bitWidth 1 (External trigger output enable)  
 
    .equ DBGMCU_APB1FZR1, DBGMCU_BASE + 0x3C @ (APB1 Low Freeze Register CPU1) 
        .equ DBGMCU_DBG_TIMER2_STOP_Shift, 0   @ bitWidth 1 (Debug Timer 2 stopped when Core is halted)  
        .equ DBGMCU_DBG_RTC_STOP_Shift, 10   @ bitWidth 1 (RTC counter stopped when core is halted)  
        .equ DBGMCU_DBG_WWDG_STOP_Shift, 11   @ bitWidth 1 (WWDG counter stopped when core is halted)  
        .equ DBGMCU_DBG_IWDG_STOP_Shift, 12   @ bitWidth 1 (IWDG counter stopped when core is halted)  
        .equ DBGMCU_DBG_I2C1_STOP_Shift, 21   @ bitWidth 1 (Debug I2C1 SMBUS timeout stopped when Core is halted)  
        .equ DBGMCU_DBG_I2C3_STOP_Shift, 23   @ bitWidth 1 (Debug I2C3 SMBUS timeout stopped when core is halted)  
        .equ DBGMCU_DBG_LPTIM1_STOP_Shift, 31   @ bitWidth 1 (Debug LPTIM1 stopped when Core is halted)  
 
    .equ DBGMCU_C2AP_B1FZR1, DBGMCU_BASE + 0x40 @ (APB1 Low Freeze Register CPU2) 
        .equ DBGMCU_DBG_LPTIM2_STOP_Shift, 0   @ bitWidth 1 (LPTIM2 counter stopped when core is halted)  
        .equ DBGMCU_DBG_RTC_STOP_Shift, 10   @ bitWidth 1 (RTC counter stopped when core is halted)  
        .equ DBGMCU_DBG_IWDG_STOP_Shift, 12   @ bitWidth 1 (IWDG stopped when core is halted)  
        .equ DBGMCU_DBG_I2C1_STOP_Shift, 21   @ bitWidth 1 (I2C1 SMBUS timeout stopped when core is halted)  
        .equ DBGMCU_DBG_I2C3_STOP_Shift, 23   @ bitWidth 1 (I2C3 SMBUS timeout stopped when core is halted)  
        .equ DBGMCU_DBG_LPTIM1_STOP_Shift, 31   @ bitWidth 1 (LPTIM1 counter stopped when core is halted)  
 
    .equ DBGMCU_APB1FZR2, DBGMCU_BASE + 0x44 @ (APB1 High Freeze Register CPU1) 
        .equ DBGMCU_DBG_LPTIM2_STOP_Shift, 5   @ bitWidth 1 (LPTIM2 counter stopped when core is halted)  
 
    .equ DBGMCU_C2APB1FZR2, DBGMCU_BASE + 0x48 @ (APB1 High Freeze Register CPU2) 
        .equ DBGMCU_DBG_LPTIM2_STOP_Shift, 5   @ bitWidth 1 (LPTIM2 counter stopped when core is halted)  
 
    .equ DBGMCU_APB2FZR, DBGMCU_BASE + 0x4C @ (APB2 Freeze Register CPU1) 
        .equ DBGMCU_DBG_TIM1_STOP_Shift, 11   @ bitWidth 1 (TIM1 counter stopped when core is halted)  
        .equ DBGMCU_DBG_TIM16_STOP_Shift, 17   @ bitWidth 1 (TIM16 counter stopped when core is halted)  
        .equ DBGMCU_DBG_TIM17_STOP_Shift, 18   @ bitWidth 1 (TIM17 counter stopped when core is halted)  
 
    .equ DBGMCU_C2APB2FZR, DBGMCU_BASE + 0x48 @ (APB2 Freeze Register CPU2) 
        .equ DBGMCU_DBG_TIM1_STOP_Shift, 11   @ bitWidth 1 (TIM1 counter stopped when core is halted)  
        .equ DBGMCU_DBG_TIM16_STOP_Shift, 17   @ bitWidth 1 (TIM16 counter stopped when core is halted)  
        .equ DBGMCU_DBG_TIM17_STOP_Shift, 18   @ bitWidth 1 (TIM17 counter stopped when core is halted)  
 

@=========================== PKA ===========================@
.equ PKA_BASE, 0x58002000 @ (PKA) 
    .equ PKA_CR, PKA_BASE + 0x0 @ (Control register) 
        .equ PKA_ADDRERRIE_Shift, 20   @ bitWidth 1 (Address error interrupt enable)  
        .equ PKA_RAMERRIE_Shift, 19   @ bitWidth 1 (RAM error interrupt enable)  
        .equ PKA_PROCENDIE_Shift, 17   @ bitWidth 1 (End of operation interrupt enable)  
        .equ PKA_MODE_Shift, 8   @ bitWidth 6 (PKA Operation Mode)  
        .equ PKA_SECLVL_Shift, 2   @ bitWidth 1 (Security Enable)  
        .equ PKA_START_Shift, 1   @ bitWidth 1 (Start the operation)  
        .equ PKA_EN_Shift, 0   @ bitWidth 1 (Peripheral Enable)  
 
    .equ PKA_SR, PKA_BASE + 0x4 @ (PKA status register) 
        .equ PKA_ADDRERRF_Shift, 20   @ bitWidth 1 (Address error flag)  
        .equ PKA_RAMERRF_Shift, 19   @ bitWidth 1 (RAM error flag)  
        .equ PKA_PROCENDF_Shift, 17   @ bitWidth 1 (PKA End of Operation flag)  
        .equ PKA_BUSY_Shift, 16   @ bitWidth 1 (PKA Operation in progress)  
 
    .equ PKA_CLRFR, PKA_BASE + 0x8 @ (PKA clear flag register) 
        .equ PKA_ADDRERRFC_Shift, 20   @ bitWidth 1 (Clear Address error flag)  
        .equ PKA_RAMERRFC_Shift, 19   @ bitWidth 1 (Clear RAM error flag)  
        .equ PKA_PROCENDFC_Shift, 17   @ bitWidth 1 (Clear PKA End of Operation flag)  
 
    .equ PKA_VERR, PKA_BASE + 0x1FF4 @ (PKA version register) 
        .equ PKA_MINREV_Shift, 0   @ bitWidth 4 (Minor revision)  
        .equ PKA_MAJREV_Shift, 4   @ bitWidth 4 (Major revision)  
 
    .equ PKA_IPIDR, PKA_BASE + 0x1FF8 @ (PKA identification register) 
        .equ PKA_ID_Shift, 0   @ bitWidth 32 (Identification Code)  
 
    .equ PKA_SIDR, PKA_BASE + 0x1FFC @ (PKA size ID register) 
        .equ PKA_SID_Shift, 0   @ bitWidth 32 (Side Identification Code)  
 

@=========================== IPCC ===========================@
.equ IPCC_BASE, 0x58000C00 @ (IPCC) 
    .equ IPCC_C1CR, IPCC_BASE + 0x0 @ (Control register CPU1) 
        .equ IPCC_TXFIE_Shift, 16   @ bitWidth 1 (processor 1 Transmit channel free interrupt enable)  
        .equ IPCC_RXOIE_Shift, 0   @ bitWidth 1 (processor 1 Receive channel occupied interrupt enable)  
 
    .equ IPCC_C1MR, IPCC_BASE + 0x4 @ (Mask register CPU1) 
        .equ IPCC_CH6FM_Shift, 21   @ bitWidth 1 (processor 1 Transmit channel 6 free interrupt mask)  
        .equ IPCC_CH5FM_Shift, 20   @ bitWidth 1 (processor 1 Transmit channel 5 free interrupt mask)  
        .equ IPCC_CH4FM_Shift, 19   @ bitWidth 1 (processor 1 Transmit channel 4 free interrupt mask)  
        .equ IPCC_CH3FM_Shift, 18   @ bitWidth 1 (processor 1 Transmit channel 3 free interrupt mask)  
        .equ IPCC_CH2FM_Shift, 17   @ bitWidth 1 (processor 1 Transmit channel 2 free interrupt mask)  
        .equ IPCC_CH1FM_Shift, 16   @ bitWidth 1 (processor 1 Transmit channel 1 free interrupt mask)  
        .equ IPCC_CH6OM_Shift, 5   @ bitWidth 1 (processor 1 Receive channel 6 occupied interrupt enable)  
        .equ IPCC_CH5OM_Shift, 4   @ bitWidth 1 (processor 1 Receive channel 5 occupied interrupt enable)  
        .equ IPCC_CH4OM_Shift, 3   @ bitWidth 1 (processor 1 Receive channel 4 occupied interrupt enable)  
        .equ IPCC_CH3OM_Shift, 2   @ bitWidth 1 (processor 1 Receive channel 3 occupied interrupt enable)  
        .equ IPCC_CH2OM_Shift, 1   @ bitWidth 1 (processor 1 Receive channel 2 occupied interrupt enable)  
        .equ IPCC_CH1OM_Shift, 0   @ bitWidth 1 (processor 1 Receive channel 1 occupied interrupt enable)  
 
    .equ IPCC_C1SCR, IPCC_BASE + 0x8 @ (Status Set or Clear register CPU1) 
        .equ IPCC_CH6S_Shift, 21   @ bitWidth 1 (processor 1 Transmit channel 6 status set)  
        .equ IPCC_CH5S_Shift, 20   @ bitWidth 1 (processor 1 Transmit channel 5 status set)  
        .equ IPCC_CH4S_Shift, 19   @ bitWidth 1 (processor 1 Transmit channel 4 status set)  
        .equ IPCC_CH3S_Shift, 18   @ bitWidth 1 (processor 1 Transmit channel 3 status set)  
        .equ IPCC_CH2S_Shift, 17   @ bitWidth 1 (processor 1 Transmit channel 2 status set)  
        .equ IPCC_CH1S_Shift, 16   @ bitWidth 1 (processor 1 Transmit channel 1 status set)  
        .equ IPCC_CH6C_Shift, 5   @ bitWidth 1 (processor 1 Receive channel 6 status clear)  
        .equ IPCC_CH5C_Shift, 4   @ bitWidth 1 (processor 1 Receive channel 5 status clear)  
        .equ IPCC_CH4C_Shift, 3   @ bitWidth 1 (processor 1 Receive channel 4 status clear)  
        .equ IPCC_CH3C_Shift, 2   @ bitWidth 1 (processor 1 Receive channel 3 status clear)  
        .equ IPCC_CH2C_Shift, 1   @ bitWidth 1 (processor 1 Receive channel 2 status clear)  
        .equ IPCC_CH1C_Shift, 0   @ bitWidth 1 (processor 1 Receive channel 1 status clear)  
 
    .equ IPCC_C1TO2SR, IPCC_BASE + 0xC @ (CPU1 to CPU2 status register) 
        .equ IPCC_CH6F_Shift, 5   @ bitWidth 1 (processor 1 transmit to process 2 Receive channel 6 status flag)  
        .equ IPCC_CH5F_Shift, 4   @ bitWidth 1 (processor 1 transmit to process 2 Receive channel 5 status flag)  
        .equ IPCC_CH4F_Shift, 3   @ bitWidth 1 (processor 1 transmit to process 2 Receive channel 4 status flag)  
        .equ IPCC_CH3F_Shift, 2   @ bitWidth 1 (processor 1 transmit to process 2 Receive channel 3 status flag)  
        .equ IPCC_CH2F_Shift, 1   @ bitWidth 1 (processor 1 transmit to process 2 Receive channel 2 status flag)  
        .equ IPCC_CH1F_Shift, 0   @ bitWidth 1 (processor 1 transmit to process 2 Receive channel 1 status flag)  
 
    .equ IPCC_C2CR, IPCC_BASE + 0x10 @ (Control register CPU2) 
        .equ IPCC_TXFIE_Shift, 16   @ bitWidth 1 (processor 2 Transmit channel free interrupt enable)  
        .equ IPCC_RXOIE_Shift, 0   @ bitWidth 1 (processor 2 Receive channel occupied interrupt enable)  
 
    .equ IPCC_C2MR, IPCC_BASE + 0x14 @ (Mask register CPU2) 
        .equ IPCC_CH6FM_Shift, 21   @ bitWidth 1 (processor 2 Transmit channel 6 free interrupt mask)  
        .equ IPCC_CH5FM_Shift, 20   @ bitWidth 1 (processor 2 Transmit channel 5 free interrupt mask)  
        .equ IPCC_CH4FM_Shift, 19   @ bitWidth 1 (processor 2 Transmit channel 4 free interrupt mask)  
        .equ IPCC_CH3FM_Shift, 18   @ bitWidth 1 (processor 2 Transmit channel 3 free interrupt mask)  
        .equ IPCC_CH2FM_Shift, 17   @ bitWidth 1 (processor 2 Transmit channel 2 free interrupt mask)  
        .equ IPCC_CH1FM_Shift, 16   @ bitWidth 1 (processor 2 Transmit channel 1 free interrupt mask)  
        .equ IPCC_CH6OM_Shift, 5   @ bitWidth 1 (processor 2 Receive channel 6 occupied interrupt enable)  
        .equ IPCC_CH5OM_Shift, 4   @ bitWidth 1 (processor 2 Receive channel 5 occupied interrupt enable)  
        .equ IPCC_CH4OM_Shift, 3   @ bitWidth 1 (processor 2 Receive channel 4 occupied interrupt enable)  
        .equ IPCC_CH3OM_Shift, 2   @ bitWidth 1 (processor 2 Receive channel 3 occupied interrupt enable)  
        .equ IPCC_CH2OM_Shift, 1   @ bitWidth 1 (processor 2 Receive channel 2 occupied interrupt enable)  
        .equ IPCC_CH1OM_Shift, 0   @ bitWidth 1 (processor 2 Receive channel 1 occupied interrupt enable)  
 
    .equ IPCC_C2SCR, IPCC_BASE + 0x18 @ (Status Set or Clear register CPU2) 
        .equ IPCC_CH6S_Shift, 21   @ bitWidth 1 (processor 2 Transmit channel 6 status set)  
        .equ IPCC_CH5S_Shift, 20   @ bitWidth 1 (processor 2 Transmit channel 5 status set)  
        .equ IPCC_CH4S_Shift, 19   @ bitWidth 1 (processor 2 Transmit channel 4 status set)  
        .equ IPCC_CH3S_Shift, 18   @ bitWidth 1 (processor 2 Transmit channel 3 status set)  
        .equ IPCC_CH2S_Shift, 17   @ bitWidth 1 (processor 2 Transmit channel 2 status set)  
        .equ IPCC_CH1S_Shift, 16   @ bitWidth 1 (processor 2 Transmit channel 1 status set)  
        .equ IPCC_CH6C_Shift, 5   @ bitWidth 1 (processor 2 Receive channel 6 status clear)  
        .equ IPCC_CH5C_Shift, 4   @ bitWidth 1 (processor 2 Receive channel 5 status clear)  
        .equ IPCC_CH4C_Shift, 3   @ bitWidth 1 (processor 2 Receive channel 4 status clear)  
        .equ IPCC_CH3C_Shift, 2   @ bitWidth 1 (processor 2 Receive channel 3 status clear)  
        .equ IPCC_CH2C_Shift, 1   @ bitWidth 1 (processor 2 Receive channel 2 status clear)  
        .equ IPCC_CH1C_Shift, 0   @ bitWidth 1 (processor 2 Receive channel 1 status clear)  
 
    .equ IPCC_C2TOC1SR, IPCC_BASE + 0x1C @ (CPU2 to CPU1 status register) 
        .equ IPCC_CH6F_Shift, 5   @ bitWidth 1 (processor 2 transmit to process 1 Receive channel 6 status flag)  
        .equ IPCC_CH5F_Shift, 4   @ bitWidth 1 (processor 2 transmit to process 1 Receive channel 5 status flag)  
        .equ IPCC_CH4F_Shift, 3   @ bitWidth 1 (processor 2 transmit to process 1 Receive channel 4 status flag)  
        .equ IPCC_CH3F_Shift, 2   @ bitWidth 1 (processor 2 transmit to process 1 Receive channel 3 status flag)  
        .equ IPCC_CH2F_Shift, 1   @ bitWidth 1 (processor 2 transmit to process 1 Receive channel 2 status flag)  
        .equ IPCC_CH1F_Shift, 0   @ bitWidth 1 (processor 2 transmit to process 1 Receive channel 1 status flag)  
 
    .equ IPCC_HWCFGR, IPCC_BASE + 0x3F0 @ (IPCC Hardware configuration register) 
        .equ IPCC_CHANNELS_Shift, 0   @ bitWidth 8 (Number of channels per CPU supported by the IP, range 1 to 16)  
 
    .equ IPCC_VERR, IPCC_BASE + 0x3F4 @ (IPCC version register) 
        .equ IPCC_MAJREV_Shift, 4   @ bitWidth 4 (Major Revision)  
        .equ IPCC_MINREV_Shift, 0   @ bitWidth 4 (Minor Revision)  
 
    .equ IPCC_IPIDR, IPCC_BASE + 0x3F8 @ (IPCC indentification register) 
        .equ IPCC_IPID_Shift, 0   @ bitWidth 32 (Identification Code)  
 
    .equ IPCC_SIDR, IPCC_BASE + 0x3FC @ (IPCC size indentification register) 
        .equ IPCC_SID_Shift, 0   @ bitWidth 32 (Size Identification Code)  
 

@=========================== EXTI ===========================@
.equ EXTI_BASE, 0x58000800 @ (External interrupt/event controller) 
    .equ EXTI_RTSR1, EXTI_BASE + 0x0 @ (rising trigger selection register) 
        .equ EXTI_RT_Shift, 0   @ bitWidth 22 (Rising trigger event configuration bit of Configurable Event input)  
        .equ EXTI_RT_31_Shift, 31   @ bitWidth 1 (Rising trigger event configuration bit of Configurable Event input)  
 
    .equ EXTI_FTSR1, EXTI_BASE + 0x4 @ (falling trigger selection register) 
        .equ EXTI_FT_Shift, 0   @ bitWidth 22 (Falling trigger event configuration bit of Configurable Event input)  
        .equ EXTI_FT_31_Shift, 31   @ bitWidth 1 (Falling trigger event configuration bit of Configurable Event input)  
 
    .equ EXTI_SWIER1, EXTI_BASE + 0x8 @ (software interrupt event register) 
        .equ EXTI_SWI_Shift, 0   @ bitWidth 22 (Software interrupt on event)  
        .equ EXTI_SWI_31_Shift, 31   @ bitWidth 1 (Software interrupt on event)  
 
    .equ EXTI_PR1, EXTI_BASE + 0xC @ (EXTI pending register) 
        .equ EXTI_PIF_Shift, 0   @ bitWidth 22 (Configurable event inputs Pending bit)  
        .equ EXTI_PIF_31_Shift, 31   @ bitWidth 1 (Configurable event inputs Pending bit)  
 
    .equ EXTI_RTSR2, EXTI_BASE + 0x20 @ (rising trigger selection register) 
        .equ EXTI_RT33_Shift, 1   @ bitWidth 1 (Rising trigger event configuration bit of Configurable Event input)  
        .equ EXTI_RT40_41_Shift, 8   @ bitWidth 2 (Rising trigger event configuration bit of Configurable Event input)  
 
    .equ EXTI_FTSR2, EXTI_BASE + 0x24 @ (falling trigger selection register) 
        .equ EXTI_FT33_Shift, 1   @ bitWidth 1 (Falling trigger event configuration bit of Configurable Event input)  
        .equ EXTI_FT40_41_Shift, 8   @ bitWidth 2 (Falling trigger event configuration bit of Configurable Event input)  
 
    .equ EXTI_SWIER2, EXTI_BASE + 0x28 @ (software interrupt event register) 
        .equ EXTI_SWI33_Shift, 1   @ bitWidth 1 (Software interrupt on event)  
        .equ EXTI_SWI40_41_Shift, 8   @ bitWidth 2 (Software interrupt on event)  
 
    .equ EXTI_PR2, EXTI_BASE + 0x2C @ (pending register) 
        .equ EXTI_PIF33_Shift, 1   @ bitWidth 1 (Configurable event inputs x+32 Pending bit.)  
        .equ EXTI_PIF40_41_Shift, 8   @ bitWidth 2 (Configurable event inputs x+32 Pending bit.)  
 
    .equ EXTI_C1IMR1, EXTI_BASE + 0x80 @ (CPUm wakeup with interrupt mask register) 
        .equ EXTI_IM_Shift, 0   @ bitWidth 32 (CPUm wakeup with interrupt Mask on Event input)  
 
    .equ EXTI_C2IMR1, EXTI_BASE + 0xC0 @ (CPUm wakeup with interrupt mask register) 
        .equ EXTI_IM_Shift, 0   @ bitWidth 32 (CPUm wakeup with interrupt Mask on Event input)  
 
    .equ EXTI_C1EMR1, EXTI_BASE + 0x84 @ (CPUm wakeup with event mask register) 
        .equ EXTI_EM0_15_Shift, 0   @ bitWidth 16 (CPUm Wakeup with event generation Mask on Event input)  
        .equ EXTI_EM17_21_Shift, 17   @ bitWidth 5 (CPUm Wakeup with event generation Mask on Event input)  
 
    .equ EXTI_C2EMR1, EXTI_BASE + 0xC4 @ (CPUm wakeup with event mask register) 
        .equ EXTI_EM0_15_Shift, 0   @ bitWidth 16 (CPUm Wakeup with event generation Mask on Event input)  
        .equ EXTI_EM17_21_Shift, 17   @ bitWidth 5 (CPUm Wakeup with event generation Mask on Event input)  
 
    .equ EXTI_C1IMR2, EXTI_BASE + 0x90 @ (CPUm wakeup with interrupt mask register) 
        .equ EXTI_IM_Shift, 0   @ bitWidth 17 (CPUm Wakeup with interrupt Mask on Event input)  
 
    .equ EXTI_C2IMR2, EXTI_BASE + 0xD0 @ (CPUm wakeup with interrupt mask register) 
        .equ EXTI_IM_Shift, 0   @ bitWidth 17 (CPUm Wakeup with interrupt Mask on Event input)  
 
    .equ EXTI_C1EMR2, EXTI_BASE + 0x94 @ (CPUm wakeup with event mask register) 
        .equ EXTI_EM_Shift, 8   @ bitWidth 2 (CPUm Wakeup with event generation Mask on Event input)  
 
    .equ EXTI_C2EMR2, EXTI_BASE + 0xD4 @ (CPUm wakeup with event mask register) 
        .equ EXTI_EM_Shift, 8   @ bitWidth 2 (CPUm Wakeup with event generation Mask on Event input)  
 
    .equ EXTI_HWCFGR5, EXTI_BASE + 0x3E0 @ (Hardware configuration registers) 
        .equ EXTI_CPUEVENT_Shift, 0   @ bitWidth 32 (HW configuration CPU event generation)  
 
    .equ EXTI_HWCFGR6, EXTI_BASE + 0x3DC @ (Hardware configuration registers) 
        .equ EXTI_CPUEVENT_Shift, 0   @ bitWidth 32 (HW configuration CPU event generation)  
 
    .equ EXTI_HWCFGR7, EXTI_BASE + 0x3D8 @ (EXTI Hardware configuration registers) 
        .equ EXTI_CPUEVENT_Shift, 0   @ bitWidth 32 (HW configuration CPU event generation)  
 
    .equ EXTI_HWCFGR2, EXTI_BASE + 0x3EC @ (Hardware configuration registers) 
        .equ EXTI_EVENT_TRG_Shift, 0   @ bitWidth 32 (HW configuration event trigger type)  
 
    .equ EXTI_HWCFGR3, EXTI_BASE + 0x3E8 @ (Hardware configuration registers) 
        .equ EXTI_EVENT_TRG_Shift, 0   @ bitWidth 32 (HW configuration event trigger type)  
 
    .equ EXTI_HWCFGR4, EXTI_BASE + 0x3E4 @ (Hardware configuration registers) 
        .equ EXTI_EVENT_TRG_Shift, 0   @ bitWidth 32 (HW configuration event trigger type)  
 
    .equ EXTI_HWCFGR1, EXTI_BASE + 0x3F0 @ (Hardware configuration register 1) 
        .equ EXTI_NBEVENTS_Shift, 0   @ bitWidth 8 (HW configuration number of event)  
        .equ EXTI_NBCPUS_Shift, 8   @ bitWidth 4 (HW configuration number of CPUs)  
        .equ EXTI_CPUEVTEN_Shift, 12   @ bitWidth 4 (HW configuration of CPUm event output enable)  
 
    .equ EXTI_VERR, EXTI_BASE + 0x3F4 @ (EXTI IP Version register) 
        .equ EXTI_MINREV_Shift, 0   @ bitWidth 4 (Minor Revision number)  
        .equ EXTI_MAJREV_Shift, 4   @ bitWidth 4 (Major Revision number)  
 
    .equ EXTI_IPIDR, EXTI_BASE + 0x3F8 @ (Identification register) 
        .equ EXTI_IPID_Shift, 0   @ bitWidth 32 (IP Identification)  
 
    .equ EXTI_SIDR, EXTI_BASE + 0x3FC @ (Size ID register) 
        .equ EXTI_SID_Shift, 0   @ bitWidth 32 (Size Identification)  
 

@=========================== CRS ===========================@
.equ CRS_BASE, 0x40006000 @ (Clock recovery system) 
    .equ CRS_CR, CRS_BASE + 0x0 @ (CRS control register) 
        .equ CRS_SYNCOKIE_Shift, 0   @ bitWidth 1 (SYNC event OK interrupt enable)  
        .equ CRS_SYNCWARNIE_Shift, 1   @ bitWidth 1 (SYNC warning interrupt enable)  
        .equ CRS_ERRIE_Shift, 2   @ bitWidth 1 (Synchronization or trimming error interrupt enable)  
        .equ CRS_ESYNCIE_Shift, 3   @ bitWidth 1 (Expected SYNC interrupt enable)  
        .equ CRS_CEN_Shift, 5   @ bitWidth 1 (Frequency error counter enable)  
        .equ CRS_AUTOTRIMEN_Shift, 6   @ bitWidth 1 (Automatic trimming enable)  
        .equ CRS_SWSYNC_Shift, 7   @ bitWidth 1 (Automatic trimming enable)  
        .equ CRS_TRIM_Shift, 8   @ bitWidth 6 (HSI48 oscillator smooth trimming)  
 
    .equ CRS_CFGR, CRS_BASE + 0x4 @ (CRS configuration register) 
        .equ CRS_RELOAD_Shift, 0   @ bitWidth 16 (Counter reload value)  
        .equ CRS_FELIM_Shift, 16   @ bitWidth 8 (Frequency error limit)  
        .equ CRS_SYNCDIV_Shift, 24   @ bitWidth 3 (SYNCDIV)  
        .equ CRS_SYNCSRC_Shift, 28   @ bitWidth 2 (SYNC signal source selection)  
        .equ CRS_SYNCPOL_Shift, 31   @ bitWidth 1 (SYNC polarity selection)  
 
    .equ CRS_ISR, CRS_BASE + 0x8 @ (CRS interrupt and status register) 
        .equ CRS_SYNCOKF_Shift, 0   @ bitWidth 1 (SYNC event OK flag)  
        .equ CRS_SYNCWARNF_Shift, 1   @ bitWidth 1 (SYNC warning flag)  
        .equ CRS_ERRF_Shift, 2   @ bitWidth 1 (Error flag)  
        .equ CRS_ESYNCF_Shift, 3   @ bitWidth 1 (Expected SYNC flag)  
        .equ CRS_SYNCERR_Shift, 8   @ bitWidth 1 (SYNC error)  
        .equ CRS_SYNCMISS_Shift, 9   @ bitWidth 1 (SYNC missed)  
        .equ CRS_TRIMOVF_Shift, 10   @ bitWidth 1 (Trimming overflow or underflow)  
        .equ CRS_FEDIR_Shift, 15   @ bitWidth 1 (Frequency error direction)  
        .equ CRS_FECAP_Shift, 16   @ bitWidth 16 (Frequency error capture)  
 
    .equ CRS_ICR, CRS_BASE + 0xC @ (CRS interrupt flag clear register) 
        .equ CRS_SYNCOKC_Shift, 0   @ bitWidth 1 (SYNC event OK clear flag)  
        .equ CRS_SYNCWARNC_Shift, 1   @ bitWidth 1 (warning clear flag)  
        .equ CRS_ERRC_Shift, 2   @ bitWidth 1 (Error clear flag)  
        .equ CRS_ESYNCC_Shift, 3   @ bitWidth 1 (Expected SYNC clear flag)  
 

@=========================== USB ===========================@
.equ USB_BASE, 0x40006800 @ (Universal serial bus full-speed device interface) 
    .equ USB_EP0R, USB_BASE + 0x0 @ (endpoint 0 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP1R, USB_BASE + 0x4 @ (endpoint 1 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP2R, USB_BASE + 0x8 @ (endpoint 2 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP3R, USB_BASE + 0xC @ (endpoint 3 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP4R, USB_BASE + 0x10 @ (endpoint 4 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP5R, USB_BASE + 0x14 @ (endpoint 5 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP6R, USB_BASE + 0x18 @ (endpoint 6 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_EP7R, USB_BASE + 0x1C @ (endpoint 7 register) 
        .equ USB_EA_Shift, 0   @ bitWidth 4 (Endpoint address)  
        .equ USB_STAT_TX_Shift, 4   @ bitWidth 2 (Status bits, for transmission transfers)  
        .equ USB_DTOG_TX_Shift, 6   @ bitWidth 1 (Data Toggle, for transmission transfers)  
        .equ USB_CTR_TX_Shift, 7   @ bitWidth 1 (Correct Transfer for transmission)  
        .equ USB_EP_KIND_Shift, 8   @ bitWidth 1 (Endpoint kind)  
        .equ USB_EP_TYPE_Shift, 9   @ bitWidth 2 (Endpoint type)  
        .equ USB_SETUP_Shift, 11   @ bitWidth 1 (Setup transaction completed)  
        .equ USB_STAT_RX_Shift, 12   @ bitWidth 2 (Status bits, for reception transfers)  
        .equ USB_DTOG_RX_Shift, 14   @ bitWidth 1 (Data Toggle, for reception transfers)  
        .equ USB_CTR_RX_Shift, 15   @ bitWidth 1 (Correct transfer for reception)  
 
    .equ USB_CNTR, USB_BASE + 0x40 @ (control register) 
        .equ USB_FRES_Shift, 0   @ bitWidth 1 (Force USB Reset)  
        .equ USB_PDWN_Shift, 1   @ bitWidth 1 (Power down)  
        .equ USB_LPMODE_Shift, 2   @ bitWidth 1 (Low-power mode)  
        .equ USB_FSUSP_Shift, 3   @ bitWidth 1 (Force suspend)  
        .equ USB_RESUME_Shift, 4   @ bitWidth 1 (Resume request)  
        .equ USB_L1RESUME_Shift, 5   @ bitWidth 1 (LPM L1 Resume request)  
        .equ USB_L1REQM_Shift, 7   @ bitWidth 1 (LPM L1 state request interrupt mask)  
        .equ USB_ESOFM_Shift, 8   @ bitWidth 1 (Expected start of frame interrupt mask)  
        .equ USB_SOFM_Shift, 9   @ bitWidth 1 (Start of frame interrupt mask)  
        .equ USB_RESETM_Shift, 10   @ bitWidth 1 (USB reset interrupt mask)  
        .equ USB_SUSPM_Shift, 11   @ bitWidth 1 (Suspend mode interrupt mask)  
        .equ USB_WKUPM_Shift, 12   @ bitWidth 1 (Wakeup interrupt mask)  
        .equ USB_ERRM_Shift, 13   @ bitWidth 1 (Error interrupt mask)  
        .equ USB_PMAOVRM_Shift, 14   @ bitWidth 1 (Packet memory area over / underrun interrupt mask)  
        .equ USB_CTRM_Shift, 15   @ bitWidth 1 (Correct transfer interrupt mask)  
 
    .equ USB_ISTR, USB_BASE + 0x44 @ (interrupt status register) 
        .equ USB_EP_ID_Shift, 0   @ bitWidth 4 (Endpoint Identifier)  
        .equ USB_DIR_Shift, 4   @ bitWidth 1 (Direction of transaction)  
        .equ USB_L1REQ_Shift, 7   @ bitWidth 1 (LPM L1 state request)  
        .equ USB_ESOF_Shift, 8   @ bitWidth 1 (Expected start frame)  
        .equ USB_SOF_Shift, 9   @ bitWidth 1 (start of frame)  
        .equ USB_RESET_Shift, 10   @ bitWidth 1 (reset request)  
        .equ USB_SUSP_Shift, 11   @ bitWidth 1 (Suspend mode request)  
        .equ USB_WKUP_Shift, 12   @ bitWidth 1 (Wakeup)  
        .equ USB_ERR_Shift, 13   @ bitWidth 1 (Error)  
        .equ USB_PMAOVR_Shift, 14   @ bitWidth 1 (Packet memory area over / underrun)  
        .equ USB_CTR_Shift, 15   @ bitWidth 1 (Correct transfer)  
 
    .equ USB_FNR, USB_BASE + 0x48 @ (frame number register) 
        .equ USB_FN_Shift, 0   @ bitWidth 11 (Frame number)  
        .equ USB_LSOF_Shift, 11   @ bitWidth 2 (Lost SOF)  
        .equ USB_LCK_Shift, 13   @ bitWidth 1 (Locked)  
        .equ USB_RXDM_Shift, 14   @ bitWidth 1 (Receive data - line status)  
        .equ USB_RXDP_Shift, 15   @ bitWidth 1 (Receive data + line status)  
 
    .equ USB_DADDR, USB_BASE + 0x4C @ (device address) 
        .equ USB_ADD_Shift, 0   @ bitWidth 7 (Device address)  
        .equ USB_EF_Shift, 7   @ bitWidth 1 (Enable function)  
 
    .equ USB_BTABLE, USB_BASE + 0x50 @ (Buffer table address) 
        .equ USB_BTABLE_Shift, 3   @ bitWidth 13 (Buffer table)  
 
    .equ USB_COUNT0_TX, USB_BASE + 0x52 @ (Transmission byte count 0) 
        .equ USB_COUNT0_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT1_TX, USB_BASE + 0x5A @ (Transmission byte count 0) 
        .equ USB_COUNT1_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT2_TX, USB_BASE + 0x62 @ (Transmission byte count 0) 
        .equ USB_COUNT2_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT3_TX, USB_BASE + 0x6A @ (Transmission byte count 0) 
        .equ USB_COUNT3_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT4_TX, USB_BASE + 0x72 @ (Transmission byte count 0) 
        .equ USB_COUNT4_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT5_TX, USB_BASE + 0x7A @ (Transmission byte count 0) 
        .equ USB_COUNT5_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT6_TX, USB_BASE + 0x82 @ (Transmission byte count 0) 
        .equ USB_COUNT6_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_COUNT7_TX, USB_BASE + 0x8A @ (Transmission byte count 0) 
        .equ USB_COUNT7_TX_Shift, 0   @ bitWidth 10 (Transmission byte count)  
 
    .equ USB_ADDR0_RX, USB_BASE + 0x54 @ (Reception buffer address 0) 
        .equ USB_ADDR0_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR1_RX, USB_BASE + 0x5C @ (Reception buffer address 0) 
        .equ USB_ADDR1_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR2_RX, USB_BASE + 0x64 @ (Reception buffer address 0) 
        .equ USB_ADDR2_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR3_RX, USB_BASE + 0x6C @ (Reception buffer address 0) 
        .equ USB_ADDR3_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR4_RX, USB_BASE + 0x74 @ (Reception buffer address 0) 
        .equ USB_ADDR4_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR5_RX, USB_BASE + 0x7C @ (Reception buffer address 0) 
        .equ USB_ADDR5_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR6_RX, USB_BASE + 0x84 @ (Reception buffer address 0) 
        .equ USB_ADDR6_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_ADDR7_RX, USB_BASE + 0x8C @ (Reception buffer address 0) 
        .equ USB_ADDR7_RX_Shift, 1   @ bitWidth 15 (Reception buffer address)  
 
    .equ USB_COUNT0_RX, USB_BASE + 0x56 @ (Reception byte count 0) 
        .equ USB_COUNT0_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT1_RX, USB_BASE + 0x5E @ (Reception byte count 0) 
        .equ USB_COUNT1_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT2_RX, USB_BASE + 0x66 @ (Reception byte count 0) 
        .equ USB_COUNT2_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT3_RX, USB_BASE + 0x6E @ (Reception byte count 0) 
        .equ USB_COUNT3_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT4_RX, USB_BASE + 0x76 @ (Reception byte count 0) 
        .equ USB_COUNT4_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT5_RX, USB_BASE + 0x7E @ (Reception byte count 0) 
        .equ USB_COUNT5_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT6_RX, USB_BASE + 0x86 @ (Reception byte count 0) 
        .equ USB_COUNT6_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_COUNT7_RX, USB_BASE + 0x8E @ (Reception byte count 0) 
        .equ USB_COUNT7_RX_Shift, 0   @ bitWidth 10 (Reception byte count)  
        .equ USB_NUM_BLOCK_Shift, 10   @ bitWidth 5 (Number of blocks)  
        .equ USB_BL_SIZE_Shift, 15   @ bitWidth 1 (Block size)  
 
    .equ USB_LPMCSR, USB_BASE + 0x54 @ (control and status register) 
        .equ USB_LPMEN_Shift, 0   @ bitWidth 1 (LPM support enable)  
        .equ USB_LPMACK_Shift, 1   @ bitWidth 1 (LPM Token acknowledge enable)  
        .equ USB_REMWAKE_Shift, 3   @ bitWidth 1 (RemoteWake value)  
        .equ USB_BESL_Shift, 4   @ bitWidth 4 (BESL value)  
 
    .equ USB_BCDR, USB_BASE + 0x58 @ (Battery charging detector) 
        .equ USB_BCDEN_Shift, 0   @ bitWidth 1 (Battery charging detector BCD enable)  
        .equ USB_DCDEN_Shift, 1   @ bitWidth 1 (Data contact detection DCD mode enable)  
        .equ USB_PDEN_Shift, 2   @ bitWidth 1 (Primary detection PD mode enable)  
        .equ USB_SDEN_Shift, 3   @ bitWidth 1 (Secondary detection SD mode enable)  
        .equ USB_DCDET_Shift, 4   @ bitWidth 1 (Data contact detection DCD status)  
        .equ USB_PDET_Shift, 5   @ bitWidth 1 (Primary detection PD status)  
        .equ USB_SDET_Shift, 6   @ bitWidth 1 (Secondary detection SD status)  
        .equ USB_PS2DET_Shift, 7   @ bitWidth 1 (DM pull-up detection status)  
        .equ USB_DPPU_Shift, 15   @ bitWidth 1 (DP pull-up control)  
 

@=========================== SCB ===========================@
.equ SCB_BASE, 0xE000ED00 @ (System control block) 
    .equ SCB_CPUID, SCB_BASE + 0x0 @ (CPUID base register) 
        .equ SCB_Revision_Shift, 0   @ bitWidth 4 (Revision number)  
        .equ SCB_PartNo_Shift, 4   @ bitWidth 12 (Part number of the processor)  
        .equ SCB_Constant_Shift, 16   @ bitWidth 4 (Reads as 0xF)  
        .equ SCB_Variant_Shift, 20   @ bitWidth 4 (Variant number)  
        .equ SCB_Implementer_Shift, 24   @ bitWidth 8 (Implementer code)  
 
    .equ SCB_ICSR, SCB_BASE + 0x4 @ (Interrupt control and state register) 
        .equ SCB_VECTACTIVE_Shift, 0   @ bitWidth 9 (Active vector)  
        .equ SCB_RETTOBASE_Shift, 11   @ bitWidth 1 (Return to base level)  
        .equ SCB_VECTPENDING_Shift, 12   @ bitWidth 7 (Pending vector)  
        .equ SCB_ISRPENDING_Shift, 22   @ bitWidth 1 (Interrupt pending flag)  
        .equ SCB_PENDSTCLR_Shift, 25   @ bitWidth 1 (SysTick exception clear-pending bit)  
        .equ SCB_PENDSTSET_Shift, 26   @ bitWidth 1 (SysTick exception set-pending bit)  
        .equ SCB_PENDSVCLR_Shift, 27   @ bitWidth 1 (PendSV clear-pending bit)  
        .equ SCB_PENDSVSET_Shift, 28   @ bitWidth 1 (PendSV set-pending bit)  
        .equ SCB_NMIPENDSET_Shift, 31   @ bitWidth 1 (NMI set-pending bit.)  
 
    .equ SCB_VTOR, SCB_BASE + 0x8 @ (Vector table offset register) 
        .equ SCB_TBLOFF_Shift, 9   @ bitWidth 21 (Vector table base offset field)  
 
    .equ SCB_AIRCR, SCB_BASE + 0xC @ (Application interrupt and reset control register) 
        .equ SCB_VECTRESET_Shift, 0   @ bitWidth 1 (VECTRESET)  
        .equ SCB_VECTCLRACTIVE_Shift, 1   @ bitWidth 1 (VECTCLRACTIVE)  
        .equ SCB_SYSRESETREQ_Shift, 2   @ bitWidth 1 (SYSRESETREQ)  
        .equ SCB_PRIGROUP_Shift, 8   @ bitWidth 3 (PRIGROUP)  
        .equ SCB_ENDIANESS_Shift, 15   @ bitWidth 1 (ENDIANESS)  
        .equ SCB_VECTKEYSTAT_Shift, 16   @ bitWidth 16 (Register key)  
 
    .equ SCB_SCR, SCB_BASE + 0x10 @ (System control register) 
        .equ SCB_SLEEPONEXIT_Shift, 1   @ bitWidth 1 (SLEEPONEXIT)  
        .equ SCB_SLEEPDEEP_Shift, 2   @ bitWidth 1 (SLEEPDEEP)  
        .equ SCB_SEVEONPEND_Shift, 4   @ bitWidth 1 (Send Event on Pending bit)  
 
    .equ SCB_CCR, SCB_BASE + 0x14 @ (Configuration and control register) 
        .equ SCB_NONBASETHRDENA_Shift, 0   @ bitWidth 1 (Configures how the processor enters Thread mode)  
        .equ SCB_USERSETMPEND_Shift, 1   @ bitWidth 1 (USERSETMPEND)  
        .equ SCB_UNALIGN__TRP_Shift, 3   @ bitWidth 1 (UNALIGN_ TRP)  
        .equ SCB_DIV_0_TRP_Shift, 4   @ bitWidth 1 (DIV_0_TRP)  
        .equ SCB_BFHFNMIGN_Shift, 8   @ bitWidth 1 (BFHFNMIGN)  
        .equ SCB_STKALIGN_Shift, 9   @ bitWidth 1 (STKALIGN)  
 
    .equ SCB_SHPR1, SCB_BASE + 0x18 @ (System handler priority registers) 
        .equ SCB_PRI_4_Shift, 0   @ bitWidth 8 (Priority of system handler 4)  
        .equ SCB_PRI_5_Shift, 8   @ bitWidth 8 (Priority of system handler 5)  
        .equ SCB_PRI_6_Shift, 16   @ bitWidth 8 (Priority of system handler 6)  
 
    .equ SCB_SHPR2, SCB_BASE + 0x1C @ (System handler priority registers) 
        .equ SCB_PRI_11_Shift, 24   @ bitWidth 8 (Priority of system handler 11)  
 
    .equ SCB_SHPR3, SCB_BASE + 0x20 @ (System handler priority registers) 
        .equ SCB_PRI_14_Shift, 16   @ bitWidth 8 (Priority of system handler 14)  
        .equ SCB_PRI_15_Shift, 24   @ bitWidth 8 (Priority of system handler 15)  
 
    .equ SCB_SHCRS, SCB_BASE + 0x24 @ (System handler control and state register) 
        .equ SCB_MEMFAULTACT_Shift, 0   @ bitWidth 1 (Memory management fault exception active bit)  
        .equ SCB_BUSFAULTACT_Shift, 1   @ bitWidth 1 (Bus fault exception active bit)  
        .equ SCB_USGFAULTACT_Shift, 3   @ bitWidth 1 (Usage fault exception active bit)  
        .equ SCB_SVCALLACT_Shift, 7   @ bitWidth 1 (SVC call active bit)  
        .equ SCB_MONITORACT_Shift, 8   @ bitWidth 1 (Debug monitor active bit)  
        .equ SCB_PENDSVACT_Shift, 10   @ bitWidth 1 (PendSV exception active bit)  
        .equ SCB_SYSTICKACT_Shift, 11   @ bitWidth 1 (SysTick exception active bit)  
        .equ SCB_USGFAULTPENDED_Shift, 12   @ bitWidth 1 (Usage fault exception pending bit)  
        .equ SCB_MEMFAULTPENDED_Shift, 13   @ bitWidth 1 (Memory management fault exception pending bit)  
        .equ SCB_BUSFAULTPENDED_Shift, 14   @ bitWidth 1 (Bus fault exception pending bit)  
        .equ SCB_SVCALLPENDED_Shift, 15   @ bitWidth 1 (SVC call pending bit)  
        .equ SCB_MEMFAULTENA_Shift, 16   @ bitWidth 1 (Memory management fault enable bit)  
        .equ SCB_BUSFAULTENA_Shift, 17   @ bitWidth 1 (Bus fault enable bit)  
        .equ SCB_USGFAULTENA_Shift, 18   @ bitWidth 1 (Usage fault enable bit)  
 
    .equ SCB_CFSR_UFSR_BFSR_MMFSR, SCB_BASE + 0x28 @ (Configurable fault status register) 
        .equ SCB_IACCVIOL_Shift, 1   @ bitWidth 1 (Instruction access violation flag)  
        .equ SCB_MUNSTKERR_Shift, 3   @ bitWidth 1 (Memory manager fault on unstacking for a return from exception)  
        .equ SCB_MSTKERR_Shift, 4   @ bitWidth 1 (Memory manager fault on stacking for exception entry.)  
        .equ SCB_MLSPERR_Shift, 5   @ bitWidth 1 (MLSPERR)  
        .equ SCB_MMARVALID_Shift, 7   @ bitWidth 1 (Memory Management Fault Address Register MMAR valid flag)  
        .equ SCB_IBUSERR_Shift, 8   @ bitWidth 1 (Instruction bus error)  
        .equ SCB_PRECISERR_Shift, 9   @ bitWidth 1 (Precise data bus error)  
        .equ SCB_IMPRECISERR_Shift, 10   @ bitWidth 1 (Imprecise data bus error)  
        .equ SCB_UNSTKERR_Shift, 11   @ bitWidth 1 (Bus fault on unstacking for a return from exception)  
        .equ SCB_STKERR_Shift, 12   @ bitWidth 1 (Bus fault on stacking for exception entry)  
        .equ SCB_LSPERR_Shift, 13   @ bitWidth 1 (Bus fault on floating-point lazy state preservation)  
        .equ SCB_BFARVALID_Shift, 15   @ bitWidth 1 (Bus Fault Address Register BFAR valid flag)  
        .equ SCB_UNDEFINSTR_Shift, 16   @ bitWidth 1 (Undefined instruction usage fault)  
        .equ SCB_INVSTATE_Shift, 17   @ bitWidth 1 (Invalid state usage fault)  
        .equ SCB_INVPC_Shift, 18   @ bitWidth 1 (Invalid PC load usage fault)  
        .equ SCB_NOCP_Shift, 19   @ bitWidth 1 (No coprocessor usage fault.)  
        .equ SCB_UNALIGNED_Shift, 24   @ bitWidth 1 (Unaligned access usage fault)  
        .equ SCB_DIVBYZERO_Shift, 25   @ bitWidth 1 (Divide by zero usage fault)  
 
    .equ SCB_HFSR, SCB_BASE + 0x2C @ (Hard fault status register) 
        .equ SCB_VECTTBL_Shift, 1   @ bitWidth 1 (Vector table hard fault)  
        .equ SCB_FORCED_Shift, 30   @ bitWidth 1 (Forced hard fault)  
        .equ SCB_DEBUG_VT_Shift, 31   @ bitWidth 1 (Reserved for Debug use)  
 
    .equ SCB_MMFAR, SCB_BASE + 0x34 @ (Memory management fault address register) 
        .equ SCB_MMFAR_Shift, 0   @ bitWidth 32 (Memory management fault address)  
 
    .equ SCB_BFAR, SCB_BASE + 0x38 @ (Bus fault address register) 
        .equ SCB_BFAR_Shift, 0   @ bitWidth 32 (Bus fault address)  
 
    .equ SCB_AFSR, SCB_BASE + 0x3C @ (Auxiliary fault status register) 
        .equ SCB_IMPDEF_Shift, 0   @ bitWidth 32 (Implementation defined)  
 

@=========================== STK ===========================@
.equ STK_BASE, 0xE000E010 @ (SysTick timer) 
    .equ STK_CTRL, STK_BASE + 0x0 @ (SysTick control and status register) 
        .equ STK_ENABLE_Shift, 0   @ bitWidth 1 (Counter enable)  
        .equ STK_TICKINT_Shift, 1   @ bitWidth 1 (SysTick exception request enable)  
        .equ STK_CLKSOURCE_Shift, 2   @ bitWidth 1 (Clock source selection)  
        .equ STK_COUNTFLAG_Shift, 16   @ bitWidth 1 (COUNTFLAG)  
 
    .equ STK_LOAD, STK_BASE + 0x4 @ (SysTick reload value register) 
        .equ STK_RELOAD_Shift, 0   @ bitWidth 24 (RELOAD value)  
 
    .equ STK_VAL, STK_BASE + 0x8 @ (SysTick current value register) 
        .equ STK_CURRENT_Shift, 0   @ bitWidth 24 (Current counter value)  
 
    .equ STK_CALIB, STK_BASE + 0xC @ (SysTick calibration value register) 
        .equ STK_TENMS_Shift, 0   @ bitWidth 24 (Calibration value)  
        .equ STK_SKEW_Shift, 30   @ bitWidth 1 (SKEW flag: Indicates whether the TENMS value is exact)  
        .equ STK_NOREF_Shift, 31   @ bitWidth 1 (NOREF flag. Reads as zero)  
 

@=========================== MPU ===========================@
.equ MPU_BASE, 0xE000ED90 @ (Memory protection unit) 
    .equ MPU_MPU_TYPER, MPU_BASE + 0x0 @ (MPU type register) 
        .equ MPU_SEPARATE_Shift, 0   @ bitWidth 1 (Separate flag)  
        .equ MPU_DREGION_Shift, 8   @ bitWidth 8 (Number of MPU data regions)  
        .equ MPU_IREGION_Shift, 16   @ bitWidth 8 (Number of MPU instruction regions)  
 
    .equ MPU_MPU_CTRL, MPU_BASE + 0x4 @ (MPU control register) 
        .equ MPU_ENABLE_Shift, 0   @ bitWidth 1 (Enables the MPU)  
        .equ MPU_HFNMIENA_Shift, 1   @ bitWidth 1 (Enables the operation of MPU during hard fault)  
        .equ MPU_PRIVDEFENA_Shift, 2   @ bitWidth 1 (Enable priviliged software access to default memory map)  
 
    .equ MPU_MPU_RNR, MPU_BASE + 0x8 @ (MPU region number register) 
        .equ MPU_REGION_Shift, 0   @ bitWidth 8 (MPU region)  
 
    .equ MPU_MPU_RBAR, MPU_BASE + 0xC @ (MPU region base address register) 
        .equ MPU_REGION_Shift, 0   @ bitWidth 4 (MPU region field)  
        .equ MPU_VALID_Shift, 4   @ bitWidth 1 (MPU region number valid)  
        .equ MPU_ADDR_Shift, 5   @ bitWidth 27 (Region base address field)  
 
    .equ MPU_MPU_RASR, MPU_BASE + 0x10 @ (MPU region attribute and size register) 
        .equ MPU_ENABLE_Shift, 0   @ bitWidth 1 (Region enable bit.)  
        .equ MPU_SIZE_Shift, 1   @ bitWidth 5 (Size of the MPU protection region)  
        .equ MPU_SRD_Shift, 8   @ bitWidth 8 (Subregion disable bits)  
        .equ MPU_B_Shift, 16   @ bitWidth 1 (memory attribute)  
        .equ MPU_C_Shift, 17   @ bitWidth 1 (memory attribute)  
        .equ MPU_S_Shift, 18   @ bitWidth 1 (Shareable memory attribute)  
        .equ MPU_TEX_Shift, 19   @ bitWidth 3 (memory attribute)  
        .equ MPU_AP_Shift, 24   @ bitWidth 3 (Access permission)  
        .equ MPU_XN_Shift, 28   @ bitWidth 1 (Instruction access disable bit)  
 

@=========================== FPU ===========================@
.equ FPU_BASE, 0xE000EF34 @ (Floting point unit) 
    .equ FPU_FPCCR, FPU_BASE + 0x0 @ (Floating-point context control register) 
        .equ FPU_LSPACT_Shift, 0   @ bitWidth 1 (LSPACT)  
        .equ FPU_USER_Shift, 1   @ bitWidth 1 (USER)  
        .equ FPU_THREAD_Shift, 3   @ bitWidth 1 (THREAD)  
        .equ FPU_HFRDY_Shift, 4   @ bitWidth 1 (HFRDY)  
        .equ FPU_MMRDY_Shift, 5   @ bitWidth 1 (MMRDY)  
        .equ FPU_BFRDY_Shift, 6   @ bitWidth 1 (BFRDY)  
        .equ FPU_MONRDY_Shift, 8   @ bitWidth 1 (MONRDY)  
        .equ FPU_LSPEN_Shift, 30   @ bitWidth 1 (LSPEN)  
        .equ FPU_ASPEN_Shift, 31   @ bitWidth 1 (ASPEN)  
 
    .equ FPU_FPCAR, FPU_BASE + 0x4 @ (Floating-point context address register) 
        .equ FPU_ADDRESS_Shift, 3   @ bitWidth 29 (Location of unpopulated floating-point)  
 
    .equ FPU_FPSCR, FPU_BASE + 0x8 @ (Floating-point status control register) 
        .equ FPU_IOC_Shift, 0   @ bitWidth 1 (Invalid operation cumulative exception bit)  
        .equ FPU_DZC_Shift, 1   @ bitWidth 1 (Division by zero cumulative exception bit.)  
        .equ FPU_OFC_Shift, 2   @ bitWidth 1 (Overflow cumulative exception bit)  
        .equ FPU_UFC_Shift, 3   @ bitWidth 1 (Underflow cumulative exception bit)  
        .equ FPU_IXC_Shift, 4   @ bitWidth 1 (Inexact cumulative exception bit)  
        .equ FPU_IDC_Shift, 7   @ bitWidth 1 (Input denormal cumulative exception bit.)  
        .equ FPU_RMode_Shift, 22   @ bitWidth 2 (Rounding Mode control field)  
        .equ FPU_FZ_Shift, 24   @ bitWidth 1 (Flush-to-zero mode control bit:)  
        .equ FPU_DN_Shift, 25   @ bitWidth 1 (Default NaN mode control bit)  
        .equ FPU_AHP_Shift, 26   @ bitWidth 1 (Alternative half-precision control bit)  
        .equ FPU_V_Shift, 28   @ bitWidth 1 (Overflow condition code flag)  
        .equ FPU_C_Shift, 29   @ bitWidth 1 (Carry condition code flag)  
        .equ FPU_Z_Shift, 30   @ bitWidth 1 (Zero condition code flag)  
        .equ FPU_N_Shift, 31   @ bitWidth 1 (Negative condition code flag)  
 

@=========================== NVIC ===========================@
.equ NVIC_BASE, 0xE000E100 @ (Nested Vectored Interrupt Controller) 
    .equ NVIC_ISER0, NVIC_BASE + 0x0 @ (Interrupt Set-Enable Register) 
        .equ NVIC_SETENA_Shift, 0   @ bitWidth 32 (SETENA)  
 
    .equ NVIC_ISER1, NVIC_BASE + 0x4 @ (Interrupt Set-Enable Register) 
        .equ NVIC_SETENA_Shift, 0   @ bitWidth 32 (SETENA)  
 
    .equ NVIC_ICER0, NVIC_BASE + 0x80 @ (Interrupt Clear-Enable Register) 
        .equ NVIC_CLRENA_Shift, 0   @ bitWidth 32 (CLRENA)  
 
    .equ NVIC_ICER1, NVIC_BASE + 0x84 @ (Interrupt Clear-Enable Register) 
        .equ NVIC_CLRENA_Shift, 0   @ bitWidth 32 (CLRENA)  
 
    .equ NVIC_ISPR0, NVIC_BASE + 0x100 @ (Interrupt Set-Pending Register) 
        .equ NVIC_SETPEND_Shift, 0   @ bitWidth 32 (SETPEND)  
 
    .equ NVIC_ISPR1, NVIC_BASE + 0x104 @ (Interrupt Set-Pending Register) 
        .equ NVIC_SETPEND_Shift, 0   @ bitWidth 32 (SETPEND)  
 
    .equ NVIC_ICPR0, NVIC_BASE + 0x180 @ (Interrupt Clear-Pending Register) 
        .equ NVIC_CLRPEND_Shift, 0   @ bitWidth 32 (CLRPEND)  
 
    .equ NVIC_ICPR1, NVIC_BASE + 0x184 @ (Interrupt Clear-Pending Register) 
        .equ NVIC_CLRPEND_Shift, 0   @ bitWidth 32 (CLRPEND)  
 
    .equ NVIC_IABR0, NVIC_BASE + 0x200 @ (Interrupt Active Bit Register) 
        .equ NVIC_ACTIVE_Shift, 0   @ bitWidth 32 (ACTIVE)  
 
    .equ NVIC_IABR1, NVIC_BASE + 0x204 @ (Interrupt Active Bit Register) 
        .equ NVIC_ACTIVE_Shift, 0   @ bitWidth 32 (ACTIVE)  
 
    .equ NVIC_IPR0, NVIC_BASE + 0x300 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR1, NVIC_BASE + 0x304 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR2, NVIC_BASE + 0x308 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR3, NVIC_BASE + 0x30C @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR4, NVIC_BASE + 0x310 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR5, NVIC_BASE + 0x314 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR6, NVIC_BASE + 0x318 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR7, NVIC_BASE + 0x31C @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR8, NVIC_BASE + 0x320 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR9, NVIC_BASE + 0x324 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR10, NVIC_BASE + 0x328 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR11, NVIC_BASE + 0x32C @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR12, NVIC_BASE + 0x330 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR13, NVIC_BASE + 0x334 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR14, NVIC_BASE + 0x338 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR15, NVIC_BASE + 0x33C @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR16, NVIC_BASE + 0x340 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 
    .equ NVIC_IPR17, NVIC_BASE + 0x344 @ (Interrupt Priority Register) 
        .equ NVIC_IPR_N0_Shift, 0   @ bitWidth 8 (IPR_N0)  
        .equ NVIC_IPR_N1_Shift, 8   @ bitWidth 8 (IPR_N1)  
        .equ NVIC_IPR_N2_Shift, 16   @ bitWidth 8 (IPR_N2)  
        .equ NVIC_IPR_N3_Shift, 24   @ bitWidth 8 (IPR_N3)  
 

@=========================== NVIC_STIR ===========================@
.equ NVIC_STIR_BASE, 0xE000EF00 @ (Nested vectored interrupt controller) 
    .equ NVIC_STIR_STIR, NVIC_STIR_BASE + 0x0 @ (Software trigger interrupt register) 
        .equ NVIC_STIR_INTID_Shift, 0   @ bitWidth 9 (Software generated interrupt ID)  
 

@=========================== SCB_ACTRL ===========================@
.equ SCB_ACTRL_BASE, 0xE000E008 @ (System control block ACTLR) 
    .equ SCB_ACTRL_ACTRL, SCB_ACTRL_BASE + 0x0 @ (Auxiliary control register) 
        .equ SCB_ACTRL_DISMCYCINT_Shift, 0   @ bitWidth 1 (DISMCYCINT)  
        .equ SCB_ACTRL_DISDEFWBUF_Shift, 1   @ bitWidth 1 (DISDEFWBUF)  
        .equ SCB_ACTRL_DISFOLD_Shift, 2   @ bitWidth 1 (DISFOLD)  
        .equ SCB_ACTRL_DISFPCA_Shift, 8   @ bitWidth 1 (DISFPCA)  
        .equ SCB_ACTRL_DISOOFP_Shift, 9   @ bitWidth 1 (DISOOFP)  
 

@=========================== FPU_CPACR ===========================@
.equ FPU_CPACR_BASE, 0xE000ED88 @ (Floating point unit CPACR) 
    .equ FPU_CPACR_CPACR, FPU_CPACR_BASE + 0x0 @ (Coprocessor access control register) 
        .equ FPU_CPACR_CP_Shift, 20   @ bitWidth 4 (CP)  
 
