

\ f (VCO clock) = f (PLL clock input) * (PLLN/PLLM)
\ f (PLL general clock output) = F (VCO clock) / PLLP
\ f (USB, RNG und andere) = f (VCO clock) / PLLQ

  1 24 lshift constant PLLON
  1 25 lshift constant PLLRDY
  1 22 lshift constant PLLSRC
$$40011008 constant USART1_BRR


: 120MHz ( -- )

  \ Set Flash waitstates !
  $104 Flash_ACR !   \ 3 Waitstates for 120 MHz with more than 2.7 V Vcc, Prefetch buffer enabled.

  PLLSRC          \ HSE clock as 8 MHz source

  8  0 lshift or  \ PLLM Division factor for main PLL and audio PLL input clock 
                  \ 8 MHz / 8 =  1 MHz. Divider before VCO. Frequency entering VCO to be between 1 and 2 MHz.

240  6 lshift or  \ PLLN Main PLL multiplication factor for VCO - between 192 and 432 MHz
                  \ 1 MHz * 240 = 240 MHz

  8 24 lshift or  \ PLLQ = 8, 240 MHz / 8 = 30 MHz

  0 16 lshift or  \ PLLP Division factor for main system clock
                  \ 0: /2  1: /4  2: /6  3: /8
                  \ 240 MHz / 2 = 120 MHz 
  RCC_PLLCFGR !

  PLLON RCC_CR bis!
    \ Wait for PLL to lock:
    begin PLLRDY RCC_CR bit@ until

  2                 \ Set PLL as clock source
  %101 10 lshift or \ APB  Low speed prescaler (APB1) - Max 42 MHz ! Here 120/4 MHz = 30 MHz.
  %100 13 lshift or \ APB High speed prescaler (APB2) - Max 90 MHz ! Here 120/2 MHz = 60 MHz.
  RCC_CFGR !

  $209  USART1_BRR ! \ Set Baud rate divider for 115200 Baud at 60 MHz.
;
