
13. May 2026, Mecrisp-Ternary 00+

  First experimental release


18. May 2026, Mecrisp-Ternary 0+-

  - Three-way comparison >=< instead of <
  - Verilog implementation of the processor
  - Targets ULX3S with ECP5 FPGA
  - Simulation in Verilator and Icarus Verilog

