
13. May 2026, Mecrisp-Ternary 00+

  First experimental release


18. May 2026, Mecrisp-Ternary 0+-

  - Three-way comparison >=< instead of <
  - Verilog implementation of the processor
  - Targets ULX3S with ECP5 FPGA
  - Simulation in Verilator and Icarus Verilog

22. June 2026

  - Experiments with interrupts in Verilator

23. June 2026

  - Experiments with interrupts in ULX3S

01. July 2026, Mecrisp-Ternary 0+0

  - Interrupt support in ULX3S and Verilator
  - Fix for d0= and d0<>
  - Cooperative multitasking
  - Balanced ternary gray code

